WO2018063374A1

WO2018063374A1 - Electron blocking layer designs for efficient gan led

Info

Publication number: WO2018063374A1
Application number: PCT/US2016/054915
Authority: WO
Inventors: Han Wui Then; Sansaptak DASGUPTA; Marko Radosavljevic
Original assignee: Intel Corporation
Priority date: 2016-09-30
Filing date: 2016-09-30
Publication date: 2018-04-05
Also published as: TW201822377A

Abstract

Embodiments of the invention include a GaN LED and methods of forming such devices. In an embodiment, the GaN LED may include a p-doped GaN layer and an electron blocking layer formed over the p-doped GaN layer. The electron blocking layer may be an Al_XGa_YIn_{1_X_Y}N. Embodiments may also include a first barrier layer formed over the electron blocking layer, a quantum well layer formed over the electron blocking layer, and a second barrier layer formed over the quantum well layer. In an embodiment the GaN LED may also include an n-doped GaN layer formed over the second barrier layer. According to an embodiment, a bandgap diagram of the LED includes an electron blocking region in the conduction band of the electron blocking layer, and no hole blocking region is formed in the valence band of the electron blocking layer.

Description

ELECTRON BLOCKING LAYER DESIGNS FOR EFFICIENT GAN LED

FIELD OF THE INVENTION

Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, formation of highly efficient quantum wells for use in GaN light emitting diodes (LEDs) and methods of forming such devices.

BACKGROUND OF THE INVENTION

GaN light emitting diodes (LEDs) suffer loss of internal quantum efficiency at high current densities. Internal quantum efficiency (IQE) is the measure of how efficient a light- emitter converts each injected charge carrier (electrons and holes) into photons (light). High current densities are required in applications where high light output is required from a small area LED (e.g., in displays, micro-LEDs, flash lighting, automotive headlights, and general purpose efficient, compact lighting). The loss in IQE at high current densities in GaN LED is due to the poor electron confinement in the quantum- wells and the poor injection efficiency of holes from p-GaN into the quantum wells.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A is a cross-sectional illustration of a semiconducting material stack that includes a quantum well with a p-AlGaN electron blocking layer.

Figure IB is a schematic of the bandgap diagram of the semiconducting material stack in Figure 1A.

Figure 2A is a cross-sectional illustration of a semiconducting material stack that includes a quantum well with a superlattice blocking layer.

Figure 2B is a schematic of the bandgap diagram of the semiconducting material stack in

Figure 2A.

Figure 3A is a cross-sectional illustration of a semiconducting material stack that includes a quantum well with a p-AlGalnN electron blocking layer, according to an embodiment of the invention.

Figure 3B is a schematic of the bandgap diagram of the semiconducting material stack in

Figure 3A, according to an embodiment of the invention.

Figure 4A is a cross-sectional illustration of a semiconducting material stack that includes a plurality of quantum wells with a p-AlGalnN electron blocking layer, according to an embodiment of the invention.

Figure 4B is a schematic of the bandgap diagram of the semiconducting material stack in Figure 4A, according to an embodiment of the invention.

Figure 5A is a cross-sectional illustration of a semiconducting stack after a p-GaN layer is formed over a semiconducting substrate, according to an embodiment of the invention.

Figure 5B is a cross-sectional illustration of the semiconducting stack after an electron blocking layer that includes p-AlGalnN is formed over the p-GaN layer, according to an embodiment of the invention.

Figure 5C is a cross-sectional illustration of the semiconducting stack after a first barrier layer is formed over the electron blocking layer, according to an embodiment of the invention.

Figure 5D is a cross-sectional illustration of the semiconducting stack after a quantum well layer is formed over the first barrier layer, according to an embodiment of the invention.

Figure 5E is a cross-sectional illustration of the semiconducting stack after a second barrier layer is formed over the quantum well layer, according to an embodiment of the invention.

Figure 5F is a cross-sectional illustration of the semiconducting stack after an n-GaN layer is formed over the second barrier layer, according to an embodiment of the invention.

Figure 5G is a cross-sectional illustration after the semiconducting stack is patterned and contacts are formed in order to form an LED, according to an embodiment of the invention.

Figure 6 is a process flow diagram of a process for forming a GaN LED with a p-AlGalnN electron blocking layer, according to an embodiment of the invention.

Figure 7 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.

Figure 8 is a schematic of a computing device that includes one or more transistors GaN LEDs built in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Described herein are systems that include a GaN LED that includes a p-AlGalnN electron blocking layer and methods for forming the GaN LED. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Light emitting diodes often include quantum wells to provide locations where electrons and holes can recombine to produce light emissions. The quantum well will, optimally, confine the electrons in the conduction band and allow for holes from the valence band to be efficiently injected into the quantum well. In order to improve the IQE, some LEDs may also include an electron blocking layer. However, increasing the confinement of the electrons typically also results in an increased barrier to the injection of holes into the quantum wells.

Referring now to Figure 1A and IB, a GaN LED with a quantum well and a p-AlGaN electron blocking layer, and the corresponding bandgap diagram are shown, respectively. In Figure 1 A, the GaN LED 100 includes a p-GaN layer 110 and an n-GaN layer 120. The p-GaN layer 110 may be separated from the n-GaN layer 120 by an electron blocking layer 130, and a quantum well layer 145 that is sandwiched between a first barrier layer 142 and an second barrier layer 147. The electron blocking layer 130 may be p-Alo.2Gao_.sN.

As illustrated in the bandgap diagram in Figure IB, the electron blocking layer 130 produces a dip 132 in the conduction band 170 that blocks the electrons 172 in the conduction band 170 from flowing towards the p-GaN layer 110 locate to the right of the dip 132.

Preventing the electrons 172 from flowing towards the p-GaN layer 110 prevents non-radiative recombination (i.e., heat) with a free carrier hole 184 in the p-GaN layer 110. However, the dip 132 in the conduction band 170 also results in a barrier 133 being formed in the valence band 180. The barrier 133 blocks the injection of holes from p-GaN 110 to the quantum well layer 145.

In Figures 2A and 2B, a GaN LED with a quantum well and a superlattice electron blocking layer, and the corresponding bandgap diagram are shown, respectively. In Figure 2A, the GaN LED 201 includes a p-GaN layer 210 and an n-GaN layer 220. The p-GaN layer 210 may be separated from the n-GaN layer 220 by the superlattice electron blocking layer 231, and a quantum well layer 245 that is sandwiched between a first barrier layer 242 and an second barrier layer 247. The superlattice electron blocking layer 231 may include alternating layers 231_A/231_B of p-Alo.₂Gao.₈N and p-In₀.iGa₀.₉N.

As shown in Figure 2B, the p-Ino.1Gao.9N has a smaller bandgap than the p-Alo_.2Gao_.8N and results in a series of traps 252 in the band diagram. The traps 252 may be closely spaced so that the holes 284 can tunnel and reach the quantum well layer 245 without being stopped by a blocking layer in the valence band 280. However, the traps 252 are also formed in the conduction band 270. As such, the electrons 272 in the conduction band 270 may also tunnel and are not trapped in the quantum well.

Accordingly, the two electron blocking layers used in GaN LEDs 100 and 201 each have drawbacks. The p-Alo_.2Gao_.sN blocking layer 130 in GaN LED 100 confines the electrons in the quantum well, but also reduces the ability of the holes to be injected into the quantum well. In contrast, the superlattice electron blocking layer 232 in GaN LED 201 allows for holes to tunnel towards the quantum well, but at the same time does not prevent the electrons from tunneling away from the quantum well. As such, the IQE of the GaN LEDs at high current densities is limited (e.g., the IQE may be approximately 50% or less) since it is not currently possible to achieve both adequate electron confinement in the quantum wells and the high injection efficiency of holes from p-GaN into the quantum wells.

Accordingly, embodiments of the invention may include GaN LEDs with improved electron blocking layers that allow for increased electron confinement in the quantum- wells while at the same time improving injection efficiency of holes from the p-GaN into the quantum wells. Particularly, embodiments of the invention include a stack of semiconducting materials that produce a bandgap with a blocking region in the conduction band between the quantum well and the p-GaN layer without forming any blocking regions in the valence band between the quantum well and the p-GanN layer. As such, the electrons in the conduction band are confined to the quantum well, whereas the holes in the valence band are able to flow from the p-GaN layer to the quantum well. With an increased concentration of holes and electrons in the quantum well, the IQE may be increased compared to the IQE of the GaN LEDs described above with respect to Figures 1A and 2A. For example, GaN LEDs formed in accordance with embodiments of the invention may have an IQE that is greater than approximately 50%. In some embodiments of the invention, the GaN LEDs may have an IQE that is approximately 80% or greater.

Such a GaN LED is described with respect to Figure 3A. In Figure 3A a GaN LED 302 is shown, according to an embodiment of the invention. In an embodiment, the p-GaN layer 310 may be formed on a substrate 307, such as a semiconductor substrate. In one implementation, the semiconductor substrate 307 may be a crystalline substrate formed using a bulk semiconductor or a semiconductor-on-insulator substructure. In one particular embodiment, the semiconductor substrate 307 may include a stack of semiconductor materials. For example, the semiconductor substrate 307 may include a silicon base layer and one or more III-V semiconductor materials grown over the silicon base layer. In one example, the p-GaN layer 310 of the GaN LED 302 may be separated from the silicon base layer 307 by one or more buffer layers (not shown). In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate 307 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

In an embodiment, the electron blocking layer 336 may be formed over the p-GaN layer 310. Embodiments include an electron blocking layer 336 that is formed with a p-doped

AlGalnN material. Particularly, the AlGalnN material may be a p-doped AlxGaylni-x-yN material where X is between approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75. In one embodiment, the p-doped AlGalnN is Alo_.2Gao_.7Ino_.1N. It is noted that indium is included in the electron blocking layer 336 to aid in providing the proper bandgap structure even though indium is typically avoided in the manufacture of portions of the LED other than in the quantum well due to the environmental impact and cost of indium.

In an embodiment, the electron blocking layer 336 may have a thickness T between approximately 10 nm and 25 nm. Decreasing the thickness T below approximately 10 nm may result in tunneling of the carriers, thereby reducing the effectiveness of the electron blocking layer. Increasing the thickness T of layer 336 above approximately 25 nm may impair the transport of electrons and holes across this layer. However, it is to be appreciated that increasing the concentration of p-type dopants may improve the transport of electrons and holes, and some embodiments may include an electron blocking layer 336 that has a thickness T above approximately 25 nm so long as the concentration of p-type dopants is also increased. While increasing the dopant concentration allows for improved conductivity, the increased dopant concentration may also decrease the bandgap of the electron blocking layer 336.

Embodiments of the invention may also include one or more quantum well layers 345 that are formed above the electron blocking layer 336. In Figure 3A, a single quantum well layer 345 is formed in the GaN LED 302. The quantum well layer 345 may be sandwiched between a first barrier layer 342 and an second barrier layer 347. The quantum well layer 345 and the barrier layers 342/347 may be typical materials used to form quantum wells in GaN LEDs. For example, the barrier layers 342/347 may be intrinsic GaN and the quantum well layer 345 may be intrinsic InGaN. In an embodiment, an n-GaN layer 320 may be formed above the second barrier layer 347.

According to an embodiment, the GaN LED 302 may have a bandgap diagram that provides improved IQE by preventing the electrons in the conduction band from flowing towards the n-GaN layer 310 while still allowing for the holes in the valence band to flow from the n- GaN layer 310 to flow towards the quantum well 345. A schematic diagram of the bandgap of the GaN LED 302 is illustrated with respect to Figure 3B.

Referring now to Figure 3B, the bandgap diagram illustrates the conduction band 370 and the valence band 380 of the GaN LED formed in Figure 3 A. The portion of the bandgap diagram that shows the region where the electron blocking layer 336 is formed is surrounded by a box 337. As shown, the conduction band 370 includes a ridge 378 that prevents electrons 372 from flowing from the quantum well region to the p-GaN layer 310. Additionally, it is to be appreciated that the ridge 378 may be approximately 20 meV or greater than the electron barrier illustrated above in Figure 1A. In some embodiments, the ridge 378 may be approximately 25 meV greater than the electron barrier layer illustrated above in Figure 1A. According to an embodiment, the valence band 380 in the electron blocking layer region 337 does not include a barrier to prevent holes from flowing into the quantum well 345. As illustrated, the valence band 380 curves down towards the quantum well 345. As illustrated, the holes 384 may flow along the curve easily without needing to tunnel or overcome any blocking ridges, such as those present in Figures IB or 2B.

In Figures 3A and 3B, a GaN LED 302 with a single quantum well 345 is shown according to an embodiment of the invention. However, additional embodiments of the invention may also include a plurality of quantum wells. A GaN LED with a plurality of quantum wells and the corresponding bandgap diagram are shown in Figures 4A and 4B.

Referring now to Figure 4A, a GaN LED 403 with a plurality of quantum well layers 445 and an electron blocking layer 436 is shown, according to an embodiment of the invention. The GaN LED 403 is substantially similar to the GaN LED 302 described above with respect to Figures 3A and 3B with the exception that a plurality of quantum wells 445 are formed. In the illustrated embodiment, three quantum wells 445 are formed, though embodiments may include any number of quantum wells. For example, some GaN LEDs 403 may include five quantum wells 445. Additional embodiments of the invention may include a GaN LED 403 that includes more than five quantum wells 445.

According to an embodiment, the GaN LED 403 with a plurality of quantum wells 445 may have a bandgap diagram that is substantially similar to the bandgap diagram for GaN LED 302 described above with respect to Figure 3B, with the exception that additional quantum well features are formed. As such, the conduction band 470 and the valence band 480 in the electron blocking layer region surrounded by box 437 may be substantially similar to the conduction band 370 and the valence band 380 in the box 337 in Figure 3B. Accordingly, the conduction band 470 includes a ridge 478 that prevents electrons 472 from flowing from the quantum well region to the p-GaN layer 410, and the valence band 480 does not include a barrier to prevent holes 484 from flowing into the quantum well 445.

Referring now to Figures 5A-5G and Figure 6, cross-sectional illustrations of a GaN LED after various fabrication operations and a process flow chart of the process for forming the GaN LED are shown, respectively, according to an embodiment of the invention. As shown in Figure 6, embodiments may include a process 690 that begins with operation 691 that includes forming the p-GaN layer 510 over a substrate 507. The resulting structure is illustrated in Figure 5A. In an embodiment, the p-GaN layer 510 may be formed with a molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or the like. In an embodiment, the p-GaN layer 510 may be doped with an implantation/diffusion process (with or without subsequent annealing) or the GaN layer may be in situ doped during the deposition of the GaN layer 510. In an embodiment, the p-type dopants may be any suitable p- type dopant for a GaN layer, such as magnesium.

Referring now to operation 692 in Figure 6 and the cross-sectional illustration in Figure 5B, embodiments of the invention may continue the process 690 by forming the electron blocking layer 536 over the p-GaN layer 510. In an embodiment the electron blocking layer 536 may be formed with processes such as, MBE, MOCVD, ALD, or the like. In an embodiment, the electron blocking layer may be a p-doped AlGalnN material. For example, the electron blocking layer 543 may be a p-doped AlxGa_YIni_x__YN material where X is between approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75. In a particular embodiment, the p- doped AlGalnN is Alo_.2Gao_.7Ino_.1N. In an embodiment electron blocking layer 536 may be doped with an implantation/diffusion process (with or without subsequent annealing) or the electron blocking layer 536 may be in situ doped during the deposition of the electron blocking layer 536. In an embodiment, the p-type dopants may be any suitable p-type dopant for an AlGalnN layer, such as magnesium. In an embodiment, the electron blocking layer 536 may be between approximately 10 nm and 25 nm thick.

Referring now to operation 693 in Figure 6 and the cross-sectional illustration in Figure 5C, embodiments of the invention may continue the process 690 by forming a first barrier layer 542 over the electron blocking layer 536. In an embodiment, the first barrier layer 542 may be an intrinsic GaN layer. In an embodiment the first barrier layer 542 may be formed with processes such as, MBE, MOCVD, ALD, or the like.

Referring now to operation 694 in Figure 6 and the cross-sectional illustration in Figure 5D, embodiments of the invention may continue the process 690 by forming a quantum well layer 545 over the first barrier layer 542. In an embodiment, the quantum well layer 545 may be an intrinsic InGaN layer. In an embodiment the quantum well layer 545 may be formed with processes such as, MBE, MOCVD, ALD, or the like.

Referring now to operation 695 in Figure 6 and the cross-sectional illustration in Figure

5E, embodiments of the invention may continue the process 690 by forming an second barrier layer 547 over the quantum well layer 545. In an embodiment, the second barrier layer 547 may be an intrinsic GaN layer. In an embodiment the second barrier layer 547 may be formed with processes such as, MBE, MOCVD, ALD, or the like.

As illustrated in Figure 6, processing operations 694 and 695 may be repeated any number of times to provide the desired number of quantum wells 545 in the GaN LED. For example, embodiments of the invention may include one quantum well layer 545, or a plurality of quantum well layers 545. For example, the GaN LED may include three, five, or more quantum well layers 545.

Referring now to operation 696 in Figure 6 and the cross-sectional illustration in Figure

5F, embodiments of the invention may continue the process 690 by forming an n-GaN layer 520 over the second barrier layer 547. In an embodiment, the n-GaN layer 520 may be formed with processes such as, MBE, MOCVD, ALD, or the like. The n-GaN layer 510 may be doped with an implantation/diffusion process (with or without subsequent annealing) or the n-GaN layer may be in situ doped during the deposition of the n-GaN layer 520. In an embodiment, the n-type dopants may be any suitable n-type dopant for a GaN layer, such as silicon.

Referring now to operation 697 in Figure 6 and the cross-sectional illustration in Figure 5G, embodiments of the invention may continue the process 690 by forming electrical contacts 588 on the p-GaN layer 510 and the n-GaN layer 520. In an embodiment, the contacts 588 may be formed after the stack of semiconductor materials is patterned to expose a portion of the p-

GaN layer 510. In an embodiment, the p-GaN layer 510 may be exposed with an etching process, such as a wet or dry etching process, as is known in the art. The contacts 588 may be formed with any suitable deposition process for depositing conductive materials, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like.

In the embodiment of the invention illustrated in Figures 5A-5G a single GaN LED is formed. However, it is to be appreciated that a plurality of GaN LEDs may be formed over a single substrate 507 in parallel with each other, as is known in many semiconductor fabrication process flows.

Figure 7 illustrates an interposer 700 that includes one or more embodiments of the invention. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die, or a display module comprising GaN LEDs that include an AlGalnN electron blocking layer, according to an embodiment of the invention. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the interposer 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700.

The interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 708 and vias 710, including but not limited to through- silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as display modules, radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 700.

Figure 8 illustrates a computing device 800 in accordance with one embodiment of the invention. The computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 800 include, but are not limited to, an integrated circuit die 802 and at least one communication chip 808. In some implementations the communication chip 808 is fabricated as part of the integrated circuit die 802. The integrated circuit die 802 may include a CPU 804 as well as on-die memory 806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM). Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 810 (e.g., DRAM), non- volatile memory 812 (e.g., ROM or flash memory), a graphics processing unit 814 (GPU), a digital signal processor 816, a crypto processor 842 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 820, an antenna 822, a display or a touchscreen display 824 (e.g., a display that includes one or more GaN LEDs with an AlGalnN electron blocking layer, formed in accordance with embodiments of the invention), a touchscreen controller 826, a battery 828 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 844, a compass 830, a motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass), a speaker 834, a camera 836, user input devices 838 (such as a keyboard, mouse, stylus, and touchpad), a mass storage device 840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth), and a flash lighting module 841.

The communications chip 808 enables wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 808. For instance, a first communication chip 808 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 808 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 804 of the computing device 800 includes one or more devices, such as an integrated circuit for controlling the GaN LEDs that include an AlGalnN electron blocking layer, according to an embodiment of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. In further embodiments, another component housed within the computing device 800 may contain one or more devices, such as integrated circuit for controlling the GaN LEDs that include an AlGaInN electron blocking layer, or an integrated circuit for executing processing operations used to form a GaN LED that includes an AlGaInN electron blocking layer, according to an embodiment of the invention.

In various embodiments, the computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: a light emitting diode (LED), comprising: a p-doped GaN layer; an electron blocking layer formed over the p-doped GaN layer, wherein the electron blocking layer is a p- doped AlGaInN layer; a first barrier layer formed over the electron blocking layer; a quantum well layer formed over the electron blocking layer; a second barrier layer formed over the quantum well layer; and an n-doped GaN layer formed over the second barrier layer.

Example 2:the LED of Example 1, wherein the p-doped AlGaInN electron blocking layer is a AlxGa_YIni_x__YN material, wherein X is between approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75.

Example 3: the LED of Example 2, wherein X is 0.2 and Y is 0.7.

Example 4: the LED of Example 1, Example 2, or Example 3 wherein the electron blocking layer has a thickness that is greater than approximately 10 nm.

Example 5: the LED of Example 1, Example 2, Example 3, or Example 4, wherein the electron blocking layer is between approximately 10 nm and approximately 25 nm. Example 6: the LED of Example 1, Example 2, Example 3, Example 4, or Example 5, wherein the first and second barrier layers are intrinsic GaN, and wherein the quantum well layer is InGaN.

Example 7: the LED of Example 1, Example 2, Example 3, Example 4, Example, 5 or Example 6, further comprising a plurality of quantum well layers, wherein each of the plurality of the quantum well layers is sandwiched between barrier layers.

Example 8: the LED of Example 7, wherein the plurality of quantum well layers includes three or five quantum well layers.

Example 9: the LED of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, or Example 8, further comprising: a first contact formed on the p-GaN layer; and a second contact formed on the n-GaN layer.

Example 10: the LED of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, wherein a bandgap diagram of the LED includes an electron blocking region in the conduction band of the electron blocking layer, and no hole blocking region is formed in the valence band of the electron blocking layer.

Example 11: the LED of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, or Example 10, wherein the p-GaN layer is formed above the underlying substrate layer.

Example 12: the LED of Example 11, wherein the underlying substrate is a silicon substrate.

Example 13: the LED of Example 11, wherein the underlying substrate is separated from the p-GaN layer by one or more buffer layers.

Example 14: a method of forming a light emitting diode (LED), comprising: forming a p- doped GaN layer; forming an electron blocking layer over the p-doped GaN layer, wherein the electron blocking layer is a p-doped AlxGa_YIni_x__YN material, wherein X is between

approximately 0.15 and 0.25, and wherein Y is between 0.65 and 0.75; forming a first barrier layer over the electron blocking layer; forming a quantum well layer over the barrier layer; forming a second barrier layer over the quantum well layer; and forming an n-doped GaN over the second barrier layer.

Example 15: the method of Example 14, wherein the n-doped GaN layer and the p-doped

GaN layer are doped in situ while the layers are formed.

Example 16: the method of Example 14, wherein the n-doped GaN layer and the p-doped GaN layer are doped with a diffusion or implantation process.

Example 17: the method of Example 14, Example 15, or Example 16, wherein each of the layers are formed with molecular beam epitaxy, metal-organic chemical vapor deposition, or atomic layer deposition.

Example 18: the method of Example 14, Example 15, Example 16, or Example 17, wherein X is 0.2, and wherein Y is 0.7.

Example 19: the method of Example 14, Example 15, Example 16, Example 17, or

Example 18, further comprising: patterning the stack of layers, wherein patterning the stack of layers exposes a portion of the p-doped GaN layer.

Example 20: the method of Example 19, further comprising: forming a first contact on the n-doped GaN layer and forming a second contact on the p-doped GaN layer.

Example 21: the method of Example 14, Example 15, Example 16, Example 17, Example

18, Example 19, or Example 20, further comprising: forming a plurality of quantum well layers, wherein each quantum well layer is formed between barrier layers.

Example 22: the method of Example 21, wherein the plurality of quantum well layers includes three or five quantum well layers.

Example 23: a GaN light emitting diode (LED), comprising: a p-doped GaN layer; an electron blocking layer formed over the p-doped GaN layer, wherein the electron blocking layer is an AlxGa_YIni_x__YN material, wherein X is between approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75; a first barrier layer formed over the electron blocking layer, wherein the first barrier layer is intrinsic GaN; a quantum well layer formed over the electron blocking layer, wherein the quantum well layer is intrinsic InGaN; a second barrier layer formed over the quantum well layer, wherein the second barrier layer is intrinsic GaN; and an n- doped GaN layer formed over the second barrier layer, wherein a bandgap diagram of the LED includes an electron blocking region in the conduction band of the electron blocking layer, and no hole blocking region is formed in the valence band of the electron blocking layer.

Example 24: the LED of Example 23, wherein the electron blocking layer is between approximately 10 nm and approximately 25 nm.

Example 25: the LED of Example 23 or Example 24, further comprising a plurality of quantum well layers, wherein each of the plurality of the quantum well layers is sandwiched between barrier layers.

Claims

CLAIMS What is claimed is:

1. A light emitting diode (LED), comprising:

a p-doped GaN layer;

an electron blocking layer formed over the p-doped GaN layer, wherein the electron blocking layer is a p-doped AlGalnN layer;

a first barrier layer formed over the electron blocking layer;

a quantum well layer formed over the electron blocking layer; a second barrier layer formed over the quantum well layer; and an n-doped GaN layer formed over the second barrier layer.

2. The LED of claim 1, wherein the p-doped AlGalnN electron blocking layer is a

AlxGaylni-x-yN material, wherein X is between approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75.

3. The LED of claim 2, wherein X is 0.2 and Y is 0.7.

4. The LED of claim 1, wherein the electron blocking layer has a thickness that is greater than approximately 10 nm.

5. The LED of claim 4, wherein the electron blocking layer is between approximately 10 nm and approximately 25 nm.

6. The LED of claim 1, wherein the first and second barrier layers are intrinsic GaN, and wherein the quantum well layer is InGaN.

7. The LED of claim 1, further comprising a plurality of quantum well layers, wherein each of the plurality of the quantum well layers is sandwiched between barrier layers.

8. The LED of claim 7, wherein the plurality of quantum well layers includes three or five quantum well layers.

9. The LED of claim 1, further comprising:

a first contact formed on the p-GaN layer; and

a second contact formed on the n-GaN layer.

10. The LED of claim 1, wherein a bandgap diagram of the LED includes an electron

blocking region in the conduction band of the electron blocking layer, and no hole blocking region is formed in the valence band of the electron blocking layer.

11. The LED of claim 1, wherein the p-GaN layer is formed above the underlying substrate layer.

12. The LED of claim 11, wherein the underlying substrate is a silicon substrate.

13. The LED of claim 11, wherein the underlying substrate is separated from the p-GaN layer by one or more buffer layers.

14. A method of forming a light emitting diode (LED), comprising:

forming a p-doped GaN layer;

forming an electron blocking layer over the p-doped GaN layer, wherein the electron blocking layer is a p-doped AlxGaylni-x-yN material, wherein X is between approximately 0.15 and 0.25, and wherein Y is between 0.65 and 0.75;

forming a first barrier layer over the electron blocking layer;

forming a quantum well layer over the barrier layer;

forming a second barrier layer over the quantum well layer; and

forming an n-doped GaN over the second barrier layer.

15. The method of claim 14, wherein the n-doped GaN layer and the p-doped GaN layer are doped in situ while the layers are formed.

16. The method of claim 14, wherein the n-doped GaN layer and the p-doped GaN layer are doped with a diffusion or implantation process.

17. The method of claim 14, wherein each of the layers are formed with molecular beam epitaxy, metal-organic chemical vapor deposition, or atomic layer deposition.

18. The method of claim 14, wherein X is 0.2, and wherein Y is 0.7.

19. The method of claim 14, further comprising:

patterning the stack of layers, wherein patterning the stack of layers exposes a portion of the p-doped GaN layer.

20. The method of claim 19, further comprising:

forming a first contact on the n-doped GaN layer and forming a second contact on the p-doped GaN layer.

21. The method of claim 14, further comprising: forming a plurality of quantum well layers, wherein each quantum well layer is formed between barrier layers.

The method of claim 21, wherein the plurality of quantum well layers includes three or five quantum well layers.

A GaN light emitting diode (LED), comprising:

a p-doped GaN layer;

an electron blocking layer formed over the p-doped GaN layer, wherein the electron blocking layer is an AlxGaylni-x-yN material, wherein X is between

approximately 0.15 and 0.25, and Y is between approximately 0.65 and 0.75;

a first barrier layer formed over the electron blocking layer, wherein the first barrier layer is intrinsic GaN;

a quantum well layer formed over the electron blocking layer, wherein the quantum well layer is intrinsic InGaN;

a second barrier layer formed over the quantum well layer, wherein the second barrier layer is intrinsic GaN; and

an n-doped GaN layer formed over the second barrier layer, wherein a bandgap diagram of the LED includes an electron blocking region in the conduction band of the electron blocking layer, and no hole blocking region is formed in the valence band of the electron blocking layer.

The LED of claim 23, wherein the electron blocking layer is between approximately 10 nm and approximately 25 nm.

The LED of claim 23, further comprising a plurality of quantum well layers, wherein each of the plurality of the quantum well layers is sandwiched between barrier layers.