WO2018063209A1

WO2018063209A1 - Resistive random access memory cell

Info

Publication number: WO2018063209A1
Application number: PCT/US2016/054305
Authority: WO
Inventors: Prashant Majhi; Ravi Pillarisetty; Elijah V. KARPOV; Niloy Mukherjee; Jame S. CLARKE
Original assignee: Intel Corporation
Priority date: 2016-09-29
Filing date: 2016-09-29
Publication date: 2018-04-05

Abstract

Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source, where the source includes a source junction, a gate, and a drain, where the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration. In an example, during the first configuration the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.

Description

RESISTIVE RANDOM ACCESS MEMORY CELL

Technical Field

[0001] The present disclosure relates generally to the field of memory cells, and more particularly, to resistive random access memory cells.

Background

[0002] Most, if not all, logic devices require some type of random access memory. Resistive random access memory (RRAM or ReRAM) is a type of non-volatile (NV) random- access computer memory that works by changing the resistance across a dielectric solid-state material. RRAM can be similar to a memristor which is a hypothetical, non-linear, passive two- terminal electrical component relating electric charge and magnetic flux linkage. The memristor's electrical resistance is not constant but depends on the history of current that had previously flowed through the device. Its present resistance depends on how much electric charge flowed in what direction it in the past. A RRAM cell is a device that remembers its history so when the electric power supply is turned off, the RRAM cell remembers its most recent resistance until it is turned on again. Using this property, the RRAM cell can be used as a memory cell or memory array for electronic devices. The cell transistors of the RRAM are usually engineered to a high Vt to be reliable at a high bias. However, the fixed Vt of the transistor results in a low drive strength.

Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIGURE 1 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0005] FIGURE 2 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0006] FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0007] FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0008] FIGURE 5A is a simplified orthogonal view diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure; [0009] FIGURE 5B is a simplified gate cut view diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0010] FIGURE 5C is a simplified fin cut view diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0011] FIGURE 6 is an interposer implementing one or more of the embodiments disclosed herein; and

[0012] FIGURE 7 is a computing device built in accordance with an embodiment disclosed herein.

[0013] The figures of the drawings are not necessarily drawn to scale, as their dimensions can be varied considerably without departing from the scope of the present disclosure.

Detailed Description

[0014] The following detailed description sets forth example embodiments of apparatuses, methods, and systems relating to a communication system for device pairing in a local network. Features such as structure(s), function(s), and/or characteristic(s), for example, are described with reference to one embodiment as a matter of convenience; various embodiments may be implemented with any suitable one or more of the described features.

[0015] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the embodiments disclosed herein may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0016] Disclosed herein are substrates, assemblies, and techniques for enabling a device that includes one or more resistive random access memory cells. In some embodiments, the device may include a source, a gate, and a drain. The source, the gate, and the drain can be on top of a support substrate such as a semiconductor substrate. In an implementation, the substrate may be a non-silicon flexible substrate.

[0017] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the embodiments disclosed herein, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0018] The terms "over," "under," "below," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0019] Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon- on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other

combinations of group lll-V or group IV materials. In other examples, the substrate may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the embodiments disclosed herein.

[0020] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. [0021] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0022] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "package" and an "IC package" are synonymous. As used herein, the terms "chip" and "die" may be used interchangeably.

[0023] FIGURE 1 is a simplified block diagram of an electronic device 100 that includes one or more resistive random access memory (RRAM) cells and arrays in accordance with an embodiment of the present disclosure. Electronic device 100 can be any electronic device that includes memory (e.g., computer, smartphone, laptop, desktop, Internet-of-Things device, vehicle, handheld electronic device, personal digital assistant, wearable, etc.). Electronic device 100 can include one or more electronic elements 102a-102d. Each electronic element 102a- 102d can include a transistor 104 and/or one or more transistor arrays 106. Each transistor array 106 can be a systematic arrangement of a plurality of transistors 104, (e.g., in rows and columns). Each transistor 104 can include a RRAM cell. Transistor 104 can be a transistor or an electronic switch that can be either in an "on" or "off" state and the term "transistor" includes a bipolar junction transistor (BJT), filed effect transistor (FET), finFET, junction gate FET (JFET), insulated gate FET (IGFET), metal-oxide-semiconductor field-effect transistors (MOSFET), n- channel field effect transistor (NFET) insulated-gate bipolar transistor, or other similar transistor that can be configured to perform the functions, features, and operations disclosed herein.

[0024] RRAM (or ReRAM) is a type of non-volatile (NV) random-access computer memory that works by changing the resistance across a dielectric solid-state material. The cell transistors of the RRAM are typically engineered to a high Vt to be reliable at a high bias.

However, the fixed Vt of the transistor results in a low drive strength in either SET or RESET operations of the RRAM due to the source follower condition in one of the polarities. The low drive strength can limit the switching currents used to operate the RRAM and result in low reliability of the RRAM cell and RRAM cell array.

[0025] Transistor 104 can be configured to resolve these issues (and others). For example, transistor 104 can be configured such that the drain of the transistor that is connected to the RRAM enables the drain to bulk resistance to be significantly lower (compared to a conventional transistor) during a RESET operation of transistor 104. For example, transistor 104 can be configured to provide, a one transistor, one resistor (1T1R) operation during SET operations and a one diode, one resistive switching device (1D1R) operation during RESET operations. This allows the source follower issue related to high switching voltages and/or low switching currents to be circumvented.

[0026] More specifically, the drain/bulk region of the transistor can be configured to significant reduce the junction resistance when forward biased. For example, when using an NFET transistor for 1T1R operation, the current flows through the transistor channel during positive bias on the drain or SET operation. During the SET operation, the drain/bulk junction is in reverse bias and as a result has a high first junction resistance. However, when the transistor bias reverses for RESET, the drain/bulk junction is under positive bias. Transistor 104 can be configured such that the drain/bulk junction resistance can be significantly reduced to a low second junction resistance and allow the current to flow through the drain/bulk junction during RESET (i.e., a 1D1R operation in RESET). For example, the drain/bulk junction can function as a diode with highly non-linear characteristics such that the resistance changes with the bias condition. In a specific illustrative example, the drain/bulk junction can be configured to allow about lOOuA current at relatively a low bias (e.g., about 0.2V) and allow for low voltage switching for the memory cell. This means the drain/bulk junction resistance can be in the range of about 1 to about 4K ohm for low second junction resistance and greater than 20Kohm for high first junction resistance.

[0027] This circumvents the high terminal voltage (Vt) related source follower issue for the 1T1R and can improves performance and reliability of RRAM memory. The drain/bulk junction of transistor 104 can be configured to tune the resistance of the drain/bulk junction with a different composition in the Si-Ge-C ternary compared to the rest of the transistor substrate. In an example, a conventional transistor can be created (e.g., by a currently standard process). The conventional transistor can be patterned and the drain region of the transistor, where the drain region of the transistor that will be coupled to the RRAM (e.g., see drain junction 124 in FIGURE 2) can be left exposed. The drain region of the convention transistor can be etched away and material (e.g., silicon germanium (SiGe) family, indium (In) family, gallium (Ga) family, arsenic (As) family, etc.) can be deposited to create the drain/bulk junction with a different composition in the Si-Ge-C ternary compared to the rest of the transistor substrate. By doing so, the drain/bulk junction resistance during RESET can be minimized.

[0028] Turning to FIGURE 2, FIGURE 2 illustrates one embodiment of transistor 104. Transistor 104 can include bit line 108, RRAM 110, a first connection 112, a second connection 114, a source 116, a gate 118, a substrate 120, a source junction 122, and drain junction 124. Bit line 108 may be a top electrode or bit line and can include a first metal 126 and a second metal 128. RRAM 110 can be located between first metal 126 and second metal 128. First connection 112 and second connection 114 can be metal connections for transistor 104. Source junction 122 is the area or region interface where source 116 is coupled or connected to insulator 130 (e.g., the interface between source 116 and insulator 130). Drain junction 124 is the area or region interface where bit line 112 is coupled or connected to insulator 130 (e.g., the interface between bit line 112 and insulator 130). Bit line 122 can include or be coupled to RRAM 110.

[0029] More specifically, first connection 112 and second connection 114 can be part of a metal-2 or metal-3 extended connection. Source 116 and gate 118 may each be configured as a word line. Substrate 120 can be a silicon base substrate. SET current 148a is flowing in one direction from on to off during a SET operation and RESET current 148b is flowing from off to on during a RESET operation. Transistor 104 can be configured to allow access to RRAM 110 and change the resistance of RRAM 110. For example, transistor 104 can be configured to program RRAM 110, deselect or not disturb RRAM 110, read RRAM 110, etc. Drain junction 124 can include SiGe, In, Ga, As, etc. and different types of material may be used for different circumstances and to tune the resistance of drain junction 124.

[0030] In a typical transistor, the stack is asymmetric. This means that the RRAM is connected to one side of the transistor (e.g., either the source side or the drain side). This asymmetry causes a difference in the effective biasing of the RRAM and causes a voltage drop during programing of the RRAM which leads to source follower issues, (explained in more detail below).

[0031] To help resolve this issue, transistor 104 can be configured to be inherently symmetric. More specifically, in transistor 104, drain junction 124 (i.e., the drain region that connects to RRAM 110) can be configured to act as a diode (ID) during one polarity and operate as a transistor (IT) during the other polarity. This corrects the reduced voltage drop during programing from the source degeneration and allows the integrated cell (transistor + RRAM) characteristic to become more symmetric. The symmetry allows the drain/bulk junction resistance (drain junction 124 resistance) during RESET to be minimized and the source follower issue related to high switching voltages and/or low switching currents can be circumvented.

[0032] During the SET operation, drain junction 124 is in reverse bias and as a result, has a relatively high first junction resistance. However, when the bias of transistor 104 reverses for RESET, drain junction 124 is under positive bias. Transistor 104 can be configured such that the resistance of drain junction 124 can be significantly reduced to a relatively low second junction resistance and allow the current to flow through the drain/bulk junction during RESET (i.e., a 1D1R operation in RESET). For example, drain junction 124 can function as a diode with highly non-linear characteristics such that the resistance changes with the bias condition of transistor 104. In a specific illustrative example, drain junction 124 can be configured to allow about lOOuA current at a relatively low bias (e.g., about 0.2V) and allow for low voltage switching for RRAM 110. This means that the resistance of drain junction 124 can be in the range of about 1 to about 4K ohm for a relatively low second junction resistance when transistor 104 is in a positive bias (e.g., drain junction 124 is under a positive bias) and greater than 20Kohm for a relatively high first junction resistance when transistor 104 is in a negative or reverse bias (e.g., drain junction is under a negative or reverse bias).

[0033] In one implementation, RRAM 110 can acquire its resistance by applying a bias running a current through bit line 108 and RRAM 110. Typically, a bi-polar RRAM is used where a positive bias turns on the RRAM (i.e., a SET) and a negative bias turns off the RRAM (i.e., a RESET). To bias transistor 104, an electrical connection can be coupled to bit line 108, source 116, and gate 118.

[0034] In order to bias transistor 104 and SET RRAM 110, or turn RRAM 110 from an "off state" to an "on state," a positive bias needs to be applied to RRAM 110. To achieve this, a positive voltage on bit line 108 can be biased positively with a high voltage, in the case of an NMOS transistor, gate 118 has to be biased positive and source 116 does not see any bias or would be biased to zero. In this example, the gate to source voltage (Vgs) would turn on transistor 104 based on the difference between the voltages on source 116 and gate 118. In this biasing condition, RRAM 110 does not interfere and the voltage to turn on transistor 104 is the voltage on source 116 and gate 118. Once transistor 104 is turned on, its resistance is lowered significantly and most of the voltage applied to bit line 108 will be used by RRAM 110. By enabling transistor 104 to turn on with a low gate to source voltage (Vgs), the configuration of transistor 104 helps ensure that RRAM 110 sees most of the applied voltage to successfully program RRAM 110 or cause RRAM 110 to change its resistance.

[0035] To turn the resistance off from a low resistance to a high resistance, different biases can be applied to bit line 108, source 116, and gate 118. For example, source 116 would still be a positive bias. Gate 118, would be biased to a positive voltage and bit line 108 would be biased to zero.

[0036] In a conventional or traditional transistor, this switches the current flow direction in the transistor and one problem or issue is that, for the transistor to turn on, the voltage from the gate to the source (Vgs) is typically greater than the threshold voltage of the transistor. The Vgs voltage is influenced by the voltage at the source, the voltage at the gate and the effective source voltage which is now on the bit line. An issue arises because the RRAM is in between the source and the gate and so the RRAM would significantly eat up the budget for the voltage to turn on the transistor which creates a source depletion or source following issue. This results in the need to apply a much higher voltage on the gate just to be able to turn on the transistor. The transistor needs to be turned on because once the transistor is turned on, it ensures that all the applied voltage would fall on the RRAM to ensure that the RRAM can successfully make the transition to the off state. In a traditional transistor, since the RRAM is always connected to one side, it makes it asymmetric in terms or ability to provide or apply high voltages to the RRAM in a bipolar fashion. If an NMOS transistor is used, a high voltage and positive polarity can be provided but a high voltage cannot be applied on negative polarity. If a PMOS transistor is used, a high voltage on the negative polarity can be provided but a high voltage on the positive polarity cannot be provided because of the source follower

configuration. As a result, a much higher voltage must be provided to effectively account for the voltage drop on the transistor as well as the RRAM. This causes the operating voltage of the transistor to be significant from an operating and power standpoint.

[0037] Transistor 104 can be configured to circumvent the source follower problem. For example, for the positive bias programing from a high resistance to a low resistance, a bias can be applied to gate 118 to turn it on and a zero bias can be applied to source 116. This provides the gate Vgs as the voltage between gate 118 to source 116 and there is no RRAM 110 between between gate 118 to source 116. As a result, there are not source follower problems as with current transistors and the bias is on bit line 108. Effectively, transistor 104 can be turned on with a low resistance and all the bias that is applied is on bit line 108 and RRAM 110. This allows for a successful transition from high resistance to low resistance using a relatively low voltage.

[0038] In the reverse polarity side, when the reverse polarity is applied and the transistor is switched to a positive bias on source 116, a zero bias on bit line 108, and a positive bias on gate 118, drain junction 124 (e.g., the drain to bulk PN junction) can effectively operate the current going from drain junction 124 (e.g., the PN junction diode) through RRAM 110 rather than going through gate 118. As a result, the voltage drop on drain junction 124 is much smaller than a conventional transistor and the voltage can be applied to RRAM 110 and allow for a successful transaction. In a specific example, drain junction 124 acts similar to the PN junction of a diode.

[0039] Turning to FIGURE 3, FIGURE 3 illustrates one embodiment of transistor 104. In a specific implementation, transistor 104a can include gate 118a. Gate 118a can include a gate metal 130 and dielectric 132. Gate metal 130 may be a gate electrode and dielectric 132 may be a gate oxide. Dielectric 132 can be configured to help ensure that there is no current, or that an applied a current or bias on gate 118a is allowed to open a channel between source junction 122 and drain junction 124. When the channel is opened, a SET current 148a (illustrated in FIGURE 2) can flow through source junction 122 and drain junction 124. When the bias is removed from gate 118a the channel is removed and SET current 148a ceases to flow. As a result, the gate for the contact (e.g., SET current 148a) is effective spread between source junction 122 and drain junction 124. Drain junction 124 can be insulating to help to ensure there is not leakage from source 116 into substrate 120.

[0040] Turning to FIGURE 4, FIGURE 4 illustrates illustrates one embodiment of transistor 104. In a specific implementation, substrate 120 can include a first silicon

composition layer 134 and a second silicon composition layer 136. First silicon composition layer 134 and second silicon composition layer 136 can allow transistor 104b to function as a diode during a RESET operation or when transitioning transition 104b from on too off.

[0041] Turning to FIGURES 5A-5C, FIGURES 5A-5C illustrate one embodiment of transistor 104. Transistor 104c can include a gate 138, a drain 140, a source 142, an oxide layer 144, and a silicon substrate 146. Gate 138 can operate similar to gate 118. Drain 140 can operate similar to bit line 108, and source 142 can operate similar to source 116.

[0042] The semiconductor substrate for substrate 120, first silicon composition layer 134, second silicon composition layer 136, and silicon substrate 146 (and any additional layers) may be formed using alternate materials, which may or may not be combined with silicon. This includes, but is not limited to, silicon, silicon germanium, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. In other examples, the substrate of any layer may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates.

[0043] In an example, a plurality of electrical components can include one or more transistors 104 and/or one or more arrays 106. In addition, a plurality of transistors, such as MOSFET or simply MOS transistors), can include one or more transistors 104, may be fabricated on the substrate. In various embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the

implementations described herein may illustrate only planar transistors, it should be noted that various embodiments may also be carried out using nonplanar transistors.

[0044] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0045] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0046] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

[0047] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0048] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0049] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group l l l-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0050] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0051] Turning to FIGURE 6, FIGURE 6 illustrates an interposer 600 that can include or interact with one or more embodiments disclosed herein. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

[0052] The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

[0053] The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes,

transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600. In accordance with various embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

[0054] Turning to FIGURE 7, FIGURE 7 illustrates a computing device 700 in accordance with various embodiments. The computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on- a-chip (SoC) die. The components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communications logic unit 708. In some implementations the communications logic unit 708 is fabricated within the integrated circuit die 702 while in other implementations the communications logic unit 708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 702. The integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).

[0055] Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), nonvolatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (a specialized processor that executes

cryptographic algorithms within hardware), a chipset 720, an antenna 722, a display or a touchscreen display 724, a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0056] The communications logic unit 708 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communications logic units 708. For instance, a first communications logic unit 708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communications logic unit 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0057] The processor 704 of the computing device 700 can communicate with one or more devices that are formed in accordance with various embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0058] The communications logic unit 708 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein. In further embodiments, another component housed within the computing device 700 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.

[0059] In various embodiments, the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

[0060] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the scope of the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the embodiments disclosed herein are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

OTHER NOTES AND EXAMPLES.

[0061] Example 1 is an apparatus including a substrate, where the substrate includes a first composition of material, a source junction, where the source junction includes a second composition of material, a gate, and a drain junction. The drain junction includes a third composition of material, where the third composition of material is different than the first composition of material and the second composition of material.

[0062] In Example 2, the subject matter of Example 1 can optionally include where the drain junction material is configured to tune the resistance of the drain junction.

[0063] In Example 3, the subject matter of any one of Examples 1-2 can optionally include where the drain junction includes silicon germanium (SiGe), indium (In), gallium (Ga), or arsenic (As).

[0064] In Example 4, the subject matter of any one of Examples 1-3 can optionally include where the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration.

[0065] In Example 5, the subject matter of any one of Examples 1-4 can optionally include where the first configuration is a SET operation.

[0066] In Example 6, the subject matter of any one of Examples 1-5 can optionally include where the second configuration is a RESET operation.

[0067] In Example 7, the subject matter of any one of Examples 1-6 can optionally include where during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, where the first junction resistance is higher than the second junction resistance. [0068] In Example 8, the subject matter of any one of Examples 1-7 can optionally include a drain, where the drain includes the drain junction and is coupled to resistive random access memory (RRAM.

[0069] In Example 9, a method can include causing a transistor to operate in a first configuration, where the transistor includes a source junction, a gate, and a drain junction, where in the first configuration the drain junction is configured to operate as a one transistor, one resistor (1T1R) and causing the transistor to switch from the first configuration to a second configuration, where in the second configuration, the drain junction is configured to operate as a one diode, one resistor (1D1R).

[0070] In Example 10, the subject matter of Example 9 can optionally include where the drain junction is configured to tune the resistance of the drain junction.

[0071] In Example 11, the subject matter of any one of Examples 9-10 can optionally include where the drain is coupled to resistive random access memory (RRAM).

[0072] In Example 12, the subject matter of any one of Examples 9-11 can optionally include where the first configuration is a SET operation.

[0073] In Example 13, the subject matter of any one of Examples 9-12 can optionally include where where the second configuration is a RESET operation.

[0074] In Example 14, the subject matter of any one of Examples 9-13 can optionally include where during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, where the first junction resistance is higher than the second junction resistance.

[0075] In Example 15, the subject matter of any one of Examples 9-14 can optionally include where the transistor further includes a drain and the drain is a bit line.

[0076] Example 16 is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor. The memory can include a source, a gate, and a drain, where the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration. [0077] Example 17 the subject matter of Example 16 can optionally include where the drain is a bit line.

[0078] In Example 18, the subject matter of Example 16-17 can optionally include where the memory further includes a substrate, where the substrate includes a first composition of material, the source includes a source junction and the source junction includes a second composition of material, and the drain junction includes a third composition of material, where the third composition of material is different than the first composition of material and the second composition of material.

[0079] In Example 19, the subject matter of any one of the Examples 16-18 can optionally include where the first configuration is a SET operation.

[0080] In Example 20, the subject matter of any one of the Examples 16-19 can optionally include where the second configuration is a RESET operation.

[0081] In Example 21, the subject matter of any one of the Examples 16-20 can optionally include where during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, where the first junction resistance is higher than the second junction resistance.

[0082] Example 22 is an integrated circuit (IC) assembly including a substrate, a source on top of the substrate, a gate on top of the substrate, and a drain on top of the substrate, where the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration.

[0083] In Example 23, the subject matter of Example 22 can optionally include where the substrate includes a first composition of material, the source includes a source junction and the source junction includes a second composition of material, and the drain junction includes a third composition of material, where the third composition of material is different than the first composition of material and the second composition of material.

[0084] In Example 24, the subject matter of any one of the Examples 22-23 can optionally include where the drain is coupled to resistive random access memory (RRAM).

[0085] In Example 25, the subject matter of any one of the Examples 22-24 can optionally include where during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, where the first junction resistance is higher than the second junction resistance.

Claims

1. An apparatus comprising:

a substrate, wherein the substrate includes a first composition of material;

a source junction, wherein the source junction includes a second composition of material;

a gate; and

a drain junction, wherein the drain junction includes a third composition of material, wherein the third composition of material is different than the first composition of material and the second composition of material.

2. The apparatus of Claim 1, wherein the drain junction material is configured to tune the resistance of the drain junction.

3. The apparatus of Claim 2, wherein the drain junction includes silicon germanium (SiGe), indium (In), gallium (Ga), or arsenic (As).

4. The apparatus of any one of Claims 1-3, wherein the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration.

5. The apparatus of Claim 4, wherein the first configuration is a SET operation.

6. The apparatus of Claim 4, wherein the second configuration is a RESET operation.

7. The apparatus of Claim 4, wherein during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second

configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.

8. The apparatus of any one of Claims 1-3, further comprising:

a drain, wherein the drain includes the drain junction and is coupled to resistive random access memory (RRAM).

9. A method comprising:

causing a transistor to operate in a first configuration, wherein the transistor includes: a source junction;

a gate; and

a drain junction, wherein in the first configuration the drain junction is configured to operate as a one transistor, one resistor (1T1R); and causing the transistor to switch from the first configuration to a second configuration, wherein in the second configuration, the drain junction is configured to operate as a one diode, one resistor (1D1R).

10. The method of Claim 9, wherein the drain junction is configured to tune the resistance of the drain junction.

11. The method of Claim 9, wherein the transistor further includes a drain and the drain is coupled to resistive random access memory (RRAM).

12. The method of any one of Claims 9-11, wherein the first configuration is a SET operation.

13. The method of any one of Claims 9-11, wherein the second configuration is a RESET operation.

14. The method of any one of Claims 9-11, wherein during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.

15. The method of any one of Claims 9-11, wherein the transistor further includes a drain and the drain is a bit line.

16. A computing device comprising:

a processor mounted on a substrate;

a communications logic unit within the processor;

a memory within the processor;

a graphics processing unit within the computing device;

an antenna within the computing device;

a display on the computing device;

a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor;

wherein the memory includes:

a source;

a gate; and a drain, wherein the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration.

17. The computing device of Claim 16, wherein the drain is a bit line.

18. The computing device of Claim 16, wherein the memory further includes:

a substrate, wherein the substrate includes a first composition of material, the source includes a source junction and the source junction includes a second composition of material, and the drain junction includes a third composition of material, wherein the third composition of material is different than the first composition of material and the second composition of material.

19. The computing device of any one of Claims 16-18, wherein the first configuration is a SET operation.

20. The computing device of any one of Claims 16-18, wherein the second configuration is a RESET operation.

21. The computing device of any one of Claims 16-18, wherein during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.

22. An integrated circuit (IC) assembly, comprising:

a substrate;

a source on top of the substrate;

a gate on top of the substrate; and

a drain on top of the substrate, wherein the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration.

23. The IC assembly of Claim 22, wherein the substrate includes a first composition of material, the source includes a source junction and the source junction includes a second composition of material, and the drain junction includes a third composition of material, wherein the third composition of material is different than the first composition of material and the second composition of material.

24. The IC assembly of Claim 22, wherein the drain is coupled to resistive random access memory (RRAM).

25. The IC assembly of any one of Claims 22-24, wherein during the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.