WO2018059134A1 - Service clock pass-through system in optical transport network - Google Patents

Service clock pass-through system in optical transport network Download PDF

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Publication number
WO2018059134A1
WO2018059134A1 PCT/CN2017/096769 CN2017096769W WO2018059134A1 WO 2018059134 A1 WO2018059134 A1 WO 2018059134A1 CN 2017096769 W CN2017096769 W CN 2017096769W WO 2018059134 A1 WO2018059134 A1 WO 2018059134A1
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Prior art keywords
adjustment
value
module
frequency
cache module
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PCT/CN2017/096769
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French (fr)
Chinese (zh)
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欧斯思
雷张伟
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华为技术有限公司
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Publication of WO2018059134A1 publication Critical patent/WO2018059134A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present application relates to the field of optical transport network technologies, and in particular, to a service clock transparent transmission system in an optical transport network.
  • OTN Optical Transport Network
  • a clock chip is usually additionally disposed outside the service chip to detect the data writing speed of the buffer in the service chip by using the clock chip, and adjust the data reading according to the data writing speed of the buffer. The speed is taken so that the data writing speed and the data reading speed of the buffer are in a balanced state, so that the normal operation of the buffer and the transparent transmission of the service clock are ensured, resulting in a large volume of the existing service clock transparent transmission system, and the cost is relatively high. high.
  • the embodiment of the present application provides a service clock transparent transmission system in an optical transmission network.
  • the service clock transparent transmission system does not need to additionally set a clock chip outside the service chip, and has a small volume and a low cost.
  • the embodiment of the present application provides the following technical solutions:
  • the application provides a service clock transparent transmission system in a transport network, where the system includes at least one service clock transparent transmission unit, and the service clock transparent transmission unit includes:
  • a cache module for buffering input business data
  • a generating module configured to acquire a current watermark value of the cache module, and generate a frequency adjustment signal according to a current watermark value of the cache module
  • phase locked loop for multiplying a local clock signal received by the same to generate a reference clock signal
  • a parallel conversion module configured to read service data in the cache module
  • An adjustment module configured to adjust the reference clock signal according to the frequency adjustment signal, generate a frequency control signal, and control a speed at which the parallel-to-serial conversion module reads data from the cache module, so that the data of the cache module The read speed is balanced with the data write speed.
  • the service clock transparent transmission system in the transmission network provided by the application does not need to additionally set a clock chip, and has a small volume and a low cost. Moreover, since the signal transmission frequency outside the chip is low, and the signal transmission frequency inside the chip is high, when the clock chip is additionally disposed outside the service chip, the reference clock signal sent by the clock chip to the service chip is before the output. A phase-locked loop is required for signal stabilization, and a phase-locked loop is required for frequency multiplication after being sent to the service chip. However, the service clock transparent transmission system in the optical transport network provided in this embodiment does not need to be additionally set.
  • the clock chip only needs one phase-locked loop in the whole working process, thereby further simplifying the structure of the service clock transparent transmission system in the optical transmission network, and reducing the service clock transparent transmission system in the optical transmission network.
  • the volume reduces the cost of the service clock transparent transmission system in the optical transport network.
  • the system includes multiple service clock transparent transmission units, and the service clock transparent transmission unit has a one-to-one correspondence with the number of data flows received by the service clock transparent transmission system, so as to improve the application range and application of the system. Sex.
  • the cache module is a first in first out memory.
  • the generating module is configured to: when generating a frequency adjustment signal according to a current watermark value of the cache module, specifically:
  • the generating module includes:
  • An obtaining unit configured to acquire a current watermark value of the cache module, and calculate a difference between a current watermark value of the cache module and a preset watermark value
  • a first adjusting unit configured to obtain a first adjustment value by multiplying a difference between a current watermark value of the cache module and a preset waterline value by a watermark adjustment factor
  • a second adjusting unit configured to use a difference between a current watermark value of the cache module and a preset watermark value, and a current watermark value and a preset of the cache module in a previous adjustment process
  • the difference between the water line values is obtained, the adjustment difference value is obtained, and the adjustment difference value is multiplied by the frequency offset adjustment factor to obtain a second adjustment value
  • a third adjusting unit configured to sum the first adjustment value and the second adjustment value to obtain a third adjustment value, and the third adjustment value is divided by a preset parameter to obtain Frequency adjustment signal;
  • the frequency adjustment signal when the third adjustment value is greater than zero, the frequency adjustment signal is a first frequency adjustment signal, and when the third adjustment value is less than zero, the frequency adjustment signal is a second frequency adjustment signal.
  • the generating module acquires a frequency of the current watermark value of the cache module to be 1 Khz, so as to ensure that the data writing speed and the data reading speed of the cache module are balanced, The frequency of reading the current watermark value of the cache module is reduced, thereby reducing the power consumption of the service clock transparent transmission system in the optical transport network.
  • the adjusting module is configured to increase a frequency of the reference clock signal according to the first frequency adjustment signal, generate a first frequency control signal, and improve the parallel-to-serial conversion module from the cache module. Reading a speed of the data, and for reducing a frequency of the reference clock signal according to the second frequency adjustment signal, generating a second frequency control signal, and reducing the parallel data conversion module to read data from the cache module speed.
  • the adjustment module adjusts the frequency of the reference clock signal by adjusting the phase of the reference clock signal to be suitable for adjustment of a smaller frequency offset.
  • the adjusting module is configured to sum the current frequency adjustment signal and the previous frequency adjustment signal, and generate And forming a final frequency adjustment signal, and adjusting a phase of the reference clock signal according to the final frequency adjustment signal to generate a frequency control signal, and controlling a speed at which the parallel-to-serial conversion module reads data from the cache module.
  • FIG. 1 is a schematic structural diagram of a service clock transparent transmission system in an optical transport network according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a specific working process of the generating module and the adjusting module in a service clock transparent transmission system in an optical transport network according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a phase of the reference clock signal when the adjustment module periodically slides 1/N cycles in a service clock transparent transmission system in an optical transport network according to an embodiment of the present disclosure.
  • the embodiment of the present application provides a service clock transparent transmission system in an optical transport network, where the system includes at least one service clock transparent transmission unit.
  • the service clock transparent transmission unit includes:
  • the cache module 100 is configured to cache the input service data.
  • a generating module 200 configured to acquire a current watermark value of the cache module 100, and generate a frequency adjustment signal according to a current watermark value of the cache module 100;
  • the phase locked loop 400 is configured to multiply the local clock signal received by the phase locked loop to generate a reference clock signal
  • the parallel-to-serial conversion module 500 is configured to read the service data in the cache module 100, and convert the parallel service data into serial service data and output the data;
  • the adjustment module 300 is configured to adjust the reference clock signal according to the frequency adjustment signal, generate a frequency control signal, and control a speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100, so that the cache The data read speed of the module 100 is in equilibrium with the data write speed.
  • the service clock transparent transmission system may include only one service clock transparent transmission unit, and may also include multiple service clock transparent transmission units, depending on the service clock transparent transmission system.
  • the service clock transparent transmission unit and the data received by the service clock transparent transmission system The number of streams corresponds one by one.
  • the cache module 100 is a first in first out memory, that is, a FIFO (First In First Out) memory.
  • the cache module 100 has a data write side and a data read side.
  • the current watermark value of the cache module 100 is also increased; when the data write speed of the data write side of the cache module 100 is smaller than the data read speed of the data read side of the cache module 100, the cache The amount of data stored in the module 100 is reduced.
  • the current watermark value of the cache module 100 is also reduced, when the data write speed of the data write side of the cache module 100 is related to the cache module.
  • the data reading speed of the 100 data reading side is in an equilibrium state, the amount of data stored in the cache module 100 is also in a dynamic balance state, and the current watermark value of the cache module 100 remains unchanged.
  • the generating module 200 acquires the current watermark value of the cache module 100, and calculates the current watermark value and the preset watermark of the cache module 100. a difference between the values; when the difference between the current watermark value of the cache module 100 and the preset watermark value is greater than zero (ie, the current watermark value of the cache module 100 is greater than a preset watermark value), generating a first Frequency adjustment signal.
  • the adjustment module 300 increases the frequency of the reference clock signal, generates a first frequency control signal, and improves the parallel-to-serial conversion module 500 to read data from the cache module 100.
  • the adjusting module 300 receives the second frequency adjustment signal, the frequency of the reference clock signal is decreased, and a second frequency control signal is generated, and the parallel-to-serial conversion module 500 is read from the cache module 100.
  • the speed of the data is taken until the difference between the current watermark value of the cache module 100 and the preset watermark value is zero, that is, the current watermark value of the cache module 100 is equal to the preset watermark value.
  • the data write speed and the data read speed of the cache module 100 are in a balanced state, and the adjustment module 300 maintains the current data read speed of the cache module 100.
  • the first control signal and the second control signal are frequency coded words.
  • the preset watermark value is different, so the specific value of the preset watermark value is not limited in the present application. Subject to availability.
  • the generating module 200 may obtain the current watermark value of the cache module 100 in real time, and may acquire the current watermark value of the cache module 100 at a preset frequency. To reduce the frequency of obtaining the current watermark value of the cache module 100, the present application does not limit this, as the case may be. Optionally, the generating module 200 acquires a frequency of the current watermark value of the cache module 100 by 1 Khz.
  • the generating module 200 includes:
  • An obtaining unit configured to acquire a current watermark value of the cache module 100, and calculate a difference between a current watermark value of the cache module 100 and a preset watermark value, When the current watermark value of the cache module 100 is greater than the preset watermark value, the difference between the current watermark value of the cache module 100 and the preset watermark value is greater than zero, when the current watermark value of the cache module 100 is less than the pre- When the watermark value is set, the cache module 100 The difference between the front watermark value and the preset watermark value is less than zero;
  • a first adjusting unit configured to obtain a first adjustment value by multiplying a difference between a current watermark value of the cache module 100 and a preset waterline value by a watermark adjustment factor ki;
  • a second adjusting unit configured to use a difference between a current watermark value of the cache module 100 and a preset watermark value, and a current watermark value of the cache module 100 during a last adjustment
  • the difference between the preset waterline values is obtained by the difference, and the adjustment difference value is obtained, and the adjustment value is multiplied by the frequency offset adjustment factor kp to obtain a second adjustment value, where the current watermark of the cache module 100 is present.
  • the adjustment difference is greater than zero
  • the buffer is The difference between the current watermark value of the module 100 and the preset watermark value is less than the difference between the current watermark value of the cache module 100 and the preset watermark value during the last adjustment, the adjustment difference is less than zero
  • a third adjusting unit configured to sum the first adjustment value and the second adjustment value to obtain a third adjustment value, and the third adjustment value is divided by a preset parameter k, Obtaining a frequency adjustment signal; wherein, when the third adjustment value is greater than zero, the frequency adjustment signal is a first frequency adjustment signal, and when the third adjustment value is less than zero, the frequency adjustment signal is a second frequency adjustment signal.
  • the adjusting module 300 is configured to sum the current frequency adjustment signal and the previous frequency adjustment signal, generate a final frequency adjustment signal, and adjust a frequency of the reference clock signal according to the final frequency adjustment signal to generate a frequency. And a control signal that controls a speed at which the parallel-to-serial conversion module reads data from the cache module.
  • the adjustment module 300 adjusts a frequency of the reference clock signal by adjusting a phase of the reference clock signal, thereby adjusting a speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100.
  • the preset watermark value is a median value, wherein the median value is half of the maximum storage capacity value of the cache module 100.
  • the process includes:
  • the generating module 200 acquires a current watermark value of the cache module, and subtracts the current watermark value from the median value to obtain a difference between the current watermark value and the median value;
  • the adjustment signal is output to the adjustment module 300, wherein the value of the preset parameter is greater than a reciprocal of the waterline adjustment factor and a reciprocal of the frequency offset adjustment factor to prevent the write speed in the cache module 100 from being too fast.
  • the phase adjustment amplitude is too large, resulting in data loss during data reading.
  • the adjustment module 300 obtains a final phase adjustment amplitude by using the phase adjustment amplitude in the current adjustment process and Z2-1 (the phase adjustment amplitude in the last adjustment process), and using the final phase adjustment amplitude to the reference clock.
  • the phase of the signal is adjusted to obtain a frequency control signal for controlling the speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100.
  • the adjustment module 300 is a phase adjuster, and the phase of the reference clock signal is adjusted by periodic sliding of the phase, thereby adjusting the reference clock signal. frequency.
  • the adjusting module 300 divides the period of the reference clock signal into N parts, and when receiving the frequency adjustment signal, implementing the phase adjustment of the period of the reference clock signal by k*1/N cycles, The periodic sliding of the phase of the reference clock signal. Where k is any integer from 0-(N-1).
  • the number of cycles of the reference clock signal is increased by one cycle in the same time, and the frequency of the reference clock signal is correspondingly increased;
  • the reference clock signal is When the phase is rotated clockwise by one clock, the number of cycles of the reference clock signal is reduced by one cycle in the same time, and the frequency of the reference clock signal is also reduced accordingly.
  • the phase of the reference clock signal is phased according to the step size of 1/(f*N) phase. Adjustment.
  • f is the natural frequency of the reference clock signal, ie the frequency before the reference clock signal is adjusted.
  • the phase of the reference clock signal is sequentially adjusted to (N-1) / (f * N), ... P / (f * N), ... 1 /(f*N), achieving a decrease in the number of cycles, generating a negative frequency offset;
  • the phase of the reference clock signal is rotated counterclockwise, the phase of the reference clock signal is sequentially adjusted to 1/(f* N), ... P / (f * N), ... (N-1) / (f * N), to achieve an increase in the number of cycles, resulting in a positive frequency offset.
  • P is any integer between 1-(N-1).
  • the service clock transparent transmission system in the optical transport network can directly acquire the current watermark value of the cache module 100 by using the generating module 200, and according to the current water of the cache module 100.
  • the line value generation frequency adjustment signal is sent to the adjustment module 300, and the adjustment module 300 is used to adjust the reference clock signal according to the frequency adjustment signal to generate a frequency control signal, and the parallel-to-serial conversion module 500 is controlled from the
  • the speed of reading data in the cache module 100 is such that the data read speed of the cache module 100 and the data write speed are in equilibrium, without the need to additionally set a clock chip, which is small in size and low in cost.
  • the reference clock signal sent by the clock chip to the service chip is before the output.
  • a phase-locked loop is required for signal stabilization, and a phase-locked loop is required for frequency multiplication after being sent to the service chip.
  • the service clock transparent transmission system in the optical transport network provided in this embodiment does not need to additionally set a clock chip. In the process, only one phase locked loop is needed, which further simplifies the structure of the service clock transparent transmission system in the optical transmission network, reduces the volume of the service clock transparent transmission system in the optical transmission network, and reduces the optical transmission. network The cost of the business clock transparent transmission system.

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Abstract

Disclosed is a service clock pass-through system in an optical transport network. The system comprises at least one service clock pass-through unit. The service clock pass-through unit comprises: a cache module for caching input service data; a generation module for obtaining a current waterline value of the cache module and generating a frequency adjustment signal according to the current waterline value of the cache module; a phase-locked loop for frequency-multiplying the received local clock signal to generate a reference clock signal; a parallel-serial conversion module for reading service data in the cache module; and an adjustment module for adjusting the reference clock signal according to the frequency adjustment signal to generate a frequency control signal, and controlling the speed of the parallel-serial conversion module for reading data from the cache module so that the data reading speed and the data writing speed of the cache module are in balance. The service clock pass-through system does not need to be additionally provided with a clock chip, and has a small size and low costs.

Description

光传送网中业务时钟透传系统Service clock transparent transmission system in optical transport network
本申请要求于2016年9月27日提交中国专利局、申请号为201610856685.9、申请名称为“光传送网中业务时钟透传系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to Chinese Patent Application No. 201610856685.9, filed on September 27, 2016, entitled "Business Clock Transparent Transmission System in Optical Transport Network", the entire contents of which are incorporated herein by reference. In the application.
技术领域Technical field
本申请涉及光传送网技术领域，尤其涉及一种光传送网中业务时钟透传系统。The present application relates to the field of optical transport network technologies, and in particular, to a service clock transparent transmission system in an optical transport network.
背景技术Background technique
随着通信系统的发展，OTN(Optical Transport Network，光传送网)逐渐成为传输网络的主流。而业务时钟透传是其一个较为普通的应用场景。With the development of communication systems, OTN (Optical Transport Network) has gradually become the mainstream of transmission networks. The transparent transmission of the service clock is a relatively common application scenario.
目前的业务时钟透传系统中，通常是在业务芯片外额外设置时钟芯片，以利用时钟芯片检测业务芯片中缓存器的数据写入速度，并根据该缓存器的数据写入速度调节其数据读取速度，以使得缓存器的数据写入速度和数据读取速度处于平衡状态，保证缓存器的正常工作和业务时钟透传的正常进行，导致现有业务时钟透传系统体积较大，成本较高。In the current service clock transparent transmission system, a clock chip is usually additionally disposed outside the service chip to detect the data writing speed of the buffer in the service chip by using the clock chip, and adjust the data reading according to the data writing speed of the buffer. The speed is taken so that the data writing speed and the data reading speed of the buffer are in a balanced state, so that the normal operation of the buffer and the transparent transmission of the service clock are ensured, resulting in a large volume of the existing service clock transparent transmission system, and the cost is relatively high. high.
发明内容Summary of the invention
为解决上述技术问题，本申请实施例提供了一种光传送网中业务时钟透传系统，该业务时钟透传系统无需在业务芯片外额外设置时钟芯片，体积较小，成本较低。To solve the above technical problem, the embodiment of the present application provides a service clock transparent transmission system in an optical transmission network. The service clock transparent transmission system does not need to additionally set a clock chip outside the service chip, and has a small volume and a low cost.
为解决上述问题，本申请实施例提供了如下技术方案：To solve the above problem, the embodiment of the present application provides the following technical solutions:
第一方面，本申请提供了一种传送网中业务时钟透传系统，该系统包括至少一个业务时钟透传单元，所述业务时钟透传单元包括：In a first aspect, the application provides a service clock transparent transmission system in a transport network, where the system includes at least one service clock transparent transmission unit, and the service clock transparent transmission unit includes:
缓存模块，用于对输入的业务数据进行缓存；a cache module for buffering input business data;
生成模块，用于获取所述缓存模块的当前水线值，并根据所述缓存模块的当前水线值生成频率调节信号；a generating module, configured to acquire a current watermark value of the cache module, and generate a frequency adjustment signal according to a current watermark value of the cache module;
锁相环，用于对其接收的本地时钟信号进行倍频，生成参考时钟信号；a phase locked loop for multiplying a local clock signal received by the same to generate a reference clock signal;
并串转换模块，用于读取所述缓存模块中的业务数据；And a parallel conversion module, configured to read service data in the cache module;
调节模块，用于根据所述频率调节信号调节所述参考时钟信号，生成频率控制信号，控制所述并串转换模块从所述缓存模块的中读取数据的速度，使得所述缓存模块的数据读取速度与数据写入速度处于平衡状态。An adjustment module, configured to adjust the reference clock signal according to the frequency adjustment signal, generate a frequency control signal, and control a speed at which the parallel-to-serial conversion module reads data from the cache module, so that the data of the cache module The read speed is balanced with the data write speed.
本申请提供的传送网中业务时钟透传系统，无需额外设置时钟芯片，体积较小，成本较低。而且，由于芯片外部的信号传输频率较低，而芯片内部的信号传输频率较高，因此，当在业务芯片外额外设置时钟芯片时，所述时钟芯片发送给业务芯片的参考时钟信号在输出前需要一个锁相环进行信号稳定，在发送给业务芯片后还需要一个锁相环进行倍频，而本实施例所提供的光传送网中业务时钟透传系统，无需额外设置 时钟芯片，整个工作过程中，只需一个锁相环即可，从而进一步简化了所述光传送网中业务时钟透传系统的结构，减小了所述光传送网中业务时钟透传系统的体积，降低了光传送网中业务时钟透传系统的成本。The service clock transparent transmission system in the transmission network provided by the application does not need to additionally set a clock chip, and has a small volume and a low cost. Moreover, since the signal transmission frequency outside the chip is low, and the signal transmission frequency inside the chip is high, when the clock chip is additionally disposed outside the service chip, the reference clock signal sent by the clock chip to the service chip is before the output. A phase-locked loop is required for signal stabilization, and a phase-locked loop is required for frequency multiplication after being sent to the service chip. However, the service clock transparent transmission system in the optical transport network provided in this embodiment does not need to be additionally set. The clock chip only needs one phase-locked loop in the whole working process, thereby further simplifying the structure of the service clock transparent transmission system in the optical transmission network, and reducing the service clock transparent transmission system in the optical transmission network. The volume reduces the cost of the service clock transparent transmission system in the optical transport network.
一种实现方式中，该系统包括多个业务时钟透传单元，所述业务时钟透传单元与所述业务时钟透传系统接收的数据流数量一一对应，以提高该系统的应用范围和适用性。In an implementation manner, the system includes multiple service clock transparent transmission units, and the service clock transparent transmission unit has a one-to-one correspondence with the number of data flows received by the service clock transparent transmission system, so as to improve the application range and application of the system. Sex.
一种实现方式中，所述缓存模块为先进先出存储器。In an implementation manner, the cache module is a first in first out memory.
一种实现方式中，所述生成模块用于据所述缓存模块的当前水线值生成频率调节信号时具体用于：In an implementation manner, the generating module is configured to: when generating a frequency adjustment signal according to a current watermark value of the cache module, specifically:
根据所述缓存模块的当前水线值，计算所述缓存模块当前水线值与预设水线值的差值；Calculating, according to a current watermark value of the cache module, a difference between a current watermark value of the cache module and a preset watermark value;
当所述缓存模块当前水线值与预设水线值的差值大于零时，生成第一频率调节信号；Generating a first frequency adjustment signal when a difference between a current watermark value of the cache module and a preset waterline value is greater than zero;
当所述缓存模块当前水线值与预设水线值的差值小于零时，生成第二频率调节信号。When the difference between the current watermark value of the cache module and the preset waterline value is less than zero, a second frequency adjustment signal is generated.
可选的，所述生成模块包括：Optionally, the generating module includes:
获取单元，所述获取单元用于获取所述缓存模块的当前水线值，并计算所述缓存模块当前水线值与预设水线值的差值；An obtaining unit, configured to acquire a current watermark value of the cache module, and calculate a difference between a current watermark value of the cache module and a preset watermark value;
第一调节单元，所述第一调节单元用于利用所述缓存模块当前水线值与预设水线值的差值乘以水线调节因子，得到第一调节值；a first adjusting unit, configured to obtain a first adjustment value by multiplying a difference between a current watermark value of the cache module and a preset waterline value by a watermark adjustment factor;
第二调节单元，所述第二调节单元用于对本次所述缓存模块当前水线值与预设水线值的差值以及上一次调节过程中所述缓存模块当前水线值与预设水线值的差值求差，获得调节差值，并利用所述调节差值乘以频偏调节因子，得到第二调节值；a second adjusting unit, configured to use a difference between a current watermark value of the cache module and a preset watermark value, and a current watermark value and a preset of the cache module in a previous adjustment process The difference between the water line values is obtained, the adjustment difference value is obtained, and the adjustment difference value is multiplied by the frequency offset adjustment factor to obtain a second adjustment value;
第三调节单元，所述第三调节单元用于对所述第一调节值和所述第二调节值求和，得到第三调节值，并所述第三调节值除以预设参数，获得频率调节信号；a third adjusting unit, configured to sum the first adjustment value and the second adjustment value to obtain a third adjustment value, and the third adjustment value is divided by a preset parameter to obtain Frequency adjustment signal;
其中，所述第三调节值大于零时，所述频率调节信号为第一频率调节信号，所述第三调节值小于零时，所述频率调节信号为第二频率调节信号。Wherein, when the third adjustment value is greater than zero, the frequency adjustment signal is a first frequency adjustment signal, and when the third adjustment value is less than zero, the frequency adjustment signal is a second frequency adjustment signal.
一种实现方式中，所述生成模块获取所述缓存模块的当前水线值的频率为1Khz，以在保证所述缓存模块的数据写入速度和数据读取速度保持平衡的前提下，降低所述缓存模块当前水线值的读取频率，从而降低所述光传送网中业务时钟透传系统的功耗。In an implementation manner, the generating module acquires a frequency of the current watermark value of the cache module to be 1 Khz, so as to ensure that the data writing speed and the data reading speed of the cache module are balanced, The frequency of reading the current watermark value of the cache module is reduced, thereby reducing the power consumption of the service clock transparent transmission system in the optical transport network.
一种实现方式中，所述调节模块用于根据所述第一频率调节信号增加所述参考时钟信号的频率，生成第一频率控制信号，提高所述并串转换模块从所述缓存模块的中读取数据的速度，并用于根据所述第二频率调节信号降低所述参考时钟信号的频率，生成第二频率控制信号，降低所述并串转换模块从所述缓存模块的中读取数据的速度。In an implementation manner, the adjusting module is configured to increase a frequency of the reference clock signal according to the first frequency adjustment signal, generate a first frequency control signal, and improve the parallel-to-serial conversion module from the cache module. Reading a speed of the data, and for reducing a frequency of the reference clock signal according to the second frequency adjustment signal, generating a second frequency control signal, and reducing the parallel data conversion module to read data from the cache module speed.
一种实现方式中，所述调节模块通过调节所述参考时钟信号的相位调节所述参考时钟信号的频率，以适用于较小频偏的调节。In one implementation, the adjustment module adjusts the frequency of the reference clock signal by adjusting the phase of the reference clock signal to be suitable for adjustment of a smaller frequency offset.
可选的，所述调节模块用于对本次频率调节信号和上一次频率调节信号求和，生 成最终频率调节信号，并根据所述最终频率调节信号调节所述参考时钟信号的相位，生成频率控制信号，控制所述并串转换模块从所述缓存模块的中读取数据的速度。Optionally, the adjusting module is configured to sum the current frequency adjustment signal and the previous frequency adjustment signal, and generate And forming a final frequency adjustment signal, and adjusting a phase of the reference clock signal according to the final frequency adjustment signal to generate a frequency control signal, and controlling a speed at which the parallel-to-serial conversion module reads data from the cache module.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.
图1为本申请实施例所提供的光传送网中业务时钟透传系统的结构示意图；1 is a schematic structural diagram of a service clock transparent transmission system in an optical transport network according to an embodiment of the present application;
图2为本申请一个实施例所提供的光传送网中业务时钟透传系统中，所述生成模块和调节模块的具体工作过程示意图；2 is a schematic diagram of a specific working process of the generating module and the adjusting module in a service clock transparent transmission system in an optical transport network according to an embodiment of the present disclosure;
图3为本申请实施例所提供的光传送网中业务时钟透传系统中，所述调节模块每次周期性滑动1/N个周期时，所述参考时钟信号的相位示意图。FIG. 3 is a schematic diagram of a phase of the reference clock signal when the adjustment module periodically slides 1/N cycles in a service clock transparent transmission system in an optical transport network according to an embodiment of the present disclosure.
具体实施方式detailed description
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。In the following description, numerous specific details are set forth in order to facilitate a full understanding of the application, but the invention may be practiced in other ways than those described herein, and those skilled in the art can do without departing from the scope of the application. The invention is not limited by the specific embodiments disclosed below.
本申请实施例提供了一种光传送网中业务时钟透传系统，该系统包括至少一个业务时钟透传单元，如图1所示，所述业务时钟透传单元包括：The embodiment of the present application provides a service clock transparent transmission system in an optical transport network, where the system includes at least one service clock transparent transmission unit. As shown in FIG. 1 , the service clock transparent transmission unit includes:
缓存模块100，用于对输入的业务数据进行缓存；The cache module 100 is configured to cache the input service data.
生成模块200，用于获取所述缓存模块100的当前水线值，并根据所述缓存模块100的当前水线值生成频率调节信号；a generating module 200, configured to acquire a current watermark value of the cache module 100, and generate a frequency adjustment signal according to a current watermark value of the cache module 100;
锁相环400，用于对其接收的本地时钟信号进行倍频，生成参考时钟信号；The phase locked loop 400 is configured to multiply the local clock signal received by the phase locked loop to generate a reference clock signal;
并串转换模块500，用于读取所述缓存模块100中的业务数据，并将其由并行业务数据转换成串行业务数据后输出；The parallel-to-serial conversion module 500 is configured to read the service data in the cache module 100, and convert the parallel service data into serial service data and output the data;
调节模块300，用于根据所述频率调节信号调节所述参考时钟信号，生成频率控制信号，控制所述并串转换模块500从所述缓存模块100的中读取数据的速度，使得所述缓存模块100的数据读取速度与数据写入速度处于平衡状态。The adjustment module 300 is configured to adjust the reference clock signal according to the frequency adjustment signal, generate a frequency control signal, and control a speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100, so that the cache The data read speed of the module 100 is in equilibrium with the data write speed.
需要说明的是，在本申请实施例中，所述业务时钟透传系统可以只包括一个业务时钟透传单元，也可以包括多个业务时钟透传单元，具体视所述业务时钟透传系统可接收的数据流数量而定，所述业务时钟透传单元与所述业务时钟透传系统接收的数据 流数量一一对应。It should be noted that, in the embodiment of the present application, the service clock transparent transmission system may include only one service clock transparent transmission unit, and may also include multiple service clock transparent transmission units, depending on the service clock transparent transmission system. Depending on the number of received data streams, the service clock transparent transmission unit and the data received by the service clock transparent transmission system The number of streams corresponds one by one.
下面以所述业务时钟透传系统包括一个业务时钟透传单元为例，对本申请实施例所提供的业务时钟透传系统进行说明。优选的，在本申请实施例中，所述缓存模块100为先进先出存储器，即FIFO(First In First Out)存储器，The service clock transparent transmission system provided by the embodiment of the present application is described below by taking the service clock transparent transmission system as a service clock transparent transmission unit as an example. Preferably, in the embodiment of the present application, the cache module 100 is a first in first out memory, that is, a FIFO (First In First Out) memory.
所述缓存模块100具有数据写入侧和数据读取侧。当所述缓存模块100的数据写入侧的数据写入速度大于所述缓存模块100数据读取侧的数据读取速度时，所述缓存模块100中所存储的数据量会增加，相应的，所述缓存模块100的当前水线值也会增加；当所述缓存模块100的数据写入侧的数据写入速度小于所述缓存模块100数据读取侧的数据读取速度时，所述缓存模块100中所存储的数据量会减少，相应的，所述缓存模块100的当前水线值也会减小，当所述缓存模块100的数据写入侧的数据写入速度与所述缓存模块100数据读取侧的数据读取速度处于平衡态时，所述缓存模块100中所存储的数据量也会处于动态平衡状态，所述缓存模块100的当前水线值维持不变。The cache module 100 has a data write side and a data read side. When the data writing speed of the data writing side of the cache module 100 is greater than the data reading speed of the data reading side of the cache module 100, the amount of data stored in the cache module 100 may increase, correspondingly, The current watermark value of the cache module 100 is also increased; when the data write speed of the data write side of the cache module 100 is smaller than the data read speed of the data read side of the cache module 100, the cache The amount of data stored in the module 100 is reduced. Correspondingly, the current watermark value of the cache module 100 is also reduced, when the data write speed of the data write side of the cache module 100 is related to the cache module. When the data reading speed of the 100 data reading side is in an equilibrium state, the amount of data stored in the cache module 100 is also in a dynamic balance state, and the current watermark value of the cache module 100 remains unchanged.
具体工作时，当所述缓存模块100有业务数据写入时，所述生成模块200获取所述缓存模块100的当前水线值，并计算所述缓存模块100当前水线值与预设水线值的差值；当所述缓存模块100当前水线值与预设水线值的差值大于零(即所述缓存模块100的当前水线值大于预设水线值)时，生成第一频率调节信号。调节模块300接收所述第一频率调节信号后，会增加所述参考时钟信号的频率，生成第一频率控制信号，提高所述并串转换模块500从所述缓存模块100的中读取数据的速度，当所述缓存模块100当前水线值与预设水线值的差值小于零(即所述缓存模块100的当前水线值小于预设水线值)时，生成第二频率调节信号，所述调节模块300接收所述第二频率调节信号后，会降低所述参考时钟信号的频率，生成第二频率控制信号，降低所述并串转换模块500从所述缓存模块100的中读取数据的速度，直至所述缓存模块100当前水线值与预设水线值的差值为零，即所述缓存模块100的当前水线值等于预设水线值，此时，所述缓存模块100的数据写入速度和数据读取速度处于平衡状态，所述调节模块300维持所述缓存模块100当前的数据读取速度。可选的，所述第一控制信号和所述第二控制信号为频率编码字。In the specific work, when the cache module 100 has the service data written, the generating module 200 acquires the current watermark value of the cache module 100, and calculates the current watermark value and the preset watermark of the cache module 100. a difference between the values; when the difference between the current watermark value of the cache module 100 and the preset watermark value is greater than zero (ie, the current watermark value of the cache module 100 is greater than a preset watermark value), generating a first Frequency adjustment signal. After receiving the first frequency adjustment signal, the adjustment module 300 increases the frequency of the reference clock signal, generates a first frequency control signal, and improves the parallel-to-serial conversion module 500 to read data from the cache module 100. Speed, when the difference between the current watermark value of the cache module 100 and the preset watermark value is less than zero (ie, the current watermark value of the cache module 100 is less than a preset watermark value), generating a second frequency adjustment signal After the adjusting module 300 receives the second frequency adjustment signal, the frequency of the reference clock signal is decreased, and a second frequency control signal is generated, and the parallel-to-serial conversion module 500 is read from the cache module 100. The speed of the data is taken until the difference between the current watermark value of the cache module 100 and the preset watermark value is zero, that is, the current watermark value of the cache module 100 is equal to the preset watermark value. The data write speed and the data read speed of the cache module 100 are in a balanced state, and the adjustment module 300 maintains the current data read speed of the cache module 100. Optionally, the first control signal and the second control signal are frequency coded words.
需要说明的是，当所述业务时钟透传单元接收的数据流类型不同，所述预设水线值也不同，故本申请对所述预设水线值的具体数值并不做限定，具体视情况而定。It should be noted that, when the type of the data stream received by the service clock transparent transmission unit is different, the preset watermark value is different, so the specific value of the preset watermark value is not limited in the present application. Subject to availability.
还需要说明的是，在本申请实施例中，所述生成模块200可以实时获取所述缓存模块100的当前水线值，还可以以预设频率获取所述缓存模块100的当前水线值，以降低所述缓存模块100当前水线值的获取频率，本申请对此并不做限定，具体视情况而定。可选的，所述生成模块200获取所述缓存模块100的当前水线值的频率为1Khz。It should be noted that, in the embodiment of the present application, the generating module 200 may obtain the current watermark value of the cache module 100 in real time, and may acquire the current watermark value of the cache module 100 at a preset frequency. To reduce the frequency of obtaining the current watermark value of the cache module 100, the present application does not limit this, as the case may be. Optionally, the generating module 200 acquires a frequency of the current watermark value of the cache module 100 by 1 Khz.
在上述任一实施例的基础上，在本申请的一个实施例中，所述生成模块200包括：On the basis of any of the above embodiments, in an embodiment of the present application, the generating module 200 includes:
获取单元，所述获取单元用于获取所述缓存模块100的当前水线值，并计算所述缓存模块100当前水线值与预设水线值的差值，需要说明的是，当所述缓存模块100的当前水线值大于预设水线值时，所述缓存模块100当前水线值与预设水线值的差值大于零，当所述缓存模块100的当前水线值小于预设水线值时，所述缓存模块100当 前水线值与预设水线值的差值小于零；An obtaining unit, configured to acquire a current watermark value of the cache module 100, and calculate a difference between a current watermark value of the cache module 100 and a preset watermark value, When the current watermark value of the cache module 100 is greater than the preset watermark value, the difference between the current watermark value of the cache module 100 and the preset watermark value is greater than zero, when the current watermark value of the cache module 100 is less than the pre- When the watermark value is set, the cache module 100 The difference between the front watermark value and the preset watermark value is less than zero;
第一调节单元，所述第一调节单元用于利用所述缓存模块100当前水线值与预设水线值的差值乘以水线调节因子ki，得到第一调节值；a first adjusting unit, configured to obtain a first adjustment value by multiplying a difference between a current watermark value of the cache module 100 and a preset waterline value by a watermark adjustment factor ki;
第二调节单元，所述第二调节单元用于对本次所述缓存模块100当前水线值与预设水线值的差值以及上一次调节过程中所述缓存模块100当前水线值与预设水线值的差值求差，获得调节差值，并利用所述调节差值乘以频偏调节因子kp，得到第二调节值，其中，当本次所述缓存模块100当前水线值与预设水线值的差值大于上一次调节过程中所述缓存模块100当前水线值与预设水线值的差值时，所述调节差值大于零，当本次所述缓存模块100当前水线值与预设水线值的差值小于上一次调节过程中所述缓存模块100当前水线值与预设水线值的差值时，所述调节差值小于零；a second adjusting unit, configured to use a difference between a current watermark value of the cache module 100 and a preset watermark value, and a current watermark value of the cache module 100 during a last adjustment The difference between the preset waterline values is obtained by the difference, and the adjustment difference value is obtained, and the adjustment value is multiplied by the frequency offset adjustment factor kp to obtain a second adjustment value, where the current watermark of the cache module 100 is present. When the difference between the value and the preset watermark value is greater than the difference between the current watermark value of the cache module 100 and the preset watermark value during the last adjustment, the adjustment difference is greater than zero, when the buffer is The difference between the current watermark value of the module 100 and the preset watermark value is less than the difference between the current watermark value of the cache module 100 and the preset watermark value during the last adjustment, the adjustment difference is less than zero;
第三调节单元，所述第三调节单元用于对所述第一调节值和所述第二调节值求和，得到第三调节值，并所述第三调节值除以预设参数k，获得频率调节信号；其中，当所述第三调节值大于零时，所述频率调节信号为第一频率调节信号，所述第三调节值小于零时，所述频率调节信号为第二频率调节信号。a third adjusting unit, configured to sum the first adjustment value and the second adjustment value to obtain a third adjustment value, and the third adjustment value is divided by a preset parameter k, Obtaining a frequency adjustment signal; wherein, when the third adjustment value is greater than zero, the frequency adjustment signal is a first frequency adjustment signal, and when the third adjustment value is less than zero, the frequency adjustment signal is a second frequency adjustment signal.
相应的，所述调节模块300用于对本次频率调节信号和上一次频率调节信号求和，生成最终频率调节信号，并根据所述最终频率调节信号调节所述参考时钟信号的频率，生成频率控制信号，控制所述并串转换模块从所述缓存模块的中读取数据的速度。Correspondingly, the adjusting module 300 is configured to sum the current frequency adjustment signal and the previous frequency adjustment signal, generate a final frequency adjustment signal, and adjust a frequency of the reference clock signal according to the final frequency adjustment signal to generate a frequency. And a control signal that controls a speed at which the parallel-to-serial conversion module reads data from the cache module.
可选的，所述调节模块300通过调节所述参考时钟信号的相位调节所述参考时钟信号的频率，从而调节所述并串转换模块500从所述缓存模块100的中读取数据的速度。Optionally, the adjustment module 300 adjusts a frequency of the reference clock signal by adjusting a phase of the reference clock signal, thereby adjusting a speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100.
下面结合图2对本申请实施例所提供的业务时钟透传系统中生成模块200和调节模块300的具体工作过程进行说明。需要说明的是，在本申请实施例中，所述预设水线值为中值，其中，所述中值为所述缓存模块100最大存储容量值的一半。The specific working process of the generating module 200 and the adjusting module 300 in the service clock transparent transmission system provided by the embodiment of the present application will be described below with reference to FIG. 2 . It should be noted that, in the embodiment of the present application, the preset watermark value is a median value, wherein the median value is half of the maximum storage capacity value of the cache module 100.
如图2所示，该过程包括：As shown in Figure 2, the process includes:
所述生成模块200获取所述缓存模块的当前水线值，将所述当前水线值与所述中值做减法，得到所述当前水线值与所述中值的差值；The generating module 200 acquires a current watermark value of the cache module, and subtracts the current watermark value from the median value to obtain a difference between the current watermark value and the median value;
将所述当前水线值与所述中值的差值乘以水线调节因子ki，得到第一调节值，并将当前水线值与所述中值的差值与Z1-1(上一次调节过程中缓存模块100当前水线值与中值的差值)做差值乘以频偏调节因子kp，得到第二调节值，其中，所述频率调节因子kp的倒数小于所述水线调节因子ki的倒数，以利用所述频偏调节因子kp实现对所述缓存模块100数据写入速度的快速跟踪，利用所述水线调节因子ki实现对所述缓存模块100数据写入速度的缓慢跟踪；Multiplying the difference between the current water line value and the median value by the water line adjustment factor ki to obtain a first adjustment value, and comparing the difference between the current water line value and the median value with Z1-1 (previous time The difference between the current water line value and the median value of the buffer module 100 during the adjustment process is multiplied by the frequency offset adjustment factor kp to obtain a second adjustment value, wherein the reciprocal of the frequency adjustment factor kp is smaller than the water line adjustment The reciprocal of the factor ki is used to achieve fast tracking of the data writing speed of the cache module 100 by using the frequency offset adjusting factor kp, and the data writing speed of the cache module 100 is slow by using the watermark adjusting factor ki track;
将所述第一调节值和所述第二调节值求和得到第三调节值，利用所述第二调节值对所述第一调节值进行调节，以实现本次调节过程中相位调节幅度的调节，如当所述第二调节值为正值时，进一步增加本次调节过程的相位调节幅度，当所述第二调节值为负值时，降低本次调节过程中相位调节幅度；And summing the first adjustment value and the second adjustment value to obtain a third adjustment value, and adjusting the first adjustment value by using the second adjustment value to implement a phase adjustment range in the current adjustment process Adjusting, for example, when the second adjustment value is a positive value, further increasing the phase adjustment amplitude of the current adjustment process, and when the second adjustment value is a negative value, reducing the phase adjustment amplitude during the current adjustment process;
将所述第三调节值除以预设参数k，得到本次调节过程中的相位调节幅度，即频率 调节信号输出给调节模块300，其中，所述预设参数的数值大于所述水线调节因子的倒数和所述频偏调节因子的倒数，以避免所述缓存模块100中的写入速度过快(体现为所述当前水线值与所述中值的差值过大)时，所述相位调节幅度过大，造成数据读取过程中的数据丢失。Dividing the third adjustment value by the preset parameter k to obtain a phase adjustment amplitude, that is, a frequency, in the current adjustment process The adjustment signal is output to the adjustment module 300, wherein the value of the preset parameter is greater than a reciprocal of the waterline adjustment factor and a reciprocal of the frequency offset adjustment factor to prevent the write speed in the cache module 100 from being too fast. When the difference between the current waterline value and the median value is too large, the phase adjustment amplitude is too large, resulting in data loss during data reading.
所述调节模块300利用所述本次调节过程中的相位调节幅度与Z2-1(上一次调节过程中相位调节幅度)求和得到最终相位调节幅度，利用该最终相位调节幅度对所述参考时钟信号的相位进行调节，得到频率控制信号，该频率控制信号用于控制所述并串转换模块500从所述缓存模块100的中读取数据的速度。The adjustment module 300 obtains a final phase adjustment amplitude by using the phase adjustment amplitude in the current adjustment process and Z2-1 (the phase adjustment amplitude in the last adjustment process), and using the final phase adjustment amplitude to the reference clock. The phase of the signal is adjusted to obtain a frequency control signal for controlling the speed at which the parallel-to-serial conversion module 500 reads data from the cache module 100.
在上述实施例的基础上，在本申请的一个实施例中，所述调节模块300为相位调节器，通过相位的周期性滑动调节所述参考时钟信号的相位，从而调节所述参考时钟信号的频率。如所述调节模块300将所述参考时钟信号的周期划分成N份，在接收到频率调节信号时，通过对所述参考时钟信号的周期进行k*1/N周期的相位调节，实现所述参考时钟信号相位的周期性滑动。其中，k为0-(N-1)中任一整数。On the basis of the foregoing embodiment, in an embodiment of the present application, the adjustment module 300 is a phase adjuster, and the phase of the reference clock signal is adjusted by periodic sliding of the phase, thereby adjusting the reference clock signal. frequency. The adjusting module 300 divides the period of the reference clock signal into N parts, and when receiving the frequency adjustment signal, implementing the phase adjustment of the period of the reference clock signal by k*1/N cycles, The periodic sliding of the phase of the reference clock signal. Where k is any integer from 0-(N-1).
具体的，当所述参考时钟信号的相位逆时钟旋转一周时，相同时间内所述参考时钟信号的周期数增加一个周期，所述参考时钟信号的频率也相应增加；当所述参考时钟信号的相位顺时钟旋转一周时，相同时间内所述参考时钟信号的周期数减少一个周期，所述参考时钟信号的频率也相应降低。Specifically, when the phase of the reference clock signal is rotated counterclockwise by one cycle, the number of cycles of the reference clock signal is increased by one cycle in the same time, and the frequency of the reference clock signal is correspondingly increased; when the reference clock signal is When the phase is rotated clockwise by one clock, the number of cycles of the reference clock signal is reduced by one cycle in the same time, and the frequency of the reference clock signal is also reduced accordingly.
如图3所示，当所述调节模块300每次周期性滑动1/N个周期时，就能实现使得所述参考时钟信号的频率按照1/(f*N)相位的步长进行相位的调节。其中，f为所述参考时钟信号的固有频率，即所述参考时钟信号被调节前的频率。当所述参考时钟信号的相位被顺时钟旋转时，所述参考时钟信号的相位依次被调节为(N-1)/(f*N)、……P/(f*N)、……1/(f*N)，实现一个周期数的减小，产生负频偏；当所述参考时钟信号的相位被逆时钟旋转时，所述参考时钟信号的相位依次被调节为1/(f*N)、……P/(f*N)、……(N-1)/(f*N)，实现一个周期数的增加，产生正频偏。其中，P为1-(N-1)之间任一整数。As shown in FIG. 3, when the adjustment module 300 periodically slides 1/N cycles at a time, the phase of the reference clock signal is phased according to the step size of 1/(f*N) phase. Adjustment. Where f is the natural frequency of the reference clock signal, ie the frequency before the reference clock signal is adjusted. When the phase of the reference clock signal is rotated clockwise, the phase of the reference clock signal is sequentially adjusted to (N-1) / (f * N), ... P / (f * N), ... 1 /(f*N), achieving a decrease in the number of cycles, generating a negative frequency offset; when the phase of the reference clock signal is rotated counterclockwise, the phase of the reference clock signal is sequentially adjusted to 1/(f* N), ... P / (f * N), ... (N-1) / (f * N), to achieve an increase in the number of cycles, resulting in a positive frequency offset. Where P is any integer between 1-(N-1).
综上所述，本申请实施例所提供的光传送网中业务时钟透传系统，可以直接利用生成模块200获取所述缓存模块100的当前水线值，并根据所述缓存模块100的当前水线值生成频率调节信号发送给所述调节模块300，并利用所述调节模块300根据所述频率调节信号调节所述参考时钟信号，生成频率控制信号，控制所述并串转换模块500从所述缓存模块100的中读取数据的速度，使得所述缓存模块100的数据读取速度与数据写入速度处于平衡状态，而无需额外设置时钟芯片，体积较小，成本较低。In summary, the service clock transparent transmission system in the optical transport network provided by the embodiment of the present application can directly acquire the current watermark value of the cache module 100 by using the generating module 200, and according to the current water of the cache module 100. The line value generation frequency adjustment signal is sent to the adjustment module 300, and the adjustment module 300 is used to adjust the reference clock signal according to the frequency adjustment signal to generate a frequency control signal, and the parallel-to-serial conversion module 500 is controlled from the The speed of reading data in the cache module 100 is such that the data read speed of the cache module 100 and the data write speed are in equilibrium, without the need to additionally set a clock chip, which is small in size and low in cost.
而且，由于芯片外部的信号传输频率较低，而芯片内部的信号传输频率较高，因此，当在业务芯片外额外设置时钟芯片时，所述时钟芯片发送给业务芯片的参考时钟信号在输出前需要一个锁相环进行信号稳定，在发送给业务芯片后还需要一个锁相环进行倍频，而本实施例所提供的光传送网中业务时钟透传系统，无需额外设置时钟芯片，整个工作过程中，只需一个锁相环即可，进一步简化了所述光传送网中业务时钟透传系统的结构，减小了所述光传送网中业务时钟透传系统的体积，降低了光传送网 中业务时钟透传系统的成本。Moreover, since the signal transmission frequency outside the chip is low, and the signal transmission frequency inside the chip is high, when the clock chip is additionally disposed outside the service chip, the reference clock signal sent by the clock chip to the service chip is before the output. A phase-locked loop is required for signal stabilization, and a phase-locked loop is required for frequency multiplication after being sent to the service chip. However, the service clock transparent transmission system in the optical transport network provided in this embodiment does not need to additionally set a clock chip. In the process, only one phase locked loop is needed, which further simplifies the structure of the service clock transparent transmission system in the optical transmission network, reduces the volume of the service clock transparent transmission system in the optical transmission network, and reduces the optical transmission. network The cost of the business clock transparent transmission system.
本说明书中各个部分采用递进的方式描述，每个部分重点说明的都是与其他部分的不同之处，各个部分之间相同相似部分互相参见即可。Each part of this manual is described in a progressive manner. Each part focuses on the differences from other parts. The same similar parts between the parts can be referred to each other.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。 The above description of the disclosed embodiments enables those skilled in the art to make or use the application. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the application is not limited to the embodiments shown herein, but the broadest scope consistent with the principles and novel features disclosed herein.

Claims (9)

  1. 一种光传送网中业务时钟透传系统，其特征在于，该系统包括至少一个业务时钟透传单元，所述业务时钟透传单元包括：A service clock transparent transmission system in an optical transport network, the system includes at least one service clock transparent transmission unit, and the service clock transparent transmission unit includes:
    缓存模块，用于对输入的业务数据进行缓存；a cache module for buffering input business data;
    生成模块，用于获取所述缓存模块的当前水线值，并根据所述缓存模块的当前水线值生成频率调节信号；a generating module, configured to acquire a current watermark value of the cache module, and generate a frequency adjustment signal according to a current watermark value of the cache module;
    锁相环，用于对其接收的本地时钟信号进行倍频，生成参考时钟信号；a phase locked loop for multiplying a local clock signal received by the same to generate a reference clock signal;
    并串转换模块，用于读取所述缓存模块中的业务数据；And a parallel conversion module, configured to read service data in the cache module;
    调节模块，用于根据所述频率调节信号调节所述参考时钟信号，生成频率控制信号，控制所述并串转换模块从所述缓存模块的中读取数据的速度，使得所述缓存模块的数据读取速度与数据写入速度处于平衡状态。An adjustment module, configured to adjust the reference clock signal according to the frequency adjustment signal, generate a frequency control signal, and control a speed at which the parallel-to-serial conversion module reads data from the cache module, so that the data of the cache module The read speed is balanced with the data write speed.
  2. 根据权利要求1所述的系统，其特征在于，该系统包括多个业务时钟透传单元，所述业务时钟透传单元与所述业务时钟透传系统接收的数据流数量一一对应。The system according to claim 1, wherein the system comprises a plurality of service clock transparent transmission units, and the service clock transparent transmission unit has a one-to-one correspondence with the number of data streams received by the service clock transparent transmission system.
  3. 根据权利要求1或2所述的系统，其特征在于，所述缓存模块为先进先出存储器。The system of claim 1 or 2 wherein said cache module is a first in first out memory.
  4. 根据权利要求1-3任一项所述的系统，其特征在于，所述生成模块用于据所述缓存模块的当前水线值生成频率调节信号时具体用于：The system according to any one of claims 1-3, wherein the generating module is configured to: when generating a frequency adjustment signal according to a current watermark value of the cache module, specifically:
    根据所述缓存模块的当前水线值，计算所述缓存模块当前水线值与预设水线值的差值；Calculating, according to a current watermark value of the cache module, a difference between a current watermark value of the cache module and a preset watermark value;
    当所述缓存模块当前水线值与预设水线值的差值大于零时，生成第一频率调节信号；Generating a first frequency adjustment signal when a difference between a current watermark value of the cache module and a preset waterline value is greater than zero;
    当所述缓存模块当前水线值与预设水线值的差值小于零时，生成第二频率调节信号。When the difference between the current watermark value of the cache module and the preset waterline value is less than zero, a second frequency adjustment signal is generated.
  5. 根据权利要求4所述的系统，其特征在于，所述生成模块包括：The system of claim 4, wherein the generating module comprises:
    获取单元，所述获取单元用于获取所述缓存模块的当前水线值，并计算所述缓存模块当前水线值与预设水线值的差值；An obtaining unit, configured to acquire a current watermark value of the cache module, and calculate a difference between a current watermark value of the cache module and a preset watermark value;
    第一调节单元，所述第一调节单元用于利用所述缓存模块当前水线值与预设水线值的差值乘以水线调节因子，得到第一调节值；a first adjusting unit, configured to obtain a first adjustment value by multiplying a difference between a current watermark value of the cache module and a preset waterline value by a watermark adjustment factor;
    第二调节单元，所述第二调节单元用于对本次所述缓存模块当前水线值与预设水线值的差值以及上一次调节过程中所述缓存模块当前水线值与预设水线值的差值求差，获得调节差值，并利用所述调节差值乘以频偏调节因子，得到第二调节值；a second adjusting unit, configured to use a difference between a current watermark value of the cache module and a preset watermark value, and a current watermark value and a preset of the cache module in a previous adjustment process The difference between the water line values is obtained, the adjustment difference value is obtained, and the adjustment difference value is multiplied by the frequency offset adjustment factor to obtain a second adjustment value;
    第三调节单元，所述第三调节单元用于对所述第一调节值和所述第二调节值求和，得到第三调节值，并所述第三调节值除以预设参数，获得频率调节信号；a third adjusting unit, configured to sum the first adjustment value and the second adjustment value to obtain a third adjustment value, and the third adjustment value is divided by a preset parameter to obtain Frequency adjustment signal;
    其中，所述第三调节值大于零时，所述频率调节信号为第一频率调节信号，所述第三调节值小于零时，所述频率调节信号为第二频率调节信号。Wherein, when the third adjustment value is greater than zero, the frequency adjustment signal is a first frequency adjustment signal, and when the third adjustment value is less than zero, the frequency adjustment signal is a second frequency adjustment signal.
  6. 根据权利要求4所述的系统，其特征在于，所述生成模块获取所述缓存模块的当前水线值的频率为1Khz。 The system according to claim 4, wherein the generating module acquires a frequency of the current watermark value of the cache module of 1 Khz.
  7. 根据权利要求5所述的系统，其特征在于，所述调节模块用于根据所述第一频率调节信号增加所述参考时钟信号的频率，生成第一频率控制信号，提高所述并串转换模块从所述缓存模块的中读取数据的速度，并用于根据所述第二频率调节信号降低所述参考时钟信号的频率，生成第二频率控制信号，降低所述并串转换模块从所述缓存模块的中读取数据的速度。The system according to claim 5, wherein the adjustment module is configured to increase a frequency of the reference clock signal according to the first frequency adjustment signal, generate a first frequency control signal, and improve the parallel-to-serial conversion module Reading a speed of data from the cache module, and for reducing a frequency of the reference clock signal according to the second frequency adjustment signal, generating a second frequency control signal, and reducing the parallel-to-serial conversion module from the cache The speed at which data is read in the module.
  8. 根据权利要求7所述的系统，其特征在于，所述调节模块通过调节所述参考时钟信号的相位调节所述参考时钟信号的频率。The system of claim 7 wherein said adjustment module adjusts a frequency of said reference clock signal by adjusting a phase of said reference clock signal.
  9. 根据权利要求8所述的系统，其特征在于，所述调节模块用于对本次频率调节信号和上一次频率调节信号求和，生成最终频率调节信号，并根据所述最终频率调节信号调节所述参考时钟信号的相位，生成频率控制信号，控制所述并串转换模块从所述缓存模块的中读取数据的速度。 The system according to claim 8, wherein the adjustment module is configured to sum the current frequency adjustment signal and the previous frequency adjustment signal, generate a final frequency adjustment signal, and adjust the signal adjustment unit according to the final frequency. Referring to the phase of the clock signal, a frequency control signal is generated to control the speed at which the parallel-to-serial conversion module reads data from the cache module.
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