WO2018058335A1 - 电容感测电路 - Google Patents

电容感测电路 Download PDF

Info

Publication number
WO2018058335A1
WO2018058335A1 PCT/CN2016/100452 CN2016100452W WO2018058335A1 WO 2018058335 A1 WO2018058335 A1 WO 2018058335A1 CN 2016100452 W CN2016100452 W CN 2016100452W WO 2018058335 A1 WO2018058335 A1 WO 2018058335A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
switch
coupled
integration
turned
Prior art date
Application number
PCT/CN2016/100452
Other languages
English (en)
French (fr)
Inventor
梁佑安
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2016/100452 priority Critical patent/WO2018058335A1/zh
Priority to KR1020177029860A priority patent/KR102032890B1/ko
Priority to EP16898879.8A priority patent/EP3324331B1/en
Priority to CN201680001054.7A priority patent/CN106663200A/zh
Priority to US15/784,075 priority patent/US10565420B2/en
Publication of WO2018058335A1 publication Critical patent/WO2018058335A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/1347—Preprocessing; Feature extraction
    • G06V40/1359—Extracting features related to ridge properties; Determining the fingerprint type, e.g. whorl or loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches

Definitions

  • the invention relates to a capacitance sensing circuit, in particular to a capacitance sensing circuit with simple circuit configuration.
  • a fingerprint sensing system uses a capacitive sensing circuit to accept finger contact, and a capacitive sensing circuit is used to receive a finger contact and form a contact capacitance with the finger.
  • the capacitive sensing circuit can measure the capacitance of the contact capacitor. Converted into an analog voltage signal, the analog voltage signal needs to be converted into a digital voltage signal, and then transmitted to the fingerprint judgment module at the back end to determine the Finger Ridge or Finger Valley corresponding to the fingerprint sensing circuit.
  • the analog voltage signal is converted to a digital voltage signal by an Analog to Digital Convertor (ADC).
  • ADC Analog to Digital Convertor
  • the analog-to-digital converter has a complicated circuit structure and occupies a large circuit area while increasing production costs. And consumes higher power. Therefore, how to provide a capacitive sensing circuit with simple circuit structure, small circuit area, low cost and low power consumption has become one of the goals of the industry.
  • the present invention provides a capacitance sensing circuit including a sample and hold circuit coupled to the contact capacitor; an integrating circuit including an integrating input coupled to the sample and hold circuit; An integrated output terminal for outputting an integrated output voltage; a comparator comprising a first input coupled to the integrated output; a second input for receiving a reference voltage; and a comparison output a counter coupled to the comparison output for accumulating a cumulative number of transitions of the comparator; a voltage boosting circuit coupled to the integral input for switching to the comparator And the logic circuit is coupled to the counter, and when the accumulated number of times is equal to a predetermined number of times, the logic circuit outputs an integration time of the integration circuit. Wherein the integration time is related to a capacitance value of the contact capacitance.
  • the logic circuit when the accumulated number of times is equal to the predetermined number of times, the logic circuit generates a control signal to terminate the integration operation of the integrating circuit.
  • the integration time is a time elapsed by the integration circuit from the start of the integration operation to the termination of the integration operation.
  • the sampling and holding circuit includes a first switch, one end of which receives a positive voltage and the other end of which is coupled to the contact capacitor; and a second switch that has one end coupled to the contact capacitor and the other end coupled Connected to the integration input terminal; wherein, at a first time, the first switch is turned on and the second switch is turned off; and at a second time, the first switch is turned off and the first The second switch is turned on.
  • the integrating circuit includes an amplifier; a third switch coupled between the integrating input terminal and the integral output terminal; an integrating capacitor coupled to the integral input terminal and the integral And a fourth switch, one end of which is coupled to the integrating capacitor, and the other end of which is coupled to the integral output end.
  • the third switch and the fourth switch are turned on; and when the integrating circuit performs an integrating operation, the third switch is turned off. The fourth switch is turned on.
  • the voltage boosting circuit includes a rising capacitor coupled to the integrating input terminal; a fifth switch having one end receiving a positive voltage and the other end coupled to the boosting capacitor; and a sixth switch One end receives a ground voltage and the other end is coupled to the lift capacitor.
  • the capacitance sensing circuit further includes a control circuit, wherein the control circuit controls the fifth switch to be turned on to control the sixth switch to be turned off at a first time; and at a second time And the control circuit controls the fifth switch to be turned off to control the sixth switch to be turned on.
  • the capacitance sensing circuit provided by the invention can convert the charge stored in the contact capacitor into a time signal, which has the advantages of simple circuit structure, small circuit area, low cost and low power consumption.
  • FIG. 1 is a schematic diagram of a capacitance sensing circuit according to an embodiment of the present invention.
  • FIG. 2 is a waveform diagram of an integrated output voltage according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a capacitive sensing circuit 10 according to an embodiment of the present invention.
  • the capacitor sensing circuit 10 is configured to sense a contact capacitor Cf, and includes a sample and hold circuit SH, an integrating circuit 100, a comparator comp, a counter cntr, a voltage boosting circuit 104, a logic circuit 102, and a control Circuit 106.
  • the integrating circuit 100 includes switches S3 and S4, an amplifier Amp and an integrating capacitor C INT .
  • An input terminal of the amplifier Amp is an integrating input terminal of the integrating circuit 100.
  • An output terminal of the amplifier Amp is an integral of the integrating circuit 100.
  • the output terminal, wherein the integral output terminal is used to output an integrated output voltage V OUT .
  • a positive input terminal (labeled with a "+” sign) coupled to the integral output terminal of the integrating circuit 100 is configured to receive the integrated output voltage V OUT
  • a negative input terminal of the comparator comp (labeled "-" sign) receives a reference voltage V REF .
  • the counter cntr is coupled to a comparison output of the comparator comp for accumulating a cumulative number of times N OUT of the comparator comp transition state.
  • the logic circuit 102 can be implemented by using a digital circuit coupled between the counter cntr and the integration circuit 100. When the cumulative number of times N OUT is equal to a predetermined number of times N TH , the logic circuit 102 outputs an integration time T OUT of the integration circuit. And the logic circuit 102 generates a control signal (not shown in FIG. 1) to the integration circuit 100 to terminate the integration operation of the integration circuit 100, wherein the integration time T OUT can represent/reflect a capacitance value of the contact capacitance Cf.
  • the sample and hold circuit SH includes a switch S1 and a switch S2.
  • One end of the switch S1 receives a positive voltage V DD , and the other end of the switch S1 is electrically connected to the contact capacitor Cf.
  • One end of the switch S2 is electrically connected to the contact.
  • the other end of the switch C2 is electrically connected to the integral input of the integrating circuit 100.
  • the switch S3 is coupled between the integral input end and the integral output end of the integrating circuit 100
  • the integrating capacitor C INT is connected in series with the switch S4, and the integrating capacitor C INT and the switch S4 are also coupled to the integral. Between the integral input of circuit 100 and the integrated output.
  • An operation mode of the integrating circuit 100 can be controlled by controlling the conduction states of the switches S3, S4. For example, in a reset mode of the capacitive sensing circuit 10, the switches S3, S4 are all turned on; and in an integration mode of the capacitive sensing circuit 10 (ie, when the integrating circuit 100 performs an integrating operation) ), the switch S3 is turned off and the switch S4 is turned on. If the integration operation of the integration circuit 100 is to be terminated, the logic circuit 102 can generate a control signal to turn off the switch S4.
  • the switch S1 When the integration circuit 100 performs an integration operation (ie, the integration circuit 100 operates in the integration mode), the switch S1 is turned “ON" and the switch S2 is turned off during a first half cycle (corresponding to the first time) in a clock cycle T. OFF, the contact capacitor Cf is charged to a positive voltage V DD ; during a second half of the clock period T (corresponding to the second time), the switch S1 is turned off and the switch S2 is turned on, and the charge stored in the contact capacitor Cf is turned on.
  • the integrating capacitor C INT Flows to the integrating capacitor C INT , in other words, when the integrating circuit 100 performs an integrating operation, the integrated output voltage V OUT decreases with time.
  • the voltage boosting circuit 104 includes switches S5 and S6 and a lifting capacitor C DAC .
  • One end of the lifting capacitor C DAC is coupled to the integrating input terminal, and the other end is coupled to the switches S5 and S6 .
  • the switch S5 and the switch S6 receive a positive voltage V DD and a ground voltage GND, respectively.
  • the control circuit 106 is coupled between the voltage boost circuit 104 and the comparison output of the comparator comp. When the integrated output voltage V OUT is less than the reference voltage V REF , the comparator comp transitions, and the control circuit 106 generates a control signal.
  • the control circuit 106 controls the switch S5 during a first half cycle of the clock cycle T′ (corresponding to the first time) is turned on and is turned off in a second half period (corresponding to the second time) of the clock period T', and the control circuit 106 controls the switch S6 to be turned off during the first half period of the clock period T'.
  • the second half of the pulse period T' is turned on. That is to say, when the integrated output voltage V OUT is decremented by integration, so that the integrated output voltage V OUT is less than the reference voltage V REF (in the instant pulse period T'), the integrated output voltage V OUT can be increased to the voltage V REF +V K . As a result, the value of the integrated output voltage V OUT will be limited between the voltage V REF +V K and the voltage V REF .
  • the integration circuit 100 performs an integration operation (ie, the integration circuit 100 operates in the integration mode)
  • the integrated output voltage V OUT is decremented such that the integrated output voltage V OUT is less than the reference voltage V REF , the comparator comp transitions, the counter cntr value is increased by one, then the control circuit 106 generates a control signal, such that the integrated output voltage V OUT to increase the specific voltage value V K (i.e., integrated output voltage V OUT increases to voltage V REF + V K).
  • the integrating circuit 100 can continue to integrate by the increased voltage V REF +V K , that is, the integrated output voltage V OUT continuously decreases from the voltage V REF +V K until the next integrated output voltage V OUT is less than the reference voltage V REF
  • the value of the counter cntr is incremented by one again, and the control circuit 106 generates a control signal again, so that the integrated output voltage V OUT is again increased by the specific voltage value V K .
  • the logic circuit 102 generates a control signal to terminate the integration operation of the integration circuit 100 and output the integration time T OUT until the logic circuit 102 determines that the cumulative number N OUT output by the counter cntr is equal to the predetermined number N TH .
  • a back-end circuit of the capacitance sensing circuit 10 (not shown in FIG. 1) can determine the capacitance value of the contact capacitance Cf according to the integration time T OUT .
  • FIG. 2 is a waveform of an integrated output voltage V OUT_1 and an integrated output voltage V OUT_2 generated by the capacitive sensing circuit 10 for capacitive sensing of a contact capacitor Cf_1 and a contact capacitor Cf_2, respectively .
  • the contact capacitance Cf_1 and the contact capacitance Cf_2 have different capacitance values
  • the broken line represents a waveform diagram of the integrated output voltage V OUT_1
  • the solid line represents a waveform diagram of the integrated output voltage V OUT_2 .
  • the capacitance sensing circuit 10 starts the integration operation (or starts to enter the integration mode) at a time t 0 , and continues to integrate with the integration circuit 100 when the capacitance sensing circuit 10 performs capacitance sensing on the contact capacitance Cf_1 .
  • the comparator comp shifts again and again until a time t 1 , that is, when the cumulative number N OUT_1 accumulated by the counter cntr (corresponding to the contact capacitance Cf_1) reaches the predetermined number N TH , the logic circuit 102 outputs an integration time.
  • T OUT_1 time T OUT_1 i.e. where the integration time of the integrating circuit 100 integrates the operation start time t 0 of the integrating operation of the termination t 1).
  • the logic circuit 102 outputs an integration time T OUT_2 (wherein the integration time T OUT_1 , that is, the time t 0 at which the integration circuit 100 starts the integration operation to the termination integration operation) Time t 2 ).
  • the back-end circuit of the capacitance sensing circuit 10 can determine the capacitance values of the contact capacitances Cf_1, Cf_2 according to the integration times T OUT_1 , T OUT_2 , respectively.
  • the present invention utilizes the voltage boosting circuit 104 and the control circuit 106 to limit the value of the integrated output voltage V OUT between the voltage V REF +V K and the voltage V REF ; using the counter cntr to calculate the comparator comp state The number of times; using the logic circuit 102, determining whether the cumulative number of times N OUT output by the counter cntr reaches a predetermined number of times N TH , when the cumulative number of times N OUT reaches a predetermined number of times N TH , the logic circuit 102 outputs the integration time T OUT , and the capacitance sensing circuit The back end circuit of 10 can judge the capacitance value of the contact capacitance Cf according to the integration time T OUT .
  • the conventional capacitive sensing circuit converts the charge stored in the contact capacitor into an analog voltage signal, and converts the analog voltage signal into a digital voltage signal through an analog to digital converter (ADC).
  • ADC analog to digital converter
  • the simulation The circuit structure of the digitizer is complicated and occupies a large circuit area.
  • the capacitance sensing circuit of the present invention converts the charge stored in the contact capacitance into a time signal (ie, integration time T OUT ) without using an analog-to-digital converter, and the back-end circuit can be integrated according to the integration.
  • the time T OUT determines the capacitance value of the contact capacitance, thereby determining whether a touch event occurs, or determining whether the capacitive sensing circuit corresponds to a Finger Ridge or a Finger Valley for fingerprint recognition.
  • the capacitance sensing circuit of the present invention can convert the charge stored in the contact capacitance into a time signal without using a conventional analog-to-digital converter. According to the integration time output by the capacitance sensing circuit of the present invention, The capacitance value of the contact capacitor can be judged. Therefore, the capacitance sensing circuit of the present invention has the advantages of simple circuit structure, small circuit area, low cost, and low power consumption.

Landscapes

  • Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Analogue/Digital Conversion (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Electronic Switches (AREA)

Abstract

一种电容感测电路（10），包括一取样保持电路（SH），耦接于一接触电容（Cf）；一积分电路（100），耦接于所述取样保持电路（SH）；一比较器（comp），耦接于所述积分电路（100）；一计数器（cntr），耦接于所述比较输出端，用来累计所述比较器（comp）转态的一累计次数（N OUT）；一电压抬升电路（104），耦接于所述积分电路（100），用来于所述比较器（comp）转态时，将一积分输出电压（V OUT）增加一特定值（V K）；以及一逻辑电路（102），耦接于所述计数器（cntr），当所述累计次数等于一预定次数（N TH）时，所述逻辑电路（102）输出所述积分电路（100）的一积分时间（T OUT）；其中，所述积分时间（T OUT）相关于所述接触电容（Cf）的一电容值。

Description

电容感测电路 技术领域
本发明涉及一种电容感测电路，尤其涉及一种电路构造简单的电容感测电路。
背景技术
随着科技日新月异，移动电话、数字相机、平板计算机、笔记本电脑等越来越多携带型电子装置已经成为了人们生活中必备的工具。由于携带型电子装置一般为个人使用，而具有一定的隐私性，因此其内部储存的数据，例如电话簿、相片、个人信息等等为私人所有。若电子装置一旦丢失，则这些数据可能会被他人所利用，而造成不必要的损失。虽然目前已有利用密码保护的方式来避免电子装置为他人所使用，但密码容易泄露或遭到破解，具有较低的安全性。并且，用户需记住密码才能使用电子装置，若忘记密码，则会带给使用者许多不便。因此，目前发展出利用个人指纹识别系统的方式来达到身份认证的目的，以提升数据安全性。
一般来说，指纹识别系统中利用一电容感测电路接受手指的接触，电容感测电路用来接受手指的接触并与手指之间形成一接触电容，电容感测电路可将接触电容的电容值转换成一模拟电压信号，模拟电压信号需转换成数字电压信号后，再传送至后端的指纹判断模块以判断电容感测电路对应于指纹的纹蜂(Finger Ridge)或纹谷(Finger Valley)。换句话说，模拟电压信号通过一模拟数字转换器(Analog to Digital Convertor，ADC)以转换成数字电压信号。然而，模拟数字转换器的电路结构复杂，且占据大幅电路面积，同时增加生产成本， 且消耗较高功率。因此，如何提供一种电路结构简单、电路面积小、成本低且低功耗的电容感测电路也就成为业界所努力的目标之一。
发明内容
因此，本发明的主要目的即在于提供一种电路构造简单的电容感测电路。
为了解决上述技术问题，本发明提供了一电容感测电路，包含有一取样保持电路，耦接于所述接触电容；一积分电路，包含有一积分输入端，耦接于所述取样保持电路；以及一积分输出端，用来输出一积分输出电压；一比较器，包含有一第一输入端，耦接于所述积分输出端；一第二输入端，用来接收一参考电压；以及一比较输出端；一计数器，耦接于所述比较输出端，用来累计所述比较器转态的一累计次数；一电压抬升电路，耦接于所述积分输入端，用来于所述比较器转态时，将所述积分输出电压增加一特定值；以及一逻辑电路，耦接于所述计数器，当所述累计次数等于一预定次数时，所述逻辑电路输出所述积分电路的一积分时间；其中，所述积分时间相关于所述接触电容的一电容值。
优选地，当所述累计次数等于所述预定次数时，所述逻辑电路产生控制信号，以终止所述积分电路的积分操作。
优选地，所述积分时间为所述积分电路自开始进行积分操作至终止积分操作所经历的时间。
优选地，所述取样保持电路包含一第一开关，其一端接收一正电压，另一端耦接于所述接触电容；以及一第二开关，其一端耦接于所述接触电容，另一端耦接于所述积分输入端；其中，于一第一时间，所述第一开关导通而所述第二开关断开；以及于一第二时间，所述第一开关断开而所述第二开关导通。
优选地，所述积分电路包含有一放大器；一第三开关，耦接于所述积分输入端与所述积分输出端之间；一积分电容，耦接于所述积分输入端与所述积分 输出端之间；以及一第四开关，其一端耦接于所述积分电容，另一端耦接于所述积分输出端。
优选地，于所述电容感测电路的一重置模式时，所述第三开关及所述第四开关导通；以及于所述积分电路进行积分操作时，所述第三开关断开而所述第四开关导通。
优选地，所述电压抬升电路包含一抬升电容，耦接于所述积分输入端；一第五开关，其一端接收一正电压，另一端耦接于所述抬升电容；以及一第六开关，其一端接收一接地电压，另一端耦接于所述抬升电容。
优选地，所述电容感测电路另包含一控制电路，其中于一第一时间，所述控制电路控制所述第五开关导通而控制所述第六开关断开；以及于一第二时间，所述控制电路控制所述第五开关断开而控制所述第六开关导通。
本发明提供的电容感测电路可将接触电容中所储存的电荷转换成一时间信号，其具有电路结构简单、电路面积小、成本低以及低功耗的优点。
附图说明
图1为本发明实施例一电容感测电路的示意图。
图2为本发明实施例积分输出电压的波形图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明的电容感测电路将接触电容中所储存的电荷转换成一时间信号，以精准地判读接触电容的电容值，同时降低电容感测电路的电路复杂度。具体来说，请参考图1，图1为本发明实施例一电容感测电路10的示意图。电容感测 电路10，用来感测一接触电容Cf，其包含一取样保持电路SH、一积分电路100、一比较器comp、一计数器cntr、一电压抬升电路104、一逻辑电路102以及一控制电路106。积分电路100包含开关S3、S4、一放大器Amp及一积分电容CINT，放大器Amp的一输入端即为积分电路100的一积分输入端，放大器Amp的一输出端即为积分电路100的一积分输出端，其中积分输出端用来输出一积分输出电压VOUT。另外，比较器comp的一正输入端(标示有「+」号)耦接于积分电路100的积分输出端，用来接收积分输出电压VOUT，比较器comp的一负输入端(标示有「－」号)接收一参考电压VREF。计数器cntr耦接于比较器comp的一比较输出端，用来累计比较器comp转态的一累计次数NOUT。逻辑电路102可利用数字电路来实现，其耦接于计数器cntr及积分电路100之间，当累计次数NOUT等于一预定次数NTH时，逻辑电路102输出所述积分电路的一积分时间TOUT，且逻辑电路102产生一控制信号(未绘示于图1)至积分电路100，以终止积分电路100的积分操作，其中，积分时间TOUT即可代表/反映接触电容Cf的一电容值。
详细来说，取样保持电路SH包含开关S1及开关S2，开关S1的一端接收一正电压VDD，开关S1的另一端电性连接于接触电容Cf；开关S2的一端电性连接于接于接触电容Cf，开关S2的另一端电性连接于积分电路100的积分输入端。另外，在积分电路100中，开关S3耦接于积分电路100的积分输入端与积分输出端之间，积分电容CINT与开关S4串接，且积分电容CINT及开关S4也耦接于积分电路100的积分输入端与积分输出端之间。藉由控制开关S3、S4的导通状态，即可控制积分电路100(或电容感测电路10)的一操作模式。举例来说，于电容感测电路10的一重置(Reset)模式中，开关S3、S4皆导通；而于电容感测电路10的一积分模式中(即当积分电路100进行积分操作时)，开关S3断开而开关S4导通。若需终止积分电路100的积分操作，逻辑电路102可产生控制信号使开关S4断开。
当积分电路100进行积分操作(即积分电路100操作于积分模式)时，于一时脉(Clock)周期T中的一前半周期(对应第一时间)，开关S1导通(ON)而开关S2断开(OFF)，接触电容Cf充电至正电压VDD；于时脉周期T中的一后半周期(对应第二时间)，开关S1断开而开关S2导通，储存于接触电容Cf的电荷流至积分电容CINT，换句话说，当积分电路100进行积分操作时，积分输出电压VOUT会随时间递减。
另外，电压抬升电路104包含开关S5、S6以及一抬升电容CDAC，抬升电容CDAC的一端耦接于积分输入端，另一端耦接于开关S5、S6。开关S5及开关S6分别接收正电压VDD及一接地电压GND。另外，控制电路106耦接于电压抬升电路104与比较器comp的比较输出端之间，当积分输出电压VOUT小于参考电压VREF时，比较器comp转态，此时控制电路106产生控制信号(未绘示于图1)来控制开关S5、S6，使得积分输出电压VOUT增加特定电压值VK(即积分输出电压VOUT增加至一电压VREF+VK)。具体来说，于积分输出电压VOUT递减以至于积分输出电压VOUT小于参考电压VREF后的下一个时脉周期T’中，控制电路106控制开关S5于时脉周期T’的一前半周期(对应第一时间)导通且于时脉周期T’的一后半周期(对应第二时间)断开，控制电路106控制而开关S6于时脉周期T’的前半周期断开且于时脉周期T’的后半周期导通。也就是说，于积分输出电压VOUT因积分而递减，以至于积分输出电压VOUT小于参考电压VREF后的瞬间(即时脉周期T’中)，积分输出电压VOUT即可增加至电压VREF+VK。如此一来，积分输出电压VOUT的值将会被限制在电压VREF+VK与电压VREF之间。
另一方面，当积分电路100进行积分操作(即积分电路100操作于积分模式)，积分输出电压VOUT递减以至于积分输出电压VOUT小于参考电压VREF时，比较器comp转态，计数器cntr的值就会加1，此时控制电路106产生控制信号， 使得积分输出电压VOUT增加特定电压值VK(即积分输出电压VOUT增加至电压VREF+VK)。接着，积分电路100即可由增加后的电压VREF+VK继续进行积分，即积分输出电压VOUT自电压VREF+VK持续递减，直到下一次积分输出电压VOUT小于参考电压VREF时，计数器cntr的值再次加1，控制电路106再次产生控制信号，使得积分输出电压VOUT再次增加特定电压值VK。如此周而复始，直到逻辑电路102判断计数器cntr所输出的累计次数NOUT等于预定次数NTH时，逻辑电路102产生控制信号以终止积分电路100的积分操作，并输出积分时间TOUT。
由于接触电容Cf的电容值与积分时间TOUT-呈反比，对相同的预定次数NTH而言，积分时间TOUT越小代表接触电容Cf的电容值越大。因此，电容感测电路10的一后端电路(未绘示于图1)即可根据积分时间TOUT判断接触电容Cf的电容值。
具体来说，请参考图2，图2为电容感测电路10分别对一接触电容Cf_1及一接触电容Cf_2进行电容感测所产生的一积分输出电压VOUT_1及一积分输出电压VOUT_2的波形图，其中接触电容Cf_1与接触电容Cf_2具有不同的电容值，虚线代表积分输出电压VOUT_1的波形图，而实线代表积分输出电压VOUT_2的波形图。由图2可知，电容感测电路10于一时间t0开始进行积分操作(或开始进入积分模式)，当电容感测电路10对接触电容Cf_1进行电容感测时，随着积分电路100持续积分，比较器comp一次又一次地转态，直到一时间t1，即当计数器cntr所累计(对应于接触电容Cf_1)的一累计次数NOUT_1达到预定次数NTH时，逻辑电路102输出一积分时间TOUT_1(其中积分时间TOUT_1即积分电路100开始进行积分操作的时间t0到终止积分操作的时间t1)。同样地，当电容感测电路10对接触电容Cf_2进行电容感测时，随着积分电路100持续积分，比较器comp一次又一次地转态，直到一时间t2，即当计数器cntr所累计(对 应于接触电容Cf_2)的一累计次数NOUT_2达到预定次数NTH时，逻辑电路102输出一积分时间TOUT_2(其中积分时间TOUT_1即积分电路100开始进行积分操作的时间t0到终止积分操作的时间t2)。在此情形下，电容感测电路10的后端电路即可根据积分时间TOUT_1、TOUT_2分别判断接触电容Cf_1、Cf_2的电容值。
简言之，本发明利用电压抬升电路104及控制电路106，将积分输出电压VOUT的值限制在电压VREF+VK与电压VREF之间；利用计数器cntr，计算比较器comp转态的次数；利用逻辑电路102，判断计数器cntr所输出的累计次数NOUT是否达到预定次数NTH，当累计次数NOUT达到预定次数NTH时，逻辑电路102输出积分时间TOUT，而电容感测电路10的后端电路即可根据积分时间TOUT判断接触电容Cf的电容值。
习知电容感测电路需将接触电容中所储存的电荷转换成一模拟电压信号，并透过一模拟数字转换器(Analog to Digital Convertor，ADC)将模拟电压信号转换成数字电压信号，然而，模拟数字转换器的电路结构复杂，且占据大幅电路面积。相较之下，本发明的电容感测电路在不使用模拟数字转换器的情况下，将接触电容中所储存的电荷转换成时间信号(即积分时间TOUT)，而后端电路即可根据积分时间TOUT判断接触电容的电容值，进而判断有无触控事件发生，或判断电容感测电路对应于指纹的纹蜂(Finger Ridge)或纹谷(Finger Valley)，以进行指纹辨识。
综上所述，本发明的电容感测电路可将接触电容中所储存的电荷转换成时间信号，而不需使用传统模拟数字转换器，根据本发明电容感测电路所输出的积分时间，即可判断接触电容的电容值。因此，本发明的电容感测电路具有电路结构简单、电路面积小、成本低以及低功耗的优点。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种电容感测电路，用来感测一接触电容，其特征在于，所述电容感测电路包括：
    一取样保持电路，耦接于所述接触电容；
    一积分电路，包含有：
    一积分输入端，耦接于所述取样保持电路；以及
    一积分输出端，用来输出一积分输出电压；
    一比较器，包含有：
    一第一输入端，耦接于所述积分输出端；
    一第二输入端，用来接收一参考电压；以及
    一比较输出端；
    一计数器，耦接于所述比较输出端，用来累计所述比较器转态的一累计次数；
    一电压抬升电路，耦接于所述积分输入端，用来于所述比较器转态时，将所述积分输出电压增加一特定值；以及
    一逻辑电路，耦接于所述计数器，当所述累计次数等于一预定次数时，所述逻辑电路输出所述积分电路的一积分时间；
    其中，所述积分时间相关于所述接触电容的一电容值。
  2. 如权利要求1所述的电容感测电路，其特征在于，当所述累计次数等于所述预定次数时，所述逻辑电路产生一控制信号以终止所述积分电路的积分操作。
  3. 如权利要求2所述的电容感测电路，其特征在于，所述积分时间为所述积分电路自开始进行积分操作至终止积分操作所经历的时间。
  4. 如权利要求1-3任一项所述的电容感测电路，其特征在于，所述取样保持电路包含：
    一第一开关，其一端接收一正电压，另一端耦接于所述接触电容；以及
    一第二开关，其一端耦接于所述接触电容，另一端耦接于所述积分输入端；
    其中，于一第一时间，所述第一开关导通而所述第二开关断开；以及于一第二时间，所述第一开关断开而所述第二开关导通。
  5. 如权利要求1-4任一项所述的电容感测电路，其特征在于，所述积分电路包含有：
    一放大器；
    一第三开关，耦接于所述积分输入端与所述积分输出端之间；
    一积分电容，耦接于所述积分输入端与所述积分输出端之间；以及
    一第四开关，其一端耦接于所述积分电容，另一端耦接于所述积分输出端。
  6. 如权利要求5所述的电容感测电路，其特征在于，于所述电容感测电路的一重置模式时，所述第三开关及所述第四开关导通；以及于所述积分电路进行积分操作时，所述第三开关断开而所述第四开关导通。
  7. 如权利要求1-6任一项所述的电容感测电路，其特征在于，所述电压抬升电路包含：
    一抬升电容，耦接于所述积分输入端；
    一第五开关，其一端接收一正电压，另一端耦接于所述抬升电容；以及
    一第六开关，其一端接收一接地电压，另一端耦接于所述抬升电容。
  8. 如权利要求7所述的电容感测电路，其特征在于，另包含一控制电路，其中于一第一时间，所述控制电路控制所述第五开关导通而控制所述第六开关断开；以及于一第二时间，所述控制电路控制所述第五开关断开而控制所述第六开关导通。
PCT/CN2016/100452 2016-09-27 2016-09-27 电容感测电路 WO2018058335A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/CN2016/100452 WO2018058335A1 (zh) 2016-09-27 2016-09-27 电容感测电路
KR1020177029860A KR102032890B1 (ko) 2016-09-27 2016-09-27 정전용량 감지 회로
EP16898879.8A EP3324331B1 (en) 2016-09-27 2016-09-27 Capacitive sensing circuit
CN201680001054.7A CN106663200A (zh) 2016-09-27 2016-09-27 电容感测电路
US15/784,075 US10565420B2 (en) 2016-09-27 2017-10-13 Capacitive sensing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/100452 WO2018058335A1 (zh) 2016-09-27 2016-09-27 电容感测电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/784,075 Continuation US10565420B2 (en) 2016-09-27 2017-10-13 Capacitive sensing circuit

Publications (1)

Publication Number Publication Date
WO2018058335A1 true WO2018058335A1 (zh) 2018-04-05

Family

ID=58839093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/100452 WO2018058335A1 (zh) 2016-09-27 2016-09-27 电容感测电路

Country Status (5)

Country Link
US (1) US10565420B2 (zh)
EP (1) EP3324331B1 (zh)
KR (1) KR102032890B1 (zh)
CN (1) CN106663200A (zh)
WO (1) WO2018058335A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3351948B1 (en) 2016-11-22 2019-08-28 Shenzhen Goodix Technology Co., Ltd. Capacitance sensing circuit and fingerprint identification system
CN107980142B (zh) * 2017-11-01 2021-07-20 深圳市汇顶科技股份有限公司 一种指纹识别电路、指纹传感器及移动终端
US11067672B2 (en) 2018-06-19 2021-07-20 Waymo Llc Shared sample and convert capacitor architecture
CN111162768B (zh) * 2018-11-07 2023-01-31 台达电子工业股份有限公司 控制装置及方法
WO2021203418A1 (zh) * 2020-04-10 2021-10-14 京东方科技集团股份有限公司 指纹识别检测电路及其控制方法、指纹识别控制芯片
GB202014008D0 (en) * 2020-09-07 2020-10-21 Touch Biometrix Ltd Biometric skin contact sensor and methods of operating a biometric skin contact sensor
GB202014011D0 (en) 2020-09-07 2020-10-21 Touch Biometrix Ltd Biometric skin contact sensor and methods of operating a biometric skin contact sensor
GB202014049D0 (en) 2020-09-07 2020-10-21 Touch Biometrix Ltd Biometric skin contact sensor and methods of operating a biometric skin contact sensor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1308878A2 (en) * 2001-11-02 2003-05-07 STMicroelectronics, Inc. Capacitive sensor element for fingerprint sensor
CN102954753A (zh) * 2012-10-22 2013-03-06 成都微阵列电子有限责任公司 电容式距离传感器
CN102957404A (zh) * 2012-10-22 2013-03-06 成都微阵列电子有限责任公司 边沿时间读出电路
CN103714330A (zh) * 2014-01-06 2014-04-09 李扬渊 电容指纹传感器
US20150162932A1 (en) * 2013-12-05 2015-06-11 Cypress Semiconductor Corporation Tunable Baseline Compensation Scheme for Touchscreen Controllers

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062075B2 (en) * 2001-05-14 2006-06-13 Nippon Telegraph And Telephone Corporation Surface shape recognition sensor device
JP2003028607A (ja) * 2001-07-12 2003-01-29 Sony Corp 静電容量検出装置およびこれを用いた指紋照合装置
JP2003090703A (ja) * 2001-07-12 2003-03-28 Sharp Corp 凹凸パターン検出器および凹凸パターン検出方法
US7965877B2 (en) * 2005-10-24 2011-06-21 Baohua Qi Fingerprint sensing device using pulse processing
US7511648B2 (en) * 2007-04-23 2009-03-31 Texas Instruments Incorporated Integrating/SAR ADC and method with low integrator swing and low complexity
TWI381173B (zh) * 2008-10-29 2013-01-01 Raydium Semiconductor Corp 電容量測電路及其電容量測方法
CN102200869B (zh) * 2010-03-24 2013-05-08 盛群半导体股份有限公司 电容式触控装置及其感测装置
CN103138762B (zh) * 2011-11-30 2016-04-27 禾瑞亚科技股份有限公司 多阶取样保持电路
US9740343B2 (en) * 2012-04-13 2017-08-22 Apple Inc. Capacitive sensing array modulation
CN103837163A (zh) * 2012-11-26 2014-06-04 矽创电子股份有限公司 电容感测电路
US8982093B2 (en) * 2012-12-20 2015-03-17 Broadcom Corporation Capacitive touch sensing system with interference rejection
EP3090384B1 (en) * 2014-10-13 2024-02-14 Shenzhen Goodix Technology Co., Ltd. Sensor pixel circuitry for fingerprint identification
CN105046194B (zh) * 2015-06-08 2020-04-10 苏州迈瑞微电子有限公司 一种包含积分器的电容指纹传感器
WO2017076292A1 (en) * 2015-11-02 2017-05-11 Shenzhen Huiding Technology Co., Ltd. Multifunction fingerprint sensor having optical sensing against fingerprint spoofing
WO2017067524A1 (en) * 2015-10-23 2017-04-27 Shenzhen Huiding Technology Co., Ltd. Capacitance detecting sensors and related devices and systems
SE539638C2 (en) * 2016-04-22 2017-10-24 Fingerprint Cards Ab Fingerprint sensing system with adaptive power control
SE1650548A1 (en) * 2016-04-22 2017-10-23 Fingerprint Cards Ab Fingerprint sensing system with sensing reference potential providing circuitry
US10121048B2 (en) * 2016-07-29 2018-11-06 Elan Microelectronics Corporation Operating method for a fingerprint sensing device and fingerprint sensing system
CN106796658A (zh) * 2016-11-21 2017-05-31 深圳市汇顶科技股份有限公司 指纹传感器及电子终端
US10346665B2 (en) * 2017-05-30 2019-07-09 Sunasic Technologies Limited Noise reduced capacitive image sensor and method operating the same
US10205895B2 (en) * 2017-07-05 2019-02-12 Sunasic Technologies Limited Capacitive image sensor with noise reduction feature and method operating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1308878A2 (en) * 2001-11-02 2003-05-07 STMicroelectronics, Inc. Capacitive sensor element for fingerprint sensor
CN102954753A (zh) * 2012-10-22 2013-03-06 成都微阵列电子有限责任公司 电容式距离传感器
CN102957404A (zh) * 2012-10-22 2013-03-06 成都微阵列电子有限责任公司 边沿时间读出电路
US20150162932A1 (en) * 2013-12-05 2015-06-11 Cypress Semiconductor Corporation Tunable Baseline Compensation Scheme for Touchscreen Controllers
CN103714330A (zh) * 2014-01-06 2014-04-09 李扬渊 电容指纹传感器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3324331A4 *

Also Published As

Publication number Publication date
US20180089490A1 (en) 2018-03-29
EP3324331A1 (en) 2018-05-23
EP3324331B1 (en) 2020-11-25
US10565420B2 (en) 2020-02-18
EP3324331A4 (en) 2018-06-20
KR102032890B1 (ko) 2019-10-16
CN106663200A (zh) 2017-05-10
KR20180048446A (ko) 2018-05-10

Similar Documents

Publication Publication Date Title
US10346668B2 (en) Capacitive sensing circuit
WO2018058335A1 (zh) 电容感测电路
CN108700621B (zh) 电容感测电路及指纹辨识系统
WO2017067108A1 (zh) 信号转换电路及指纹识别系统
WO2017016103A1 (zh) 指纹检测电路及指纹辨识系统
WO2018201432A1 (zh) 电压转换装置和指纹检测系统
WO2018119604A1 (zh) 指纹辨识系统
WO2018058337A1 (zh) 指纹辨识系统
TWI793627B (zh) 可規劃喚醒感測組態之電容式指紋晶片及利用其之電子設備
TWI765704B (zh) 電容式指紋感測裝置喚醒方法、電容式指紋感測裝置、觸控顯示面板和資訊處理裝置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20177029860

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2016898879

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16898879

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE