WO2018054492A1

WO2018054492A1 - Calibration device for a direct digital modulator

Info

Publication number: WO2018054492A1
Application number: PCT/EP2016/072748
Authority: WO
Inventors: Pieter PALMERS; Niels Christoffers; Patrick Vandenameele; Johannes Gerardus SAMSOM; Koen Cornelissens
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2016-09-23
Filing date: 2016-09-23
Publication date: 2018-03-29
Also published as: CN109690982B; CN109690982A

Abstract

The disclosure relates to a calibration device (1110) for a direct digital modulator (DDM) (1120), wherein the DDM (1120) comprises a plurality of elements (1121) to generate an output signal (1124) based on a modulation of an input signal (1122) according to a predetermined constellation, the calibration device (1110) comprising: a calibration controller (1111) configured to provide a stimulus (1113) to at least one (1121a) of the elements (1121); and a measurement device (1112) configured to measure an output signal (1124) of the DDM (1120) responsive to the stimulus (1113) provided to the at least one element (1121a), wherein the calibration controller (1111) is configured to provide the stimulus (1113) based on an oscillation signal applied to the input of the DDM (1120) and an anti-phase oscillation signal applied to an error compensation path of the DDM (1120).

Description

Calibration device for a direct digital modulator

TECHNICAL FIELD

The present disclosure relates to a calibration device for a direct digital modulator (DDM), a DDM and a method for calibrating a DDM. BACKGROUND

The effective accuracy in Direct-Digital to RF Modulators (DDRM) employed in wireless transmitters can be degraded due to the fact that the effective contribution of each unit to the output does not correspond to the nominal contribution of such a unit, resulting amongst others in increased noise levels. Especially outside of the desired transmit signal spectrum this can be problematic as it might cause violation of spectral emission requirements or system specifications. The receive band of an FDD (frequency division duplex) system in particular is a problematic spectral region as the receiver is desensitized reducing the usable operation range of the transceiver.

To achieve the specifications for e.g. cellular systems it is necessary to mitigate the errors introduced by the mismatch between expected and effective unit weight. Multiple techniques can be used for this, such as calibration or feed-forward compensation. For these techniques to work it is required that error generated by the DDRM due to the mismatch between units can be quantified one way or the other.

The most common method to measure/calibrate errors in normal DAC's is to directly measure the differences between units by checking their static contribution. This could be used also but does not incorporate dynamic effects that are introduced by the modulation inherent to a DDRM. As factors such as pulse width mismatch affect the way the static error is modulated to RF it is required to measure at RF.

A first measurement method is to directly measure the output of the DDRM for a set of codes using a measurement device connected to the output. As the output power of the DDRM increases with code the limited dynamic range of the measurement device will make that the measurements are less accurate either at the high output codes (if adaptive gain is applied) or at the low output codes (if no adaptive gain is used). This will make the output of such measurement less useful to characterize the random deviations of each element as the measurement error can become larger than the expected error between elements. It is very difficult to design a direct measurement system that can provide the required accuracy under all conditions of output signal.

SUMMARY

It is the object of the invention to improve a DDRM system, in particular to provide a mechanism to measure and calculate mismatches between different units in a DDRM system and to calculate the aggregate errors generated from these unit errors.

This object is achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures. In particular, this object is achieved by determining the deviation of each unit element value from its nominal value using a calibration procedure executed during factory calibration, at transceiver startup or in the background while the system is running. At run-time it is then determined what specific unit elements are turned at any given time and what their combined deviation from the aggregate nominal value is. The calibration procedure employs an indirect measurement technique that avoids generating large signals at the output of the DDRM by compensating the error until the signal at the output is minimized. As such the dynamic range requirement on the measurement receiver can be relaxed. In order to avoid measurement accuracy degradation due to e.g. LO (local oscillator) feedthrough and 1/f noise the measurement technique modulates the error to a side-band. A receiver is used to measure the output signal. For this a low-if receiver is used as it allows to separate receiver-induced errors (e.g. nonlinearity) from issues present in the transmit signal.

The basic concept is a measurement technique to create a calibration table containing the error vectors for each possible state of a DDRM. This is done by first comparing unit elements, or simply referred to as "elements" hereinafter, to each other and/or to a common reference using either a direct measurement or an indirect measurement technique. From these comparison results an aggregate error vector is calculated for each DDRM state by summing the contribution of all unit elements that are turned on. The indirect measurement technique employs a compensation path of which the signal is tuned to cancel the signal generated by the unit elements under comparison. By choosing the input signals to the unit elements appropriately the signal generated by the compensation path contains (amongst others) the error between the slices and can be used to calculate this error.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

RF: Radio Frequency

DDM: Direct-Digital Modulator

DDRM: Direct-Digital RF Modulator

ADC: Analog-to-Digital Converter

DAC: Digital-to-Analog Converter

1: ln-phase component

Q: Quadrature component

LO: Local Oscillator

ErrorDAC: Error feed-forward path with DAC

INL: integral nonlinearity

DNL: differential nonlinearity

A Direct-Digital RF Modulator is a wireless transmitter circuit that directly modulates a digital baseband signal onto an RF carrier frequency. This is done by multiplying the baseband signal with a signal that contains a strong frequency component at the desired RF frequency (also referred to as the Local Oscillator). A Direct-Digital Modulator is a transmitter circuit that directly modulates a digital signal, e.g. a digital baseband signal, onto a carrier frequency, e.g. an RF carrier frequency.

Figure 1 illustrates the quadrature up-converter chain 100. In most modern transmitters the starting point is baseband data (l,Q) in a digital representation. This digital baseband data is converted into an analog equivalent signal by a baseband Digital-to-Analog converter (DAC) 101 . It is followed by a reconstruction filter 103 that is then used to remove the artifacts due to the digital nature of the source signal such as aliases and quantization noise. Furthermore, the filter removes all effects of non-idealities from the D/A converter itself, e.g. mismatch noise, thermal noise and out-of-band distortion components that fall outside of the filter bandwidth. The filtered signal is then applied to the quadrature mixer 105 that performs a multiplication with the Local Oscillator (LO). The resulting RF signal is then amplified with an amplification stage 107, 109 that consists of one or more amplifiers, eventually delivering the power to the antenna 1 1 1 . A conceptual representation of the up-conversion and amplification stage 200 is shown in figure 2. The analog baseband signal is shown by the graph 201 (in-phase) and the graph

202 (quadrature). The solid line represents the positive signal in a differential signal pair, while the dashed lines are the opposite sign. One way to implement an up-conversion operation of such a baseband signal with a given LO having frequency FLO is to split the LO period into 4 equal parts, each with a length of T4LO = 0.25/FLO. It can be shown that alternating between the positive in-phase 201 , positive quadrature 202, negative in-phase

203 and negative quadrature 204 signals in one LO period will implement an up-conversion of the complex baseband signal to the LO frequency. The RF output 205 of such a mixer can then be fed into an amplifier that is biased 206 e.g. in Class-AB operation.

Fig. 3 shows a block diagram illustrating a DDRM based transmitter 300. The DDRM differs from a traditional quadrature up-conversion chain by the fact that the digital signal is first mixed 307 to LO and then recombined into an RF signal. First the digital baseband signal (I, Q) is digitally up-sampled 301 and digitally filtered 303 to ensure proper quantization noise performance and sufficient alias distance. Afterwards it is applied directly to the DDRM 305 that combines the functions of the DAC, mixer and first amplification stage. The DDRM 305 basically is a combination of several weighted slices consisting of a mixer and a power generation block. Based upon the magnitude of the baseband data a number of these slices are enabled in such a way that the signal presented to the antenna 31 1 corresponds to the desired signal.

As illustrated by figure 4 the output waveforms 400 can be very similar to those of a traditional TX. The analog baseband signal is shown by the graphs 401 (positive in-phase), 402 (negative in-phase), 403 (positive quadrature) and 404 (negative quadrature).

The transmitter output over time can also be represented as a trajectory 504 through the baseband equivalent constellation diagram 500 in which every point represents a state of the transmitter in time as indicated in figure 5. Points 501 represent the quantized ideal DDRM constellation points; points 502 represent the baseband constellation points and points 503 represent the sampled trajectory points. The generation of a modulated signal can be represented by following a certain trajectory over time, as indicated by the line 504. An ideal transmitter traverses such a trajectory with infinite precision and infinitesimal small time steps. In a time discrete, amplitude continuous transmitter the change in state happens at regular time intervals as shown by the crossed circles 503 that represent the sampled trajectory points in such a transmitter. Such a transmitter can still take on any state required, but it can only change from one state to another at specific points in time. The analog voltage sampling TX described before is such a transmitter. It has a continuous set of amplitude states for both I (in-phase) and Q (quadrature) signals, but the transition between one (I, Q) pair to the next happens only every LO period. A DDRM is not only time discrete, but also amplitude discrete and hence the set of available states is discrete as indicated by the grid of circles 503. In a DDRM the sampled trajectory point is rounded to the nearest available constellation point 502 resulting in an error vector 505. This error vector 505 is the quantization error in the DDRM. In addition to the quantization error the imperfect manufacturing will make that the effective state of the DDRM will be slightly different than the expected state as illustrated in figure 6. The constellation point 602 generated by a DDRM for a given state configuration will differ for each manufactured device from the ideal DDRM constellation point 601. This yields an additional error vector that is the mismatch error.

According to a first aspect, the invention relates to a calibration device for a direct digital modulator (DDM), wherein the DDM comprises a plurality of elements to generate an output signal based on a modulation of an input signal according to a predetermined constellation, the calibration device comprising: a calibration controller configured to provide a stimulus to at least one of the elements; and a measurement device configured to measure an output signal of the DDM responsive to the stimulus provided to the at least one element, wherein the calibration controller is configured to provide the stimulus based on an oscillation signal applied to the input of the DDM and an anti-phase oscillation signal applied to an error compensation path of the DDM.

The calibration device as defined above provides a measurement technique to obtain the error vectors for each possible state of a DDRM. This is done by providing the stimulus to the elements and measuring the output signal of the DDRM in response to the stimulus. From these data an aggregate error vector can be calculated for each DDRM state by summing the contribution of all unit elements that are turned on.

The calibration device thus provides a direct measurement system that can provide the required accuracy under (nearly) all conditions of output signal. In a first possible implementation form of the device according to the first aspect, the calibration controller is configured to perform an aggregate error vector which is calculated by deviation information of each of the elements compared to its nominal value. This provides the advantage that the aggregate error vector can be simply derived by providing the stimulus to each of the elements. In a second possible implementation form of the device according to the first implementation form of the first aspect, the calibration controller is configured to provide the deviation information as a calibration table comprising at least one aggregate error vector.

This provides the advantage that the calibration table can be stored during factory calibration and reused for field calibration of the DDRM.

In a third possible implementation form of the device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the calibration controller is configured to adjust the stimulus provided to the at least one element based on the measured output signal in accordance to a calibration algorithm.

This provides the advantage that an iterative calibration approach can be realized where the accuracy can be improved with each iteration. In a fourth possible implementation form of the device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the calibration controller is configured to adjust a gain factor of the error compensation path in order to obtain a spur-free output signal at the output of the DDM. This provides the advantage that a high accuracy of the DDM can be achieved when providing a spur-free output signal.

In a fifth possible implementation form of the device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the calibration controller is configured to provide the stimulus based on toggling an amplitude code word (ACW), applied to the DDM, between two values, in particular between two contiguous values.

This provides the advantage that the accuracy of the error compensation path of the DDM can be measured and a gain for the error compensation path can be adjusted in order to improve the accuracy of the error-compensated DDM. In a sixth possible implementation form of the device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the calibration controller is configured to provide the stimulus based on an oscillation signal, in particular a clock signal, applied to a first one of the elements and an anti-phase oscillation signal applied to a second one of the elements.

This provides the advantage that an exact reference measurement can be implemented where one element is the reference element and another element is the measurement element. Such a reference measurement provides a high accuracy.

In a seventh possible implementation form of the device according to the sixth

implementation form of the first aspect, the measurement device is configured to measure a mismatch of an output signal of the second element with respect to an output signal of the first element.

This provides the advantage that such a reference measurement does not require external references and yet provides high accurate results.

In an eighth possible implementation form of the device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the

measurement device comprises: a down-mixer connectable to the output of the DDM; and an analog-to-digital converter, coupled to the down-mixer, and configured to provide a measurement value of the output signal of the DDM. This provides the advantage that the output of the DDM can be represented in digital domain where the measurement values can be efficiently stored in a memory.

In a ninth possible implementation form of the device according to the eighth implementation form of the first aspect, the measurement device comprises: a low noise amplifier (LNA) connectable to the output of the DDM or to an output of the down-mixer.

This provides the advantage that the LNA provides an output with low noise, i.e. high accuracy. In a tenth possible implementation form of the device according to the ninth or the eighth implementation form of the first aspect, the measurement device comprises: a filter coupled between the down-mixer and the analog-to-digital converter. This provides the advantage that the filter can shift the noise to a bandwidth that is not disturbing the measurement. In an eleventh possible implementation form of the device according to any of the eighth to the tenth implementation forms of the first aspect, a local oscillator of the measurement device is independent of a local oscillator of the DDM.

This provides the advantage that the measurement device is decoupled from the DDM.

Transmission of undesired harmonics between measurement device and DDM is interrupted, thereby increasing accuracy of the device.

In a twelfth possible implementation form of the device according to any of the eighth to the eleventh implementation forms of the first aspect, the calibration controller is configured to write the measurement value provided by the measurement device to a memory for implementing offline calibration.

This provides the advantage that processing resources of the DDM can be saved when implementing offline calibration.

In a thirteenth possible implementation form of the device according to any of the eighth to the twelfth implementation forms of the first aspect, the calibration controller is configured to control an error compensation path of the DDM based on the measurement value provided by the measurement device for implementing online calibration.

This provides the advantage that fast calibration during runtime of the DDM can be performed, e.g. during operation in the field.

According to a second aspect, the invention relates to a direct digital modulator (DDM), comprising: a plurality of elements, configured to generate an output signal of the DDM based on a modulation of an input signal according to a predetermined constellation; and a calibration device according to the first aspect as such or any one of the implementation forms of the first aspect. The calibration device provides a measurement technique to obtain the error vectors for each possible state of a DDRM. The calibration device thus provides a direct measurement system that can provide the required accuracy under (nearly) all conditions of output signal. A DDM with such a calibration device can achieve a high precision of the resulting constellation points.

According to a third aspect, the invention relates to a method for calibrating a direct digital modulator (DDM), wherein the DDM comprises a plurality of elements to generate an output signal based on a modulation of an input signal according to a predetermined constellation, the method comprising: providing a stimulus to at least one of the elements, wherein the stimulus is based on an oscillation signal and an anti-phase oscillation signal; and measuring an output signal of the DDM responsive to the stimulus provided to the at least one element.

Such a calibration method provides a direct measurement that can provide the required accuracy under (nearly) all conditions of output signal.

In a first possible implementation form of the method according to the third aspect, the method further comprises: performing an aggregate error vector which is calculated by deviation information of each of the elements compared to its nominal value.

This provides the advantage that the aggregate error vector can be simply derived by providing the stimulus to each of the elements.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a block diagram illustrating an analog quadrature up-converter 100;

Fig. 2 shows a graph 200 illustrating exemplary analog up-conversion waveforms over time at a single-ended output;

Fig. 3 shows a block diagram illustrating a DDRM based transmitter 300;

Fig. 4 shows a graph 400 illustrating exemplary output waveforms of a digital transmitter at a single-ended output;

Fig. 5 shows a baseband equivalent constellation diagram 500 illustrating an exemplary trajectory; Fig. 6 shows a constellation diagram 600 illustrating exemplary mismatch errors;

Fig. 7 shows a schematic diagram illustrating an indirect measurement to measure the differential non-linearity (DNL) of an error-compensated DDRM 700 according to an implementation form;

Fig. 8a shows an exemplary spectrum representing the DDRM sidebands and the Error DAC sidebands of an error-compensated DDRM as shown in Fig. 7;

Fig. 8b shows an exemplary spectrum illustrating the resulting signal at the DDRM output for the configuration of Fig. 8a;

Fig. 9 shows a block diagram illustrating mismatched unit current sources representing a DDRM 900 controlled by antiphase LO-signals 901 , 902 according to an implementation form;

Fig. 10 shows a block diagram illustrating a calibration system 1000 including unit cells and calibration blocks required in the digital baseband according to an implementation form;

Fig. 1 1 shows a block diagram illustrating a calibration system 1 100 including a calibration device 1 1 10 and a DDM 1 120 according to a first implementation form;

Fig. 12 shows a block diagram illustrating a calibration system 1200 including a DDRM 1210 and a calibration device with a measurement device 1220, a calibration controller 1230 and an optional memory 1240 according to a second implementation form;

Fig. 13 shows a block diagram illustrating a calibration system 1300 including a DDRM 1310 and a calibration device with a measurement device 1320 and a calibration controller 1330 according to a third implementation form;

Fig. 14 shows a block diagram illustrating a DDRM 1400 according to an implementation form; Fig. 15 shows a constellation diagram 1500 illustrating an exemplary reconstructed DDRM constellation; and Fig. 16 shows a schematic diagram illustrating a method 1600 for calibrating a DDM according to an implementation form.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

In the following devices and method are described that use quantization errors. Quantization is the process of mapping a large set of input values, e.g. analog data to a countable smaller set, e.g. to a set of digital values. Examples of quantization processes are rounding and truncation operations. The quantization error is the difference between an input value and its quantized value, e.g. the round-off error or the truncation error. A quantizer is a device that performs quantization. Examples of a quantizers are analog-to-digital converters or

DDRAMs. Fig. 7 shows a schematic diagram illustrating an indirect measurement to measure the differential non-linearity (DNL) of an error-compensated DDRM 700 according to an implementation form.

The purpose of the measurement is to characterize two things: First, the deviation of each of the elements compared to its nominal value. The nominal value can be equal to its designed- for value or can be any other element that is chosen as reference. Second, the overall nonlinear transfer function of the DDRM. The error-compensated DDRM 700 includes a direct digital radio frequency modulator (DDRM) 701 coupled in parallel to an error compensating digital-to-analog converter (ErrorDAC) 703. An amplitude control word 0 (ACWO) 704, added 705 to an LSB oscillation signal 702, is provided as input signal to the DDRM 701 . The oscillation signal 702, multiplied 707 by a negative step size a, is provided as input signal to the ErrorDAC 703. An output adder 709 adds the output signals 706, 708 of DDRM 701 and ErrorDAC 703 to provide the DNL 710. Figure 7 shows how steps can be measured and at the same time referenced to the compensation path („ErrorDAC") 703 output.

To measure the output step between ACWO and ACW0+1 the ACW put into the DDRM 701 is toggled between the values ACWO and ACW0+1 . An anti-phase oscillation of magnitude a is applied to the ErrorDAC 703. The DDRM 701 will put out a rectangular oscillation 706 of step size Δ , the ErrorDAC 703 an antiphase oscillation 708 of step size a. The resulting output signal of the error-compensated DDRM 700 will be an oscillation 710 of magnitude Δ ^{~ #} . This method shall be referred to as the toggling-method to measure the DNL. The value of a is changed using e.g. numerical optimization techniques while the output oscillation 710 is measured using a measurement device attached to the combined output of the DDRM 701 and ErrorDAC 703, i.e. the output of the error-compensated DDRM 700. As soon as the measured envelope is equal to zero, the programmed value of a is equal to the unknown weight of the elements being toggled and the ErrorDAC unit value. Note that a can be a complex value in which case phase and/or delay effects can also be measured.

Also note that the signals depicted in Figure 7 are equivalent baseband-signals. So, a signal that is actually at the carrier frequency would be represented by a DC-signal in the notation used in Figure 7. The oscillation 702 applied to both DDRM 701 and ErrorDAC 703 is actually a double side-band modulation of the carrier. Such a modulation is much easier to detect and measure than is a static carrier; the down-conversion of a static carrier would be impeded by typical direct-down-conversion receiver impairments like LO-leakage, DC-offsets and 1/f-noise. Moreover, the target is to minimize the modulation visible at the RF-DAC output. As it is ideally 0 also the input to any potential nonlinearity of a calibration receiver path is ideally 0. So, for this kind of measurement it is conceivable that the linearity spec of a calibration receiver is not very tight. A generalization of this method is to toggle between an arbitrary ACW code and one code higher: toggling between ACWk and ACWk+1 (generalized toggling method). The same ErrorDAC control can be used. This method can be used if the DDRM doesn't have individual control of current sources in which case the other methods cannot be used.

The main advantage is that an integral non-linearity (INL) measurement can be performed this way, as the total level of the code can be measured directly. However, it also means that a large output LO tone is appearing at the output. The small oscillation amplitude shall be detected next to this tone. This leads to a desensitization specification for the

measurement device that can become very stringent, yielding it impractical to use this method for all possible ACW codes in high-accuracy applications.

Fig. 8a shows an exemplary spectrum representing the DDRM sidebands and the Error DAC sidebands of an error-compensated DDRM as shown in Fig. 7 according to the toggling method. Fig. 8b shows an exemplary spectrum illustrating the resulting signal at the DDRM output for the configuration of Fig. 8a. Figure 8a and 8b show the frequency domain signals at the DDRM 701 and error-DAC 703 input as well as the DDRM 701 output for ^Δ = ^α . In this case DDRM 701 and error-DAC 703 cancel perfectly and only noise can be measured at the DDRM 701 output (see Fig. 8a). In case they don't cancel ( Δ≠ a ) many spurs can be measured set off from the carrier at the DDRM 701 output (see Fig. 8b). Thus, the step A can be measured indirectly finding a in such a way that the output of the DDRM is spur free.

Fig. 9 shows a block diagram illustrating mismatched unit current sources 910 representing a DDRM 900 controlled by antiphase LO-signals 901 , 902 according to an implementation form.

The array 910 of N mismatched current sources (also referred to as current cells) 910a, 910b, 910c, 91 Od, 91 Oe and 91 Of is driving a resonant load 912. The first current source 910a is used as a reference. The mismatch of the nth DNL current idni.n with respect to the reference current source 910a is measured. To do so the reference current source 910a and the current source to measure will be modulated with antiphase clock signals 901 , 902. As a result only the mismatch current idni.n will flow to the resonant load 912 and cause there a voltage Vdni.nfrom which the mismatch current can be inferred. Note that in another implementation, the sign of the current idni.n is modulated in order to offset it from the carrier. The error current idni.n can be measured by measuring the voltage generated over the load 912 using a measurement device connected to the output 913, e.g. as described below with respect to Figures 10 to 13. The error can be related to a common reference by also measuring the chosen reference cell.

Instead of directly measuring the error current, in another implementation, an antiphase compensation signal similar to the toggling methods described before is generated. In this case the aim is to find a gain factor a that makes the voltage measured at the output equal to 0 while applying the modulation signals as described above with respect to Figures 7 to 9.

The gain factor will then be a measure of the magnitude of the error expressed in ErrorDAC units. This can then be converted towards an arbitrary reference by measuring that reference with a toggling test. Fig. 10 shows a block diagram illustrating a calibration system 1000 including unit cells and calibration blocks required in the digital baseband according to an implementation form.

Figure 10 shows the digital system 1000 to be used for calibration along with the set of current cells 1010, the modulating AND-gates 1008, the re-timing flip flops 1007 and the digital baseband 1001 used in transmission mode operation. A layer of multiplexers 1006 is between the re-timing flip flops 1007 and the remainder of the digital base band 1001. These multiplexers 1006 are configured per unit cell using a source selection register 1005. The source selection register 1005 decides whether a unit cell of the set of current cells 1010 receives its data from the transmission mode TX digital baseband 1001 or one of two ternary memories 1003, 1004 that belong to the calibration mode digital baseband 1002. Each of the ternary memories 1003, 1004 hold a sequence of numbers that can be either -1 ,0, or 1. In calibration mode, these sequences get transmitted to the multiplexers 1006 and from there they are forwarded to individual current cells of the set of current cells 1010 following the settings in the source selection register 1005. That way a number of individual current cells of the set of current cells 1010 can be driven by the sequence stored in memory I 1003 whereas another group of individual cells of the set of current cells 1010 can be driven by the sequence stored in memory II 1004. The remainder of the cells of the set of current cells 1010 still receive their input from the transmission mode digital baseband 1001 , which can be programmed to any output value (e.g. 0,1 or a particular signal). The structure shown in Fig.10 allows applying any of the test signals mentioned above with respect to Figures 7 to 9 to individual cells or individual groups of current cells from the set of current cells 1010. Fig.11 shows a block diagram illustrating a calibration system 1100 including a calibration device 1110 and a DDM 1120 according to a first implementation form. The DDM 1120 includes a plurality of elements 1121, also called unit elements or current cells, to generate an output signal 1124 based on a modulation of an input signal 1122 according to a predetermined constellation. The calibration device 1110 includes a calibration controller 1111 and a measurement device 1112. The calibration controller 1111 provides a stimulus 1113 to at least one 1121a of the elements 1121. The measurement device 1112 measures an output signal 1124 of the DDM 1120 responsive to the stimulus 1113 provided to the at least one element 1121a. The calibration controller 1111 provides the stimulus 1113 based on an oscillation signal applied to the input of the DDM 1120 and an anti-phase oscillation signal applied to an error compensation path of the DDM 1120.

The calibration controller 1111 may perform an aggregate error vector which is calculated by deviation information of each of the elements 1121 compared to its nominal value. The calibration controller 1111 may provide the deviation information as a calibration table comprising at least one aggregate error vector. The calibration controller 1111 may adjust the stimulus 1113 provided to the at least one element 1121a based on the measured output signal 1124 in accordance to a calibration algorithm. The calibration controller 1111 may adjust a gain factor of the error compensation path in order to obtain a spur-free output signal 1124 at the output of the DDM 1120. The calibration controller 1111 may provide the stimulus 1113 based on toggling an amplitude code word (ACW), applied to the DDM 1120, between two values, in particular between two contiguous values, e.g. as described above with respect to Fig.7. The calibration controller 1111 may provide the stimulus 1113 based on an oscillation signal, in particular a clock signal, applied to a first one 1121 a of the elements 1121 and an anti-phase oscillation signal applied to a second one 1121b of the elements 1121.

The measurement device 1112 may measure a mismatch of an output signal of the second element 1121b with respect to an output signal of the first element 1121a, e.g. as described above with respect to Fig.9.

The measurement device 1112 may include: a down-mixer, e.g. as down-mixer 1222 as described below with respect to Fig.12, connectable to the output of the DDM 1120; and an analog-to-digital converter, e.g. an AD-converter 1225 as described below with respect to Fig. 12, coupled to the down-mixer 1222, and configured to provide a measurement value of the output signal of the DDM 1 120. The measurement device 1 1 12 may further include a low noise amplifier (LNA) connectable to the output of the DDM 1 120 or to an output of the down- mixer, e.g. as described below with respect to Fig. 12. The measurement device 1 1 12 may further include a filter coupled between the down-mixer and the analog-to-digital converter, e.g. as described below with respect to Fig. 12.

A local oscillator of the measurement device 1 1 12 may be independent of a local oscillator of the DDM 1 120.

The calibration controller 1 1 1 1 may be configured to write the measurement value provided by the measurement device 1 1 12 to a memory for implementing offline calibration, e.g. as described below with respect to Fig. 12.

The calibration controller 1 1 1 1 may be configured to control an error compensation path of the DDM, e.g. an error compensation path 1212, 1214 of the DDM 1210 as described below with respect to Fig. 12, based on the measurement value provided by the measurement device 1 1 12 for implementing online calibration.

Figure 1 1 also shows a direct digital modulator (DDM) 1 120 including a plurality of elements 1 121 , configured to generate an output signal 1 124 of the DDM 1 120 based on a modulation of an input signal 1 122 according to a predetermined constellation; and a calibration device 1 1 10 as described above.

Fig. 12 shows a block diagram illustrating a calibration system 1200 including a DDRM 1210 and a calibration device with a measurement device 1220, a calibration controller 1230 and an optional memory 1240 according to a second implementation form. The calibration system 1200 is an exemplary implementation of the calibration system 1 100 described above with respect to Fig. 1 1. The calibration device includes a measurement device 1220, a calibration controller 1230 and a measurement receiver (MRX) 1240. The measurement device 1220 is coupled to an output of the DDRM 1210 and the calibration controller 1230 is coupled between an output of the measurement device 1220 and an input of the DDRM 1210, thereby forming a calibration loop. The MRX 1240 is coupled to an output of the measurement device 1220. The MRX 1240 output can be written to a memory or the calibration loop can be digitally implemented. The DDRM 1210 may be realized as an error- compensated DDRM as described above with respect to Fig. 7. The DDRM 1210 may include an in-phase path including an in-phase DDRM 121 1 and an in-phase ErrorDAC 1212 and a quadrature path including a quadrature DDRM 1213 and a quadrature ErrorDAC 1214.

In an implementation form of the calibration system 1200 as shown in Fig. 12, the

measurement device 1220 may include a Low-Noise Amplifier (LNA) 1221 , a down-mixer 1222, a gain & filter stage 1224 and an Analog-to-Digital Converter (ADC) 1225. The LNA 1221 is optional and the gain & filter stage 1224 is optional. I.e. in an alternative

implementation form, the measurement device 1220 may include a down-mixer 1222 and an Analog-to-Digital Converter (ADC) 1225.

The calibration controller 1230 may be implemented as a stage including a unit for generating a join complex number 1233 from the in-phase and quadrature outputs of the measurement device 1220 which are measured by the MRX 1240, a digital down-mixer 1232 and an integrator 1231 .

One important aspect is that the local oscillator (LO) used for the measurement path, i.e. the path measured by the measurement device 1220, can be independent of the transmitter LO; in other words, a low-IF (intermediate frequency) down-mixing can be used. Doing so will allow frequency planning to avoid folding the different RF harmonics of the test signal on top of each other at baseband. Hence the error contribution at different RF harmonics can be separated digitally and if required only the contribution in the band of interest can be used to steer the calibration. This is an important technique to end up with a feasible calibration loop.

The MRX 1240 output can be written to a memory (not shown in Fig. 12), allowing to implement the calibration 'off-line' (e.g. in Matlab). Alternatively the control loop, i.e. path through the calibration controller 1230, can be closed on-chip directly controlling the on-chip ErrorDac controller.

When implementing calibration with the memory, operation is as follows: The DDRM 1210 is generating a certain signal. The MRX 1240 is activated and the down-mixed signal is digitized by the ADC 1225 and written to the memory. The memory content is then read out and further processed by down-mixing 1232 and filtering the signals to DC and integrating 1231 to yield an error estimate 1234. A new set of errdac inputs are calculated from this that are expected to minimize the error and a new run is done. This may be iterated until the error measurement 1234 is small enough. With the hardware calibration loop, operation is as follows: At the beginning of the calibration all blocks are switched on, including a DDRM 1210 input. The DDRM 121 1 , 1213 puts out a signal and the ErrorDAC 1212, 1214 is trying to cancel that signal to zero. The error on this cancellation is measured by the calibration receiver, i.e. measurement device 1220, digitized by the ADCs 1225, mixed 1232 to DC, integrated 1231 and fed back to the ErrorDAC 1212, 1214 input. After some time the loop settles and the stabilized input of the ErrorDAC 1212, 1214 can be read off and post-processed to extract the DNL.

The DDRM stimuli can be chosen in such a way that information can be gathered about individual DNLs. The following DDRM inputs can be applied during operation of the calibration loop: 1 ) Toggling between two neighboring control words ACW0 and ACWO+1 ; 2) Toggling between the states all LSB cells on, all MSBs off and all LSB cells off, a specific MSB cell on; and 3) Two cells of equal weight active at different phases, the active phase being toggled to offset the generated signal from the carrier.

Fig. 13 shows a block diagram illustrating a calibration system 1300 including a DDRM 1310 and a calibration device with a measurement device 1320 and a calibration controller 1330 according to a third implementation form. The calibration system 1300 is an exemplary implementation of the calibration system 1 100 described above with respect to Fig. 1 1 .

The calibration device includes a measurement device 1320, a calibration controller 1330 and a measurement receiver (MRX) (not shown in Fig. 13). The measurement device 1320 is coupled to an output of the DDRM 1310 and the calibration controller 1330 is coupled between an output of the measurement device 1320 and an input of the DDRM 1310, thereby forming a calibration loop. The DDRM 1310 may be realized as an error- compensated DDRM as described above with respect to Fig. 7. The DDRM 1310 may include an in-phase path including an in-phase DDRM 131 1 and a quadrature path including a quadrature DDRM 1312. The DDRM 1310 may further include an ErrorDAC 1313 for error compensation of both, in-phase and quadrature paths.

As an alternative to the full receiver 1222, 1223, 1224 shown in Fig. 12, a rectifier 1321 may be used. The measurement device 1320 may include the rectifier 1321 , a tunable amplifier 1322 and an ADC 1323 to provide the measurement signal. The calibration controller 1330 may include a mixer 1331 mixing the measurement signal of the ADC 1323 by a complex carrier signal 1332 and a calibration algorithm 1338 for evaluating the complex signal. Depending on the evaluation, a measurement value 1335 may be output and a stimulus 1334 may be provided to the input of the DDRM 1310. A number of iterations for running the calibration loop may be determined by the calibration controller 1310, in particular by the calibration algorithm 1338. The calibration system 1300 differs from the calibration system 1200 shown above in Fig. 12 that the DDRM 1310 is calibrated by using a rectifier 1321 . The calibration receiver 1222, 1223, 1224 is replaced by a (simpler) rectifier 1321 . Only one ADC 1323 is used to process its output. At the rectifier 1321 the output spectrum of the DDRM 1310 mixes with itself to DC. The stimulus 1334 makes sure that the output of the DDRM 1310 contains a strong carrier and a spur offset from this, from which amplitude the DNL can be concluded. Again the ErrorDAC 1313 input canceling that spur will be the measured value.

In one implementation of the calibration device, the calibration algorithm 1333 works as follows:

Step 1 : errorDAC 1313 off, DDRM 1310 generates spur and carrier, measure

amplitude using rectifier 1321 , ADC 1323, mixer 1332

Step 2: errorDAC 1313 on, DDRM 1310 generates only carrier (DC input), measure

Step 3: errorDAC 1313 on, DDRM 1310 generates spur and carrier, measure

Step 4: find ideal error-DAC 1313 input from the previous 3 measurements using a numerical search algorithm such as triangulation.

Step 5: error-DAC 1313 canceled the spur? If not, go back to Step 1

Step 6: measurement done.

Such a solution provides the advantage of saving chip-area.

Fig. 14 shows a block diagram illustrating a DDRM 1400 according to an implementation form. The DDRM 1400 includes a digital front end 1410, an LSB 1430 and an MSB section 1420 which outputs are connected to a load 912. The LSB 1430 section comprises a plurality of current cells 1431 , e.g. a number of NLSB current cells. The MSB 1420 section comprises a plurality of current cells 1421 , e.g. a number of NMSB current cells. The aim of the calibration is to express all the LSB and MSB cells in terms of a single reference. The reference itself may be not exactly known in Volts or Amperes. However, its error translates into a mere amplitude error at the DDRM output that may be compensated. There will not be excessive out of band emissions because of an amplitude error of the reference.

In one implementation of the DDRM 1400 the LSB section 1430 consists of 5 binary weighted current-cells 1431 . Provided there would be an option to connect the control signal of each of these individually to ground, a positive or a negative LO-signal individual LSB- section-cells could be compared against the sum of all lower-significant cells. The nominal result of these comparisons would always be 1 LSB. As a consequence, it is not possible to generate a signal that is nominally zero. At the LO-frequency there would always be a carrier signal impacting the dynamic range specification of the calibration receiver.

To be able to generate a signal that is nominally 0 with no component at the LO-frequency a dummy LSB can be added. This dummy LSB can be characterized using the toggling- method as described above with respect to Fig. 7. Therefore, at least for the characterization of the dummy-cell the calibration receiver has to be done in the presence of a relatively strong blocker.

In one implementation, binary coded LSB vs LSB measurements may be performed as follows: Let the actual outputs of the LSB-cells be w_n · i_ref + i_mm,n, where w_n is the weight of the LSB cell, 2^n"1, i_mm,n is the mismatch current, and i_ref is the nominal output current for one LSB. Let /^'o = iref + i_mm,o be the current an extra dummy cell.

In the binary coded case the measurements i_mm,_n can be generated through direct cell comparison:

Note that the equation system above contains NLSB equations for NLSB+ 1 unknowns. The additional unknown is the mismatch of the dummy cell. The mismatch of that can be found using the toggling method as described above with respect to Fig. 7.

In one implementation, MSBs versus MSBs, and unary coded LSBs versus LSBs

measurements may be performed as follows: Let the actual outputs of the unary coded be hef + nm,n. . for unary coded LSBs or MSBs, l_mm,n is the mismatch current, and l_ref is the nominal output current for one unary. In the binary coded case the measurements r_mmn can be generated:

Note that the Equation system above contains N-1 equations for N-1 unknowns.

In one implementation, all LSBs versus 1 MSB measurements may be performed as follows: Let the unary-mismatches I mm.MSB.n be the mismatches of the MSB cells 1421 . Assume a dummy cell belongs to the LSBs 1431 and the nominal sum of all LSBs 1431 is one MSB. So, it is possible to compare the sum of all LSB mismatches to l_mm,MSB,n using direct unit cell comparison.

In the following, interpolation to derive data from measurements at different frequencies is described. The characterization techniques described above measure mismatch between the first harmonic outputs of different DDRM elements. As such this mismatch is frequency dependent.

The 1 ^st harmonic of the output current in time domain current is

ii(t) = ^■ [i_ref + Ai)^■ sin (π^■ -^- + π^■ Δτ · f_LO ^■ cos(2 · π^■ f_lot + φ₀ + 2 · π^■ At_p ^■ f_L0), where

0o = 2 · π^■ t_p ^■ f_L0

When— is kept at 0.25 the time domain output changes its phase linearly with LO frequency and its amplitude sinusoidally with LO frequency.

This effect is exploited to reduce the amount of measurements required to calculate calibration tables at different LO frequencies. The measurements are done at two LO frequencies, typically the maximum and minimum frequency of the band of interest.

Afterwards the tables at a given LO frequency are calculated by applying the relations above.

The following terms apply:

At_p Deviation from nominal pulse position

due to mismatch

ef Nominal pulse magnitude

Ai Deviation from nominal pulse magnitude

due to mismatch

T Clock period

fio = 1/T_L0 Clock frequency

Fig. 15 shows a constellation diagram 1500 illustrating an exemplary reconstructed DDRM constellation. Reference sign 1501 denotes ideal DDRM constellation; reference sign 1502 denotes effective DDRM constellation and reference sign 1503 denotes the residual error.

In order to calculate the appropriate input data for the feedforward compensation mechanism the effective error generated at any constellation point has to be known. In the following, a method is described that uses the measurements as described above with respect to Fig. 14 and extracts the residual error that can be used to predict the errors generated by the DDRM.

In a first step the measurement techniques described before is used to measure the DNL table. If no measurement data is available for the LO frequency of interest it can also be obtained by interpolation from two measurements at other LO frequencies as described before.

For every complex input code the DDRM cells that are turned on can be determined. The error values from the DNL table are summed for all cells that are on to calculate the combined error generated by this specific combination of cells. This is illustrated in Figure 15.

Note that the combination of cells that are turned on at any given point in time can depend on more than just the complex input code. This is the case e.g. when using dynamic element matching where the unit cells used to generate a specific code are randomized over time. In such cases the randomization has to be taken into account and the combined error must be recalculated over time.

This procedure yields the residual error 1503 for any given DDRM input code at any given point in time. This residue can be used to calculate the input of a feedforward compensation path. Fig. 16 shows a schematic diagram illustrating a method for calibrating a DDM according to an implementation form. The method 1600 is for calibrating a direct digital modulator (DDM), wherein the DDM comprises a plurality of elements to generate an output signal based on a modulation of an input signal according to a predetermined constellation, e.g. as described above with respect to Figures 3 to 15.

The method 1600 includes providing a stimulus 1601 to at least one of the elements, wherein the stimulus is based on an oscillation signal and an anti-phase oscillation signal, e.g. as described above with respect to Fig. 7.

The method 1600 further includes measuring an output signal 1602 of the DDM responsive to the stimulus provided to the at least one element. The method 1600 may further include performing an aggregate error vector which is calculated by deviation information of each of the elements compared to its nominal value, e.g. as described above with respect to Figures 7 to 15.

The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the steps of the method 1600 described above with respect to Figure 16 or the method 700 as described above with respect to Fig. 7. Such a computer program product may include a readable non-transitory storage medium storing program code thereon for use by a computer. The program code may perform the methods 700 and 1600 described above with respect to Figs 7 and 16.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent

implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein. Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1 . A calibration device (1 1 10) for a direct digital modulator (DDM) (1 120), wherein the DDM (1 120) comprises a plurality of elements (1 121 ) to generate an output signal (1 124) based on a modulation of an input signal (1 122) according to a predetermined constellation, the calibration device (1 1 10) comprising: a calibration controller (1 1 1 1 ) configured to provide a stimulus (1 1 13) to at least one (1 121 a) of the elements (1 121 ); and a measurement device (1 1 12) configured to measure an output signal (1 124) of the DDM (1 120) responsive to the stimulus (1 1 13) provided to the at least one element (1 121 a), wherein the calibration controller (1 1 1 1 ) is configured to provide the stimulus (1 1 13) based on an oscillation signal applied to the input of the DDM (1 120) and an anti-phase oscillation signal applied to an error compensation path of the DDM (1 120).

2. The calibration device (1 1 10) of claim 1 , wherein the calibration controller (1 1 1 1 ) is configured to perform an aggregate error vector which is calculated by deviation information of each of the elements (1 121 ) compared to its nominal value.

3. The calibration device (1 1 10) of claim 2, wherein the calibration controller (1 1 1 1 ) is configured to provide the deviation information as a calibration table comprising at least one aggregate error vector.

4. The calibration device (1 1 10) of one of the preceding claims, wherein the calibration controller (1 1 1 1 ) is configured to adjust the stimulus (1 1 13) provided to the at least one element (1 121 a) based on the measured output signal (1 124) in accordance to a calibration algorithm.

5. The calibration device (1 1 10) of one of the preceding claims, wherein the calibration controller (1 1 1 1 ) is configured to adjust a gain factor of the error compensation path in order to obtain a spur-free output signal (1 124) at the output of the DDM (1 120).

6. The calibration device (1 1 10) of one of the preceding claims, wherein the calibration controller (1 1 1 1 ) is configured to provide the stimulus (1 1 13) based on toggling an amplitude code word (ACW), applied to the DDM (1 120), between two values, in particular between two contiguous values.

7. The calibration device (1 1 10) of one of the preceding claims, wherein the calibration controller (1 1 1 1 ) is configured to provide the stimulus (1 1 13) based on an oscillation signal, in particular a clock signal, applied to a first one (1 121 a) of the elements (1 121 ) and an anti-phase oscillation signal applied to a second one (1 121 b) of the elements (1 121 ).

8. The calibration device (1 1 10) of claim 7, wherein the measurement device (1 1 12) is configured to measure a mismatch of an output signal of the second element (1 121 b) with respect to an output signal of the first element (1 121 a).

9. The calibration device (1 1 10) of one of the preceding claims, wherein the

measurement device (1220) comprises: a down-mixer (1222) connectable to the output of the DDM (1210); and an analog-to-digital converter (1225), coupled to the down-mixer (1222), and configured to provide a measurement value of the output signal of the DDM (1210).

10. The calibration device (1 1 10) of claim 9, wherein the measurement device (1220) comprises: a low noise amplifier (LNA) (1221 ) connectable to the output of the DDM (1210) or to an output of the down-mixer (1222).

1 1 . The calibration device (1 1 10) of claim 9 or 10, wherein the measurement device (1220) comprises: a filter (1224) coupled between the down-mixer (1222) and the analog-to-digital converter (1225).

12. The calibration device (1 1 10) of one of claims 9 to 1 1 , wherein a local oscillator of the measurement device (1220) is independent of a local oscillator of the DDM (1210).

13. The calibration device (1 1 10) of one of claims 9 to 12 wherein the calibration controller (1230) is configured to write the measurement value provided by the measurement device (1220) to a memory (1240) for implementing offline calibration.

14. The calibration device (1 1 10) of one of claims 9 to 13, wherein the calibration controller (1230) is configured to control an error

compensation path (1212, 1214) of the DDM (1210) based on the measurement value provided by the measurement device (1220) for implementing online calibration.

15. A direct digital modulator (DDM) (1 120), comprising: a plurality of elements (1 121 ), configured to generate an output signal (1 124) of the

DDM (1 120) based on a modulation of an input signal (1 122) according to a predetermined constellation; and a calibration device (1 1 10) according to one of claims 1 to 14.

16. A method (1600) for calibrating a direct digital modulator (DDM), wherein the DDM comprises a plurality of elements to generate an output signal based on a modulation of an input signal according to a predetermined constellation, the method comprising: providing a stimulus (1601 ) to at least one of the elements, wherein the stimulus is based on an oscillation signal and an anti-phase oscillation signal; and measuring an output signal (1602) of the DDM responsive to the stimulus provided to the at least one element.

17. The method (1600) of claim 16, further comprising: performing an aggregate error vector which is calculated by deviation information of each of the elements compared to its nominal value.