WO2018054186A1 - Interleaving and de-interleaving methods, and device - Google Patents

Abstract

Disclosed are interleaving and de-interleaving methods, and a device. The interleaving method comprises: obtaining a to-be-interleaved sequence comprising k bits to be interleaved; filling positions of matrix elements in an interleaving matrix with the to-be-interleaved sequence row by row, wherein the interleaving matrix has m rows and n columns; and putting a bit corresponding to the position of each matrix element in the interleaving matrix into a sequence position in an output sequence corresponding to the position of the matrix element, so as to obtain a first interleaving sequence, wherein the output sequence comprises n bit segments, the q^th sequence position in the p^th bit segment in the output sequence corresponds to the position of the matrix element at the q1^th row and the p^th column in the interleaving matrix, and q1 corresponds to the bit-reversal order value of q. By means of the methods and apparatuses provided by the present application, an interleaving sequence with better performance can be generated without using a permutation sequence, and therefore, unnecessary storage space waste can be reduced.

Description

Interleaving method and deinterleaving method and device

The present application claims priority to Chinese Patent Application No. 201610841993.4, entitled "Interlacing Method and Deinterlacing Method and Apparatus" on September 22, 2016, the entire contents of which are incorporated herein by reference. in.

Technical field

The present application relates to the field of wireless communications, and in particular, to an interleaving method and a de-interleaving method and device.

Background technique

Polar Code is the only coding scheme that can theoretically prove that the performance can reach the Shannon limit when the code length approaches infinity. After encoding the data to be transmitted using the polarization code, the wireless communication device needs to use an interleaver to perform sequence interleaving on the code to be interleaved sequence to generate an interleaving sequence, interleave the coding sequence to generate an interleaving sequence, and then transmit, which can reduce data coding. The data correlation of the sequence, thereby reducing the impact of burst transmission errors on decoding and improving the anti-interference performance of the data transmission process.

In actual use, the wireless communication device can generally interleave the interleaved sequence using a random interleaving manner. Due to the interleaving of the interleaved sequences, a permutation sequence is required. Therefore, when the wireless communication device is in an offline state, if the interleaving sequence is to be interleaved, it is necessary to store the replacement sequence in advance. Since the length of the permutation sequence corresponds to the length of the sequence to be interleaved, when the length of the sequence to be interleaved is long, the length of the permutation sequence is correspondingly long, which consumes more data storage resources.

Summary of the invention

The present application provides an interleaving method and a de-interleaving method and device to reduce storage resource consumption caused by storing a permutation sequence when interleaving a sequence to be interleaved.

In a first aspect, the present application provides an interleaving method, which includes: acquiring a sequence to be interleaved including k bits to be interleaved; and filling the sequence to be interleaved row by row into a matrix element position in an interleave matrix, where The interleaving matrix is a matrix of m rows and n columns, m, n, k are all positive integers, and k ≤ m × n; bits corresponding to positions of each matrix element in the interleaving matrix are respectively put into outputs a sequence position corresponding to a position of the matrix element in the sequence, thereby obtaining a first interleaving sequence; wherein the output sequence comprises n bit segments, and the qth sequence position and position in the pth bit segment in the output sequence The position of the matrix element of the qth row and the pth column in the interleaving matrix corresponds to each other, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ M-1, 0 ≤ p ≤ n-1. The interleaving method provided can generate an interleaving sequence with better performance without using a permutation sequence, thereby reducing unnecessary waste of storage space.

In conjunction with the first aspect, in a first possible implementation of the first aspect, q1 is a bit reverse order value of q. With this implementation, it is convenient to determine the correspondence between the qth sequence position and the q1th line when the value of m is 2 to the power of a.

With reference to the first aspect, in a second possible implementation manner of the first aspect, the bits corresponding to each matrix element position in the interleaving matrix are respectively placed before the sequence position corresponding to the position of the matrix element in the output sequence. , also The method includes: calculating a bit reverse order value corresponding to each line number of the interlace matrix; and arranging the bit reverse order value in ascending or descending order to obtain a reverse order value sequence, where q1 is a position of a bit reverse order value of q in the reverse sequence Serial number.

With reference to the first aspect, or any one of the first to the second possible implementation manners of the first aspect, in the third possible implementation manner of the first aspect, acquiring the sequence to be interleaved including the k to be interleaved bits includes: acquiring An original sequence of k1 bits, where k1 < m×n; padding bits are added at predetermined positions of the original sequence to generate a sequence of k to be interleaved, where k=m×n, the padding bits The value is a predetermined value.

With reference to the first aspect, or any one of the first to the second possible implementation manners of the first aspect, in the fourth possible implementation manner of the first aspect, the to-be-interleaved sequence is padded row by row to a matrix in the interlace matrix The element position includes: when k<m×n, the line to be interleaved is filled line by line to the position of the matrix element in the interlace matrix, and padding bits are filled in the position of the idle matrix element in the interlace matrix, where The idle matrix element position refers to a matrix element in the interlace matrix that is not occupied by the to-be-interleaved bits.

With reference to the third or fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the method further includes: removing the padding bit in the first interleaving sequence, thereby obtaining The second interleaving sequence.

In a second aspect, the present application further provides a deinterleaving method, the method comprising: acquiring a first interleaving sequence comprising k interleaving bits, wherein the first interleaving sequence comprises n bit segments; Each of the interleaved bits is respectively placed in a matrix element position corresponding to each interleave bit in the interleaving matrix, the interleaving matrix is a matrix of m rows and n columns, and values of m, n, k are positive integers, and k ≤ m×n, wherein the qth sequence position in the pth bit segment in the first interleaving sequence corresponds to the matrix element position of the q1th row and the pth column in the interleaving matrix, and the bit sequence of q1 and q is reversed Corresponding values, p, q, q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1; each bit in the interleaving matrix is The row arrangement forms a de-interleaving sequence.

With reference to the second aspect, in a first possible implementation manner of the second aspect, acquiring the first interleaving sequence including k interleaving bits comprises: acquiring a second interleaving sequence including k1 bits, where k1<m×n; A padding bit is added to a predetermined position in the second interleaving sequence, thereby generating a first interleaving sequence including k interleaving bits, where k = m x n, and the value of the padding bit is a predetermined value.

With reference to the second aspect, in a second possible implementation manner of the second aspect, when k<m×n, the padding bits are filled in the position of the idle matrix element in the interleaving matrix, wherein the location of the idle matrix element It refers to a matrix element in the interlace matrix that is not occupied by the bits to be interleaved.

With reference to the second aspect, or any one of the first to the second possible implementation manners of the second aspect, in the third possible implementation manner of the second aspect, q1 is a bit reverse order value of q.

With reference to the second aspect, or any one of the first to the second possible implementation manners of the second aspect, in the fourth possible implementation manner of the second aspect, the interleaving bits in the interleaving sequence are separately interleaved Before the position of the matrix element corresponding to each interleave bit in the matrix, the method further includes: calculating a bit reverse order value corresponding to each row number of the interlace matrix; and arranging the bit reverse order value in ascending or descending order to obtain a sequence of reverse order values, where Q1 is the position number of the bit reverse order value of q in the reverse sequence.

With reference to the second aspect, in a fifth possible implementation manner of the second aspect, the method further includes: removing the padding bits in the deinterleaved bits.

In a third aspect, the present application further provides a wireless communication device, which may include a unit module module such as a receiving unit and a processing unit for performing the method steps in various implementation manners of the first aspect.

In a fourth aspect, the present application further provides another wireless communication device, which may include The unit module module such as the receiving unit and the processing unit of the method step in the second aspect of the second aspect.

In a fifth aspect, the present application further provides another communication device, including: a processor, a memory, and a transceiver module; the processor can execute a program or an instruction stored in the memory, thereby implementing the first aspect and the The interleaving method described in various implementation manners on the one hand; or the de-interleaving method described in the second aspect and various implementation manners of the second aspect.

In a sixth aspect, the present application further provides a storage medium, where the computer storage medium can store a program, and the program can implement some or all of the steps in the embodiments including the interleaving method provided by the application. The present application also provides another storage medium, which may store a program, which may perform some or all of the steps in the embodiments including the deinterleaving method provided by the present application.

DRAWINGS

In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly described below. Obviously, for those skilled in the art, without any creative labor, Other drawings can also be obtained from these figures.

1 is a schematic flow chart of an embodiment of an interleaving method according to the present application;

2 is a schematic structural diagram of an interlace matrix of the present application;

3 is a schematic structural diagram of a sequence to be interleaved according to the present application;

4 is a schematic structural diagram of an initial sequence of the present application;

FIG. 5 is another schematic structural diagram of a sequence to be interleaved according to the present application;

FIG. 6 is a schematic diagram of an effect of filling a coding matrix of the present application; FIG.

FIG. 7 is another schematic diagram of the effect of filling the coding matrix of the present application; FIG.

FIG. 8 is a schematic diagram of still another effect of the coding matrix filling of the present application; FIG.

9 is a schematic diagram of a correspondence between a bit reverse order value and a position number of the present application;

10 is a schematic structural diagram of a first interleaving sequence of the present application;

11 is another schematic structural diagram of a first interleaving sequence of the present application;

12 is a schematic structural diagram of still another first interleaving sequence of the present application;

13 is a schematic structural diagram of a second interleaving sequence of the present application;

14 is a schematic flow chart of an embodiment of a method for deinterleaving according to the present application;

15 is a schematic structural diagram of an embodiment of a wireless communication device of the present application;

16 is a schematic structural diagram of another embodiment of a wireless communication device of the present application;

17 is a schematic diagram of a comparison of interleaving methods and random interleaving performances of the present application;

FIG. 18 is another schematic diagram of the comparison of the interleaving method and the random interleaving performance of the present application; FIG.

FIG. 19 is still another schematic diagram of the comparison between the interleaving method and the random interleaving performance of the present application; FIG.

FIG. 20 is still another schematic diagram of the comparison of the interleaving method and the random interleaving performance of the present application.

Detailed ways

FIG. 1 is a schematic flowchart diagram of an embodiment of an interleaving method according to the present application, where the method includes the following steps:

Step 101: The wireless communication device acquires an interlace matrix with a number of rows of m and a number of columns of n.

The wireless communication device may first acquire an interlace matrix before the interleaving sequence is generated, and the interlace matrix may be a matrix of m rows and n columns. Wherein, the values of m and n are both positive integers. In order to meet the interleaving requirements of the interleaved sequence, The product of m and n needs to be no smaller than the maximum length of the sequence to be interleaved.

As shown in FIG. 2, if the maximum length of the sequence to be interleaved is 18 bits, the interlace matrix may be a matrix of 6 rows and 3 columns, that is, the value of m is 6, and the value of n is 3, thereby The product of m and n needs to be not less than 18, wherein the coding matrix row numbers can be represented by 0 to 5, respectively, and the column numbers of the matrix can be represented by 0 to 2, respectively; or the interleaving matrix It can also be a matrix of 4 rows and 5 columns, that is, the value of m is 4, and the value of n is 5, and the code matrix row numbers can be represented by 0 to 3, respectively, and the column numbers of the matrix are It can be represented by 0 to 4 respectively.

To simplify the process of sequence generation, the value of m can be a power of 2, where a is a positive integer. For example, the value of m can be 4, 6, 8, and the like.

The number of columns of the interleaving matrix can then be determined by the length of the sequence to be interleaved. In general, the value of n can be determined by the length of the sequence to be interleaved. For example, the value of n can be determined in the following manner one or two.

For example, the value of n can be determined by mode 1, that is, a positive integer h can be set first; for example, the value of h can be 3999; if k<400, the value of n can be 1; if 400≤k <h, then the value of n can be

If h≤k<21000, then the value of n can be

If k> 21000, then the value of n can be

For another example, the value of n can be determined by mode 2, that is, if k<400, the value of n can be 1; if 300<k≤10100, the value of n can be 72; if 10100<k≤ 16000, then the value of n can be 90; if k>16000, then the value of n can be

It should be noted that the wireless communication device may acquire the interlace matrix only once, and then use the same interlace matrix each time the interleaving sequence is generated; the wireless communication device may before each generation of the interlace matrix, The interleaving matrix is acquired once, so that different interleaving matrices are used each time an interleaving sequence is generated.

Step 102: Acquire a sequence to be interleaved including k bits to be interleaved.

The wireless communication device can directly acquire the sequence to be interleaved including k bits to be interleaved. Alternatively, the original sequence containing k1 bits may also be first acquired, k1<k; then padding bits are added at predetermined positions of the original sequence, thereby generating a sequence to be interleaved including k bits to be interleaved.

For example, the wireless communication device can directly acquire a sequence of 18 bits to be interleaved as shown in FIG. Each of the bits in the sequence to be interleaved may be represented by S0 to S17, and the value of each bit in the sequence to be interleaved may be 0 or 1.

For another example, the wireless communication device may also first obtain an initial sequence of 16 bits in length as shown in FIG. 4; then add 2 padding bits at the end of the initial sequence, thereby obtaining a length of 18 bits to be interleaved as shown in FIG. 5. A sequence in which S16 and S17 are padding bits. The values of the padding bits X1 and X2 may both be predetermined values, for example, both are 0 or both are 1. Setting the padding bit to a predetermined value may enable the decoding device to directly determine the bit value of the padding bit as the predetermined value when decoding, without having to decode the padding bit by using a complicated decoding process, thereby reducing the decoding process. The resource consumption brought.

It should be noted here that in order to simplify the process of sequence generation, when padding bits are added at predetermined positions of the original sequence to generate a sequence to be interleaved including k bits to be interleaved, k=m×n can be made.

Step 103: Fill the to-be-interleaved sequence row by row to the interlace matrix.

After the interlace matrix and the to-be-interleaved sequence are both determined, the wireless communication device may fill the to-be-interleaved sequence into the interlace matrix in a row-by-row manner. Thereby, each of the bits to be interleaved in the sequence to be interleaved corresponds to a position of a matrix element in the interleaving matrix.

When k=m×n, the sequence to be interleaved may completely fill the interleaving matrix.

For example, as shown in FIG. 6, when the length of the sequence to be interleaved is 18 bits and the interleave matrix is 6 rows and 3 columns, the sequence to be interleaved may just fill the interlace matrix. Wherein, S0 to S17 are respectively used to indicate respective bits in the sequence to be interleaved.

When k<m×n, the to-be-interleaved sequence is padded into the interleaving matrix row by row, and some idle matrix element positions may be generated in the interlaced matrix, where the idle matrix element positions are not filled. Any bit of the interleaved sequence. In order to avoid the inconvenience of the idle matrix element position for subsequent processing, padding bits may be filled in the free matrix element position.

For example, as shown in FIG. 7, when the length of the sequence to be interleaved is 16 bits and the interleave matrix is 6 rows and 3 columns, after the sequence to be interleaved is filled into the interleaving matrix row by row, the interleaving The fifth row, the first column, and the fifth row and the second column in the matrix are the positions of the idle matrix elements. In this case, the wireless communication device can fill a padding bit for each of the free matrix element locations. The filled interleaving matrix can be as shown in FIG. Where T1 and T2 represent two padding bits, respectively. The two padding bits may represent X3 and X4, and X3 and X4 may both be predetermined values.

Step 104: The bits corresponding to each matrix element position in the interleaving matrix are respectively placed into sequence positions corresponding to the positions of the matrix elements in the output sequence, thereby obtaining a first interleaving sequence.

In addition to predetermining the coding matrix, the wireless communication device can also predetermine the output sequence. The output sequence may be composed of n bit segments of equal bit length, and each of the bit segments may have a length of m bits.

After the interlace matrix and the to-be-interleaved sequence are determined to be determined, the wireless communication device may put the bit corresponding to each matrix element position in the interlace matrix into the output sequence and the matrix element position. Corresponding sequence positions, resulting in a first interleaved sequence. The bits corresponding to the positions of the matrix elements in the interlace matrix may include bits to be interleaved, and may also include padding bits.

The qth sequence position of the pth bit segment uniquely corresponds to the matrix element position of the q1th row and the pth column in the interlace matrix. Where q1 corresponds to the bit reverse order value of q, 0≤q1≤m-1, 0≤q≤m-1, 0≤p≤n-1. Usually q1 can be the bit reverse order value of q. The following is a brief description of the calculation process of the bit reverse order:

If the decimal number i is expressed in binary form as (b ₁ , b ₂ , . . . , b _c ), then the binary representation of the bit reverse order value of i is (b _c , b _c-1 , . . . , b ₁ ). Where c is the bit length when i is expressed in binary form, and the value of c is different according to the value of c. The value of c can be determined by the value of m, usually 2 c The power is not less than the value of m. When the value of m is 2 to the power of a, the value of c can be the same as the value of a.

For example, when the value of c is 3, the process of performing bit reverse order operation on the line numbers 0 to 5 respectively to obtain the bit reverse order value can be as shown in Table 1:

Table 1

Because when the value of m is not 2 to the power of a. Performing bit reverse ordering of q will generate q2, and the q2th row may not exist in the interleaving matrix. For example, when the value of m is 6, there are only 0th to 5th rows in the interleaving matrix. If the value of q is 3, then the value of the bit reverse order value q2 of q is 6. The sixth row does not exist in the interleaving matrix.

In order to avoid the occurrence of a row corresponding to the bit reverse order value of q in the interleaving matrix. Before the bits corresponding to the position of each matrix element in the interleaving matrix are respectively placed in the sequence position corresponding to the position of the matrix element in the output sequence, the wireless communication device may first calculate the bit reverse order value corresponding to each line number; The bit reverse order values are arranged in ascending or descending order to obtain a sequence of reverse order values. In this case, q1 is the position number of the bit reverse order value of q in the reverse sequence.

For example, when the row number of the interleaving matrix is 0 to 5, the corresponding bit reverse order value includes: 0, 4, 2, 6, 1, 5; the correspondence between the bit reverse order value and the position number may be as shown in FIG. .

After all the bits in the interleaving matrix are placed in the output sequence, the first interleaving sequence can be obtained. The wireless communication device can further encode the first interleaved sequence to obtain a sequence to be transmitted.

For example, when the sequence to be interleaved is as shown in FIG. 3, the first interleaving sequence may be as shown in FIG. When the sequence to be interleaved is as shown in FIG. 4, the first interleaving sequence may be as shown in FIG. When the sequence to be interleaved is as shown in FIG. 5, the first interleaving sequence may be as shown in FIG.

By using the interleaving method provided in this embodiment, an interleaving sequence with better performance can be generated without using a permutation sequence, thereby reducing unnecessary waste of storage space.

In another embodiment, after step 104, the method further includes: removing the padding bits in the first interleaving sequence to obtain a second interleaving sequence.

Since some padding bits may be included in the first interleaving sequence, when the padding bits are large, unnecessary resource overhead is caused for encoding and subsequent data transmission. For example, when the first interleaving sequence is as shown in FIG. 11 or FIG. 12, the first interleaving sequence and the second interleaving sequence each include padding bits. Therefore, after the first interleaving sequence is generated, the wireless communication device can remove the padding bits in the first interleaving sequence, thereby obtaining a second interleaving sequence. The padding bits removed by the wireless communication device may be padding bits filled in the original sequence, or may be padding bits filled in the interlace matrix.

For example, when the first interleaving sequence is as shown in FIG. 11 or 12, padding bits in the interleaving sequence may be removed, thereby obtaining a second interleaving sequence as shown in FIG.

With this implementation manner, the length of the interleaving sequence can be reduced, thereby reducing the resource consumption caused by the interleaving process.

In another embodiment of the present application, after the generating the first interleaving sequence or the second interleaving sequence, The wireless communication device can also perform polarization code encoding on the first interleaving sequence or the second interleaving sequence to generate a coding sequence; and then transmit the encoded sequence to its device. The technical solution provided by the embodiment can not only reduce the waste of the storage space, but also improve the transmission performance of the coding sequence.

FIG. 14 is a schematic flowchart diagram of an embodiment of a method for deinterleaving according to the present application. The deinterleaving method may deinterleave the interleaved sequence generated by the foregoing sequence interleaving method. As shown in FIG. 14, the method may include:

Step 1401: Acquire a first interleaving sequence including k interleaved bits.

The wireless communication device may first receive a first interleaving sequence comprising k interleaved bits. The first interleaving sequence includes n bit segments. The structure of the first interleaving sequence can be referred to the foregoing, and details are not described herein again. For example, the structure of the first interleaving sequence can be as shown in FIG.

The wireless communication device may also first acquire a second interleaving sequence comprising k1 bits, and then add padding bits at predetermined locations in the second interleaving sequence to generate a first interleaving sequence comprising k interleaved bits. The structure of the second interleaving sequence can be referred to the foregoing, and details are not described herein again. Wherein the predetermined location may be determined by the wireless communication device according to the interlace matrix. For example, when the structure of the second interleaving sequence can be as shown in FIG. 13, a first interleaving sequence as shown in FIG. 12 can be generated.

Step 1402: Place each interleave bit in the first interleaving sequence into a matrix element position corresponding to each interleave bit in the interlace matrix.

After the first interleaving sequence is determined, the wireless communication device may place each interleaved bit in the first interleaving sequence into a matrix element position corresponding to each interleaving bit in the interlace matrix. The interleave matrix is a matrix of m rows and n columns, and the values of m, n, and k are all positive integers, and k ≤ m×n, wherein the p-th bit segment in the first interleaving sequence The qth sequence position corresponds to the position of the matrix element of the q1th row and the pth column in the interleaving matrix, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0≤q1≤m -1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1. The structure of the interlace matrix can be referred to the foregoing. For example, when the first interleaving sequence is as shown in FIG. 11, the effect of putting each interlaced bit in the first interleaving sequence into the interlacing matrix may be as shown in FIG. 8.

Step 1403, the bits in the interlace matrix are grouped into a deinterleaving sequence in a row-by-row arrangement.

After the respective bits in the first interleaving sequence are correspondingly placed into the matrix element positions in the interleaving matrix, the wireless communication device may compose each bit in the interlacing matrix into a deinterleaving sequence in a row-by-row arrangement. The deinterleaving sequence may also include m bit segments, and the qth bit segment in the deinterleaving sequence is composed of interleaved bits located in the qth row in the interlace matrix, and in the qth bit In the segment, the interleaved bits are arranged according to column numbers. If the deinterleaving sequence does not include padding bits, the deinterleaving sequence is the original sequence; if the deinterleaving sequence includes padding bits, the sequence generated after removing the deinterleaving bits is Original sequence.

For example, when the first interleaving sequence is as shown in FIG. 10, then the deinterleaving sequence is the original sequence; and when the first interleaving sequence is as shown in FIG. 12, the deinterleaving sequence may be as As shown in FIG. 5, since there are padding bits in the de-interleaving sequence, the padding bits can be removed to obtain the original sequence, and the original sequence can be as shown in FIG.

FIG. 15 is a schematic structural diagram of an embodiment of a wireless communication device according to the present application. The wireless communication device provided by this embodiment may be used to perform the interleaving method provided in the foregoing embodiments.

As shown in FIG. 15, the wireless communication device may include: a receiving unit 1501 and a processing unit 1502; the device may further include a transmitting unit 1503 in addition to the receiving unit 1501 and the processing unit 1502.

When the wireless communication device is configured to generate an interleaving sequence, the receiving unit 1501 is configured to acquire a sequence to be interleaved including k to be interleaved bits, and the processing unit 1502 is configured to fill the to-be-interleaved sequence row by row into the interlace matrix. Position of the matrix element, wherein the interleave matrix is a matrix of m rows and n columns, m, n, k are all positive integers, and k ≤ m × n; each matrix element position in the interleaving matrix Corresponding bits are respectively placed in sequence positions corresponding to positions of matrix elements in the output sequence, thereby obtaining a first interleaving sequence; wherein the output sequence includes n bit segments, and the p-th bit segment in the output sequence The qth sequence position corresponds to the position of the matrix element of the q1th row and the pth column in the interleaving matrix, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0≤q1≤ M-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1.

Optionally, the processing unit 1502 is further configured to calculate a bit reverse order value corresponding to each line number of the interlace matrix; and arrange the bit reverse order value in ascending or descending order to obtain a sequence of reverse order values, where q1 is q The position number of the bit reverse order value in the reverse sequence. Alternatively, q1 is the bit reverse order value of q.

Optionally, the receiving unit 1501 is further configured to acquire an original sequence that includes k1 bits, where k1<m×n; adding padding bits at a predetermined position of the original sequence, thereby generating a length k to be interleaved A sequence, where k = m x n, the value of the padding bit being a predetermined value.

Optionally, the processing unit 1502 is further configured to: when k<m×n, fill the to-be-interleaved sequence row by row to a matrix element position in an interlace matrix, and idle matrix elements in the interlace matrix The padding bits are filled in the location, wherein the idle matrix element location refers to a matrix element in the interlace matrix that is not occupied by the to-be-interleaved bits.

Optionally, the processing unit 1502 is further configured to remove the padding bit in the first interleaving sequence to obtain a second interleaving sequence.

Optionally, the processing unit 1502 is further configured to encode the first interleaving sequence or the second interleaving sequence to generate a coding sequence. The sending unit 1503 is further configured to send the code sequence.

When the wireless communication device is configured to deinterleave the interleaving sequence, the receiving unit 1501 is configured to acquire a first interleaving sequence including k interleaving bits, where the first interleaving sequence includes n bit segments; and the processing unit 1502 And each of the interleaved bits in the first interleaving sequence is respectively placed into a matrix element position corresponding to each interleave bit in the interlace matrix, where the interlace matrix is a matrix of m rows and n columns, m, n, k The value is a positive integer, and k≤m×n, wherein the qth sequence position in the pth bit segment in the first interleaving sequence and the matrix element in the q1th row and the pth column in the interlaced matrix Corresponding to the position, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1; Each bit in the interleaving matrix constitutes a de-interleaving sequence in a row-by-row arrangement.

Optionally, the receiving unit 1501 is further configured to acquire a second interleaving sequence that includes k1 bits, where k1<m×n; the processing unit 1502 is further configured to be in the second interleaving sequence. A padding bit is added to the predetermined location to generate a first interleaving sequence comprising k interleaved bits, where k = m x n and the padding bit has a value of a predetermined value.

Optionally, the processing unit 1502 is further configured to: when k<m×n, fill the padding bits in the position of the idle matrix element in the interlace matrix, where the idle matrix element location refers to the A matrix element in the interlace matrix that is not occupied by the bits to be interleaved.

Optionally, the processing unit 1502 is further configured to calculate a bit reverse order value corresponding to each line number of the interlace matrix; and arrange the bit reverse order value in ascending or descending order to obtain a sequence of reverse order values, where q1 is q The position number of the bit reverse order value in the reverse sequence. Alternatively, q1 is the bit reverse order value of q.

Optionally, the processing unit 1502 is further configured to remove padding bits in the deinterleaved bits.

FIG. 16 is a schematic structural diagram of another embodiment of a wireless communication device according to the present application. The wireless communication device provided by this embodiment may be used to perform the interleaving method provided in the foregoing embodiments. It should be noted that, in various embodiments of the present application, the wireless communication device may be a terminal device or a network device.

The terminal device may be a device that provides voice and/or data connectivity to the user, a handheld device with wireless connectivity, or other processing device that is connected to the wireless modem. The terminal device can communicate with one or more core networks via a radio access network (RAN), and the terminal device can be a mobile terminal, such as a mobile phone (or "cellular" phone) and has a mobile terminal. The computer, for example, can be a portable, pocket, handheld, computer built-in or in-vehicle mobile device that exchanges language and or data with the wireless access network. For example, personal communication service (PCS) telephone, cordless telephone, session initiation protocol (SIP) telephone, wireless local loop (WLL) station, personal digital assistant (personal Digital assistant, PDA for short. The terminal device may also be referred to as a system, a subscriber unit (SU), a subscriber station (referred to as SS), a mobile station (MS), a remote station (RS), and an access station. Point (access point, AP for short), remote terminal (RT), access terminal (AT), user terminal (UT), user agent (UA) User equipment, or user equipment (UE). The network device may be a base station, an enhanced base station, or a relay having a scheduling function, or a device having a base station function, or the like. The base station may be an evolved Node B (eNB) in the LTE system, or may be a base station in other systems, which is not limited in the embodiment of the present invention.

As shown in FIG. 16, the wireless communication device may include a processor 1601, a memory 1602, and a transceiver module 1603. The transceiver module 1603 may include components such as a receiver, a transmitter, and an antenna. The wireless communication device may also include more or less components, or a combination of certain components, or different component arrangements, which are not limited by the present invention.

The processor 1601 is a control center of the wireless communication device that connects various portions of the entire wireless communication device using various interfaces and lines, by running or executing software programs and/or modules stored in the memory 1602, and recalling stored in the memory. Data to perform various functions and/or process data of the wireless communication device. The processor 1601 may be composed of an integrated circuit (IC), for example, may be composed of a single packaged IC, or may be composed of a plurality of packaged ICs having the same function or different functions. For example, the processor may include only a central processing unit (CPU), or may be a GPU, a digital signal processor (DSP), and a control chip (for example, a baseband) in the transceiver module 1603. A combination of chips). In the embodiment of the present application, the CPU may be a single operation core, and may also include a multi-operation core.

The transceiver module 1603 is configured to establish a communication channel, and the wireless communication device is connected to the receiving device through the communication channel, thereby implementing data transmission between the wireless communication devices. The transceiver module 1603 may include a wireless local area network (WLAN) module, a Bluetooth module, a baseband module, and the like, and a radio frequency (RF) circuit corresponding to the communication module. Used for wireless local area network communication, Bluetooth communication, infrared communication, and/or cellular communication system communication, such as wideband code division multiple access (WCDMA) and/or high speed downlink packet access (high speed) Downlink packet access (HSDPA). The transceiver module 1603 is configured to control communication of components in the wireless communication device and can support direct memory access.

In various embodiments of the present application, the various transceiver modules 1603 in the transceiver module 1603 are generally in the form of integrated circuit chips, and can be selectively combined without including all transceiver modules 1603 and Corresponding antenna group. For example, the transceiver module 1603 can include only baseband chips, radio frequency chips, and corresponding antennas to provide communication functionality in a cellular communication system. The wireless communication device can be connected to a cellular network or the Internet via a wireless communication connection established by the transceiver module 1603, such as wireless local area network access or WCDMA access. In some optional implementation manners of the present application, the communication module in the transceiver module 1603, such as a baseband module, may be integrated into the processor, typically an APQ+MDM series platform provided by Qualcomm. The radio frequency circuit is used for receiving and transmitting signals during information transmission and reception or during a call. For example, after the downlink information of the wireless communication device is received, it is processed by the processor; in addition, the designed uplink data is transmitted to the wireless communication device. Generally, the radio frequency circuit includes well-known circuits for performing these functions, including but not limited to an antenna system, a radio frequency transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a codec. (codec) chipset, Subscriber Identity Module (SIM) card, memory, etc. In addition, the RF circuit can communicate with the network and other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to a global system of mobile communication (GSM), a general packet radio service (gprs), and code division multiple access. (code division multiple access, CDMA for short), wideband code division multiple access (WCDMA), high speed uplink packet access (HSUPA), long-term evolution (long) Term evolution (LTE), e-mail, short messaging service (SMS), etc.

The processor 1601 may perform the interleaving method provided by the foregoing implementation to generate the first interleaving sequence or the second interleaving sequence; wherein the to-be-interleaved sequence may be acquired by the processor 1601 from the memory 1602. Alternatively, it may be acquired by the processor 1601 from the other device through the transceiver module 1603. The processor 1601 is further configured to perform polarization code encoding on the first interleaving sequence or the second interleaving sequence to generate a coding sequence, and the transceiver module 1603 may further be configured to send the coding sequence.

It should be noted that the receiving unit 1601 shown in FIG. 16 may be implemented by the transceiver module 1603 shown in FIG. 16 or controlled by the processor 1601; the processing unit shown in FIG. 1602; may be implemented by the processor 1601 shown in FIG. 16; the transmitting unit shown in FIG. 16 may also be implemented by the transceiver module 1603 shown in FIG. 16 or the transceiver module 1603 may be controlled by the processor 1601. achieve.

In a specific implementation, the present invention further provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in each embodiment of the interleaving method or the deinterleaving method provided by the present invention. . The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

It should be noted that the sequence is interleaved and deinterleaved by using the technical solution provided by the present application, which can save data storage resources and improve the performance of the polarization code.

The performance comparison between the interleaving method and the random interleaving provided by the present application can be as shown in FIGS. 17 to 20. In FIGS. 17 to 20, the abscissa is a symbol-to-noise ratio (Es/No) in units of decibels (dB); the ordinate is a block error rate; and R is a code rate; wherein, R can be 1/5. 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, 8/9, the range of values shown in the figure is {0.2, 0.33333, 0.4, 0.5, 0.66667, 0.75, 0.83333, 0.88889}. At different code rates, the performance of random interleaving and fixed interleaving can be shown in the curve in the figure, where the fixed interleaving shown in the figure is the former The interleaving method described in the embodiments.

When the value of n is determined by the first method in the foregoing embodiment, if the value of k is 400, that is, the information bit length shown in the figure is 400, the performance comparison of the polarization code can be as shown in each different code rate. 17; if the value of k is 8000, that is, the information bit length shown in the figure is 8000, the performance comparison of the polarization code at each different code rate can be as shown in FIG. 18.

When the value of n is determined by the second method in the foregoing embodiment, if the value of k is 400, that is, the information bit length shown in the figure is 400, the performance comparison of the polarization code can be as shown in each different code rate. 19; if the value of k is 4000, that is, the information bit length shown in the figure is 4000, the performance comparison of the polarization code at each different code rate can be as shown in FIG.

It will be apparent to those skilled in the art that the techniques in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product, which may be stored in a storage medium such as a ROM/RAM. , a disk, an optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention or portions of the embodiments.

The same and similar parts between the various embodiments in this specification can be referred to each other. In particular, for the device and the wireless communication device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant places can be referred to the description in the method embodiment.

The embodiments of the invention described above are not intended to limit the scope of the invention.

Claims (30)

1. An interleaving method, comprising:

   Obtaining a sequence to be interleaved comprising k bits to be interleaved;

   And the sequence to be interleaved is padded to a matrix element position in the interlace matrix, wherein the interlace matrix is a matrix of m rows and n columns, and values of m, n, and k are positive integers, and k≤m× n;

   And respectively input a bit corresponding to each matrix element position in the interleaving matrix into a sequence position corresponding to a position of the matrix element in the output sequence, thereby obtaining a first interleaving sequence;

   The output sequence includes n bit segments, and the qth sequence position in the pth bit segment of the output sequence corresponds to the matrix element position of the q1th row and the pth column in the interlace matrix, q1 and The bit reverse order value of q corresponds, p, q, q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1.
2. The method of claim 1 wherein q1 is a bit reverse order value of q.
3. The method according to claim 1, wherein before the bits corresponding to the position of each of the matrix elements in the interleaving matrix are respectively placed in the sequence position corresponding to the position of the matrix element in the output sequence, the method further includes:

   Calculating a bit reverse order value corresponding to each row number of the interlace matrix;

   Arranging the bit reverse order values in ascending or descending order to obtain a sequence of reverse order values, wherein q1 is a position number of a bit reverse order value of q in the reverse order sequence.
4. The method according to any one of claims 1 to 3, wherein acquiring the sequence to be interleaved comprising k bits to be interleaved comprises:

   Obtaining an original sequence containing k1 bits, where k1 < m×n;

   A padding bit is added at a predetermined position of the original sequence, thereby generating a sequence to be interleaved having a length of k, where k = m × n, and the value of the padding bit is a predetermined value.
5. The method according to any one of claims 1 to 3, wherein filling the sequence of the to-be-interleaved line by row into the matrix element position in the interlace matrix comprises:

   When k<m×n, the sequence to be interleaved is padded row by row to the position of the matrix element in the interlace matrix, and the padding bits are filled in the position of the idle matrix element in the interleave matrix, wherein the idle matrix The element position refers to a matrix element in the interleaving matrix that is not occupied by the bits to be interleaved.
6. The method of claim 4 or 5, wherein the method further comprises:

   Removing the padding bits in the first interleaving sequence to obtain a second interleaving sequence.
7. A de-interlacing method, comprising:

   Obtaining a first interleaving sequence comprising k interleaved bits, wherein the first interleaving sequence comprises n bit segments;

   Inserting each interleaved bit in the interleaved sequence into an interlace matrix corresponding to each interleaved bit a matrix element position, the interleaving matrix is a matrix of m rows and n columns, m, n, k are all positive integers, and k≤m×n, wherein the pth bit segment in the first interleaving sequence The qth sequence position corresponds to the position of the matrix element of the q1th row and the pth column in the interleaving matrix, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0≤q1 ≤m-1,0≤q≤m-1,0≤p≤n-1;

   Each bit in the interleaving matrix is grouped into a deinterleaving sequence in a row-by-row arrangement.
8. The method of claim 7, wherein acquiring the first interleaving sequence comprising k interleaved bits comprises:

   Obtaining a second interleaving sequence comprising k1 bits, where k1 < m×n;

   A padding bit is added at a predetermined position in the second interleaving sequence to generate a first interleaving sequence including k interleaving bits, where k = m x n, and the value of the padding bit is a predetermined value.
9. The method of claim 7 further comprising:

   When k<m×n, padding bits are filled in the positions of the idle matrix elements in the interleaving matrix, wherein the idle matrix element positions refer to the interlaced matrix not occupied by the bits to be interleaved Matrix element.
10. The method according to any one of claims 7 to 9, wherein q1 is a bit reverse order value of q.
11. The method according to any one of claims 7 to 9, wherein before each of the interleaved bits in the interleaving sequence is placed in a position of a matrix element corresponding to each interleave bit in the interlace matrix, the method further includes:

    Calculating a bit reverse order value corresponding to each row number of the interlace matrix;

    Arranging the bit reverse order values in ascending or descending order to obtain a sequence of reverse order values, wherein q1 is a position number of a bit reverse order value of q in the reverse order sequence.
12. The method of claim 7 further comprising:

    The padding bits in the de-interleaved bits are removed.
13. A wireless communication device, comprising:

    a receiving unit, configured to acquire a sequence to be interleaved including k bits to be interleaved;

    a processing unit, configured to fill the to-be-interleaved sequence row by row to a matrix element position in the interleave matrix, where the interleave matrix is a matrix of m rows and n columns, and values of m, n, and k are positive integers. And k≤m×n; placing bits corresponding to positions of each matrix element in the interleaving matrix into sequence positions corresponding to positions of matrix elements in the output sequence, thereby obtaining a first interleaving sequence; wherein the output The sequence includes n bit segments, and the qth sequence position in the pth bit segment of the output sequence corresponds to the matrix element position of the q1th row and the pth column in the interleaving matrix, and the bit reverse order value of q1 and q Correspondingly, p, q, and q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, and 0 ≤ p ≤ n-1.
14. The apparatus of claim 13 wherein q1 is a bit reverse order value of q.
15. The device of claim 13 wherein:

    The processing unit is further configured to calculate a bit reverse order value corresponding to each line number of the interlace matrix; and arrange the bit reverse order value in ascending or descending order to obtain a reverse order value sequence, where q1 is a bit reverse order value of q The position number in the reverse sequence.
16. A device according to any one of claims 13 to 15, wherein

    The receiving unit is further configured to acquire an original sequence including k1 bits, where k1<m×n; adding a padding bit at a predetermined position of the original sequence, thereby generating a sequence to be interleaved with a length of k, where k = m × n, the value of the padding bit is a predetermined value.
17. A device according to any one of claims 13 to 15, wherein

    The processing unit is further configured to fill the to-be-interleaved sequence row by row to a matrix element position in the interlaced matrix when k<m×n, and fill the padding in the idle matrix element position in the interlacing matrix a bit, wherein the idle matrix element position refers to a matrix element in the interlace matrix that is not occupied by the to-be-interleaved bit.
18. The device according to claim 16 or 17, wherein

    The processing unit is further configured to remove the padding bit in the first interleaving sequence to obtain a second interleaving sequence.
19. A wireless communication device, comprising:

    a receiving unit, configured to acquire a first interleaving sequence that includes k interleaving bits, where the first interleaving sequence includes n bit segments;

    a processing unit, configured to place each interleave bit in the first interleaving sequence into a matrix element position corresponding to each interleave bit in an interlace matrix, where the interlace matrix is a matrix of m rows and n columns, m, n, The value of k is a positive integer, and k ≤ m × n, wherein the qth sequence position in the pth bit segment in the first interleaving sequence and the qth row and the pth column in the interleaving matrix The position of the matrix element corresponds, q1 and q correspond to the bit reverse order value, p, q, q1 are positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1 And translating each bit in the interleaving matrix into a deinterleaving sequence in a row-by-row arrangement.
20. The device of claim 19, wherein

    The receiving unit is further configured to acquire a second interleaving sequence including k1 bits, where k1<m×n;

    The processing unit is further configured to add a padding bit at a predetermined position in the second interleaving sequence, thereby generating a first interleaving sequence including k interleaving bits, where k=m×n, the value of the padding bit Is the predetermined value.
21. The device of claim 19, wherein

    The processing unit is further configured to: when k<m×n, fill bits in a position of a free matrix element in the interlace matrix, where the position of the idle matrix element refers to not being in the interlace matrix The matrix elements occupied by the bits to be interleaved.
22. The apparatus according to any one of claims 19 to 21, wherein q1 is a bit reverse order value of q.
23. The device according to any one of claims 19 to 21, wherein the processing unit is further configured to calculate a bit reverse order value corresponding to each line number of the interlace matrix; and the bit reverse order value is in ascending order or The descending order obtains a sequence of reverse order values, where q1 is the position number of the bit reverse order value of q in the reverse order sequence.
24. The device of claim 19, wherein

    The processing unit is further configured to remove padding bits in the deinterleaved bits.
25. A computer readable storage medium, comprising instructions that, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 6.
26. A computer readable storage medium, comprising instructions that, when run on a computer, cause the computer to perform the method of any one of claims 7 to 12.
27. A computer program product, characterized in that it, when run on a computer, causes the computer to perform the method of any one of claims 1 to 6.
28. A computer program product, characterized in that it, when run on a computer, causes the computer to perform the method of any one of claims 7 to 12.
29. A communication device, comprising: a processor, the process is configured to acquire a sequence to be interleaved comprising k bits to be interleaved; and the sequence to be interleaved is padded row by row to a position of a matrix element in an interlace matrix, where The interleaving matrix is a matrix of m rows and n columns, m, n, k are all positive integers, and k ≤ m×n; bits corresponding to positions of each matrix element in the interleaving matrix are respectively placed Outputting a sequence position corresponding to a position of the matrix element in the sequence, thereby obtaining a first interleaving sequence; wherein the output sequence includes n bit segments, and the qth sequence position in the pth bit segment of the output sequence is The positions of the matrix elements of the qth row and the pth column in the interleaving matrix correspond, the bit reverse order values of q1 and q correspond, p, q, q1 are positive integers, and 0≤q1≤m-1,0≤q ≤ m-1, 0 ≤ p ≤ n-1.
30. A communication device, comprising: a processor, the process for acquiring a first interleaving sequence comprising k interleaved bits, wherein the first interleaving sequence comprises n bit segments; Each of the interleaved bits is respectively placed in a matrix element position corresponding to each interleave bit in the interlace matrix, the interleaving matrix is a matrix of m rows and n columns, and m, n, k are all positive integers, and k ≤ m ×n, wherein the qth sequence position in the pth bit segment of the first interleaving sequence corresponds to the matrix element position of the q1th row and the pth column in the interleaving matrix, and the bit reverse order value of q1 and q Correspondingly, p, q, q1 are all positive integers, and 0 ≤ q1 ≤ m-1, 0 ≤ q ≤ m-1, 0 ≤ p ≤ n-1; each bit in the interleaving matrix is progressive The arrangement forms a de-interleaving sequence.

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