WO2018051447A1 - Matching device - Google Patents

Matching device Download PDF

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Publication number
WO2018051447A1
WO2018051447A1 PCT/JP2016/077211 JP2016077211W WO2018051447A1 WO 2018051447 A1 WO2018051447 A1 WO 2018051447A1 JP 2016077211 W JP2016077211 W JP 2016077211W WO 2018051447 A1 WO2018051447 A1 WO 2018051447A1
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WIPO (PCT)
Prior art keywords
variable capacitor
value
capacitance
matching
capacitance value
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PCT/JP2016/077211
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French (fr)
Japanese (ja)
Inventor
高橋 直人
押田 善之
規一 加藤
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株式会社日立国際電気
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Application filed by 株式会社日立国際電気 filed Critical 株式会社日立国際電気
Priority to PCT/JP2016/077211 priority Critical patent/WO2018051447A1/en
Priority to JP2018539016A priority patent/JPWO2018051447A1/en
Publication of WO2018051447A1 publication Critical patent/WO2018051447A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05HPLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00Generating plasma; Handling plasma
    • H05H1/24Generating plasma
    • H05H1/46Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38Impedance-matching networks

Definitions

  • the present disclosure relates to a matching device and can be applied to, for example, a matching device that matches the output of a high frequency power supply device to a load.
  • a plasma processing apparatus is used in a semiconductor manufacturing process in which etching or thin film formation is performed.
  • a high frequency power supply device is used as a power supply source of the plasma processing apparatus.
  • a matching unit is inserted between a high frequency power supply device and a plasma processing apparatus.
  • the matching unit is configured to include a matching circuit having a matching element for matching impedance between the high-frequency power supply device and the plasma processing apparatus.
  • the matching circuit is configured to include a variable capacitor, an inductance, and a transmission line.
  • a variable capacitor uses a stepping motor to change the capacitance value, but due to the capacitance accuracy of the variable capacitor, there are rare instances where the capacitance value of the variable capacitor is completely different from the set value even if it is set.
  • Matching devices equipped with the variable capacitors have the same impedance as other matching devices, but the impedance is completely different, so there is a significant difference in matching operation (trajectory, time) even when connected to a plasma load.
  • the throughput of the device depends on the individual matchers and is not stable. The subject of this indication is providing the matching device which reduces the capacity
  • the matching device includes a directional coupler, a matching circuit having a first variable capacitor and a second variable capacitor, a control unit, a third variable capacitor of the reference matcher, and a first variable capacitor.
  • the capacitance value of the first variable capacitor obtained based on the set value of the capacitance value of the variable capacitor of 4 and the impedance of the reference matching device when the set value is set, and the second A storage unit that stores a correction setting value of the capacitance value of the variable capacitor.
  • the control unit sets a capacitance value of the first variable capacitor and a set value of the capacitance value of the second variable capacitor, and sets the capacitance value of the first variable capacitor and the second variable of the storage unit. Correction is made based on the correction setting value of the capacitance value of the capacitor.
  • the capacity error can be reduced.
  • FIG. 1 is a functional block diagram of the matching device according to the embodiment.
  • FIG. 2 is a configuration diagram of the matching circuit according to the embodiment.
  • FIG. 3 is a configuration diagram of a storage unit according to the embodiment.
  • FIG. 4 is a diagram for explaining an example of the locus of the reflection coefficient when the capacitance of the variable capacitor is changed.
  • FIG. 5 is a diagram for explaining another example of the locus of the reflection coefficient when the capacitance of the variable capacitor is changed.
  • FIG. 6 is a diagram illustrating a locus of a reflection coefficient according to the example.
  • FIG. 7 is a flowchart of impedance matching processing according to the embodiment.
  • FIG. 8 is a diagram showing the impedance (with VC1 fixed) of a matching unit equipped with a correctly adjusted variable capacitor.
  • FIG. 9 is a diagram showing the impedance (with VC2 fixed) of a matching device equipped with a correctly adjusted variable capacitor.
  • FIG. 10 is a diagram illustrating the impedance (VC1 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted.
  • FIG. 11 is a diagram showing the impedance (VC2 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted.
  • FIG. 12 is a flowchart showing the capacity adjustment and matching operation of the variable capacitor.
  • FIG. 13 is a diagram showing the relationship (VC2 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B).
  • FIG. 14 is a diagram showing the relationship (VC1 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B).
  • FIG. 15 is a diagram showing a conversion table (VC1).
  • FIG. 16 shows the conversion table (VC2).
  • FIG. 1 is a functional block diagram of the matching device according to the embodiment.
  • a matching device 10 is inserted between the high frequency power supply device 2 and the plasma processing device 3.
  • plasma is generated in the plasma processing device 3.
  • the input impedance of the plasma processing device 3 may be converted by the matching device 10 so that the input impedance of the matching device 10 is 50 ⁇ .
  • the input impedance of the plasma processing apparatus 3 varies depending on the type, flow rate, pressure, temperature, etc. of the gas input to the plasma processing apparatus 3. Therefore, the matching unit 10 needs to adaptively match according to the input impedance of the plasma processing apparatus 3 that changes with time.
  • the control unit 20 for controlling the circuit constant of the matching element of the matching circuit 30 and the storage unit 25 are configured.
  • High-frequency power (traveling wave: Pf) traveling from the RFin terminal toward the RFout terminal is detected by the directional coupler 11 and output to the FORWARD terminal.
  • High frequency power (reflected wave: Pr) traveling from the RFout terminal to the RFin terminal is detected by the directional coupler 11 and output to the REFLECT terminal.
  • the high-frequency power (Pf) traveling from the RFin terminal toward the RFout terminal is not detected by the REFECT terminal but is small even if detected.
  • the high-frequency power (Pr) traveling from the RFout terminal toward the RFin terminal is not detected at the FORWARD terminal and is small if detected.
  • the control unit 20 is configured to include a reflection coefficient calculation unit 21, a capacitance calculation unit 22, and a capacitance setting unit 23.
  • the traveling wave (Pf) and the reflected wave (Pr) detected by the directional coupler 11 are input to the reflection coefficient calculation unit 21 of the control unit 20.
  • the reflection coefficient ( ⁇ ) is defined as in Expression (1) from the amplitude ratio (r) of the reflected wave (Pr) to the traveling wave (Pf) and the phase difference ( ⁇ ).
  • r ⁇ exp (j ⁇ ⁇ ) (j: imaginary unit) (1) Therefore, if the amplitude ratio (r) and the phase difference ( ⁇ ) of the reflected wave (Pr) with respect to the traveling wave (Pf) are known, the reflection coefficient ( ⁇ ) can be obtained.
  • the reflection coefficient calculator 21 calculates the amplitude ratio (r) and the phase difference ( ⁇ ) based on the traveling wave (Pf) and the reflected wave (Pr), and calculates the reflection coefficient ( ⁇ ).
  • the traveling wave (Pf) and the reflected wave (Pr) are converted into a frequency domain by FFT (Fast Fourier Transform), and the traveling wave is the same frequency as the high-frequency power output from the high-frequency power supply device 2.
  • the amplitude ratio (r) and the phase difference ( ⁇ ) may be calculated by comparing the amplitude and phase of (Pf) and the reflected wave (Pr).
  • the capacitance calculation unit 22 calculates a capacitor capacity for making the reflection coefficient ( ⁇ ) close to zero based on the reflection coefficient ( ⁇ ) calculated by the reflection coefficient calculation unit 21. A method for calculating the capacitor capacity will be described later.
  • the capacitance setting unit 23 sets and changes the capacitance of the variable capacitance capacitor in the matching circuit 30 based on the capacitance of the capacitor calculated by the capacitance calculation unit 22.
  • FIG. 2 is a configuration diagram of the matching circuit according to the embodiment.
  • the circuit configuration of the matching circuit 30 is determined by the range in which the input impedance of the plasma processing apparatus 3 serving as a load varies.
  • the matching circuit 30 includes a first variable capacitor 31, a second variable capacitor 32, an inductance 33, a transmission line 35, and a transmission line 36.
  • the transmission line 35 and the transmission line 36 can be configured by a coaxial cable, a metal plate, or the like, or can be configured to include a lumped constant circuit of an inductor or a capacitor.
  • the transmission line 35 connects the input terminal 30 a of the matching circuit 30 and one end of the first variable capacitor 31. The other end of the first variable capacitor 31 is grounded.
  • the transmission line 36 connects the output terminal 30 b of the matching circuit 30 and one end of the second variable capacitor 32. The other end of the second variable capacitor 32 is grounded.
  • the first variable capacitor 31, the second variable capacitor 32, and the inductance 33 are matching elements for impedance matching between the high frequency power supply device 2 and the plasma processing device 3.
  • the matching circuit 30 includes a variable capacitor control terminal 31a for controlling the capacitance of the first variable capacitor 31 and a variable capacitor control terminal 32a for controlling the capacitance of the second variable capacitor 32. Is provided.
  • Control of the variable capacitor of the matching circuit 30 is controlled so that the magnitude of the reflection coefficient ( ⁇ ) calculated from the traveling wave (Pf) detected by the directional coupler 11 and the reflected wave (Pr) becomes small. .
  • the control unit 20 calculates the reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and uses the reflection coefficient to determine the capacitance value of the first variable capacitor 31. (VC1) and the capacitance value (VC2) of the second variable capacitor 32 are controlled.
  • the storage unit 25 stores circle information and the like described later. As shown in FIG. 3, the storage unit 25 includes a CPU built-in SRAM 251, an external SRAM (volatile memory) 252, and an external EEPROM (nonvolatile memory) 253.
  • the circle information is the circle information drawn by the locus of the reflection coefficient ( ⁇ ) passing through the matching point (the point where the real part and the imaginary part of the reflection coefficient ( ⁇ ) are zero) on the Smith chart. Information on the position and size of the circle. It is known that this circle information is determined based on the condition of the transmission line 35, that is, the characteristic impedance (ZL) and the line length (L) of the transmission line 35.
  • the capacitance calculation unit 22 is a matching circuit corresponding to the calculated reflection coefficient ( ⁇ ) based on the reflection coefficient ( ⁇ ) calculated by the reflection coefficient calculation unit 21 and the circle information stored in the storage unit 25.
  • the capacitance value (VC1) of the 30 first variable capacitor 31 and the capacitance value (VC2) of the second variable capacitor 32 are calculated. That is, VC1 and VC2 that reduce the calculated reflection coefficient ( ⁇ ) are calculated.
  • the capacitance calculation unit 22 is configured so that the reflection coefficient ( ⁇ ) calculated by the reflection coefficient calculation unit 21 approaches the circle stored in the storage unit 25.
  • a capacity value (VC2) of 32 is calculated.
  • the capacitance setting unit 23 changes the capacitance value (VC2) of the second variable capacitor 32 so that the calculated capacitance is obtained. Thereby, the capacitance setting unit 23 positions the reflection coefficient ⁇ on the circle.
  • the capacitance calculation unit 22 calculates the capacitance value (VC1) of the first variable capacitor 31 of the matching circuit 30 so that the reflection coefficient ⁇ calculated by the reflection coefficient calculation unit 21 becomes small. Then, the capacitance setting unit 23 changes the capacitance value (VC1) of the first variable capacitor 31 so that the calculated capacitance is obtained. Thereby, the capacity setting unit 23 positions the reflection coefficient ( ⁇ ) at the matching point (the point where the reflection coefficient ( ⁇ ) is 0).
  • circle information corresponding to the transmission line 35 is stored in advance.
  • the information (position and size) of the circle is determined based on the condition of the transmission line 35, that is, the sex impedance (ZL) and the line length (L) of the transmission line 35.
  • ZL the sex impedance
  • L the line length of the transmission line 35.
  • the circle becomes a circle R1 shown in FIG.
  • the transmission line 35 has a characteristic impedance of 50 ⁇ and a line length of ⁇ / 4
  • the circle is a circle R2 shown in FIG. 5 and a circle R3 shown in FIG.
  • the concept of the matching algorithm of this embodiment will be described.
  • the locus of the reflection coefficient ( ⁇ ) draws a circle R1 whose diameter is a line segment connecting the F point and the G point in a matched state.
  • the reflection coefficient ( ⁇ ) at point F has zero imaginary part ( ⁇ i) and zero real part ( ⁇ r) (the input impedance of the matching device 10 is 50 ⁇ ).
  • the reflection coefficient ( ⁇ ) at point G has an imaginary part of zero and a real part of ⁇ 1.
  • FIG. 4 shows a case where the transmission line 35 can be ignored, but in reality it may not be ignored.
  • the Smith chart of FIG. 5 shows the locus of the reflection coefficient ( ⁇ ) when the characteristic impedance of the transmission line 35 is 50 ⁇ and the line length is ⁇ / 4.
  • the locus of the reflection coefficient ( ⁇ ) draws a circle R2 whose diameter is a line segment connecting the F point and the H point in a matched state.
  • the reflection coefficient ( ⁇ ) at point H has an imaginary part of zero and a real part of 1 (the input impedance of the matching device 10 is infinite).
  • Z2 is determined by the following equation (2).
  • Z1 is an input impedance when the transmission line 35 can be ignored (FIG. 4)
  • Z2 is an input impedance when the transmission line 35 cannot be ignored (FIG. 5).
  • the circle R1 in FIG. 4 becomes the circle R2 in FIG.
  • FIG. 6 shows a reflection coefficient (when the impedance matching is performed according to the embodiment in the case of the matching circuit 30 similar to FIG. 5, that is, when the characteristic impedance of the transmission line 35 is 50 ⁇ and the line length is ⁇ / 4. It is a Smith chart which shows the locus
  • the point C is the reflection coefficient ( ⁇ ) when VC1 and VC2 are initial values (for example, the minimum value of the variable capacitor), that is, the input impedance of the matching unit 10 when the plasma load is at a certain input impedance value. It is.
  • the control unit 20 increases only VC2 until the reflection coefficient ( ⁇ ) reaches the point D in contact with the circle R3 from the initial point C of VC1 and VC2.
  • the circle R3 is the same as the circle R2 in FIG. Information on the circle R3 is stored in the storage unit 25.
  • VC2 becomes Y which is the capacity at the time of matching.
  • VC2 is controlled to the matching value, but VC1 remains at the initial value. Therefore, the control unit 20 then increases VC1.
  • VC1 is increased, as described above, the reflection coefficient ( ⁇ ) moves on the circle R3. Therefore, it is only necessary to increase VC1 and stop increasing VC1 when the reflection coefficient ( ⁇ ) becomes zero.
  • VC1 at that time is X, which is a capacity at the time of matching.
  • the minimum value of the variable capacitor is selected as the initial value of VC1 and VC2, but it may be the maximum value of the variable capacitor or any other value. In that case, of course, the position of the point C changes. However, regardless of the initial values of VC1 and VC2, if VC2 is the value at the time of matching, the phenomenon that the reflection coefficient ( ⁇ ) moves on the circle R3 when VC1 is changed. Will not change.
  • VC1 is controlled as follows. That is, when the imaginary part of the reflection coefficient ( ⁇ ) is positive, VC1 is a value larger than the matching value X. Therefore, the control is performed so that the reflection coefficient ( ⁇ ) becomes 0 by reducing VC1. To do. On the contrary, when the imaginary part of the reflection coefficient ( ⁇ ) is negative, VC1 is smaller than X. Therefore, by increasing VC1, control is performed so that the reflection coefficient ( ⁇ ) becomes zero.
  • VC1 and VC1 are controlled as described above. That is, VC1 is controlled after controlling VC2 so that the reflection coefficient ( ⁇ ) is in contact with the circle R3.
  • the case where the characteristic impedance of the transmission line 35 is 50 ⁇ and the line length is ⁇ / 4 in the matching circuit 30 of FIG. 2 has been described as an example. It is not limited to the case. If the condition of the transmission line 35 is different from the above condition, the locus of the circle when VC1 is changed under the condition that VC2 is the capacity at the time of matching is the locus of the circle R3 shown in FIGS. Since they are different, the locus of the circle may be set according to the condition of the transmission line 35 by the above-described equation (2).
  • FIG. 7 is a flowchart of impedance matching processing according to the embodiment. This process is executed by the control unit 20.
  • the circle information position and size on the Smith chart shown in FIGS. 5 and 6 is stored and stored in the storage unit 25 (step S1 in FIG. 7).
  • step S1 initial values of VC1 and VC2 are also set.
  • the reflection coefficient ( ⁇ ) at that time is calculated from the traveling wave (Pf) and the reflected wave (Pr) obtained from the directional coupler 11 (step S2).
  • the absolute value of the reflection coefficient ( ⁇ ) is compared with a predetermined value (L) (step S3).
  • the process returns to Step S2, and the traveling wave (Pf) and the reflected wave (Pr) are obtained from the directional coupler 11, and again Then, the reflection coefficient ( ⁇ ) at that time is calculated.
  • step S3 If the absolute value of the reflection coefficient ( ⁇ ) is larger than L (No in step S3), the process proceeds to step S4.
  • This L is a threshold value for determining that matching has been achieved and is ideally 0, but in reality, it is difficult to set the reflection coefficient ( ⁇ ) to 0. Judgment is made by providing (L).
  • This L is a value determined by the reflection resistant power of the high frequency power supply device 2 and the required specifications of the plasma processing apparatus 3 using the high frequency power supply device 2.
  • step S4 in order to determine whether or not there is a reflection coefficient ( ⁇ ) on the circle defined in the initial setting (step S1), information on the circle is acquired from the storage unit 25, and the reflection coefficient ( ⁇ ), the circle, The minimum value (P) of the distance is calculated. If this value (P) is larger than the predetermined threshold value (M) (Yes in step S5), since VC2 is not a matching value, control is performed to change VC2. Specifically, it is determined that the reflection coefficient ( ⁇ ) is not on a circle, and the process proceeds to step S6.
  • This M is also ideally 0, but in reality it is difficult to make it 0, so it is set to a predetermined value.
  • step S5 If P is equal to or less than the predetermined threshold (M) (No in step S5), VC2 is a matching value, so there is no need to change VC2. Therefore, the process proceeds to the control operation of VC1 (that is, the first variable capacitor 31). That is, it is determined that the reflection coefficient ( ⁇ ) is on a circle, and the process proceeds to step S10.
  • step S6 in order to determine the direction in which VC2 (that is, the second variable capacitor 32) is controlled, it is determined whether or not the reflection coefficient ( ⁇ ) is inside the circle. If the reflection coefficient ( ⁇ ) is inside the circle (Yes in step S6), VC2 is smaller than Y, so VC2 is increased (step S7). If the reflection coefficient ⁇ is outside the circle (No in step S6), VC2 is larger than Y, so VC2 is reduced (step S8). At this time, the amount to be reduced and the amount to be increased may be set in advance.
  • step S5 a predetermined threshold value (M)
  • the reflection coefficient
  • step S10 it is determined whether or not the imaginary part of the reflection coefficient ( ⁇ ) is negative, that is, whether or not VC1 is smaller than X.
  • VC1 is smaller than X when the imaginary part of the reflection coefficient ( ⁇ ) is negative, and VC1 is larger than X when the imaginary part of the reflection coefficient ( ⁇ ) is positive. Therefore, when the imaginary part of the reflection coefficient ( ⁇ ) is negative (Yes in step S10), VC1 is increased. If the imaginary part of the reflection coefficient ( ⁇ ) is positive (No in step S10), VC1 is decreased. Thus, by changing VC1, the reflection coefficient ( ⁇ ) is brought close to zero. The amount of increase / decrease at this time is also set in advance.
  • the control unit 20 calculates a reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and a circle drawn by the locus of the reflection coefficient passing through the matching point on the Smith chart. And the calculated reflection coefficient is larger than a predetermined value, the capacitance value of the second variable capacitor 32 is changed, and the calculated reflection coefficient is changed to change the distance. When the distance is within the predetermined value and the distance is within the predetermined value, the capacitance value of the first variable capacitor 31 is changed, and the calculated reflection coefficient is reduced without changing the distance.
  • control unit 20 calculates a reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and the first variable capacitance capacitor 31 is configured so that the calculated reflection coefficient becomes small.
  • the capacitance value and the capacitance value of the second variable capacitor 32 are changed.
  • FIG. 8 is a diagram showing the impedance (with VC1 fixed) of a matching unit equipped with a correctly adjusted variable capacitor.
  • FIG. 9 is a diagram showing the impedance (with VC2 fixed) of a matching device equipped with a correctly adjusted variable capacitor.
  • FIG. 10 is a diagram illustrating the impedance (VC1 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted.
  • FIG. 11 is a diagram showing the impedance (VC2 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted.
  • the matching unit is left to the capacitor manufacturer to adjust the capacitance value of the variable capacitor mounted inside, so even if the capacitance value of the variable capacitor is set due to human factors such as adjustment errors by the manufacturer There are rare individuals with completely different capacities. As shown in FIGS. 8 and 10, the reflection coefficients (U, V) when VC1 is fixed and VC2 is changed are completely different. Further, as shown in FIGS. 9 and 11, the reflection coefficients (U, V) when VC2 is fixed and VC1 is changed are completely different.
  • a matching device equipped with variable capacitance capacitors with different capacitance values has a completely different impedance even if the same capacitance value is set as other matching devices, so matching operation (trajectory, time) even when connected to plasma load
  • the throughput of the plasma processing apparatus depends on individual matching devices and is not stable.
  • the capacitance value-impedance data of the variable capacitor of the reference matching device is prepared, and the capacitance of the variable capacitance capacitor is obtained by bringing the impedance of the other matching device closer to the data of the reference matching device. Differences in individual matching operations due to errors are solved, and uniform matching operations are performed uniformly. Details will be described below.
  • FIG. 12 is a flowchart showing the capacity adjustment and matching operation of the variable capacitor.
  • FIG. 13 is a diagram showing the relationship (VC2 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B).
  • FIG. 14 is a diagram showing the relationship (VC1 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B).
  • FIG. 15 is a diagram showing a conversion table (VC1).
  • FIG. 16 shows the conversion table (VC2).
  • Step S21 The data (C, D) as a set of the variable capacitor step value (C) of the reference matching unit (hereinafter referred to as matching unit (A)) and the impedance (D) at that time are measured in advance.
  • matching unit (A) the reference matching unit
  • D impedance
  • the reflection coefficient (U, V) is measured.
  • Step S22 A matching unit on the correction side, that is, a matching unit equipped with a variable capacitor that is not correctly adjusted (hereinafter referred to as a matching unit (B)) is the matching unit (A) obtained in step S21.
  • a step value (E) that becomes the impedance (D) of the variable capacitor is measured and prepared. For example, (E0, D0), (E1, D1), (E2, D2), (E3, D3), ..., (En, Dn).
  • the VC1 step value of the matching unit (B) is fixed at 347, and the VC2 value of the matching unit (A) is changed from 0 to 640 by changing the step value of VC2 (U, V) value.
  • Search for the value of VC2 such that The result is shown in FIG.
  • the VC2 step value of the matching unit (B) is fixed at 363 from the search result in step S21, and the VC1 of the matching unit (A) is changed in 80 steps from 0 to 640 by changing the step value of VC1.
  • Step S23 The data acquired in step S22 is downloaded from an external terminal such as the PC 40 to the matching unit and stored in a nonvolatile storage medium such as an EEPROM in the storage unit.
  • the VC1 data sets (0, 30), (80, 110), (160, 190), (240, 268), (320) of the matching units (A) and (B) shown in FIG. , 347), (400, 424), (480, 499), (560, 575), and (640, 640) are stored in the external EEPROM 253 of the storage unit 25 using an external terminal such as the PC 40.
  • Step S24 When the matching unit is powered on, a table is created on a volatile storage medium such as SRAM of the storage unit with reference to the data stored in Step S23.
  • the table interpolates between data depending on the resolution of the original data.
  • control unit 20 refers to the data stored in the external EEPROM in step S24 when the matching unit (B) is powered on, and determines the two points from the relationship shown in the graphs of FIGS. By repeating this interpolation, the correction step value for each step is obtained for each of the VC1 and VC2 steps 0 to 640 of the matching unit (B) with respect to the true step value. Then, as shown in FIGS. 15 and 16, the control unit 20 develops 0 to 640 in the external SRAM 252 of the storage unit 25 as indexes (addresses) on the memory (stores correction step values).
  • Step S25 The capacity of the matching device derived by the calculation and algorithm at the time of matching operation is step-converted by the table created in step S24, and the capacitance value actually set in the variable capacitor is determined from the step value and set.
  • the control unit 20 performs the capacity calculation of VC1 and VC2 to be set in the matching operation using the reflection coefficient and the algorithm in the capacity calculation unit 22 of FIG. Is actually set to the first variable capacitor 31 and the second variable capacitor 32 by the capacitance setting unit 23 to perform the matching operation.
  • the calculation result in the capacity calculation unit 22 is compared with the capacity setting unit 23 in order from 0 to 640 of the indexes in the tables of FIG. 15 and FIG. 16, and the correction capacity value corresponding to the index that matches the calculation result is set. .
  • the capacity calculation unit 22 acquires a step value from the first variable capacitor 31 or the second variable capacitor 32 as necessary, and uses it as a material for calculating the set capacity. In that case, the acquired step value and the correction capacitance value in the table are compared in order from the top, and the index of the matching correction capacitance value becomes the step value before correction.
  • the throughput of the plasma processing equipment does not depend on each matching unit and is stabilized. Even if an inexpensive variable capacitor with inferior capacity accuracy is used, capacity correction can be performed using a high performance variable capacitor as reference data, leading to cost reduction.
  • the matching device is suitable for a microwave power source for generating plasma, and can be used in a wide frequency including ISM bands such as 13.56 MHz, 915 MHz, 2.45 GHz, and 5.8 GHz.
  • This specification includes at least the following configurations related to the present invention.
  • the matching device of the first configuration is: A directional coupler for detecting traveling waves and reflected waves; An input terminal, an output terminal, a first variable capacitor having one end connected to the input terminal via a first transmission line and the other end grounded, and one end connected to the output via a second transmission line A second variable capacitor connected to the terminal and grounded at the other end; one end connected to the one end of the first variable capacitor; the other end connected to the one end of the second variable capacitor.
  • a matching circuit having an inductance; and A control unit for controlling a capacitance value of the first variable capacitor and a capacitance value of the second variable capacitor based on a traveling wave and a reflected wave detected by the directional coupler; The value obtained based on the set value of the capacitance value of the third variable capacitor and the fourth variable capacitor of the reference matching unit and the impedance of the reference matching unit when the set value is set A storage unit that stores a correction value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor; With The controller is Based on the traveling wave and the reflected wave detected by the directional coupler, a reflection coefficient is calculated, Changing the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor so that the calculated reflection coefficient becomes small; Calculating a set value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor; The capacitance value of the first variable capacitor and the set value of the capacitance value of the second variable capacitor are set
  • the matching device of the second configuration is the first configuration
  • the correction set values of the first variable capacitor and the second variable capacitor are set values of the first variable capacitor and the second variable capacitor of the matching device that are the impedance of the reference matching device. Is obtained by measuring.
  • the matching device of the third configuration is the second configuration
  • the storage unit includes a nonvolatile storage medium
  • the setting values of the capacitance values of the third variable capacitor and the fourth variable capacitance capacitor, the correction values of the capacitance values of the first variable capacitance capacitor, and the capacitance value of the second variable capacitance capacitor are non-volatile. Stored in a sexual storage medium.
  • the matching device of the fourth configuration is the third configuration
  • the storage unit further includes a volatile storage medium
  • the control unit sets a set value of capacitance values of the third variable capacitor and the fourth variable capacitor, a capacitance value of the first variable capacitor, and the second variable when the matching unit is powered on. Interpolation data is calculated based on the correction setting value of the capacitance value of the capacitor and a table is created and stored in the volatile storage medium.
  • the matching device of the fifth configuration is the fourth configuration
  • the table includes a first table configured to read out a correction setting value of the capacitance value of the first variable capacitor using the setting value of the capacitance value of the third variable capacitor as an index, and the fourth table And a second table configured to read out a correction setting value of the capacitance value of the second variable capacitor using the setting value of the capacitance value of the variable capacitor as an index.
  • DESCRIPTION OF SYMBOLS 2 ... High frequency power supply device, 3 ... Plasma processing apparatus, 10 ... Matching device, 11 ... Directional coupler, 20 ... Control part, 21 ... Reflection coefficient calculating part, 22 ... Capacity calculating part, 23 ... Capacity setting part, 25 ... Storage unit 30 ... matching circuit 30a ... input terminal 30b ... output terminal 31 ... first variable capacitor 32 ... second variable capacitor 31a ... control terminal 32a ... control terminal 33 ... inductance 35, 36 ... transmission lines.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Plasma Technology (AREA)

Abstract

This matching device is provided with: a directional coupler; a matching circuit comprising a first variable capacitor and a second variable capacitor; a control unit; and a storage unit that stores corrected setting values for the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor determined on the basis of set values for the capacitance values of a third variable capacitor and a fourth variable capacitor in a matching device serving as a reference and of the impedance of the matching device serving as the reference when the set values were set. The control unit corrects the set values for the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor on the basis of the corrected setting values for the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor in the storage unit.

Description

整合器Matcher
 本開示は整合器に関し、例えば高周波電源装置の出力を負荷に整合させる整合器に適用可能である。 The present disclosure relates to a matching device and can be applied to, for example, a matching device that matches the output of a high frequency power supply device to a load.
 エッチングや薄膜形成を行う半導体製造工程では、プラズマ処理装置が用いられる。このプラズマ処理装置の電力供給源として、高周波電源装置が用いられる。高周波電源装置からプラズマ処理装置に対し、効率良く電力を供給するには、高周波電源装置とプラズマ処理装置(負荷)との間でインピーダンスを整合させる必要がある。インピーダンスを整合させる手段として、例えば特許文献1に示されるように、高周波電源装置とプラズマ処理装置との間に整合器が挿入される。整合器は高周波電源装置とプラズマ処理装置との間でインピーダンスを整合させる整合素子を有する整合回路を含むように構成されている。整合回路は、可変容量コンデンサ、インダクタンス、伝送線路を含むように構成されている。 A plasma processing apparatus is used in a semiconductor manufacturing process in which etching or thin film formation is performed. A high frequency power supply device is used as a power supply source of the plasma processing apparatus. In order to efficiently supply power from the high frequency power supply device to the plasma processing apparatus, it is necessary to match the impedance between the high frequency power supply apparatus and the plasma processing apparatus (load). As a means for matching impedance, for example, as shown in Patent Document 1, a matching unit is inserted between a high frequency power supply device and a plasma processing apparatus. The matching unit is configured to include a matching circuit having a matching element for matching impedance between the high-frequency power supply device and the plasma processing apparatus. The matching circuit is configured to include a variable capacitor, an inductance, and a transmission line.
WO2015/129678号公報WO2015 / 129678
 可変容量コンデンサはステッピングモータを用いて容量値の変更制御を行うが、可変容量コンデンサの容量精度の要因により、可変容量コンデンサの容量値を設定しても設定値と全く異なる容量となる個体が稀に存在する。その可変容量コンデンサを搭載した整合器は他の整合器と同じ容量を設定してもインピーダンスが全く異なるためプラズマ負荷と接続しても整合動作(軌跡、時間)に顕著な違いが生まれ、プラズマ処理装置のスループットが個々の整合器に依存し、安定しない。
  本開示の課題は、可変容量コンデンサの容量誤差を低減する整合器を提供することにある。
A variable capacitor uses a stepping motor to change the capacitance value, but due to the capacitance accuracy of the variable capacitor, there are rare instances where the capacitance value of the variable capacitor is completely different from the set value even if it is set. Exists. Matching devices equipped with the variable capacitors have the same impedance as other matching devices, but the impedance is completely different, so there is a significant difference in matching operation (trajectory, time) even when connected to a plasma load. The throughput of the device depends on the individual matchers and is not stable.
The subject of this indication is providing the matching device which reduces the capacity | capacitance error of a variable capacitor.
 本開示のうち代表的なものの概要を簡単に説明すれば下記の通りである。
  すなわち、整合器は、方向性結合器と、第1の可変容量コンデンサと第2の可変容量コンデンサとを有する整合回路と、制御部と、基準とする整合器の第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記設定値が設定されたときの前記基準とする整合器のインピーダンスとに基づいて求めた前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値を格納する記憶部と、を備える。前記制御部は、前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の設定値を前記記憶部の前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値に基づいて補正する。
An outline of typical ones of the present disclosure will be briefly described as follows.
That is, the matching device includes a directional coupler, a matching circuit having a first variable capacitor and a second variable capacitor, a control unit, a third variable capacitor of the reference matcher, and a first variable capacitor. The capacitance value of the first variable capacitor obtained based on the set value of the capacitance value of the variable capacitor of 4 and the impedance of the reference matching device when the set value is set, and the second A storage unit that stores a correction setting value of the capacitance value of the variable capacitor. The control unit sets a capacitance value of the first variable capacitor and a set value of the capacitance value of the second variable capacitor, and sets the capacitance value of the first variable capacitor and the second variable of the storage unit. Correction is made based on the correction setting value of the capacitance value of the capacitor.
 上記整合器によれば、容量誤差を低減することができる。 According to the matching device, the capacity error can be reduced.
図1は実施例に係る整合器の機能ブロック図である。FIG. 1 is a functional block diagram of the matching device according to the embodiment. 図2は実施例に係る整合回路の構成図である。FIG. 2 is a configuration diagram of the matching circuit according to the embodiment. 図3は実施例に係る記憶部の構成図である。FIG. 3 is a configuration diagram of a storage unit according to the embodiment. 図4は可変容量コンデンサの容量を変えたときの反射係数の軌跡の一例を説明する図。FIG. 4 is a diagram for explaining an example of the locus of the reflection coefficient when the capacitance of the variable capacitor is changed. 図5は可変容量コンデンサの容量を変えたときの反射係数の軌跡の他の例を説明する図。FIG. 5 is a diagram for explaining another example of the locus of the reflection coefficient when the capacitance of the variable capacitor is changed. 図6は実施例に係る反射係数の軌跡を示す図である。FIG. 6 is a diagram illustrating a locus of a reflection coefficient according to the example. 図7は実施例に係るインピーダンス整合の処理フローチャートである。FIG. 7 is a flowchart of impedance matching processing according to the embodiment. 図8は正しく調整された可変容量コンデンサを搭載した整合器のインピーダンス(VC1を固定)を示す図である。FIG. 8 is a diagram showing the impedance (with VC1 fixed) of a matching unit equipped with a correctly adjusted variable capacitor. 図9は正しく調整された可変容量コンデンサを搭載した整合器のインピーダンス(VC2を固定)を示す図である。FIG. 9 is a diagram showing the impedance (with VC2 fixed) of a matching device equipped with a correctly adjusted variable capacitor. 図10は正しく調整されていない可変容量コンデンサを搭載した整合器のインピーダンス(VC1を固定)を示す図である。FIG. 10 is a diagram illustrating the impedance (VC1 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted. 図11は正しく調整されていない可変容量コンデンサを搭載した整合器のインピーダンス(VC2を固定)を示す図である。FIG. 11 is a diagram showing the impedance (VC2 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted. 図12は可変容量コンデンサの容量調整および整合動作を示すフローチャートである。FIG. 12 is a flowchart showing the capacity adjustment and matching operation of the variable capacitor. 図13は整合器(A)(B)のVCステップ値と反射係数(U,V)値の関係(VC2固定)を示す図である。FIG. 13 is a diagram showing the relationship (VC2 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B). 図14は整合器(A)(B)のVCステップ値と反射係数(U,V)値の関係(VC1固定)を示す図である。FIG. 14 is a diagram showing the relationship (VC1 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B). 図15は変換テーブル(VC1)を示す図である。FIG. 15 is a diagram showing a conversion table (VC1). 図16は変換テーブル(VC2)を示す図である。FIG. 16 shows the conversion table (VC2).
 以下、実施例について、図面を用いて説明する。ただし、以下の説明において、同一構成要素には同一符号を付し繰り返しの説明を省略することがある。 Hereinafter, examples will be described with reference to the drawings. However, in the following description, the same components may be denoted by the same reference numerals and repeated description may be omitted.
 図1は、実施例に係る整合器の機能ブロック図である。図1では、高周波電源装置2とプラズマ処理装置3との間に、整合器10が挿入されている。高周波電源装置2から出力した高周波電力を、整合器10を介してプラズマ処理装置3に供給することで、プラズマ処理装置3でプラズマを発生させる。高周波電源装置2からプラズマ処理装置3に効率よく電力を供給するためには、高周波電源装置2とプラズマ処理装置3との間でインピーダンスを整合させる必要がある。高周波電源装置2の出力インピーダンスは通常50Ωであるため、プラズマ処理装置3の入力インピーダンスを、整合器10によって変換し、整合器10の入力インピーダンスを50Ωにすればよい。 FIG. 1 is a functional block diagram of the matching device according to the embodiment. In FIG. 1, a matching device 10 is inserted between the high frequency power supply device 2 and the plasma processing device 3. By supplying high-frequency power output from the high-frequency power supply device 2 to the plasma processing device 3 via the matching unit 10, plasma is generated in the plasma processing device 3. In order to efficiently supply power from the high frequency power supply device 2 to the plasma processing apparatus 3, it is necessary to match the impedance between the high frequency power supply apparatus 2 and the plasma processing apparatus 3. Since the output impedance of the high-frequency power supply device 2 is normally 50Ω, the input impedance of the plasma processing device 3 may be converted by the matching device 10 so that the input impedance of the matching device 10 is 50Ω.
 プラズマ処理装置3の入力インピーダンスは、プラズマ処理装置3に入力されるガスの種類や流量、圧力、温度等によって変化する。よって、整合器10は、時間的に変化するプラズマ処理装置3の入力インピーダンスに合わせて、適応的に整合する必要がある。 The input impedance of the plasma processing apparatus 3 varies depending on the type, flow rate, pressure, temperature, etc. of the gas input to the plasma processing apparatus 3. Therefore, the matching unit 10 needs to adaptively match according to the input impedance of the plasma processing apparatus 3 that changes with time.
 図1の整合器10は、進行波と反射波とを検出する方向性結合器11と、高周波電源装置2とプラズマ処理装置3との間でインピーダンスを整合させる整合素子を有する整合回路30と、整合回路30の整合素子の回路定数を制御するための制御部20と、記憶部25と、を含むように構成される。 1 includes a directional coupler 11 for detecting traveling waves and reflected waves, a matching circuit 30 having a matching element for matching impedance between the high-frequency power supply device 2 and the plasma processing device 3, The control unit 20 for controlling the circuit constant of the matching element of the matching circuit 30 and the storage unit 25 are configured.
 方向性結合器11の動作を説明する。RFin端子からRFout端子に向かって進む高周波電力(進行波:Pf)は、方向性結合器11で検出され、FORWARD端子に出力される。RFout端子からRFin端子に向かって進む高周波電力(反射波:Pr)は、方向性結合器11で検出され、REFLECT端子に出力される。また、RFin端子からRFout端子に向かって進む高周波電力(Pf)は、REFLECT端子では検出されず、もし検出されても僅かである。同様に、RFout端子からRFin端子に向かって進む高周波電力(Pr)は、FORWARD端子では検出されず、もし検出されても僅かである。 The operation of the directional coupler 11 will be described. High-frequency power (traveling wave: Pf) traveling from the RFin terminal toward the RFout terminal is detected by the directional coupler 11 and output to the FORWARD terminal. High frequency power (reflected wave: Pr) traveling from the RFout terminal to the RFin terminal is detected by the directional coupler 11 and output to the REFLECT terminal. Further, the high-frequency power (Pf) traveling from the RFin terminal toward the RFout terminal is not detected by the REFECT terminal but is small even if detected. Similarly, the high-frequency power (Pr) traveling from the RFout terminal toward the RFin terminal is not detected at the FORWARD terminal and is small if detected.
 制御部20は、反射係数演算部21と、容量演算部22と、容量設定部23とを含むように構成される。 The control unit 20 is configured to include a reflection coefficient calculation unit 21, a capacitance calculation unit 22, and a capacitance setting unit 23.
 方向性結合器11で検出された進行波(Pf)と反射波(Pr)は、制御部20の反射係数演算部21に入力される。反射係数(Γ)は、進行波(Pf)に対する反射波(Pr)の振幅比(r)と位相差(θ)から、式(1)のように定義される。
      Γ=r・exp(j・θ) (j:虚数単位)・・・(1)
 よって、進行波(Pf)に対する反射波(Pr)の振幅比(r)と位相差(θ)が分かれば、反射係数(Γ)を求めることが出来る。反射係数演算部21では、進行波(Pf)と反射波(Pr)とに基づき、上記振幅比(r)と位相差(θ)を計算し、反射係数(Γ)を算出する。具体的な方法としては、進行波(Pf)と反射波(Pr)をFFT(高速フーリエ変換)によって周波数領域に変換し、高周波電源装置2が出力している高周波電力と同じ周波数について、進行波(Pf)と反射波(Pr)の振幅と位相を比較し、振幅比(r)と位相差(θ)を計算すればよい。
The traveling wave (Pf) and the reflected wave (Pr) detected by the directional coupler 11 are input to the reflection coefficient calculation unit 21 of the control unit 20. The reflection coefficient (Γ) is defined as in Expression (1) from the amplitude ratio (r) of the reflected wave (Pr) to the traveling wave (Pf) and the phase difference (θ).
Γ = r · exp (j · θ) (j: imaginary unit) (1)
Therefore, if the amplitude ratio (r) and the phase difference (θ) of the reflected wave (Pr) with respect to the traveling wave (Pf) are known, the reflection coefficient (Γ) can be obtained. The reflection coefficient calculator 21 calculates the amplitude ratio (r) and the phase difference (θ) based on the traveling wave (Pf) and the reflected wave (Pr), and calculates the reflection coefficient (Γ). As a specific method, the traveling wave (Pf) and the reflected wave (Pr) are converted into a frequency domain by FFT (Fast Fourier Transform), and the traveling wave is the same frequency as the high-frequency power output from the high-frequency power supply device 2. The amplitude ratio (r) and the phase difference (θ) may be calculated by comparing the amplitude and phase of (Pf) and the reflected wave (Pr).
 容量演算部22は、反射係数演算部21で計算された反射係数(Γ)に基づき、反射係数(Γ)をゼロに近づけるためのコンデンサ容量を計算する。コンデンサ容量の計算方法については後述する。容量設定部23は、容量演算部22で算出したコンデンサの容量に基づき、整合回路30内の可変容量コンデンサの容量を設定、変更する。 The capacitance calculation unit 22 calculates a capacitor capacity for making the reflection coefficient (Γ) close to zero based on the reflection coefficient (Γ) calculated by the reflection coefficient calculation unit 21. A method for calculating the capacitor capacity will be described later. The capacitance setting unit 23 sets and changes the capacitance of the variable capacitance capacitor in the matching circuit 30 based on the capacitance of the capacitor calculated by the capacitance calculation unit 22.
 図2は実施例に係る整合回路の構成図である。整合回路30は、負荷となるプラズマ処理装置3の入力インピーダンスが変動する範囲によって回路構成が決まるが、ここでは、π型の整合回路を例にして説明する。この整合回路30は、第1の可変容量コンデンサ31、第2の可変容量コンデンサ32、インダクタンス33、伝送線路35、伝送線路36を含むように構成されている。この伝送線路35と伝送線路36は、同軸ケーブルや金属板などで構成することができ、また、インダクタやコンデンサの集中定数回路を含むように構成することもできる。 FIG. 2 is a configuration diagram of the matching circuit according to the embodiment. The circuit configuration of the matching circuit 30 is determined by the range in which the input impedance of the plasma processing apparatus 3 serving as a load varies. Here, a description will be given by using a π-type matching circuit as an example. The matching circuit 30 includes a first variable capacitor 31, a second variable capacitor 32, an inductance 33, a transmission line 35, and a transmission line 36. The transmission line 35 and the transmission line 36 can be configured by a coaxial cable, a metal plate, or the like, or can be configured to include a lumped constant circuit of an inductor or a capacitor.
 伝送線路35は、整合回路30の入力端子30aと第1の可変容量コンデンサ31の一端を接続する。第1の可変容量コンデンサ31の他端は接地されている。伝送線路36は、整合回路30の出力端子30bと第2の可変容量コンデンサ32の一端を接続する。第2の可変容量コンデンサ32の他端は接地されている。 The transmission line 35 connects the input terminal 30 a of the matching circuit 30 and one end of the first variable capacitor 31. The other end of the first variable capacitor 31 is grounded. The transmission line 36 connects the output terminal 30 b of the matching circuit 30 and one end of the second variable capacitor 32. The other end of the second variable capacitor 32 is grounded.
 第1の可変容量コンデンサ31、第2の可変容量コンデンサ32、インダクタンス33は、高周波電源装置2とプラズマ処理装置3との間のインピーダンス整合を行うための整合素子である。また、整合回路30は、第1の可変容量コンデンサ31の容量を制御するための可変容量コンデンサ制御端子31aと、第2の可変容量コンデンサ32の容量を制御するための可変容量コンデンサ制御端子32aとを備える。 The first variable capacitor 31, the second variable capacitor 32, and the inductance 33 are matching elements for impedance matching between the high frequency power supply device 2 and the plasma processing device 3. The matching circuit 30 includes a variable capacitor control terminal 31a for controlling the capacitance of the first variable capacitor 31 and a variable capacitor control terminal 32a for controlling the capacitance of the second variable capacitor 32. Is provided.
 整合回路30の可変容量コンデンサの制御は、方向性結合器11で検波した進行波(Pf)と反射波(Pr)から計算される反射係数(Γ)の大きさが小さくなるように制御される。 Control of the variable capacitor of the matching circuit 30 is controlled so that the magnitude of the reflection coefficient (Γ) calculated from the traveling wave (Pf) detected by the directional coupler 11 and the reflected wave (Pr) becomes small. .
 前述したように、制御部20は、方向性結合器11で検出した進行波と反射波とに基づき、反射係数を算出し、該反射係数を用いて、第1の可変容量コンデンサ31の容量値(VC1)と第2の可変容量コンデンサ32の容量値(VC2)とを制御する。記憶部25は、後述する円の情報等を記憶する。なお、図3に示すように、記憶部25はCPU内蔵SRAM251と外部SRAM(揮発性メモリ)252と外部EEPROM(不揮発性メモリ)253とを備える。 As described above, the control unit 20 calculates the reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and uses the reflection coefficient to determine the capacitance value of the first variable capacitor 31. (VC1) and the capacitance value (VC2) of the second variable capacitor 32 are controlled. The storage unit 25 stores circle information and the like described later. As shown in FIG. 3, the storage unit 25 includes a CPU built-in SRAM 251, an external SRAM (volatile memory) 252, and an external EEPROM (nonvolatile memory) 253.
 ここで、円の情報とは、スミスチャート上で整合点(反射係数(Γ)の実部と虚部がゼロの点)を通過する反射係数(Γ)の軌跡が描く円の情報であって、円の位置や大きさに関する情報である。この円の情報は、伝送線路35の条件、つまり伝送線路35の特性インピーダンス(ZL)や線路長(L)に基づき、決定されることが知られている。 Here, the circle information is the circle information drawn by the locus of the reflection coefficient (Γ) passing through the matching point (the point where the real part and the imaginary part of the reflection coefficient (Γ) are zero) on the Smith chart. Information on the position and size of the circle. It is known that this circle information is determined based on the condition of the transmission line 35, that is, the characteristic impedance (ZL) and the line length (L) of the transmission line 35.
 容量演算部22は、反射係数演算部21で算出された反射係数(Γ)と、記憶部25に記憶している円の情報とに基づき、算出された反射係数(Γ)に対応する整合回路30の第1の可変容量コンデンサ31の容量値(VC1)および第2の可変容量コンデンサ32の容量値(VC2)を算出する。つまり、算出された反射係数(Γ)を小さくするようなVC1とVC2を算出する。 The capacitance calculation unit 22 is a matching circuit corresponding to the calculated reflection coefficient (Γ) based on the reflection coefficient (Γ) calculated by the reflection coefficient calculation unit 21 and the circle information stored in the storage unit 25. The capacitance value (VC1) of the 30 first variable capacitor 31 and the capacitance value (VC2) of the second variable capacitor 32 are calculated. That is, VC1 and VC2 that reduce the calculated reflection coefficient (Γ) are calculated.
 詳しくは、容量演算部22は、反射係数演算部21で算出される反射係数(Γ)が、記憶部25に記憶している円に接近するように、整合回路30の第2の可変容量コンデンサ32の容量値(VC2)を算出する。そして、容量設定部23は、上記算出した容量になるよう、第2の可変容量コンデンサ32の容量値(VC2)を変更する。これにより、容量設定部23は、反射係数Γを、前記円上に位置させる。 Specifically, the capacitance calculation unit 22 is configured so that the reflection coefficient (Γ) calculated by the reflection coefficient calculation unit 21 approaches the circle stored in the storage unit 25. A capacity value (VC2) of 32 is calculated. Then, the capacitance setting unit 23 changes the capacitance value (VC2) of the second variable capacitor 32 so that the calculated capacitance is obtained. Thereby, the capacitance setting unit 23 positions the reflection coefficient Γ on the circle.
 その後、容量演算部22は、反射係数演算部21で算出される反射係数Γが小さくなるように、整合回路30の第1の可変容量コンデンサ31の容量値(VC1)を算出する。そして、容量設定部23は、上記算出した容量になるよう、第1の可変容量コンデンサ31の容量値(VC1)を変更する。これにより、容量設定部23は、反射係数(Γ)を、整合点(反射係数(Γ)が0の点)に位置させる。 After that, the capacitance calculation unit 22 calculates the capacitance value (VC1) of the first variable capacitor 31 of the matching circuit 30 so that the reflection coefficient Γ calculated by the reflection coefficient calculation unit 21 becomes small. Then, the capacitance setting unit 23 changes the capacitance value (VC1) of the first variable capacitor 31 so that the calculated capacitance is obtained. Thereby, the capacity setting unit 23 positions the reflection coefficient (Γ) at the matching point (the point where the reflection coefficient (Γ) is 0).
 記憶部25には、伝送線路35に応じた円の情報が、予め記憶されている。この円の情報(位置と大きさ)は、前述したように、伝送線路35の条件、つまり伝送線路35の性インピーダンス(ZL)や線路長(L)に基づき決定される。例えば、伝送線路35が、無視できるほどに短い場合は、円は、後述する図4に示す円R1となる。また、伝送線路35が、特性インピーダンスが50Ωで、線路長がλ/4である場合は、円は、後述する図5に示す円R2や、図6に示す円R3となる。 In the storage unit 25, circle information corresponding to the transmission line 35 is stored in advance. As described above, the information (position and size) of the circle is determined based on the condition of the transmission line 35, that is, the sex impedance (ZL) and the line length (L) of the transmission line 35. For example, when the transmission line 35 is short enough to be ignored, the circle becomes a circle R1 shown in FIG. Further, when the transmission line 35 has a characteristic impedance of 50Ω and a line length of λ / 4, the circle is a circle R2 shown in FIG. 5 and a circle R3 shown in FIG.
 ここで、本実施形態の整合アルゴリズムの考え方を説明する。あるプラズマ負荷のときに、高周波電源装置2とプラズマ処理装置3との間のインピーダンスが整合する(つまり反射係数(Γ)が0)ときのVC1とVC2の値を、VC1=X、VC2=Yとする。説明を解り易くするために、整合する条件であるVC1=X、VC2=Yの状態から、VC1を変えたときの、整合回路30の入力インピーダンスの軌跡、つまり、反射係数(Γ)の軌跡を図4のスミスチャートに示す。この場合、伝送線路35は、進行波や反射波の波長(λ)に比べ、無視できるほど短いものとする。 Here, the concept of the matching algorithm of this embodiment will be described. When the impedance between the high frequency power supply device 2 and the plasma processing device 3 matches (that is, the reflection coefficient (Γ) is 0) at a certain plasma load, the values of VC1 and VC2 are VC1 = X and VC2 = Y. And For easy understanding, the locus of the input impedance of the matching circuit 30, that is, the locus of the reflection coefficient (Γ) when VC1 is changed from the matching conditions VC1 = X and VC2 = Y. This is shown in the Smith chart of FIG. In this case, the transmission line 35 is assumed to be negligibly short compared to the wavelength (λ) of the traveling wave or the reflected wave.
 図4において、VC1を変えると、反射係数(Γ)の軌跡は、整合がとれている状態であるF点と、G点とを結ぶ線分を直径とする円R1を描く。F点における反射係数(Γ)は、その虚部(Γi)がゼロであり、その実部(Γr)がゼロである(整合器10の入力インピーダンスは50Ω)。G点における反射係数(Γ)は、その虚部がゼロであり、その実部が-1である。 4, when VC1 is changed, the locus of the reflection coefficient (Γ) draws a circle R1 whose diameter is a line segment connecting the F point and the G point in a matched state. The reflection coefficient (Γ) at point F has zero imaginary part (Γi) and zero real part (Γr) (the input impedance of the matching device 10 is 50Ω). The reflection coefficient (Γ) at point G has an imaginary part of zero and a real part of −1.
 詳しくは、図4において、整合がとれている状態(F点)でVC1を増やすと、反射係数(Γ)は、円R1上をF点からA点の方向に動く。また、VC1を減らすと、円R1上をF点からB点の方向に動く。このことは、第1の可変容量コンデンサ31と第2の可変容量コンデンサ32とインダクタンス33とを含む図2のπ型整合回路30において、第1の可変容量コンデンサ31がグランドに接続(接地)されているときのインピーダンス軌跡として、一般的に知られているため、詳細な説明は割愛する。 Specifically, in FIG. 4, when VC1 is increased in a state of matching (point F), the reflection coefficient (Γ) moves on the circle R1 from the point F to the point A. Further, when VC1 is decreased, it moves on the circle R1 from the point F to the point B. This is because the first variable capacitor 31 is connected (grounded) to the ground in the π-type matching circuit 30 of FIG. 2 including the first variable capacitor 31, the second variable capacitor 32, and the inductance 33. Since it is generally known as an impedance locus when it is, detailed description is omitted.
 図4では、伝送線路35が無視できる場合を示したが、現実には無視できないこともある。図5のスミスチャートに、伝送線路35の特性インピーダンスが50Ωで線路長がλ/4の場合の、反射係数(Γ)の軌跡を示す。図4において、反射係数(Γ)の軌跡は、整合がとれている状態であるF点と、H点とを結ぶ線分を直径とする円R2を描くことが知られている。H点における反射係数(Γ)は、その虚部がゼロであり、その実部が1である(整合器10の入力インピーダンスは無限大)。 FIG. 4 shows a case where the transmission line 35 can be ignored, but in reality it may not be ignored. The Smith chart of FIG. 5 shows the locus of the reflection coefficient (Γ) when the characteristic impedance of the transmission line 35 is 50Ω and the line length is λ / 4. In FIG. 4, it is known that the locus of the reflection coefficient (Γ) draws a circle R2 whose diameter is a line segment connecting the F point and the H point in a matched state. The reflection coefficient (Γ) at point H has an imaginary part of zero and a real part of 1 (the input impedance of the matching device 10 is infinite).
 図2の整合回路30において、伝送線路35の右端から見た入力インピーダンスをZ1とし、伝送線路35の左端から見た入力インピーダンスをZ2とすると、Z2は、次の式(2)により決まる。式(2)において、Z1は、伝送線路35が無視できる場合(図4)の入力インピーダンスであり、Z2は、伝送線路35が無視できない場合(図5)の入力インピーダンスである。伝送線路35が無視できない場合(図5)、図4の円R1は、図5の円R2になる。 In the matching circuit 30 of FIG. 2, assuming that the input impedance viewed from the right end of the transmission line 35 is Z1, and the input impedance viewed from the left end of the transmission line 35 is Z2, Z2 is determined by the following equation (2). In Expression (2), Z1 is an input impedance when the transmission line 35 can be ignored (FIG. 4), and Z2 is an input impedance when the transmission line 35 cannot be ignored (FIG. 5). When the transmission line 35 cannot be ignored (FIG. 5), the circle R1 in FIG. 4 becomes the circle R2 in FIG.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
 このように、図5の軌跡は、特性インピーダンスが50Ωで線路長がλ/4の伝送線路35を挿入しているため、図4の軌跡において、反射係数(Γ)の実部と虚部がゼロの点(F点)を中心にして、180°回転した状態になる。よって、図5において、整合がとれている状態(F点)でVC1を増やすと、反射係数(Γ)は、円R2上をA´点の方向(反射係数(Γ)の虚部が正の方向)に動く。また、VC1を減らすと、反射係数(Γ)は、円R2上をB´点の方向(反射係数(Γ)の虚部が負の方向)に動く。すなわち、図5の円R2上において、反射係数(Γ)の虚部が正の場合は、VC1が整合値Xよりも大きく、反射係数(Γ)の虚部が負の場合は、VC1が整合値Xよりも小さい。 As described above, since the transmission line 35 having the characteristic impedance of 50Ω and the line length of λ / 4 is inserted in the locus in FIG. 5, the real part and the imaginary part of the reflection coefficient (Γ) are in the locus in FIG. The state is rotated by 180 ° around the zero point (F point). Therefore, in FIG. 5, when VC1 is increased in a matched state (point F), the reflection coefficient (Γ) becomes the direction of the point A ′ on the circle R2 (the imaginary part of the reflection coefficient (Γ) is positive). Direction). When VC1 is decreased, the reflection coefficient (Γ) moves on the circle R2 in the direction of the point B ′ (the imaginary part of the reflection coefficient (Γ) is negative). That is, on the circle R2 in FIG. 5, when the imaginary part of the reflection coefficient (Γ) is positive, VC1 is larger than the matching value X, and when the imaginary part of the reflection coefficient (Γ) is negative, VC1 is matched. Less than value X.
 このように、図5では、整合点(F点)において、VC1を増加、又は減少させると、反射係数(Γ)は、円R2を描くような軌跡をたどる。このことは、VC2が整合値にある状態で、VC1を変えると、反射係数(Γ)は、図5で示した円R2上を移動することを示している。従って、まず、反射係数(Γ)が図5の円R2上にのるようにVC2を制御し、その後、反射係数(Γ)が0になるように、VC1を制御すればよいことが解る。 As described above, in FIG. 5, when VC1 is increased or decreased at the matching point (point F), the reflection coefficient (Γ) follows a locus that draws a circle R2. This indicates that when VC1 is changed in a state where VC2 is at the matching value, the reflection coefficient (Γ) moves on the circle R2 shown in FIG. Therefore, it can be understood that VC1 is first controlled so that the reflection coefficient (Γ) is on the circle R2 in FIG. 5, and then VC1 is controlled so that the reflection coefficient (Γ) becomes zero.
 図6は、図5と同様の整合回路30の場合、つまり、伝送線路35の特性インピーダンスが50Ωで線路長がλ/4の場合において、実施例に係るインピーダンス整合を行う際における、反射係数(Γ)の軌跡を示すスミスチャートである。C点は、プラズマ負荷がある入力インピーダンス値にある場合において、VC1とVC2が初期値(例えば、可変容量コンデンサの最小値)のときの、反射係数(Γ)、つまり、整合器10の入力インピーダンスである。 FIG. 6 shows a reflection coefficient (when the impedance matching is performed according to the embodiment in the case of the matching circuit 30 similar to FIG. 5, that is, when the characteristic impedance of the transmission line 35 is 50Ω and the line length is λ / 4. It is a Smith chart which shows the locus | trajectory of (GAMMA). The point C is the reflection coefficient (Γ) when VC1 and VC2 are initial values (for example, the minimum value of the variable capacitor), that is, the input impedance of the matching unit 10 when the plasma load is at a certain input impedance value. It is.
 まず、制御部20は、反射係数(Γ)が、VC1とVC2の初期値のC点から、円R3に接するD点に達するまで、VC2のみを増やす。円R3は、図5の円R2と同じである。円R3の情報は、記憶部25に記憶されている。反射係数(Γ)が、円R3に接するD点に到達すると、VC2は、整合時の容量であるYとなる。この状態では、VC2は、整合値に制御されているが、VC1は初期値のままである。そこで、制御部20は、次にVC1を増やしていく。VC1を増やすと、前述したように、反射係数(Γ)は、円R3上を移動する。したがって、VC1を増やしていき、反射係数(Γ)が0になるところで、VC1の増加を止めればよい。そのときのVC1は、整合時の容量であるXとなる。 First, the control unit 20 increases only VC2 until the reflection coefficient (Γ) reaches the point D in contact with the circle R3 from the initial point C of VC1 and VC2. The circle R3 is the same as the circle R2 in FIG. Information on the circle R3 is stored in the storage unit 25. When the reflection coefficient (Γ) reaches the point D in contact with the circle R3, VC2 becomes Y which is the capacity at the time of matching. In this state, VC2 is controlled to the matching value, but VC1 remains at the initial value. Therefore, the control unit 20 then increases VC1. When VC1 is increased, as described above, the reflection coefficient (Γ) moves on the circle R3. Therefore, it is only necessary to increase VC1 and stop increasing VC1 when the reflection coefficient (Γ) becomes zero. VC1 at that time is X, which is a capacity at the time of matching.
 図6の軌跡は、プラズマ負荷の入力インピーダンスがある値にある場合の一例であるが、プラズマ負荷の入力インピーダンスが変われば、当然、C点やD点の位置は変化する。ただし、VC2が整合時の容量である場合に、反射係数(Γ)が円R3上にあることは変わらない。 6 is an example when the input impedance of the plasma load is at a certain value. However, if the input impedance of the plasma load is changed, the positions of the point C and the point D naturally change. However, when VC2 is the capacitance at the time of matching, the reflection coefficient (Γ) is on the circle R3.
 また、図6のC点の場合は、VC1とVC2の初期値として、可変容量コンデンサの最小値を選んでいるが、可変容量コンデンサの最大値でもよく、また、その他の値でもよい。その場合、当然、C点の位置は変わる。しかし、VC1とVC2の初期値が何れの値であっても、VC2が整合時の値になっていれば、VC1を変えたときに、反射係数(Γ)が円R3上を移動するという現象は変わらない。 In the case of point C in FIG. 6, the minimum value of the variable capacitor is selected as the initial value of VC1 and VC2, but it may be the maximum value of the variable capacitor or any other value. In that case, of course, the position of the point C changes. However, regardless of the initial values of VC1 and VC2, if VC2 is the value at the time of matching, the phenomenon that the reflection coefficient (Γ) moves on the circle R3 when VC1 is changed. Will not change.
 よって、反射係数(Γ)が円R3に接するまで、VC2のみを制御し、円R3に接した後は、VC1のみを制御するという、制御部20の動作は変わらない。VC2の制御において、VC2が整合値であるYよりも大きいときは、反射係数(Γ)が円R3の外にあるので、VC2を減らすことにより、反射係数(Γ)が円R3に接するように制御する。逆に、VC2が整合値であるYよりも小さいときは、反射係数(Γ)が円R3の内にあるので、VC2を増やすことにより、反射係数(Γ)が円R3に接するように制御する。 Therefore, until the reflection coefficient (Γ) touches the circle R3, only the VC2 is controlled, and after touching the circle R3, only the VC1 is controlled. In the control of VC2, when VC2 is larger than the matching value Y, the reflection coefficient (Γ) is outside the circle R3, so that by reducing VC2, the reflection coefficient (Γ) is in contact with the circle R3. Control. On the contrary, when VC2 is smaller than the matching value Y, the reflection coefficient (Γ) is in the circle R3. Therefore, by increasing VC2, control is performed so that the reflection coefficient (Γ) is in contact with the circle R3. .
 そして、反射係数(Γ)が円R3に接するようにVC2を制御した後、VC1を次のように制御する。すなわち、反射係数(Γ)の虚数部が正の場合は、VC1が整合値であるXよりも大きい値の場合であるので、VC1を減らすことにより、反射係数(Γ)が0になるよう制御する。逆に、反射係数(Γ)の虚数部が負の場合は、VC1がXよりも小さい場合なので、VC1を増やすことにより、反射係数(Γ)が0になるよう制御する。 Then, after controlling VC2 so that the reflection coefficient (Γ) is in contact with the circle R3, VC1 is controlled as follows. That is, when the imaginary part of the reflection coefficient (Γ) is positive, VC1 is a value larger than the matching value X. Therefore, the control is performed so that the reflection coefficient (Γ) becomes 0 by reducing VC1. To do. On the contrary, when the imaginary part of the reflection coefficient (Γ) is negative, VC1 is smaller than X. Therefore, by increasing VC1, control is performed so that the reflection coefficient (Γ) becomes zero.
 また、プラズマ負荷の入力インピーダンスが、VC1とVC2を制御している途中に変化した場合においても、上述したようにVC2とVC1を制御する。すなわち、反射係数(Γ)が円R3に接するようにVC2を制御した後、VC1を制御する。 Further, even when the input impedance of the plasma load changes during the control of VC1 and VC2, VC2 and VC1 are controlled as described above. That is, VC1 is controlled after controlling VC2 so that the reflection coefficient (Γ) is in contact with the circle R3.
 なお、図5や図6の説明では、図2の整合回路30において、伝送線路35の特性インピーダンスが50Ωで、線路長がλ/4の条件である場合を例として説明したが、これらの条件である場合に限られない。伝送線路35の条件が上記の条件と異なれば、VC2が整合時の容量であるという条件下においてVC1を変えた場合の円の軌跡は、図5や図6で示した円R3の軌跡とは異なるので、前述した式(2)により、伝送線路35の条件に合わせた円の軌跡を設定すればよい。 In the description of FIG. 5 and FIG. 6, the case where the characteristic impedance of the transmission line 35 is 50Ω and the line length is λ / 4 in the matching circuit 30 of FIG. 2 has been described as an example. It is not limited to the case. If the condition of the transmission line 35 is different from the above condition, the locus of the circle when VC1 is changed under the condition that VC2 is the capacity at the time of matching is the locus of the circle R3 shown in FIGS. Since they are different, the locus of the circle may be set according to the condition of the transmission line 35 by the above-described equation (2).
 図7は、実施例に係るインピーダンス整合の処理フローチャートである。この処理は、制御部20において実行される。先ず、初期設定として、図5や図6で示した円の情報(スミスチャート上の位置と大きさ)を、記憶部25に記憶し保存する(図7のステップS1)。上述したように、この円の情報は、伝送線路35によって決まるため、整合回路30に応じた情報を与える必要がある。また、ステップS1では、VC1とVC2の初期値も設定する。 FIG. 7 is a flowchart of impedance matching processing according to the embodiment. This process is executed by the control unit 20. First, as an initial setting, the circle information (position and size on the Smith chart) shown in FIGS. 5 and 6 is stored and stored in the storage unit 25 (step S1 in FIG. 7). As described above, since the information on this circle is determined by the transmission line 35, it is necessary to provide information according to the matching circuit 30. In step S1, initial values of VC1 and VC2 are also set.
 次に、そのときの反射係数(Γ)を、方向性結合器11から得られた進行波(Pf)と反射波(Pr)から演算する(ステップS2)。次に、反射係数(Γ)の絶対値と所定値(L)とを比較する(ステップS3)。反射係数(Γ)の絶対値がL以下である場合は(ステップS3でYes)、ステップS2に戻り、方向性結合器11から進行波(Pf)と反射波(Pr)を取得して、再度、そのときの反射係数(Γ)を演算する。 Next, the reflection coefficient (Γ) at that time is calculated from the traveling wave (Pf) and the reflected wave (Pr) obtained from the directional coupler 11 (step S2). Next, the absolute value of the reflection coefficient (Γ) is compared with a predetermined value (L) (step S3). When the absolute value of the reflection coefficient (Γ) is L or less (Yes in Step S3), the process returns to Step S2, and the traveling wave (Pf) and the reflected wave (Pr) are obtained from the directional coupler 11, and again Then, the reflection coefficient (Γ) at that time is calculated.
 反射係数(Γ)の絶対値がLよりも大きい場合は(ステップS3でNo)、ステップS4に進む。このLは、整合がとれたことを判断するための閾値であり、理想的には0であるが、現実的には、反射係数(Γ)を0にするのは困難であるため、ある閾値(L)を設けて判断する。このLは、高周波電源装置2の耐反射電力や、高周波電源装置2を使うプラズマ処理装置3の要求仕様によって決定される値である。 If the absolute value of the reflection coefficient (Γ) is larger than L (No in step S3), the process proceeds to step S4. This L is a threshold value for determining that matching has been achieved and is ideally 0, but in reality, it is difficult to set the reflection coefficient (Γ) to 0. Judgment is made by providing (L). This L is a value determined by the reflection resistant power of the high frequency power supply device 2 and the required specifications of the plasma processing apparatus 3 using the high frequency power supply device 2.
 ステップS4では、初期設定(ステップS1)で定義した円上に反射係数(Γ)があるか否かを判定するため、記憶部25から円の情報を取得し、反射係数(Γ)と円との距離の最小値(P)を演算する。この値(P)が所定の閾値(M)よりも大きい場合は(ステップS5でYes)、VC2が整合値でないので、VC2を変更するように制御する。具体的には、反射係数(Γ)が円上にないと判定し、ステップS6に進む。このMも、理想的には0であるが、現実には0にするのは困難であるため、所定の値に設定する。 In step S4, in order to determine whether or not there is a reflection coefficient (Γ) on the circle defined in the initial setting (step S1), information on the circle is acquired from the storage unit 25, and the reflection coefficient (Γ), the circle, The minimum value (P) of the distance is calculated. If this value (P) is larger than the predetermined threshold value (M) (Yes in step S5), since VC2 is not a matching value, control is performed to change VC2. Specifically, it is determined that the reflection coefficient (Γ) is not on a circle, and the process proceeds to step S6. This M is also ideally 0, but in reality it is difficult to make it 0, so it is set to a predetermined value.
 Pが所定の閾値(M)以下の場合は(ステップS5でNo)、VC2が整合値であるので、VC2を変更する必要はない。そこで、VC1(つまり第1の可変容量コンデンサ31)の制御動作へ進む。すなわち、反射係数(Γ)が円上にあると判定し、ステップS10に進む。 If P is equal to or less than the predetermined threshold (M) (No in step S5), VC2 is a matching value, so there is no need to change VC2. Therefore, the process proceeds to the control operation of VC1 (that is, the first variable capacitor 31). That is, it is determined that the reflection coefficient (Γ) is on a circle, and the process proceeds to step S10.
 ステップS6では、VC2(つまり第2の可変容量コンデンサ32)を制御する方向を判断するため、反射係数(Γ)が円よりも内側にあるか否かを判定する。反射係数(Γ)が円の内側にある場合は(ステップS6でYes)、VC2がYよりも小さいので、VC2を増やす(ステップS7)。反射係数Γが円の外側にある場合は(ステップS6でNo)、VC2がYよりも大きいので、VC2を減らす(ステップS8)。このとき、減らす量、増やす量は予め設定しておけばよい。 In step S6, in order to determine the direction in which VC2 (that is, the second variable capacitor 32) is controlled, it is determined whether or not the reflection coefficient (Γ) is inside the circle. If the reflection coefficient (Γ) is inside the circle (Yes in step S6), VC2 is smaller than Y, so VC2 is increased (step S7). If the reflection coefficient Γ is outside the circle (No in step S6), VC2 is larger than Y, so VC2 is reduced (step S8). At this time, the amount to be reduced and the amount to be increased may be set in advance.
 こうして、ステップS2からステップS7又はS8までの処理を繰り返すことにより、Pを所定の閾値(M)以下とすることができる、つまり、ほぼ円上に反射係数(Γ)をのせることができる。こうして、ステップS5において、PがM以下であると判定されると、ステップS10に進み、VC1(つまり第1の可変容量コンデンサ31)の制御動作を行う。 Thus, by repeating the processing from step S2 to step S7 or S8, P can be made equal to or less than a predetermined threshold value (M), that is, the reflection coefficient (Γ) can be placed almost on the circle. Thus, when it is determined in step S5 that P is equal to or less than M, the process proceeds to step S10, and the control operation of VC1 (that is, the first variable capacitor 31) is performed.
 ステップS10では、反射係数(Γ)の虚部が負であるか否かを判定、つまり、VC1がXより小さいか否かを判定する。前述したように、反射係数(Γ)の虚部が負の場合は、VC1がXよりも小さく、反射係数(Γ)の虚部が正の場合は、VC1がXよりも大きい。したがって、反射係数(Γ)の虚部が負である場合は(ステップS10でYes)、VC1を増やす。反射係数(Γ)の虚部が正である場合は(ステップS10でNo)、VC1を減らす。こうして、VC1を変更することにより、反射係数(Γ)をゼロに近づける。このときの増減の量も予め設定しておく。 In step S10, it is determined whether or not the imaginary part of the reflection coefficient (Γ) is negative, that is, whether or not VC1 is smaller than X. As described above, VC1 is smaller than X when the imaginary part of the reflection coefficient (Γ) is negative, and VC1 is larger than X when the imaginary part of the reflection coefficient (Γ) is positive. Therefore, when the imaginary part of the reflection coefficient (Γ) is negative (Yes in step S10), VC1 is increased. If the imaginary part of the reflection coefficient (Γ) is positive (No in step S10), VC1 is decreased. Thus, by changing VC1, the reflection coefficient (Γ) is brought close to zero. The amount of increase / decrease at this time is also set in advance.
 以上説明したように、制御部20は、方向性結合器11で検出した進行波と反射波とに基づき、反射係数を算出し、スミスチャート上で整合点を通過する反射係数の軌跡が描く円と、前記算出された反射係数との間の距離が所定値より大きい場合は、第2の可変容量コンデンサ32の容量値を変更し、前記算出される反射係数を変更することにより、前記距離を前記所定値以内とし、前記距離が前記所定値以内になると、第1の可変容量コンデンサ31の容量値を変更し、前記距離を変えることなく、前記算出される反射係数を小さくする。すなわち、制御部20は、方向性結合器11で検出した進行波と反射波とに基づき、反射係数を算出し、前記算出される反射係数が小さくなるように、第1の可変容量コンデンサ31の容量値および前記第2の可変容量コンデンサ32の容量値を変更する。 As described above, the control unit 20 calculates a reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and a circle drawn by the locus of the reflection coefficient passing through the matching point on the Smith chart. And the calculated reflection coefficient is larger than a predetermined value, the capacitance value of the second variable capacitor 32 is changed, and the calculated reflection coefficient is changed to change the distance. When the distance is within the predetermined value and the distance is within the predetermined value, the capacitance value of the first variable capacitor 31 is changed, and the calculated reflection coefficient is reduced without changing the distance. That is, the control unit 20 calculates a reflection coefficient based on the traveling wave and the reflected wave detected by the directional coupler 11, and the first variable capacitance capacitor 31 is configured so that the calculated reflection coefficient becomes small. The capacitance value and the capacitance value of the second variable capacitor 32 are changed.
 次に、可変容量コンデンサの容量値の調整について図8~11を用いて説明する。図8は正しく調整された可変容量コンデンサを搭載した整合器のインピーダンス(VC1を固定)を示す図である。図9は正しく調整された可変容量コンデンサを搭載した整合器のインピーダンス(VC2を固定)を示す図である。図10は正しく調整されていない可変容量コンデンサを搭載した整合器のインピーダンス(VC1を固定)を示す図である。図11は正しく調整されていない可変容量コンデンサを搭載した整合器のインピーダンス(VC2を固定)を示す図である。 Next, adjustment of the capacitance value of the variable capacitor will be described with reference to FIGS. FIG. 8 is a diagram showing the impedance (with VC1 fixed) of a matching unit equipped with a correctly adjusted variable capacitor. FIG. 9 is a diagram showing the impedance (with VC2 fixed) of a matching device equipped with a correctly adjusted variable capacitor. FIG. 10 is a diagram illustrating the impedance (VC1 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted. FIG. 11 is a diagram showing the impedance (VC2 is fixed) of a matching device equipped with a variable capacitor that is not correctly adjusted.
 整合器は内部に搭載する可変容量コンデンサの容量値に関する調整はコンデンサメーカー任せとなっているため、メーカーによる調整ミス等の人的要因により、可変容量コンデンサの容量値を設定しても設定値と全く異なる容量となる個体が稀に存在する。図8および図10に示すように、VC1を固定しVC2を変化させた場合の反射係数(U,V)は全く異なる。また、図9および図11に示すように、VC2を固定しVC1を変化させた場合の反射係数(U,V)は全く異なる。このように、容量値の異なる可変容量コンデンサを搭載した整合器は他の整合器と同じ容量値を設定してもインピーダンスが全く異なるため、プラズマ負荷と接続しても整合動作(軌跡、時間)に顕著な違いが生まれ、プラズマ処理装置のスループットが個々の整合器に依存し、安定しない。 The matching unit is left to the capacitor manufacturer to adjust the capacitance value of the variable capacitor mounted inside, so even if the capacitance value of the variable capacitor is set due to human factors such as adjustment errors by the manufacturer There are rare individuals with completely different capacities. As shown in FIGS. 8 and 10, the reflection coefficients (U, V) when VC1 is fixed and VC2 is changed are completely different. Further, as shown in FIGS. 9 and 11, the reflection coefficients (U, V) when VC2 is fixed and VC1 is changed are completely different. In this way, a matching device equipped with variable capacitance capacitors with different capacitance values has a completely different impedance even if the same capacitance value is set as other matching devices, so matching operation (trajectory, time) even when connected to plasma load The throughput of the plasma processing apparatus depends on individual matching devices and is not stable.
 本実施例では、基準とする整合器の可変容量コンデンサの容量値-インピーダンスのデータを用意し、他の整合器のインピーダンスを、基準とする整合器のデータに近づけることにより、可変容量コンデンサの容量誤差による個々の整合動作の違いを解決し、一律同様の整合動作を行う。以下、詳細に説明する。 In this embodiment, the capacitance value-impedance data of the variable capacitor of the reference matching device is prepared, and the capacitance of the variable capacitance capacitor is obtained by bringing the impedance of the other matching device closer to the data of the reference matching device. Differences in individual matching operations due to errors are solved, and uniform matching operations are performed uniformly. Details will be described below.
 まず、可変容量コンデンサの容量調整について図12~16を用いて説明する。図12は可変容量コンデンサの容量調整および整合動作を示すフローチャートである。図13は整合器(A)(B)のVCステップ値と反射係数(U,V)値の関係(VC2固定)を示す図である。図14は整合器(A)(B)のVCステップ値と反射係数(U,V)値の関係(VC1固定)を示す図である。図15は変換テーブル(VC1)を示す図である。図16は変換テーブル(VC2)を示す図である。 First, the capacity adjustment of the variable capacitor will be described with reference to FIGS. FIG. 12 is a flowchart showing the capacity adjustment and matching operation of the variable capacitor. FIG. 13 is a diagram showing the relationship (VC2 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B). FIG. 14 is a diagram showing the relationship (VC1 fixed) between the VC step value and the reflection coefficient (U, V) value of the matching units (A) and (B). FIG. 15 is a diagram showing a conversion table (VC1). FIG. 16 shows the conversion table (VC2).
 ステップS21:基準となる整合器(以下、整合器(A)という。)の可変容量コンデンサのステップ値(C)とその時のインピーダンス(D)の組となるデータ(C,D)をあらかじめ測定し用意する。例えば、(C0,D0)、(C1,D1)、(C2,D2)、(C3,D3)、・・・、(Cn,Dn)であり、C0(=0)はステップの最小値、Cnはステップの最大値とする。 Step S21: The data (C, D) as a set of the variable capacitor step value (C) of the reference matching unit (hereinafter referred to as matching unit (A)) and the impedance (D) at that time are measured in advance. prepare. For example, (C0, D0), (C1, D1), (C2, D2), (C3, D3), ..., (Cn, Dn), where C0 (= 0) is the minimum value of the step, Cn Is the maximum value of the step.
 具体的は、整合器(A)の第1の可変容量コンデンサ31のステップ値をVC1=0~640の80ステップ刻みで、第2の可変容量コンデンサ32のステップ値をVC2=320で固定して、反射係数(U,V)を測定する。また、VC2=0~640の80ステップ刻みでVC1=320で固定して、反射係数(U,V)を測定する。ここで、C=(VC1,VC2)、D=(U,V)である。 Specifically, the step value of the first variable capacitor 31 of the matching unit (A) is fixed at 80 steps from VC1 = 0 to 640, and the step value of the second variable capacitor 32 is fixed at VC2 = 320. The reflection coefficient (U, V) is measured. The reflection coefficient (U, V) is measured by fixing VC1 = 320 in steps of 80 steps of VC2 = 0 to 640. Here, C = (VC1, VC2) and D = (U, V).
 ステップS22:補正する側の整合器、すなわち正しく調整されていない可変容量コンデンサを搭載している整合器(以下、整合器(B)という。)は、ステップS21で取得した整合器(A)の可変容量コンデンサのインピーダンス(D)となるステップ値(E)を測定し用意する。例えば、(E0,D0)、(E1,D1)、(E2,D2)、(E3,D3)、・・・、(En,Dn)とする。 Step S22: A matching unit on the correction side, that is, a matching unit equipped with a variable capacitor that is not correctly adjusted (hereinafter referred to as a matching unit (B)) is the matching unit (A) obtained in step S21. A step value (E) that becomes the impedance (D) of the variable capacitor is measured and prepared. For example, (E0, D0), (E1, D1), (E2, D2), (E3, D3), ..., (En, Dn).
 具体的には、ステップS21で取得した整合器(A)の(VC1,VC2)=(320,320)に設定した際の(U,V)=(-399.82,321.05)を基準とする。整合器(B)は、整合器(A)の反射係数(U,V)=(-399.82,321.05)になるべく近づくようなVC1,VC2のステップ値をあらかじめ探探しておく。探索の結果、例えば、整合器(B)のステップ値を(VC1,VC2)=(347,363)に設定することにより、(U,V)=(-394.17,327.13)となる。この結果から整合器(B)のVC1ステップ値を347に固定し、VC2のステップ値を可変させることで整合器(A)のVC2が0~640の80ステップ刻みでの(U,V)値になるようなVC2の値を探索する。この結果は、図13に示される。同様に、ステップS21で探索した結果から整合器(B)のVC2ステップ値を363に固定し、VC1のステップ値を可変させることで整合器(A)のVC1が0~640の80ステップ刻みでの(U,V)値になるようなVC1の値を探索する。この結果は、図14に示される。ここで、E=(VC1,VC2)、D=(U,V)である。 Specifically, the reference is (U, V) = (− 399.82, 321.05) when (VC1, VC2) = (320, 320) of the matching unit (A) acquired in step S21. And The matching unit (B) searches for the step values of VC1 and VC2 in advance so that the reflection coefficient (U, V) = (− 399.82, 321.05) of the matching unit (A) is as close as possible. As a result of the search, for example, by setting the step value of the matching unit (B) to (VC1, VC2) = (347,363), (U, V) = (− 394.17,327.13). . From this result, the VC1 step value of the matching unit (B) is fixed at 347, and the VC2 value of the matching unit (A) is changed from 0 to 640 by changing the step value of VC2 (U, V) value. Search for the value of VC2 such that The result is shown in FIG. Similarly, the VC2 step value of the matching unit (B) is fixed at 363 from the search result in step S21, and the VC1 of the matching unit (A) is changed in 80 steps from 0 to 640 by changing the step value of VC1. Search for the value of VC1 that is the (U, V) value of. The result is shown in FIG. Here, E = (VC1, VC2) and D = (U, V).
 図13に示すように、例えば整合器(B)のインピーダンスを整合器(A)のVC1=0ステップのインピーダンスに近づけたい場合はVC1=30ステップと補正することで対応可能となる。 As shown in FIG. 13, for example, when it is desired to bring the impedance of the matching unit (B) closer to the impedance of VC1 = 0 step of the matching unit (A), this can be handled by correcting VC1 = 30 steps.
 ステップS23:PC40等の外部端末より、ステップS22で取得したデータを整合器にダウンロードし、記憶部のEEPROM等の不揮発性記憶媒体等に保存しておく。 Step S23: The data acquired in step S22 is downloaded from an external terminal such as the PC 40 to the matching unit and stored in a nonvolatile storage medium such as an EEPROM in the storage unit.
 具体的には、図13に示す整合器(A)、(B)のVC1のデータの組(0,30)、(80,110)、(160,190)、(240,268)、(320,347)、(400,424)、(480,499)、(560,575)、(640,640)を記憶部25の外部EEPROM253にPC40等の外部端末を用いて保存する。同様に図14に示す整合器(A)、(B)のVC2のデータの組(0,34)、(80,122)、(160,202)、(240,283)、(320,363)、(400,443)、(480,523)、(560,603)、(640,640)を記憶部25の外部EEPROM253にPC40等の外部端末を用いて保存する。PC40と制御部20とはRS232C通信経由で送受信する。 Specifically, the VC1 data sets (0, 30), (80, 110), (160, 190), (240, 268), (320) of the matching units (A) and (B) shown in FIG. , 347), (400, 424), (480, 499), (560, 575), and (640, 640) are stored in the external EEPROM 253 of the storage unit 25 using an external terminal such as the PC 40. Similarly, the VC2 data sets (0, 34), (80, 122), (160, 202), (240, 283), (320, 363) of the matching units (A) and (B) shown in FIG. , (400, 443), (480, 523), (560, 603), and (640, 640) are stored in the external EEPROM 253 of the storage unit 25 using an external terminal such as the PC 40. The PC 40 and the control unit 20 transmit and receive via RS232C communication.
 ステップS24:整合器の電源起動時に、ステップS23で保存されているデータを参照し、記憶部のSRAM等の揮発性記憶媒体上にテーブルを作成する。なお、テーブルは元データの分解能によってはデータ間を補間する。 Step S24: When the matching unit is powered on, a table is created on a volatile storage medium such as SRAM of the storage unit with reference to the data stored in Step S23. The table interpolates between data depending on the resolution of the original data.
 具体的には、制御部20は、整合器(B)の電源起動時に、ステップS24で外部EEPROMに保存しておいたデータを参照し、図13、図14に示すグラフの関係から2点間の補間を繰り返し行うことにより、真のステップ値に対して整合器(B)のVC1、VC2それぞれ0~640ステップに対しての1ステップ毎の補正ステップ値を求める。そして、制御部20は、図15および図16に示すように、0~640をそれぞれメモリ上のインデックス(アドレス)として記憶部25の外部SRAM252に展開する(補正ステップ値を格納する)。 Specifically, the control unit 20 refers to the data stored in the external EEPROM in step S24 when the matching unit (B) is powered on, and determines the two points from the relationship shown in the graphs of FIGS. By repeating this interpolation, the correction step value for each step is obtained for each of the VC1 and VC2 steps 0 to 640 of the matching unit (B) with respect to the true step value. Then, as shown in FIGS. 15 and 16, the control unit 20 develops 0 to 640 in the external SRAM 252 of the storage unit 25 as indexes (addresses) on the memory (stores correction step values).
 ステップS25:整合動作時の演算やアルゴリズムで導き出した整合器の容量をステップS24で作成したテーブルでステップ変換を行い、ステップ値から実際に可変容量コンデンサに設定する容量値を決定し、設定する。 Step S25: The capacity of the matching device derived by the calculation and algorithm at the time of matching operation is step-converted by the table created in step S24, and the capacitance value actually set in the variable capacitor is determined from the step value and set.
 具体的には、整合器(B)の運用時、制御部20は図1の容量演算部22で反射係数とアルゴリズムを用いて整合動作で設定するべきVC1、VC2の容量演算を行い、その結果を容量設定部23により実際に第1の可変容量コンデンサ31および第2の可変容量コンデンサ32に設定して整合動作を行う。このとき、容量設定部23に容量演算部22での演算結果を図15、図16のテーブルのインデックスの0から640まで順に照らし合わせ、演算結果と一致するインデックスに対応する補正容量値を設定する。 Specifically, when the matching unit (B) is operated, the control unit 20 performs the capacity calculation of VC1 and VC2 to be set in the matching operation using the reflection coefficient and the algorithm in the capacity calculation unit 22 of FIG. Is actually set to the first variable capacitor 31 and the second variable capacitor 32 by the capacitance setting unit 23 to perform the matching operation. At this time, the calculation result in the capacity calculation unit 22 is compared with the capacity setting unit 23 in order from 0 to 640 of the indexes in the tables of FIG. 15 and FIG. 16, and the correction capacity value corresponding to the index that matches the calculation result is set. .
 また容量演算部22では必要に応じて第1の可変容量コンデンサ31または第2の可変容量コンデンサ32からステップ値を取得し、設定容量演算する材料として使用する。その場合は取得したステップ値とテーブルの補正容量値を上から順に照らし合わせ、一致した補正容量値のインデックスが補正前のステップ値となる。 Further, the capacity calculation unit 22 acquires a step value from the first variable capacitor 31 or the second variable capacitor 32 as necessary, and uses it as a material for calculating the set capacity. In that case, the acquired step value and the correction capacitance value in the table are compared in order from the top, and the index of the matching correction capacitance value becomes the step value before correction.
 本実施例では、元のアルゴリズムを大幅に変えることなく、メモリ上にテーブルを持つだけで整合動作を補正することが可能となる。 In this embodiment, it is possible to correct the alignment operation by simply having a table on the memory without significantly changing the original algorithm.
 プラズマ処理装置のスループットが個々の整合器に依存しなくなり、安定する。容量精度の劣る安価な可変容量コンデンサを用いても、性能の高い可変容量コンデンサを基準データとして容量補正を行うことができ、原価低減に繋がる。 】 The throughput of the plasma processing equipment does not depend on each matching unit and is stabilized. Even if an inexpensive variable capacitor with inferior capacity accuracy is used, capacity correction can be performed using a high performance variable capacitor as reference data, leading to cost reduction.
 実施例に係る整合器はプラズマ発生用のマイクロ波電源などに好適であり、13.56MHz、915MHz、2.45GHz、5.8GHz等のISMバンドを含む広い周波数で利用できる。 The matching device according to the embodiment is suitable for a microwave power source for generating plasma, and can be used in a wide frequency including ISM bands such as 13.56 MHz, 915 MHz, 2.45 GHz, and 5.8 GHz.
 本明細書には、本発明に関する少なくとも次の構成が含まれる。 This specification includes at least the following configurations related to the present invention.
 第1の構成の整合器は、
 進行波と反射波とを検出する方向性結合器と、
 入力端子と、出力端子と、一端が第1の伝送線路を介して前記入力端子に接続され他端が接地された第1の可変容量コンデンサと、一端が第2の伝送線路を介して前記出力端子に接続され他端が接地された第2の可変容量コンデンサと、一端が前記第1の可変容量コンデンサの前記一端に接続され他端が前記第2の可変容量コンデンサの前記一端に接続されたインダクタンスと、を有する整合回路と、
 前記方向性結合器で検出した進行波と反射波とに基づき、前記第1の可変容量コンデンサの容量値と前記第2の可変容量コンデンサの容量値とを制御する制御部と、
 基準とする整合器の第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記設定値が設定されたときの前記基準とする整合器のインピーダンスとに基づいて求めた前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値を格納する記憶部と、
を備え、
 前記制御部は、
 前記方向性結合器で検出した進行波と反射波とに基づき、反射係数を算出し、
 前記算出される反射係数が小さくなるように、前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値を変更し、
 前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の設定値を演算し、
 前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の前記設定値を前記記憶部の前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値に基づいて補正する。
The matching device of the first configuration is:
A directional coupler for detecting traveling waves and reflected waves;
An input terminal, an output terminal, a first variable capacitor having one end connected to the input terminal via a first transmission line and the other end grounded, and one end connected to the output via a second transmission line A second variable capacitor connected to the terminal and grounded at the other end; one end connected to the one end of the first variable capacitor; the other end connected to the one end of the second variable capacitor. A matching circuit having an inductance; and
A control unit for controlling a capacitance value of the first variable capacitor and a capacitance value of the second variable capacitor based on a traveling wave and a reflected wave detected by the directional coupler;
The value obtained based on the set value of the capacitance value of the third variable capacitor and the fourth variable capacitor of the reference matching unit and the impedance of the reference matching unit when the set value is set A storage unit that stores a correction value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor;
With
The controller is
Based on the traveling wave and the reflected wave detected by the directional coupler, a reflection coefficient is calculated,
Changing the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor so that the calculated reflection coefficient becomes small;
Calculating a set value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor;
The capacitance value of the first variable capacitor and the set value of the capacitance value of the second variable capacitor are set as the capacitance value of the first variable capacitor and the capacitance of the second variable capacitor of the storage unit. Correction is performed based on the value correction setting value.
 第2の構成の整合器は、第1の構成において、
 第1の可変容量コンデンサおよび第2の可変容量コンデンサの補正設定値は、前記基準とする整合器の前記インピーダンスになる該整合器の第1の可変容量コンデンサおよび第2の可変容量コンデンサの設定値を測定して求めたものである。
The matching device of the second configuration is the first configuration,
The correction set values of the first variable capacitor and the second variable capacitor are set values of the first variable capacitor and the second variable capacitor of the matching device that are the impedance of the reference matching device. Is obtained by measuring.
 第3の構成の整合器は、第2の構成において、
 前記記憶部は不揮発性記憶媒体を備え、
 前記第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値とは前記不揮発性記憶媒体に格納されている。
The matching device of the third configuration is the second configuration,
The storage unit includes a nonvolatile storage medium,
The setting values of the capacitance values of the third variable capacitor and the fourth variable capacitance capacitor, the correction values of the capacitance values of the first variable capacitance capacitor, and the capacitance value of the second variable capacitance capacitor are non-volatile. Stored in a sexual storage medium.
 第4の構成の整合器は、第3の構成において、
 前記記憶部は、さらに、揮発性記憶媒体を備え、
 前記制御部は、該整合器の電源起動時に、前記第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値とに基づいて補間データを算出してテーブルを作成し揮発性記憶媒体に格納する。
The matching device of the fourth configuration is the third configuration,
The storage unit further includes a volatile storage medium,
The control unit sets a set value of capacitance values of the third variable capacitor and the fourth variable capacitor, a capacitance value of the first variable capacitor, and the second variable when the matching unit is powered on. Interpolation data is calculated based on the correction setting value of the capacitance value of the capacitor and a table is created and stored in the volatile storage medium.
 第5の構成の整合器は、第4の構成において、
 前記テーブルは、前記第3の可変容量コンデンサの容量値の設定値をインデックスとし、前記第1の可変容量コンデンサの容量値の補正設定値を読み出すように構成される第1テーブルと、前記第4の可変容量コンデンサの容量値の設定値をインデックスとし、前記第2の可変容量コンデンサの容量値の補正設定値を読み出すように構成される第2テーブルと、を有する。
The matching device of the fifth configuration is the fourth configuration,
The table includes a first table configured to read out a correction setting value of the capacitance value of the first variable capacitor using the setting value of the capacitance value of the third variable capacitor as an index, and the fourth table And a second table configured to read out a correction setting value of the capacitance value of the second variable capacitor using the setting value of the capacitance value of the variable capacitor as an index.
 以上、本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は、上記実施例に限定されるものではなく、種々変更可能であることはいうまでもない。 As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and can be variously modified.
 2…高周波電源装置、3…プラズマ処理装置、10…整合器、11…方向性結合器、20…制御部、21…反射係数演算部、22…容量演算部、23…容量設定部、25…記憶部、30…整合回路、30a…入力端子、30b…出力端子、31…第1の可変容量コンデンサ、32…第2の可変容量コンデンサ、31a…制御端子、32a…制御端子、33…インダクタンス、35,36…伝送線路。 DESCRIPTION OF SYMBOLS 2 ... High frequency power supply device, 3 ... Plasma processing apparatus, 10 ... Matching device, 11 ... Directional coupler, 20 ... Control part, 21 ... Reflection coefficient calculating part, 22 ... Capacity calculating part, 23 ... Capacity setting part, 25 ... Storage unit 30 ... matching circuit 30a ... input terminal 30b ... output terminal 31 ... first variable capacitor 32 ... second variable capacitor 31a ... control terminal 32a ... control terminal 33 ... inductance 35, 36 ... transmission lines.

Claims (5)

  1.  進行波と反射波とを検出する方向性結合器と、
     入力端子と、出力端子と、一端が第1の伝送線路を介して前記入力端子に接続され他端が接地された第1の可変容量コンデンサと、一端が第2の伝送線路を介して前記出力端子に接続され他端が接地された第2の可変容量コンデンサと、一端が前記第1の可変容量コンデンサの前記一端に接続され他端が前記第2の可変容量コンデンサの前記一端に接続されたインダクタンスと、を有する整合回路と、
     前記方向性結合器で検出した進行波と反射波とに基づき、前記第1の可変容量コンデンサの容量値と前記第2の可変容量コンデンサの容量値とを制御する制御部と、
     基準とする整合器の第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記設定値が設定されたときの前記基準とする整合器のインピーダンスとに基づいて求めた前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値を格納する記憶部と、
    を備え、
     前記制御部は、
     前記方向性結合器で検出した進行波と反射波とに基づき、反射係数を算出し、
     前記算出される反射係数が小さくなるように、前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値を変更し、
     前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の設定値を演算し、
     前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の前記設定値を前記記憶部の前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値に基づいて補正する
     整合器。
    A directional coupler for detecting traveling waves and reflected waves;
    An input terminal, an output terminal, a first variable capacitor having one end connected to the input terminal via a first transmission line and the other end grounded, and one end connected to the output via a second transmission line A second variable capacitor connected to the terminal and grounded at the other end; one end connected to the one end of the first variable capacitor; the other end connected to the one end of the second variable capacitor. A matching circuit having an inductance; and
    A control unit for controlling a capacitance value of the first variable capacitor and a capacitance value of the second variable capacitor based on a traveling wave and a reflected wave detected by the directional coupler;
    The value obtained based on the set value of the capacitance value of the third variable capacitor and the fourth variable capacitor of the reference matching unit and the impedance of the reference matching unit when the set value is set A storage unit that stores a correction value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor;
    With
    The controller is
    Based on the traveling wave and the reflected wave detected by the directional coupler, a reflection coefficient is calculated,
    Changing the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor so that the calculated reflection coefficient becomes small;
    Calculating a set value of the capacitance value of the first variable capacitor and the capacitance value of the second variable capacitor;
    The capacitance value of the first variable capacitor and the set value of the capacitance value of the second variable capacitor are set as the capacitance value of the first variable capacitor and the capacitance of the second variable capacitor of the storage unit. A matcher that corrects based on the correction setting value.
  2.  請求項1において、
     第1の可変容量コンデンサおよび第2の可変容量コンデンサの補正設定値は、前記基準とする整合器の前記インピーダンスになる該整合器の第1の可変容量コンデンサおよび第2の可変容量コンデンサの設定値を測定して求めたものである
     整合器。
    In claim 1,
    The correction set values of the first variable capacitor and the second variable capacitor are set values of the first variable capacitor and the second variable capacitor of the matching device that are the impedance of the reference matching device. It is obtained by measuring the matcher.
  3.  請求項2において、
     前記記憶部は不揮発性記憶媒体を備え、
     前記第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値とは前記不揮発性記憶媒体に格納されている
     整合器。
    In claim 2,
    The storage unit includes a nonvolatile storage medium,
    The setting values of the capacitance values of the third variable capacitor and the fourth variable capacitance capacitor, the correction values of the capacitance values of the first variable capacitance capacitor, and the capacitance value of the second variable capacitance capacitor are non-volatile. Matching unit stored in a sexual storage medium.
  4.  請求項3において、
     前記記憶部は、さらに、揮発性記憶媒体を備え、
     前記制御部は、該整合器の電源起動時に、前記第3の可変容量コンデンサおよび第4の可変容量コンデンサの容量値の設定値と前記第1の可変容量コンデンサの容量値および前記第2の可変容量コンデンサの容量値の補正設定値とに基づいて補間データを算出してテーブルを作成し揮発性記憶媒体に格納する
     整合器。
    In claim 3,
    The storage unit further includes a volatile storage medium,
    The control unit sets a set value of capacitance values of the third variable capacitor and the fourth variable capacitor, a capacitance value of the first variable capacitor, and the second variable when the matching unit is powered on. A matching unit that calculates interpolation data based on the correction setting value of the capacitance value of the capacitor and creates a table and stores it in a volatile storage medium.
  5.  請求項4において、
     前記テーブルは、前記第3の可変容量コンデンサの容量値の設定値をインデックスとし、前記第1の可変容量コンデンサの容量値の補正設定値を読み出すように構成される第1テーブルと、前記第4の可変容量コンデンサの容量値の設定値をインデックスとし、前記第2の可変容量コンデンサの容量値の補正設定値を読み出すように構成される第2テーブルと、を有する
     整合器。
    In claim 4,
    The table includes a first table configured to read out a correction setting value of the capacitance value of the first variable capacitor using the setting value of the capacitance value of the third variable capacitor as an index, and the fourth table And a second table configured to read out a correction setting value of the capacitance value of the second variable capacitor using the setting value of the capacitance value of the variable capacitor as an index.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096066A (en) * 2002-07-12 2004-03-25 Tokyo Electron Ltd Plasma processor and method of calibrating means for variable impedance
WO2015129678A1 (en) * 2014-02-28 2015-09-03 株式会社日立国際電気 Matcher and matching method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689215A (en) * 1996-05-23 1997-11-18 Lam Research Corporation Method of and apparatus for controlling reactive impedances of a matching network connected between an RF source and an RF plasma processor
JP5799897B2 (en) * 2012-06-12 2015-10-28 株式会社日本自動車部品総合研究所 Method of adjusting applied voltage of communication device and matching circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096066A (en) * 2002-07-12 2004-03-25 Tokyo Electron Ltd Plasma processor and method of calibrating means for variable impedance
WO2015129678A1 (en) * 2014-02-28 2015-09-03 株式会社日立国際電気 Matcher and matching method

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