WO2018049956A1

WO2018049956A1 - Rf signal processing circuit and set-top box

Info

Publication number: WO2018049956A1
Application number: PCT/CN2017/097328
Authority: WO
Inventors: 朱明伟
Original assignee: 深圳创维数字技术有限公司
Priority date: 2016-09-19
Filing date: 2017-08-14
Publication date: 2018-03-22
Also published as: CN206136156U

Abstract

An RF signal processing circuit and a set-top box. The RF signal processing circuit comprises a PIN diode signal attenuation circuit. The PIN diode signal attenuation circuit comprises a PIN diode D1, a resistor R1, and a resistor R2. The anode of the PIN diode D1 is connected to an RF signal input end and a first end of the resistor R1. The cathode of the PIN diode D1 is connected to a first end of the resistor R2 and an RF signal output end. A second end of the resistor R1 is connected to a voltage input end. A second end of the resistor R2 is grounded.

Description

RF signal processing circuit and set top box

Technical field

The present disclosure relates to the field of set top boxes, for example, to an RF signal processing circuit and a set top box.

Background technique

With the widespread adoption of digital television technology, digital TV set-top boxes have become one of the devices for digital TV front-end receiving systems. Set-top boxes include Digital Video Broadcasting-Terrestrial (DVB-T) set-top boxes, Digital Video Broadcasting-Satellitic (DVB-S) set-top boxes and Digital Video Broadcasting-Cable (DVB-C) ) Several types of set-top boxes. In order to effectively receive the digital TV signal, the set-top box front-end signal receiving system will add appropriate radio frequency signal (Radio Frequency Signal, RF signal) processing circuit, for example, when the set-top box needs to be applied to an environment with excessive signal strength, in order to ensure the tuner Tuner Correctly demodulating the TV signal will add a circuit at the front of the tuner to attenuate the RF signal to ensure that the RF signal entering the tuner is in a suitable range.

In order to attenuate the RF signal at the front end of the tuner, a method may be employed: adding an attenuation resistor network at the front end of the tuner to attenuate the RF signal, as shown in FIG. 1, which is an attenuation resistor network in the related art. In the circuit diagram, the RF signal is attenuated by the attenuation resistor network. The resistance parameter value of the attenuation resistor network can be calculated according to the actual required attenuation signal strength value. For example, when the RF signal needs to be attenuated by 10 dB, the resistor R11 and the resistor R12 and The resistance of resistor R13 can be set to 106Ω, 144Ω and 144Ω respectively. This method has the characteristics of low cost. However, the resistance of the attenuation resistor network can not be adjusted after the resistance is determined. The attenuation amplitude cannot be adjusted. When the tuner works, In a weak signal environment, the reception of digital television signals may be degraded due to the presence of attenuating resistor networks.

Summary of the invention

The present disclosure provides an RF signal processing circuit and a set top box. The amplitude of the bias voltage of the PIN diode can be controlled by changing the voltage input at the voltage input terminal, and the attenuation amplitude of the RF signal can be adjusted. The RF signal processing circuit provided by the present disclosure is applied to the set top box. The set top box can receive a wider range of RF signals.

In a first aspect, an RF signal processing circuit is provided, the RF signal processing circuit including a PIN a diode signal attenuation circuit, the PIN diode signal attenuation circuit comprising a PIN diode D1, a resistor R1 and a resistor R2, the anode of the PIN diode D1 being connected to an input end of the RF signal and a first end of the resistor R1, the PIN diode The negative terminal of D1 is connected to the first end of the resistor R2 and the RF signal output end, the second end of the resistor R1 is connected to the voltage input end, and the second end of the resistor R2 is grounded.

Wherein the RF signal processing circuit further includes a tuner and a central processor; wherein the tuner is coupled to the RF signal output, the tuner is configured to process an RF signal passing through the PIN diode signal attenuation circuit and to detect And storing a signal strength value of the RF signal passing through the PIN diode signal attenuation circuit; the central processor is configured to emit a pulse width modulated wave according to the signal strength value, and the central processor outputs the first pulse width modulated wave The terminal is connected to the voltage input, and the second end of the central processor is connected to the tuner.

The second end of the central processor is coupled to the tuner via an IIC bus to read the signal strength value in the tuner.

The first end of the central processor outputting the pulse width modulated wave is further connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded.

The model of the PIN diode D1 is BAP65.

The model of the PIN diode D1 is BAR65.

Wherein, the resistance of the resistor R1 is 1KΩ.

Wherein, the resistance of the resistor R2 is 1KΩ.

The capacitance of the capacitor C1 is 470 nF.

In a second aspect, a set top box is provided, the set top box comprising the RF signal processing circuit described above.

The RF signal processing circuit provided by the present disclosure includes a PIN diode signal attenuation circuit including a PIN diode D1, a resistor R1 and a resistor R2, the anode of the PIN diode D1 is connected to the output end of the RF signal and the The first end of the resistor R1, the negative end of the PIN diode D1 is connected to the first end of the resistor R2 and the RF signal output end, the second end of the resistor R1 is connected to the voltage input end, and the second end of the resistor R2 is grounded. The RF signal processing circuit provided by the present disclosure controls the magnitude of the bias current of the PIN diode by changing the voltage input at the voltage input terminal, thereby changing the on-resistance of the PIN diode to adjust the attenuation of the RF signal passing through the PIN diode signal attenuation circuit. Amplitude.

DRAWINGS

1 is a circuit diagram of a damping resistor network in the related art.

2 is a circuit diagram of an RF signal processing circuit provided by this embodiment.

detailed description

The technical solutions of the present embodiment will be described in detail below with reference to the accompanying drawings.

For the problem that the attenuation amplitude of the RF signal processing circuit in the related art is not adjustable, the embodiment provides an RF signal processing circuit. Referring to FIG. 2, the RF signal processing circuit includes a positive-intrinsic-negative diode (Positive- Intrinsic-Negative Diode (PIN diode) signal attenuating circuit in which a PIN diode is a thin layer of a low-doped intrinsic semiconductor layer (I layer) between a P-type semiconductor material and an N-type semiconductor material. The PIN diode signal attenuating circuit comprises a PIN diode D1, a resistor R1 and a resistor R2. The anode of the PIN diode D1 is connected to the input end of the RF signal and the first end of the resistor R1, and the anode of the PIN diode D1 is connected to the resistor. The first end of the R2 and the RF signal output end, the second end of the resistor R1 is connected to the voltage input end, and the second end of the resistor R2 is grounded.

In this embodiment, the on-resistance of the PIN diode is proportional to the forward bias current, and the magnitude of the on-resistance is changed by controlling the magnitude of the bias current to adjust the attenuation amplitude of the RF signal. As shown in FIG. 2, the PIN diode signal attenuation circuit is composed of a resistor R1, a PIN diode D1, and a resistor R2. When the on-resistance Rs of the PIN diode changes, the RF signal generates a signal attenuation through a series resistor R1, a PIN diode D1 and a resistor R2, wherein the on-resistance Rs and the forward bias current I of the PIN diode D1 are generated. _{F is} inversely proportional, and its relationship formula is as follows:

Where: W is the thickness of the I layer, I _F is the forward bias current, τ is the carrier lifetime, μ _n is the mobility of the electron, and μ _p is the mobility of the hole.

As can be seen from the equation, the on-resistance Rs can be controlled by controlling the forward bias current I _F . The forward bias current I _F can be adjusted by adjusting the voltage applied to the resistor R1, that is, the on-resistance Rs can be adjusted by loading different voltages on the resistor R1, that is, inputting different voltages at the voltage input terminal. The on-resistance Rs can be adjusted. When the voltage input to the voltage input terminal increases, the forward bias current I _F also increases, thereby reducing the on-resistance Rs, and the amplitude of the signal attenuation of the RF signal through the PIN diode is also reduced; when the voltage input is input When the voltage is reduced, the forward bias current I _F is also reduced, so that the on-resistance Rs is increased, and the signal attenuation of the RF signal through the PIN diode is increased.

Optionally, the RF signal processing circuit provided by this embodiment further includes a tuner and a central processing unit (CPU).

A tuner is coupled to the RF signal output, the tuner being configured to process an RF signal passing through the PIN diode signal attenuating circuit and to detect and preserve a signal strength value of an RF signal passing through the PIN diode signal attenuating circuit.

The central processor is configured to emit a pulse width modulated wave according to the signal strength value, and the first end of the central processor outputting the pulse width modulated wave (PWM wave) is connected to the voltage input end, The second end of the central processor is coupled to the tuner.

Optionally, the second end of the central processor is connected to the tuner through an Inter-Integrated Circuit Bus (IIC bus) to read the signal strength value in the tuner.

The RF signal enters the tuner after passing through the PIN diode signal attenuation circuit. The tuner also detects the strength of the RF signal during the signal processing, and saves the signal strength value of the RF signal in the register of the tuner for central processing. The device is connected to the tuner through an IIC bus, and the central processor can read the signal strength value in the tuner through the IIC bus, that is, the signal input intensity value of the RF signal input to the tuner. The central processor reads the signal strength value of the RF signal input to the tuner through the IIC bus, and when the central processor monitors the intensity of the RF signal input to the tuner is too high, and affects the tuner's reception of the input RF signal and When processing performance, the central processor reduces the voltage input to the voltage input by reducing the amplitude of the RF signal input by loading the pulse width modulated wave to the voltage input terminal of the resistor R1, so that the input of the tuner is increased. The RF signal is weakened; when the central processor detects that the input signal strength is relatively weak, the central processor increases the voltage input to the voltage input by adjusting the PWM wave, thereby reducing the attenuation amplitude of the RF signal, so that the input of the tuner is The RF signal is enhanced. Therefore, the attenuation amplitude of the RF signal can be adjusted according to the actual situation of the field environment, and the problem that the signal processing abnormality of the tuner occurs due to the excessive strength of the RF signal when operating in a strong signal environment can be avoided. At the same time, it can also avoid the problem that when the signal is in the weak signal environment, the RF signal input at the front end of the tuner becomes weaker due to the signal attenuation circuit at the front end of the tuner, which causes the receiving performance of the tuner to decrease under the weak signal. The RF signal processing circuit provided in the example is applied to the set top box, which can effectively raise the set top box. The sensitivity of the receiving range enhances the adaptability of the set-top box in different signal environments.

Optionally, in the RF signal processing circuit provided in this embodiment, the voltage input by the voltage input terminal may be adjusted by the central processing unit, and the voltage input by the voltage input terminal may be adjusted by other methods. For example, the independent voltage regulating circuit may be used. The output voltage is applied to the voltage input of the PIN diode signal attenuation circuit.

Optionally, the first end of the central processor outputting the pulse width modulated wave is further connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded. The pulse width modulated wave is smoothed by the capacitor C1 and then loaded onto the resistor R1 to enhance the stability of the circuit.

The model of the PIN diode D1 is BAP65, or the model of the PIN diode D1 is BAR65, and the user can also select other types of PIN diodes having the same function. The resistance of the resistor R1 is 1KΩ, and the resistance of the resistor R is 1KΩ. The user can also select resistor R1 and resistor R2 of other resistance values as needed.

The capacitance of the capacitor C1 is 470 nF. The user can also select the capacitor C1 of other capacitance values as needed, which is not limited herein.

The present disclosure also provides a set top box including the RF signal processing circuit described above.

The RF signal processing circuit provided by the present disclosure controls the magnitude of the forward bias current of the PIN diode by changing the voltage input at the voltage input terminal, thereby changing the on-resistance of the PIN diode to adjust the RF signal passing through the PIN diode signal attenuation circuit. Attenuation amplitude. In this embodiment, the attenuation amplitude of the RF signal can be adjusted according to the actual situation of the field environment, and the problem that the signal processing abnormality of the tuner occurs due to the excessive strength of the RF signal when operating in a strong signal environment can be avoided. At the same time, it can also avoid the problem that when the signal is in the weak signal environment, the RF signal input to the front end of the tuner becomes weaker due to the signal attenuation circuit at the front end of the tuner, which causes the receiving performance of the tuner to decrease under the weak signal. The RF signal processing circuit provided by the embodiment is applied to the set top box, which can effectively improve the sensitivity receiving range of the set top box and enhance the adaptability of the set top box in different signal environments.

Industrial applicability

The RF signal processing circuit provided by the present disclosure controls the magnitude of the forward bias current of the PIN diode by changing the voltage input at the voltage input terminal, thereby changing the on-resistance of the PIN diode to adjust the RF signal passing through the PIN diode signal attenuation circuit. Attenuation amplitude. RF signal provided by the present disclosure The circuit is applied in the set-top box, which can effectively improve the sensitivity receiving range of the set-top box and enhance the adaptability of the set-top box in different signal environments.

Claims

An RF RF signal processing circuit includes a PIN diode signal attenuation circuit, and the PIN diode signal attenuation circuit includes a PIN diode D1, a resistor R1 and a resistor R2, and an anode of the PIN diode D1 is connected to an input end of the RF signal and the resistor The first end of the PIN diode D1 is connected to the first end of the resistor R2 and the RF signal output end, the second end of the resistor R1 is connected to the voltage input end, and the second end of the resistor R2 is grounded.
The circuit of claim 1 further comprising a tuner and a central processing unit; wherein

The tuner is coupled to the RF signal output, the tuner being configured to process an RF signal passing through the PIN diode signal attenuation circuit and to detect and preserve a signal strength value of an RF signal passing through the PIN diode signal attenuation circuit ;

The central processor is configured to emit a pulse width modulated wave according to the signal strength value, the first end of the central processor outputting the pulse width modulated wave is connected to the voltage input end, and the second end of the central processing unit The terminal is connected to the tuner.
The circuit of claim 2 wherein the second end of the central processor is coupled to the tuner via an integrated circuit IIC bus to read the signal strength value in the tuner.
The circuit of claim 2 wherein said first end of said central processor outputting said pulse width modulated wave is further coupled to a first end of capacitor C1, said second end of said capacitor C1 being coupled to ground.
The circuit of claim 2 wherein said PIN diode D1 is of the type BAP65.
The circuit of claim 2 wherein said PIN diode D1 is of the type BAR65.
The circuit according to claim 5 or 6, wherein said resistor R1 has a resistance of 1 k?.
The circuit according to claim 7, wherein said resistor R2 has a resistance of 1 k?.
The circuit of claim 4 wherein said capacitor C1 has a capacitance of 470 nF.
A set top box comprising the RF signal processing circuit of any one of claims 1 to 9.