WO2018039928A1

WO2018039928A1 - Data transmission method and apparatus

Info

Publication number: WO2018039928A1
Application number: PCT/CN2016/097384
Authority: WO
Inventors: 孟凡博; 刘森; 魏星; 姚波
Original assignee: 华为技术有限公司
Priority date: 2016-08-30
Filing date: 2016-08-30
Publication date: 2018-03-08

Abstract

A data transmission method and apparatus, for use in resolving the problems of increased complexity and poor stability of an FPGA prototype verification platform caused when a data flow signal and a control flow signal are respectively transmitted by using designed different physical channels among FPGA chips. The method comprises: determining physical channels used for transmitting data flow signals among multiple chips; and determining that a physical channel having an idle resource exists among the physical channels, and transmitting a control flow signal through the physical channel having the idle resource. A control flow signal is transmitted by means of an idle resource of a physical channel for transmitting a data flow signal, so that a physical channel specially used for transmitting a control flow signal does not need to be established, thereby reducing the complexity of an FPGA prototype verification platform, and improving the stability of the FPGA prototype verification platform.

Description

Data transmission method and device

Technical field

The embodiments of the present invention relate to the field of data transmission technologies, and in particular, to a data transmission method and apparatus.

Background technique

With the development of integrated circuit manufacturing technology, the scale of system chip design is getting larger and larger, and the verification technology of system chip design has always been a problem that plagues the industry. Field-Programmable Gate Array (FPGA) prototyping technology has been developed rapidly because of its proximity to the real application environment, fast speed and relatively low cost. The FPGA prototype verification platform is built according to the FPGA prototype verification technology, and the system chip design is verified by the bearer. The FPGA prototype verification platform includes multiple FPGA chips. However, as the scale of system chip design increases, the number of FPGA chips required increases. When the number of FPGA chips reaches a certain level, the interconnection technology between FPGA chips becomes a major bottleneck of FPGA prototype verification technology.

The signals of the FPGA chip are mainly divided into two types: the data stream signal and the control stream signal. In the prior art, for the data stream signal and the control stream signal, different physical channels need to be designed between the FPGA chips to respectively perform the data stream signal and the control flow. The signal transmission leads to the complexity of the system chip design and reduces the stability of the FPGA prototype verification platform. The control stream signal is characterized by small bit width, low utilization rate of the physical channel between the FPGA chips, and low cost-benefit.

Summary of the invention

The embodiment of the invention provides a data transmission method and device, which solves the problem that different physical channels are designed between the FPGA chips to respectively transmit the data stream signal and the control stream signal, thereby increasing the complexity of the FPGA prototype verification platform, and the FPGA prototype Verify the poor stability of the platform.

In a first aspect, an embodiment of the present invention provides a data transmission method, where the method includes:

Determining a physical channel for transmitting a data stream signal between the plurality of chips; at the physical channel A physical channel in which an idle resource exists is determined, and a control flow signal is transmitted through the determined physical channel in which the idle resource exists.

The embodiment of the invention transmits the control flow signal by using the idle resource of the physical channel of the data stream signal, and does not need to establish a physical channel dedicated to transmitting the control flow signal, thereby reducing the complexity of the FPGA prototype verification platform, thereby improving the FPGA prototype verification. The stability of the platform.

In conjunction with the first aspect, in a first possible implementation, a physical channel for transmitting a data stream signal between any two of the plurality of chips is determined.

With reference to the first aspect, in a second possible implementation manner, a physical channel in which a free resource exists in a physical channel for transmitting a data stream signal between any two chips is determined; and a first chip in the plurality of chips is determined a shortest path formed by the physical channel having the idle resource between the second chip; and a control flow signal between the first chip and the second chip is transmitted through the shortest path.

In the embodiment of the present invention, the control flow signal between the first chip and the second chip is performed by the shortest path formed by the physical channel having the idle resource, so that the speed of transmitting the control flow signal from the first chip to the second chip can be improved.

With reference to the first aspect and the second possible implementation manner of the first aspect, in a third possible implementation, before using the shortest path to transmit the control signal of the first chip and the second chip, The idle resource that needs to be used in the physical channel included in the shortest path may be further marked, where the identifier is used to identify a corresponding idle resource for transmitting control between the first chip and the second chip. a stream signal; when idle resources in the physical channel included in the shortest path also need to send control flow signals from other first chips to other second chips, it is necessary to select idle resources other than the above tags; The resource transmits a control flow signal between the first chip and the second chip.

In the embodiment of the present invention, the idle resources that need to be used in the physical path included in the shortest path when the first chip and the second chip transmit the control flow signal are marked, so that multiple control flows can be avoided in the same physical channel. When the signal is used, the use of idle resources conflicts, which improves the accuracy of control flow signal transmission.

In the embodiment of the present invention, a physical channel for transmitting a data stream signal is determined, and the object is used. Before the control channel transmits the control flow signal, it is determined whether the physical channel is a physical channel supporting selection multiplexing; if the channel is a physical channel supporting selection multiplexing, the physical channel can use idle resource transmission control other than the transmission data stream signal. Stream signal.

In a second aspect, an embodiment of the present invention provides a data transmission apparatus, where the apparatus includes:

a determining module, configured to determine a physical channel for transmitting a data stream signal between the plurality of chips; and a processing module, configured to determine a physical channel that has an idle resource in the physical channel, and transmit the physical channel through the idle resource Control flow signal.

In conjunction with the second aspect, in a first possible implementation, the determining module is configured to determine a physical channel for transmitting a data stream signal between any two of the plurality of chips.

With reference to the second aspect, in a second possible implementation, the processing module is configured to determine a physical channel in which a free resource exists in a physical channel for transmitting a data stream signal between any two chips; The shortest path formed by the physical channel having the idle resource between the first chip and the second chip in the chip; the control flow signal between the first chip and the second chip is transmitted through the shortest path.

With reference to the second aspect, the second possible implementation manner of the second aspect, in a third possible implementation, the processing module uses the shortest path to transmit the first chip and the second chip sending control Before the stream signal, the idle resources that need to be used in the physical path included in the shortest path may be further marked, where the identifier is used to identify the corresponding idle resource for transmitting the first chip and the second chip. Control flow signal between;

And the processing module is configured to transmit, by using the shortest path, a control flow signal between the first chip and the second chip, by using the idle resource that has been marked in the shortest path to transmit the first chip and the Control flow signal between the second chips.

In a third aspect, an embodiment of the present invention provides a data transmission system including a controller and an FPGA prototype verification platform, the controller including a processor and a memory connected to the processor, where:

a memory for storing a preset computer program;

A processor for reading a computer program stored in the memory, performing the following process:

Determining a physical channel between the plurality of chips for transmitting the data stream signal; determining a physical channel in the physical channel where the idle resource exists, and transmitting the control stream signal through the physical channel having the idle resource.

In conjunction with the third aspect, in a first possible implementation, the processor performs the following process:

A physical channel in which a free resource exists in a physical channel for transmitting a data stream signal between any two chips is determined.

In conjunction with the third aspect, in a second possible implementation, the processor performs the following process:

Determining a physical channel in which there is an idle resource in a physical channel for transmitting a data stream signal between any two chips; determining that the first chip and the second chip among the plurality of chips are constituted by the physical channel having the idle resource The shortest path; the control flow signal between the first chip and the second chip is transmitted through the shortest path.

With reference to the third aspect, the second possible implementation manner of the third aspect, in a third possible implementation manner, the processor further performs the following process:

Before transmitting the control stream signal by using the shortest path, the first chip and the second chip may further mark an idle resource that needs to be used in a physical channel included in the shortest path, where the label is used for marking Identifying a corresponding idle resource for transmitting a control flow signal between the first chip and the second chip; and transmitting, by using the shortest path, a control flow signal between the first chip and the second chip, And a method for transmitting a control flow signal between the first chip and the second chip by an idle resource that has been marked in the shortest path.

DRAWINGS

FIG. 1 is a schematic flowchart of a data transmission method according to an embodiment of the present disclosure;

2 is a schematic flowchart of still another data transmission method according to an embodiment of the present invention;

FIG. 3 is a schematic flowchart of still another data transmission method according to an embodiment of the present disclosure;

4 is a schematic flowchart of another data transmission method according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of hardware of a data transmission apparatus according to an embodiment of the present invention.

detailed description

The embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It is to be understood that the embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the system chip design, the system chip design needs to be verified, and the FPGA prototype verification platform is built to verify the system chip design. The system chip is divided, and each divided area corresponds to one FPGA chip in the FPGA prototype verification platform, and data flow transmission and control flow transmission are required between each FPGA chip in the FPGA prototype verification platform.

The following describes the data transmission scheme provided by the embodiment of the present invention by taking the FPGA prototype verification platform as an example. The scheme is also applicable to other types of chip verification platforms or chips.

The embodiment of the invention provides a data transmission method. As shown in FIG. 1 , the method includes the following process:

S11. Determine a physical channel for transmitting a data stream signal in the FPGA prototype verification platform.

Optionally, a physical channel for transmitting a data stream signal between any two adjacent FPGA chips in the FPGA prototype verification platform is determined.

S12. Determine a physical channel that has an idle resource in the physical channel, and transmit a control flow signal by using the physical channel that has an idle resource.

Optionally, a physical channel in which a free resource exists in a physical channel for transmitting a data stream signal between any two adjacent FPGA chips is determined.

Optionally, determining a physical path in which the idle resource exists in the physical channel; determining a shortest path between the first chip and the second chip in the FPGA prototype verification platform, where the physical channel having the idle resource exists; The shortest path transmits a control flow signal between the first chip and the second chip.

In the embodiments of the present invention, it should be understood that in the description of the present application, the terms "first", "second" and the like are used only to distinguish the purpose of description, and are not to be construed as indicating or implying relative importance. It cannot be understood as an indication or an implied order.

For example: Suppose there are 16 FPGA chips in the FPGA prototype verification platform, 16 The interconnection topology between the chips is shown by the solid line in FIG. 2, and the solid line indicates the physical channel between the FPGA chips for transmitting the data stream signal, from the first chip to the second chip. Among the plurality of paths formed by the physical channels having the idle resources, the shortest path formed by the physical channels having the idle resources between the first chip and the second chip is determined;

Specifically, it is assumed that a control flow signal transmission needs to be performed between the FPGA chip 1 and the chip 8, and it is first determined that the path of the control stream signal transmission can be performed by the chip 1 and the chip 8, and it is determined that three paths can be used for control flow signal transmission, such as As indicated by the broken line in FIG. 2, 1>2>6>7>8: respectively indicates that the control flow signal flows from the chip 1 to the chip 2, from the chip 2 to the chip 6, from the chip 6 to the chip 7, and from the chip 7 to the chip. 8; 1>2>6>10>11>12>8, indicating that the control flow signal flows from the chip 1 to the chip 2, from the chip 2 to the chip 6, from the chip 6 to the chip 10, from the chip 10 to the chip 11, and from the chip 11 flows to the chip 12, and flows from the chip 12 to the chip 8; 1>5>9>13>14>15>16>12>8, indicating that the control flow signal flows from the chip 1 to the chip 5, from the chip 5 to the chip 9, and from the chip 9 flows to the chip 14, flows from the chip 14 to the chip 15, flows from the chip 15 to the chip 16, flows from the chip 16 to the chip 12, and flows from the chip 12 to the chip 8. The shortest path is determined to be 1>2>6>7>8.

Optionally, the direction of the path is bidirectional, and the data stream signal may be sent from the chip 1 to the chip 8 or the data stream signal may be sent from the chip 8 to the chip 1 through the path.

Optionally, the idle resources are grouped, and the method is not limited in the embodiment of the present invention.

For example: Suppose that the physical channels of two FPGA chips can transmit 400 signals. Among them, 300 signals are needed to transmit the data flow between two FPGA chips, and the idle resource that can be used to transmit the control flow signal is 100. The signals are divided into 20 groups, and each group can be used to transmit 5 control stream signals.

In the embodiment of the present invention, a physical channel for transmitting a data stream signal in the FPGA prototype verification platform is determined; a physical channel having an idle resource in the physical channel is determined, and a control flow signal is transmitted through the physical channel having the idle resource. . The control stream signal is transmitted through the idle resource of the physical channel transmitting the data stream signal, and the physical channel dedicated to transmitting the control stream signal is not required, which reduces the complexity of the FPGA prototype verification platform, thereby improving the stability of the FPGA prototype verification platform. Qualitative.

In the embodiment of the present invention, before the control flow signal between the first chip and the second chip is transmitted through the shortest path, the method further includes:

And marking the determined idle resource in the physical path included in the shortest path, where the flag is used to identify a corresponding idle resource for transmitting a control flow signal between the first chip and the second chip ;

Transmitting the control flow signal between the first chip and the second chip by using the shortest path, including:

Transmitting a control flow signal between the first chip and the second chip by an idle resource already marked in the shortest path.

For example, assuming that the path 1>2>6>7>8, the physical channel between the chip 1 and the chip 2 has 10 idle resources, and when the control flow signal is sent from the chip 1 to the chip 8, two idles are needed. The resource is selected by selecting two idle resources among the 10 idle resources for marking, and the two idle resources that are marked are used for transmitting control flow signals from the chip 1 to the chip 8. When the physical channel between the chip 1 and the chip 2 also needs to transmit other control flow signals, idle resources are selected among the remaining 8 idle resources of the 10 idle resources for control flow signal transmission.

In the implementation of the present invention, a physical channel for transmitting a data stream signal is determined. Before using the physical channel to transmit a control stream signal, determining whether the physical channel is a physical channel supporting selective multiplexing; if the channel is a support selection complex The physical channel used can transmit the control stream signal using idle resources other than the transport stream signal.

Specifically, determining whether any physical channel in the physical channel supports selective multiplexing includes the following two implementation manners:

Manner 1: If any of the physical channels supports selective multiplexing, the physical channel supporting the selective multiplexing can transmit the control flow signal by using idle resources other than the transmitted data stream signal.

For example, when the physical channel between two FPGA chips supports selective multiplexing, when it is determined that the physical channel has idle resources, the physical channel can perform control flow data transmission.

Manner 2, if any of the physical communication options are not multiplexed, then the data flow signal uses the Any physical channel is transmitted, and the control stream signal cannot be transmitted using any of the physical channels, and the control stream signal selects another reusable physical channel for transmission.

For example, when the physical channel selection between two FPGA chips is not multiplexed, the physical channel is intelligently used to transmit a data stream signal between the two FPGA chips, even if the physical channel has idle resources, the physical channel does not Control stream data transmission can be performed, and other reusable physical channels need to be selected for transmission of control flow signals between the two FPGA chips.

In the embodiment of the present invention, when the control flow signal is sent from the first chip to the second chip, there are two cases:

Case 1: The shortest path when the first chip sends the control flow signal to the second chip is a physical channel, that is, the first chip is directly connected to the second chip through one physical channel. Take the control flow signal from FPGA1 to FPGA2 as an example, as shown in Figure 3.

In this case, the control circuit 301 of the FPGA 1 transmits a control flow signal to the control flow transmission engine 302, and the service circuit 303 transmits the data flow signal to the data flow transmission engine 304, and the control flow transmission engine 302 transmits the received control flow signal. To the multiplexing module 305, the data stream sending engine 304 sends the received data stream signal to the multiplexing module 305, and the multiplexing module multiplexes the control stream signal and the data stream signal, and then sends the signal through the serial virtual input/output interface SVIO306. The SVIO307 in the FPGA2 receives the multiplexed control stream signal and the data stream signal from the SVIO307 in the FPGA2, and sends the signal to the demultiplexing module 308, which demodulates the control stream signal and the data stream signal. After multiplexing, it is sent to the control flow receiving engine 309 and the data stream receiving engine 310, respectively, and the control flow receiving engine 309 sends the received control flow signal to the control circuit 311, and the data stream receiving engine 310 transmits the received data stream signal. To the business circuit 312.

In the second case, the shortest path when the first chip sends the control flow signal to the second chip is at least two physical channels, that is, the first chip is connected to the second chip through at least two physical channels. The FPGA 4 is taken as an example when transmitting a control flow signal from the FPGA 3 to the FPGA 5, as shown in FIG. 4 .

In this case, the control circuit 401 of the FPGA 3 transmits a control flow signal to the control flow transmission engine 402, and the service circuit 403 transmits the data flow signal to the data flow transmission engine 404, and the control flow transmission engine 402 transmits the received control flow signal. To the multiplexing module 405, the data stream sending engine 404 will The received data stream signal is sent to the multiplexing module 405. The multiplexing module 405 multiplexes the control stream signal with the data stream signal, and then sends it to the SVIO407 in the FPGA4 through the serial virtual input/output interface SVIO406, and the SVIO407 in the FPGA4 receives the signal. After the multiplexed control stream signal and the data stream signal are sent to the demultiplexing module 408, the demultiplexing module 408 demultiplexes the control stream signal and the data stream signal, and sends the control stream signal to the control stream forwarding 409. With the data stream receiving engine 410, the control stream forwarding 409 sends the received control stream signal to the multiplexing module 411, and the data stream receiving engine 410 transmits the received data stream signal to the service circuit 412, and the service circuit 413 of the FPGA 4 transmits the data. The stream signal is sent to the data stream sending engine 414 of the FPGA 4, and the data stream sending engine 414 of the FPGA 4 sends the data stream signal to the multiplexing module 411. The multiplexing module 411 multiplexes the control stream signal with the data stream signal and sends it through the SVIO415. After receiving the multiplexed control stream signal and the data stream signal, the SVIO 416 in the FPGA 5 receives the multiplexed control stream signal and the data stream signal, and sends the signal to the demultiplexing module 417. The module 417 demultiplexes the control stream signal and the data stream signal, and sends the control stream signal to the control stream receiving engine 418 and the data stream receiving engine 419, respectively, and the control stream receiving engine 418 sends the received control stream signal to the control circuit 420, the data stream. The receiving engine 419 transmits the received data stream signal to the service circuit 421.

Based on the same inventive concept, an apparatus for data transmission according to an embodiment of the present invention, as shown in FIG. 5, includes:

The determining module 51 is configured to determine a physical channel for transmitting a data stream signal in the FPGA prototype verification platform.

The processing module 52 is configured to determine a physical channel in which the idle resource exists in the physical channel, and transmit the control flow signal by using the physical channel in which the idle resource exists.

In the embodiment of the present invention, a physical channel for transmitting a data stream signal in the FPGA prototype verification platform is determined; a physical channel having an idle resource in the physical channel is determined, and a control flow signal is transmitted through the physical channel having the idle resource. . The control stream signal is transmitted through the idle resource of the physical channel transmitting the data stream signal, and the physical channel dedicated to transmitting the control stream signal is not required, which reduces the complexity of the FPGA prototype verification platform, thereby improving the stability of the FPGA prototype verification platform. .

Optionally, the determining module is configured to:

Determine the physical channel between the adjacent two FPGA chips for transmitting data stream signals in the FPGA prototype verification platform.

Optionally, the processing module is configured to:

Determining a physical channel in which the idle resource exists in the physical channel;

Determining a shortest path formed by the physical channel having the idle resource between the first chip and the second chip among the plurality of FPGA chips;

Transmitting a control flow signal between the first chip and the second chip through the shortest path.

Optionally, the processing module is further configured to:

The structure and processing manner of the apparatus provided by the embodiments of the present invention are described below in conjunction with a preferred hardware structure.

The embodiment of the present invention provides a data transmission system, including a controller 600 and an FPGA prototype verification platform 630. The controller 600 includes a processor 610 and a memory 620 connected to the processor, where:

a memory 620, configured to store a preset computer program;

The processor 610 is configured to read a computer program stored in the memory 620 and perform the following process:

A physical channel for transmitting a data stream signal in the FPGA prototype verification platform 630 is determined; a physical channel having an idle resource in the physical channel is determined, and a control flow signal is transmitted through the physical channel in which the idle resource exists.

Optionally, the processor 610 performs the following processes:

Determining a physical channel for transmitting a data stream signal between any two adjacent FPGA chips in the FPGA prototype verification platform 630;

Optionally, the processor 610 performs the following processes:

Optionally, the processor 610 further performs the following processes:

Before the control flow signal between the first chip and the second chip is transmitted through the shortest path, the idle resources in the physical path included in the determined shortest path are marked, and the identifier is used to identify Corresponding idle resources are used to transmit a control flow signal between the first chip and the second chip;

When the processor 610 transmits the control flow signal between the first chip and the second chip by using the shortest path, the processor 610 is configured to: transmit the first chip by using an idle resource that has been marked in the shortest path Control flow signal between the second chips.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. To implement the functions specified in one or more blocks of a flow or a flow and/or block diagram of a flowchart Device.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

While the preferred embodiment of the invention has been described, it will be understood that Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A data transmission method, characterized in that the method comprises:

Determining a physical channel between the plurality of chips for transmitting a data stream signal;

Determining a physical channel in which there is an idle resource in the physical channel, and transmitting a control flow signal through the physical channel in which the idle resource exists.
The method of claim 1 wherein determining a physical channel for transmitting data stream signals between the plurality of chips comprises:

A physical channel for transmitting a data stream signal between any two of the plurality of chips is determined.
The method according to claim 1, wherein the physical channel in which the idle resource exists in the physical channel is determined, and the control flow signal is transmitted through the physical channel in which the idle resource exists, including:

Determining a physical channel in which the idle resource exists in the physical channel;

Determining a shortest path between the first chip and the second chip among the plurality of chips, the physical channel having the idle resource;

Transmitting a control flow signal between the first chip and the second chip through the shortest path.
The method of claim 3, wherein before the transmitting the control flow signal between the first chip and the second chip by using the shortest path, the method further includes:

And marking the determined idle resource in the physical path included in the shortest path, where the flag is used to identify a corresponding idle resource for transmitting a control flow signal between the first chip and the second chip ;

Transmitting the control flow signal between the first chip and the second chip by using the shortest path, including:

Transmitting a control flow signal between the first chip and the second chip by an idle resource already marked in the shortest path.
A data transmission device, characterized in that the device comprises:

a determining module, configured to determine a physical channel between the plurality of chips for transmitting the data stream signal;

The processing module is configured to determine a physical channel in which the idle resource exists in the physical channel, and transmit the control flow signal by using the physical channel in which the idle resource exists.
The apparatus of claim 5 wherein said determining module is for:

Determining a physical channel for transmitting a data stream signal between any two of the plurality of chips;
The apparatus of claim 5 wherein said processing module is operative to:

Determining a physical channel in which the idle resource exists in the physical channel;

Determining a shortest path between the first chip and the second chip among the plurality of chips, the physical channel having the idle resource;

Transmitting a control flow signal between the first chip and the second chip through the shortest path.
The device according to claim 7, wherein the processing module is further configured to:

Before the control flow signal between the first chip and the second chip is transmitted through the shortest path, the idle resources in the physical path included in the determined shortest path are marked, and the identifier is used to identify Corresponding idle resources are used to transmit a control flow signal between the first chip and the second chip;

When the processing module transmits the control flow signal between the first chip and the second chip by using the shortest path, the processing module is configured to:

Transmitting a control flow signal between the first chip and the second chip by an idle resource already marked in the shortest path.