WO2018037828A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2018037828A1
WO2018037828A1 PCT/JP2017/027286 JP2017027286W WO2018037828A1 WO 2018037828 A1 WO2018037828 A1 WO 2018037828A1 JP 2017027286 W JP2017027286 W JP 2017027286W WO 2018037828 A1 WO2018037828 A1 WO 2018037828A1
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WO
WIPO (PCT)
Prior art keywords
input
output
test control
control signal
negative
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PCT/JP2017/027286
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French (fr)
Japanese (ja)
Inventor
六都也 本島
Original Assignee
株式会社デンソー
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Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to DE112017004223.2T priority Critical patent/DE112017004223T5/en
Publication of WO2018037828A1 publication Critical patent/WO2018037828A1/en
Priority to US16/249,986 priority patent/US10573402B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Definitions

  • the present disclosure relates to a semiconductor device.
  • a terminal that serves both as a high voltage application for memory writing and a test input may be provided as an input terminal.
  • the VPP detection circuit detects that the TEST terminal is at a desired high voltage when writing to the memory.
  • the TEST output is set to the low level (GND) through the transistor. Therefore, test mode switching and memory write voltage application cannot be performed simultaneously.
  • a semiconductor device including a nonvolatile memory element therein and an input terminal that receives a test control signal input and a write voltage input from the outside, the test control signal output terminal; When the test control signal is positive, this is detected and output to the test control signal output terminal, and when the test control signal is negative, the detected signal is inverted and the test control signal is inverted.
  • a negative pulse detection circuit for outputting to the signal output terminal.
  • the positive pulse detection circuit detects this and outputs it to the test control signal output terminal as a test control signal To do. Further, when a negative test control signal and a negative memory write / erase voltage are input, the negative pulse detection circuit detects this and outputs it to the test control signal output terminal as an inverted test control signal.
  • the input terminal can be used for both positive and negative test control signals and positive and negative memory write / erase voltage inputs, and any input can be output as a test control signal to the test control output terminal.
  • FIG. 1 is an electrical configuration diagram showing the first embodiment.
  • FIG. 2 is a diagram illustrating a relationship between an input signal and a threshold value.
  • FIG. 3 is a time chart of an input signal and an output signal, and is an example (part 1) when a test control input and a write voltage are continuously input
  • FIG. 4 is a time chart of the input signal and the output signal, and is an example (part 2) in the case where the test control input and the write voltage are continuously input
  • FIG. 5 is a time chart of the input signal and the output signal, and is an example (part 3) in the case where the test control input and the write voltage are continuously input
  • FIG. 3 is a time chart of an input signal and an output signal, and is an example (part 1) when a test control input and a write voltage are continuously input
  • FIG. 4 is a time chart of the input signal and the output signal, and is an example (part 2) in the case where the test control input and the write voltage are continuously input
  • FIG. 5 is a time chart of the input
  • FIG. 6 is an electrical configuration diagram configured by adding a pull-down resistor and an ESD protection circuit.
  • FIG. 7 is an electrical configuration diagram showing the second embodiment.
  • FIG. 8 is an example of a case where the test control input and the write voltage are continuously input in the time chart of the input signal and the output signal,
  • FIG. 9 is an electrical configuration diagram showing the third embodiment.
  • FIG. 10 is an electrical configuration diagram showing the fourth embodiment.
  • FIG. 11 is an example of a case where the test control input and the write voltage are continuously input in the time chart of the input signal and the output signal,
  • FIG. 12 is an electrical configuration diagram showing the fifth embodiment.
  • the semiconductor device 1 of the present embodiment includes a nonvolatile memory inside, and a write / erase voltage for the nonvolatile memory is input as an input signal Vin to an input terminal A serving as a pad for connection to the outside. In addition, a test signal is input.
  • the input terminal A is connected to the non-illustrated nonvolatile memory circuit side, and is connected to the positive pulse detection circuit 3 and the negative pulse detection circuit 4 via the overvoltage protection circuit 2.
  • the overvoltage protection circuit 2 includes an overvoltage protection circuit 2a connected from the input terminal A to the power supply terminal VD side, and an overvoltage protection circuit 2b connected from the input terminal A to the ground side. Positive and negative overvoltage signals such as noise entering from the external terminal A are released to the power supply side or the ground side via the overvoltage circuits 2a and 2b.
  • the positive pulse detection circuit 3 is a circuit including a buffer circuit 3a and is supplied with power from a power supply terminal VD.
  • Vth + When the input signal Vin from the input terminal A exceeds the positive threshold value Vth +, it is output as a high level signal H, and when it is equal to or lower than the threshold value Vth +, it is output as a low level signal L and input to one input terminal of the OR circuit 5.
  • the negative pulse detection circuit 4 includes an inverter circuit 4a, a MOSFET 4b, and a resistor 4c.
  • the drain of the MOSFET 4b is connected to the power supply terminal VD through the resistor 4c, the source is connected to the input terminal A, and the gate is connected to the ground.
  • the input terminal of the inverter circuit 4 a is connected to the drain of the MOSFET 4 b and the output terminal is connected to the other input terminal of the OR circuit 5.
  • the negative pulse detection circuit 4 outputs a high level signal H when the input signal Vin from the input terminal A falls below the negative threshold value Vth ⁇ , and outputs a low level signal L when the input signal Vin exceeds the threshold value Vth ⁇ .
  • the OR circuit 5 outputs the high level signal H to the output terminal B of the test control signal when the high level signal H is input to at least one of the output of the buffer circuit 3a and the output of the inverter circuit 4a.
  • the negative pulse detection circuit 4 turns on the MOSFET 4b when the level of the input pulse falls below the negative threshold value Vth ⁇ , The input terminal of the inverter circuit 4a becomes low level. As a result, the inverter circuit 4a outputs a high level signal H. That is, the negative pulse is output as a signal inverted to the positive pulse. At this time, the positive pulse detection circuit 3 is in a state of outputting a low level signal L regardless of the change state of the negative pulse because the negative pulse does not exceed the threshold value.
  • OR circuit 5 outputs high level signal H of both positive pulse detection circuit 3 and negative pulse detection circuit 4.
  • a high level signal of a positive pulse in the test mode and a high level signal are output to the output terminal B according to the positive memory write / erase voltage VPP.
  • a high level signal H is output in response to the input of the high level signal to the negative side of the negative pulse and the negative memory write / erase voltage VBB.
  • FIG. 3 shows the output of the output terminal B when three positive pulses are applied to the input terminal A as the input signal Vin and then the positive memory write / erase voltage VPP is continuously applied. Note that several positive pulses or negative pulses input here, for example, three positive pulses are input as measures for preventing malfunction, and do not shift to the test mode.
  • the positive pulse detection circuit 3 In a state where a positive pulse is input, the positive pulse detection circuit 3 outputs a high level signal H to the output terminal B when the positive pulse becomes high level H. When a high level positive memory write / erase voltage VPP is applied following the input state of three positive pulses, the positive pulse detection circuit 3 continues the high level signal H at the output terminal B. Output.
  • FIG. 4 shows the output of the output terminal B when a negative memory write / erase voltage VBB is continuously applied to the input terminal A as an input signal Vin after applying a negative pulse.
  • the negative pulse detection circuit 4 outputs a high level signal H to the output terminal B when the negative pulse becomes a high level H. Further, when a high level negative memory write / erase voltage VBB is applied to the negative side following the input state of the negative pulse, the negative pulse detection circuit 4 continues the high level signal H at the output terminal B. Output.
  • FIG. 5 two positive pulses are applied to the input terminal A as the input signal Vin, one negative pulse is subsequently applied, and then a negative memory write / erase voltage VBB is continuously applied.
  • the output of the output terminal B is shown.
  • a high level signal H is output to the output terminal B when the positive pulse or the negative pulse becomes a high level H by the positive pulse detection circuit 3 and the negative pulse detection circuit 4, respectively.
  • the negative pulse detection circuit 4 continues the high level signal H at the output terminal B. Output.
  • FIG. 6 shows one usage pattern of the semiconductor device 1 configured as described above.
  • the protection circuit 6 is externally attached to the input terminal A of the semiconductor device 1.
  • the protection circuit 6 includes a resistor 6a that pulls down the input terminal A and an ESD (Electro-Static-Discharge) protection circuit 6b.
  • ESD Electro-Static-Discharge
  • both the positive pulse and the negative pulse can be handled while the input terminal A is shared.
  • a memory write / erase voltage VPP or VBB is input, the memory can be written or erased while the level of the output terminal B is held at a high level. become.
  • FIG. 7 and FIG. 8 show the second embodiment, and only the parts different from the first embodiment will be described below.
  • the OR circuit 5 is not provided, the output of the positive pulse detection circuit 3 is output to the output terminal B1, and the output of the negative pulse detection circuit 4 is output to the output terminal B2. It is configured as follows.
  • the test signal and the memory write / erase voltages VPP and VBB are output at the output terminal B1 with respect to the positive pulse and the positive voltage VPP, and the negative pulse The output for the negative voltage VBB is performed at the output terminal B2.
  • the positive pulse and the negative pulse can be distinguished and output by the output terminals B1 and B2, respectively.
  • FIG. 8 shows an example of output.
  • An input signal Vin is input to the input terminal A with a positive pulse, followed by data with a negative pulse, and then a negative memory write / erase voltage.
  • the output of the output terminals B1 and B2 when VBB is input is shown.
  • a positive pulse of an address is input to the input terminal A, this is detected by the positive pulse detection circuit 3, and a signal corresponding to the address is output from the output terminal B1.
  • positive and negative pulses and the memory write / erase voltage VBB can be input from the same input terminal A as the input signal Vin as in the first embodiment.
  • the output of the positive pulse detection circuit 3 is output to the output terminal B1
  • the output of the negative pulse detection circuit 4 is output to the output terminal B2. Negative pulses can be detected and output separately.
  • FIG. 9 shows the third embodiment.
  • the semiconductor device 20 has a configuration in which a protection circuit 12 similar to the protection circuit 6 externally connected in FIG. 6 of the first embodiment is provided inside.
  • the semiconductor device 20 has a protection circuit 21 connected to the input path from the input terminal A to the write / proof voltage of the nonvolatile memory or the input path to the voltage protection circuit 2.
  • the protection circuit 21 includes a pull-down resistor 21a that fixes the potential of the input terminal A and an ESD protection circuit 21b.
  • the protection circuit 21 since the protection circuit 21 is integrally provided in the semiconductor device 20, the potential is fixed to the ground level by the pull-down resistor 21a when there is no input at the input terminal A. Therefore, malfunction can be prevented. Further, the ESD protection circuit 21b can block noise that enters the input terminal A.
  • FIG. 10 and FIG. 11 show the fourth embodiment, and only the parts different from the first embodiment will be described below.
  • the semiconductor device 30 includes an output circuit 31 between the output terminal of the OR circuit 5 and the output terminal B.
  • the output circuit 31 includes a low-pass filter 32 and a buffer circuit 33.
  • the low-pass filter 32 includes a resistor 32a and a capacitor 32b, and is connected from the output terminal of the OR circuit 5 to the input terminal of the buffer circuit 33 via the resistor 32a.
  • the output terminal of the buffer circuit 33 is connected to the output terminal B.
  • FIG. 11 shows an example of the above pattern.
  • the input signal Vin to the input terminal A changes from the positive pulse to the positive memory write / read voltage VPP, and then the negative memory write / read voltage VBB. It is a case where it changes to.
  • the voltage VPP changes from the positive pulse to the positive memory write / read voltage VPP, as described above, this is detected by the positive pulse detection circuit 3, and the high level output signal corresponding to the voltage VPP is output from the output corresponding to the pulse signal. Obtainable.
  • the write / read operation is performed while the output of the output terminal B is held at the enable high level.
  • the erase voltage can be switched from the positive voltage VPP to the negative voltage VBB.
  • FIG. 12 shows the fifth embodiment.
  • a negative pulse detection circuit 41 is provided as a semiconductor device 40 instead of the negative pulse detection circuit 4.
  • a diode 42 is interposed in a path from the input terminal A to the source of the MOSFET 4b.
  • the diode 42 has an anode connected to the source of the MOSFET 4 b and a cathode connected to the input terminal A.
  • the MOSFET 4b when the input signal Vin to the input terminal A is negative, the MOSFET 4b is turned on when the sum of the forward voltage Vf of the diode 42 and the threshold voltage of the MOSFET 4b is reached.
  • the provision of the diode 42 makes it possible to adjust the threshold voltage Vth ⁇ when detecting a negative pulse.
  • the fifth embodiment it is possible to obtain the same effect as that of the first embodiment, and to adjust the threshold voltage for detecting the negative pulse by providing the diode 42 in the negative pulse detection circuit 41. Will be able to.
  • the configuration in which the output terminals shown in the second embodiment are provided as B1 and B2 can also be applied to the third embodiment, the fourth embodiment, and the fifth embodiment.
  • the configuration incorporating the protection circuit 21 shown in the third embodiment can also be applied to the fourth embodiment and the fifth embodiment.
  • the configuration provided with the output circuit 31 shown in the fourth embodiment can also be applied to the fifth embodiment.
  • the diode 42 in the configuration in which the diode 42 is provided in the negative pulse detection circuit 41, two or more diodes can be connected in series for the purpose of adjusting the threshold voltage.

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  • General Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

Provided is a semiconductor device comprising an internal nonvolatile memory element and an input terminal (A) for receiving an external test control signal input and a input signal for writing/erasing voltage, wherein the semiconductor device is provided with: an output terminal (B) for the test control signal; a positive pulse detection circuit (3) for detecting that the test control signal is positive and outputting the test control signal to the test control signal output terminal when the test control signal is positive; and a negative pulse detection circuit (4) for detecting that the test control signal is negative and outputting the inverted test control signal to the test control signal output terminal when the test control signal is negative.

Description

半導体装置Semiconductor device 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１６年８月２５日に出願された日本出願番号２０１６－１６４６５０号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2016-164650 filed on August 25, 2016, the contents of which are incorporated herein by reference.
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　不揮発性メモリ素子あるいは不揮発性メモリを備えた半導体装置では、入力端子として、メモリ書込み用高電圧印加とテスト入力を兼用した端子が設けられることがある。例えば特許文献１のものでは、ＴＥＳＴ端子は、テストモード切り替えを行わないときはローレベルに固定する必要があるため、メモリ書込み時にはＶＰＰ検知回路で所望の高電圧であることを検知し、Ｑ１のトランジスタを介してＴＥＳＴ出力をローレベル（ＧＮＤ）にしている。そのため、テストモード切り替えとメモリ書込み電圧印加を同時に行えない。 In a semiconductor device including a nonvolatile memory element or a nonvolatile memory, a terminal that serves both as a high voltage application for memory writing and a test input may be provided as an input terminal. For example, in Patent Document 1, since the TEST terminal needs to be fixed to a low level when the test mode is not switched, the VPP detection circuit detects that the TEST terminal is at a desired high voltage when writing to the memory. The TEST output is set to the low level (GND) through the transistor. Therefore, test mode switching and memory write voltage application cannot be performed simultaneously.
　またメモリ書込み電圧が負電圧の場合には対応していないので、使い勝手が良くない。 Also, it is not compatible when the memory write voltage is negative, so it is not easy to use.
特許第３５３０４０２号公報Japanese Patent No. 3530402
　本開示は、テストモード切り替えとメモリ書込み電圧印加を同時に行うことができ、しかもメモリ書込み電圧が負電圧の場合にも対応した構成の半導体装置を提供することを目的とする。 It is an object of the present disclosure to provide a semiconductor device having a configuration in which test mode switching and memory write voltage application can be performed at the same time and the memory write voltage is a negative voltage.
　本開示の第一の態様において、内部に不揮発性メモリ素子を備え、外部からテスト制御信号入力および書込み電圧の入力を受ける入力端子を備えた半導体装置であって、テスト制御信号出力端子と、前記テスト制御信号が正の場合にこれを検出して前記テスト制御信号出力端子に出力する正パルス検出回路と、前記テスト制御信号が負の場合にこれを検出して反転させた信号を前記テスト制御信号出力端子に出力する負パルス検出回路とを備えている。 In a first aspect of the present disclosure, a semiconductor device including a nonvolatile memory element therein and an input terminal that receives a test control signal input and a write voltage input from the outside, the test control signal output terminal; When the test control signal is positive, this is detected and output to the test control signal output terminal, and when the test control signal is negative, the detected signal is inverted and the test control signal is inverted. A negative pulse detection circuit for outputting to the signal output terminal.
　上記構成を採用することにより、正パルス検出回路は、正のテスト制御信号および正のメモリ書込み／消去の電圧が入力されると、これを検出してテスト制御信号としてテスト制御信号出力端子に出力する。また、負パルス検出回路は、負のテスト制御信号および負のメモリ書込み／消去の電圧が入力されると、これを検出して反転したテスト制御信号としてテスト制御信号出力端子に出力する。これにより、入力端子を正負のテスト制御信号および正負のメモリ書込み／消去の電圧の入力を兼用したものとし、いずれの入力に対してもテスト制御出力端子にテスト制御信号として出力することができる。 By adopting the above configuration, when a positive test control signal and a positive memory write / erase voltage are input, the positive pulse detection circuit detects this and outputs it to the test control signal output terminal as a test control signal To do. Further, when a negative test control signal and a negative memory write / erase voltage are input, the negative pulse detection circuit detects this and outputs it to the test control signal output terminal as an inverted test control signal. As a result, the input terminal can be used for both positive and negative test control signals and positive and negative memory write / erase voltage inputs, and any input can be output as a test control signal to the test control output terminal.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図１は、第１実施形態を示す電気的構成図であり、 図２は、入力信号と閾値との関係を示す図であり、 図３は、入力信号および出力信号のタイムチャートで、テスト制御入力および書き込み電圧が連続的に入力される場合の例（その１）であり、 図４は、入力信号および出力信号のタイムチャートで、テスト制御入力および書き込み電圧が連続的に入力される場合の例（その２）であり、 図５は、入力信号および出力信号のタイムチャートで、テスト制御入力および書き込み電圧が連続的に入力される場合の例（その３）であり、 図６は、プルダウン抵抗およびＥＳＤ保護回路を付加して構成した電気的構成図であり、 図７は、第２実施形態を示す電気的構成図であり、 図８は、入力信号および出力信号のタイムチャートで、テスト制御入力および書き込み電圧が連続的に入力される場合の例であり、 図９は、第３実施形態を示す電気的構成図であり、 図１０は、第４実施形態を示す電気的構成図であり、 図１１は、入力信号および出力信号のタイムチャートで、テスト制御入力および書き込み電圧が連続的に入力される場合の例であり、 図１２は、第５実施形態を示す電気的構成図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is an electrical configuration diagram showing the first embodiment. FIG. 2 is a diagram illustrating a relationship between an input signal and a threshold value. FIG. 3 is a time chart of an input signal and an output signal, and is an example (part 1) when a test control input and a write voltage are continuously input, FIG. 4 is a time chart of the input signal and the output signal, and is an example (part 2) in the case where the test control input and the write voltage are continuously input, FIG. 5 is a time chart of the input signal and the output signal, and is an example (part 3) in the case where the test control input and the write voltage are continuously input, FIG. 6 is an electrical configuration diagram configured by adding a pull-down resistor and an ESD protection circuit. FIG. 7 is an electrical configuration diagram showing the second embodiment. FIG. 8 is an example of a case where the test control input and the write voltage are continuously input in the time chart of the input signal and the output signal, FIG. 9 is an electrical configuration diagram showing the third embodiment. FIG. 10 is an electrical configuration diagram showing the fourth embodiment. FIG. 11 is an example of a case where the test control input and the write voltage are continuously input in the time chart of the input signal and the output signal, FIG. 12 is an electrical configuration diagram showing the fifth embodiment.
　（第１実施形態）
　以下、第１実施形態について、図１～図６を参照して説明する。本実施形態の半導体装置１は、内部に不揮発メモリを備えており、外部と接続するためのパッドとなる入力端子Ａには、入力信号Ｖｉｎとして、不揮発メモリに対する書込み／消去の電圧が入力されると共に、テスト信号が入力される構成である。 (First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. The semiconductor device 1 of the present embodiment includes a nonvolatile memory inside, and a write / erase voltage for the nonvolatile memory is input as an input signal Vin to an input terminal A serving as a pad for connection to the outside. In addition, a test signal is input.
　入力端子Ａと入力段の構成を示す図１において、入力端子Ａは、図示しない不揮発メモリ回路側に接続されると共に、過電圧保護回路２を介して正パルス検出回路３および負パルス検出回路４に接続される。過電圧保護回路２は、入力端子Ａから電源端子ＶＤ側に接続される過電圧保護回路２ａと、入力端子Ａからグランド側に接続される過電圧保護回路２ｂとを備える。外部端子Ａから侵入するノイズなどの正負の過電圧信号を過電圧回路２ａ、２ｂを介して電源側あるいはグランド側に逃すものである。 In FIG. 1 showing the configuration of the input terminal A and the input stage, the input terminal A is connected to the non-illustrated nonvolatile memory circuit side, and is connected to the positive pulse detection circuit 3 and the negative pulse detection circuit 4 via the overvoltage protection circuit 2. Connected. The overvoltage protection circuit 2 includes an overvoltage protection circuit 2a connected from the input terminal A to the power supply terminal VD side, and an overvoltage protection circuit 2b connected from the input terminal A to the ground side. Positive and negative overvoltage signals such as noise entering from the external terminal A are released to the power supply side or the ground side via the overvoltage circuits 2a and 2b.
　正パルス検出回路３は、バッファ回路３ａを備える回路で、電源端子ＶＤから給電される。入力端子Ａからの入力信号Ｖｉｎが正の閾値Ｖｔｈ＋を超えるときにはハイレベルの信号Ｈとし、閾値Ｖｔｈ＋以下のときにはローレベルの信号Ｌとして出力し、ＯＲ回路５の一方の入力端子に入力する。 The positive pulse detection circuit 3 is a circuit including a buffer circuit 3a and is supplied with power from a power supply terminal VD. When the input signal Vin from the input terminal A exceeds the positive threshold value Vth +, it is output as a high level signal H, and when it is equal to or lower than the threshold value Vth +, it is output as a low level signal L and input to one input terminal of the OR circuit 5.
　負パルス検出回路４は、インバータ回路４ａ、ＭＯＳＦＥＴ４ｂおよび抵抗４ｃを備えている。ＭＯＳＦＥＴ４ｂのドレインは抵抗４ｃを介して電源端子ＶＤに接続され、ソースは入力端子Ａに接続され、ゲートはグランドに接続される。インバータ回路４ａの入力端子はＭＯＳＦＥＴ４ｂのドレインに接続され、出力端子はＯＲ回路５の他方の入力端子に接続される。負パルス検出回路４は、入力端子Ａからの入力信号Ｖｉｎが負の閾値Ｖｔｈ－を下回るときにはハイレベルの信号Ｈとし、閾値Ｖｔｈ－以上のときにはローレベルの信号Ｌとして出力する。 The negative pulse detection circuit 4 includes an inverter circuit 4a, a MOSFET 4b, and a resistor 4c. The drain of the MOSFET 4b is connected to the power supply terminal VD through the resistor 4c, the source is connected to the input terminal A, and the gate is connected to the ground. The input terminal of the inverter circuit 4 a is connected to the drain of the MOSFET 4 b and the output terminal is connected to the other input terminal of the OR circuit 5. The negative pulse detection circuit 4 outputs a high level signal H when the input signal Vin from the input terminal A falls below the negative threshold value Vth−, and outputs a low level signal L when the input signal Vin exceeds the threshold value Vth−.
　ＯＲ回路５は、バッファ回路３ａの出力およびインバータ回路４ａの出力の少なくとも一方にハイレベルの信号Ｈが入力されているとハイレベルの信号Ｈをテスト制御信号の出力端子Ｂに出力する。 The OR circuit 5 outputs the high level signal H to the output terminal B of the test control signal when the high level signal H is input to at least one of the output of the buffer circuit 3a and the output of the inverter circuit 4a.
　次に、上記構成の作用について、図２から図５も参照して説明する。
　まず、基本動作について図２を参照して説明する。入力端子Ａの入力信号Ｖｉｎとして、テストモードの正パルスが入力されると、正パルス検出回路３において、入力されるパルスのレベルが閾値Ｖｔｈ＋を超えるとバッファ回路３ａからハイレベルの信号Ｈが出力される。このとき、負パルス検出回路４においては、正パルスの変化状態にかかわらずＭＯＳＦＥＴ４ｂがオフ状態に保持されるので、インバータ回路４ａの入力端子は抵抗４ｃによりハイレベルの入力状態となり、ローレベルの信号Ｌを出力する状態である。 Next, the operation of the above configuration will be described with reference to FIGS.
First, the basic operation will be described with reference to FIG. When a positive pulse in the test mode is input as the input signal Vin of the input terminal A, the high level signal H is output from the buffer circuit 3a in the positive pulse detection circuit 3 when the level of the input pulse exceeds the threshold value Vth +. Is done. At this time, in the negative pulse detection circuit 4, the MOSFET 4b is held in the off state regardless of the change state of the positive pulse. In this state, L is output.
　次に、入力端子Ａに入力信号Ｖｉｎとして、テストモードの負パルスが入力されると、負パルス検出回路４において、入力されるパルスのレベルが負の閾値Ｖｔｈ－を下回るとＭＯＳＦＥＴ４ｂがオンし、インバータ回路４ａの入力端子はローレベルになる。これにより、インバータ回路４ａは、ハイレベルの信号Ｈを出力するようになる。つまり、負パルスが正パルスに反転された信号として出力されるようになる。このとき、正パルス検出回路３においては、負パルスでは閾値を超えることがないので、負パルスの変化状態にかかわらずローレベルの信号Ｌを出力する状態である。 Next, when a negative pulse in the test mode is input as the input signal Vin to the input terminal A, the negative pulse detection circuit 4 turns on the MOSFET 4b when the level of the input pulse falls below the negative threshold value Vth−, The input terminal of the inverter circuit 4a becomes low level. As a result, the inverter circuit 4a outputs a high level signal H. That is, the negative pulse is output as a signal inverted to the positive pulse. At this time, the positive pulse detection circuit 3 is in a state of outputting a low level signal L regardless of the change state of the negative pulse because the negative pulse does not exceed the threshold value.
　次に、入力端子Ａに、入力信号Ｖｉｎとして、正負のメモリ書込み／消去の電圧ＶＰＰ、ＶＢＢが印加された場合について説明する。まず、正のメモリ書込み／消去の電圧ＶＰＰが入力端子Ａに印加されると、正パルス検出回路３において、ハイレベルの信号Ｈが出力されるようになる。また、負のメモリ書込み／消去の電圧ＶＢＢが入力端子Ａに印加されると、負パルス検出回路４において、ハイレベルの信号Ｈが出力されるようになる。 Next, a case where positive and negative memory write / erase voltages VPP and VBB are applied to the input terminal A as the input signal Vin will be described. First, when a positive memory write / erase voltage VPP is applied to the input terminal A, the positive pulse detection circuit 3 outputs a high level signal H. When a negative memory write / erase voltage VBB is applied to the input terminal A, the negative pulse detection circuit 4 outputs a high level signal H.
　ＯＲ回路５は、正パルス検出回路３および負パルス検出回路４の双方のハイレベルの信号Ｈを出力する。この結果、図２に示すように、出力端子Ｂには、テストモードの正パルスのハイレベルの信号、および正のメモリ書込み／消去の電圧ＶＰＰに応じてハイレベルの信号が出力され、テストモードの負パルスの負側へのハイレベルの信号、および負のメモリ書込み／消去の電圧ＶＢＢの入力に応じてハイレベルの信号Ｈが出力される。 OR circuit 5 outputs high level signal H of both positive pulse detection circuit 3 and negative pulse detection circuit 4. As a result, as shown in FIG. 2, a high level signal of a positive pulse in the test mode and a high level signal are output to the output terminal B according to the positive memory write / erase voltage VPP. A high level signal H is output in response to the input of the high level signal to the negative side of the negative pulse and the negative memory write / erase voltage VBB.
　図３は入力端子Ａに、入力信号Ｖｉｎとして、３個の正パルスを印加した後、正のメモリ書込み／消去の電圧ＶＰＰを連続的に印加した場合の出力端子Ｂの出力を示している。なお、ここで入力する数回例えばここでは３回の正パルスあるいは負パルスは、誤動作防止の処置として入力するもので、テストモードに移行するものではない。 FIG. 3 shows the output of the output terminal B when three positive pulses are applied to the input terminal A as the input signal Vin and then the positive memory write / erase voltage VPP is continuously applied. Note that several positive pulses or negative pulses input here, for example, three positive pulses are input as measures for preventing malfunction, and do not shift to the test mode.
　正パルスが入力される状態では、正パルス検出回路３により、正パルスがハイレベルＨになると出力端子Ｂにハイレベルの信号Ｈを出力する。また、３個の正パルスの入力状態に続けて、ハイレベルの正のメモリ書込み／消去の電圧ＶＰＰが印加されると、正パルス検出回路３は出力端子Ｂのハイレベルの信号Ｈを継続して出力する。 In a state where a positive pulse is input, the positive pulse detection circuit 3 outputs a high level signal H to the output terminal B when the positive pulse becomes high level H. When a high level positive memory write / erase voltage VPP is applied following the input state of three positive pulses, the positive pulse detection circuit 3 continues the high level signal H at the output terminal B. Output.
　図４は、入力端子Ａに、入力信号Ｖｉｎとして、負パルスを印加した後、負のメモリ書込み／消去の電圧ＶＢＢを連続的に印加した場合の出力端子Ｂの出力を示している。負パルスが入力される状態では、負パルス検出回路４により、負パルスがハイレベルＨになると出力端子Ｂにハイレベルの信号Ｈを出力する。また、負パルスの入力状態に続けて、負側にハイレベルの負のメモリ書込み／消去の電圧ＶＢＢが印加されると、負パルス検出回路４は出力端子Ｂのハイレベルの信号Ｈを継続して出力する。 FIG. 4 shows the output of the output terminal B when a negative memory write / erase voltage VBB is continuously applied to the input terminal A as an input signal Vin after applying a negative pulse. In a state in which a negative pulse is input, the negative pulse detection circuit 4 outputs a high level signal H to the output terminal B when the negative pulse becomes a high level H. Further, when a high level negative memory write / erase voltage VBB is applied to the negative side following the input state of the negative pulse, the negative pulse detection circuit 4 continues the high level signal H at the output terminal B. Output.
　図５は、入力端子Ａに、入力信号Ｖｉｎとして、２個の正パルスを印加し、続けて１個の負パルスを印加した後、負のメモリ書込み／消去の電圧ＶＢＢを連続的に印加した場合の出力端子Ｂの出力を示している。正パルスおよび負パルスが入力される状態では、正パルス検出回路３および負パルス検出回路４のそれぞれにより、正パルスあるいは負パルスがハイレベルＨになると出力端子Ｂにハイレベルの信号Ｈを出力する。また、負パルスの入力状態に続けて、負側にハイレベルの負のメモリ書込み／消去の電圧ＶＢＢが印加されると、負パルス検出回路４は出力端子Ｂのハイレベルの信号Ｈを継続して出力する。 In FIG. 5, two positive pulses are applied to the input terminal A as the input signal Vin, one negative pulse is subsequently applied, and then a negative memory write / erase voltage VBB is continuously applied. The output of the output terminal B is shown. In a state where a positive pulse and a negative pulse are input, a high level signal H is output to the output terminal B when the positive pulse or the negative pulse becomes a high level H by the positive pulse detection circuit 3 and the negative pulse detection circuit 4, respectively. . Further, when a high level negative memory write / erase voltage VBB is applied to the negative side following the input state of the negative pulse, the negative pulse detection circuit 4 continues the high level signal H at the output terminal B. Output.
　図６は、上記のように構成した半導体装置１の一使用形態を示している。この構成では、半導体装置１の入力端子Ａに保護回路６を外付けしている。保護回路６は、入力端子Ａをプルダウンする抵抗６ａおよびＥＳＤ（Electro-Static-Discharge）保護回路６ｂを備えている。これにより、入力端子Ａに対する入力がない状態ではプルダウン抵抗６ａにより電位をグランドレベルに固定することができるので、誤動作を防止できる。また、入力端子Ａに侵入する静電気放電などに対してＥＳＤ保護回路６ｂにより保護することができるようになる。 FIG. 6 shows one usage pattern of the semiconductor device 1 configured as described above. In this configuration, the protection circuit 6 is externally attached to the input terminal A of the semiconductor device 1. The protection circuit 6 includes a resistor 6a that pulls down the input terminal A and an ESD (Electro-Static-Discharge) protection circuit 6b. As a result, in a state where there is no input to the input terminal A, the potential can be fixed to the ground level by the pull-down resistor 6a, so that malfunction can be prevented. Further, the ESD protection circuit 6b can protect against electrostatic discharge or the like entering the input terminal A.
　以上説明したように、本実施形態によれば、正パルス検出回路３および負パルス検出回路４を設けることで、入力端子Ａを共用する構成としながら、正パルスおよび負パルスのいずれにも対応することができ、しかも、メモリ書込み／消去の電圧ＶＰＰやＶＢＢが入力されたときに、出力端子Ｂのレベルをハイレベルに保持した状態でメモリへの書込みや消去の処理を実施させることができるようになる。 As described above, according to the present embodiment, by providing the positive pulse detection circuit 3 and the negative pulse detection circuit 4, both the positive pulse and the negative pulse can be handled while the input terminal A is shared. In addition, when a memory write / erase voltage VPP or VBB is input, the memory can be written or erased while the level of the output terminal B is held at a high level. become.
　（第２実施形態）
　図７および図８は第２実施形態を示すもので、以下、第１実施形態と異なる部分について説明する。この実施形態では、図７に示すように、ＯＲ回路５を設けない構成とし、正パルス検出回路３の出力を出力端子Ｂ１に出力し、負パルス検出回路４の出力を出力端子Ｂ２に出力するように構成している。 (Second Embodiment)
FIG. 7 and FIG. 8 show the second embodiment, and only the parts different from the first embodiment will be described below. In this embodiment, as shown in FIG. 7, the OR circuit 5 is not provided, the output of the positive pulse detection circuit 3 is output to the output terminal B1, and the output of the negative pulse detection circuit 4 is output to the output terminal B2. It is configured as follows.
　上記構成を採用することで、入力端子Ａへの入力信号Ｖｉｎにおいて、テスト信号とメモリ書込み／消去の電圧ＶＰＰ、ＶＢＢについて、正パルスおよび正の電圧ＶＰＰに対する出力を出力端子Ｂ１で行い、負パルスおよび負の電圧ＶＢＢに対する出力を出力端子Ｂ２で行うようにしている。これにより、正パルスと負パルスをそれぞれ出力端子Ｂ１、Ｂ２により区別して出力することができる。 By adopting the above configuration, in the input signal Vin to the input terminal A, the test signal and the memory write / erase voltages VPP and VBB are output at the output terminal B1 with respect to the positive pulse and the positive voltage VPP, and the negative pulse The output for the negative voltage VBB is performed at the output terminal B2. Thereby, the positive pulse and the negative pulse can be distinguished and output by the output terminals B1 and B2, respectively.
　図８は出力の一例を示すもので、入力端子Ａに、入力信号Ｖｉｎとして、正パルスでアドレスが入力され、続けて負パルスでデータが入力され、さらにその後、負のメモリ書込み／消去の電圧ＶＢＢが入力された場合の出力端子Ｂ１、Ｂ２の出力を示している。入力端子Ａにアドレスの正パルスが入力されると、正パルス検出回路３によりこれが検出されて出力端子Ｂ１からアドレスに対応する信号を出力する。 FIG. 8 shows an example of output. An input signal Vin is input to the input terminal A with a positive pulse, followed by data with a negative pulse, and then a negative memory write / erase voltage. The output of the output terminals B1 and B2 when VBB is input is shown. When a positive pulse of an address is input to the input terminal A, this is detected by the positive pulse detection circuit 3, and a signal corresponding to the address is output from the output terminal B1.
　入力端子Ａにデータの負パルスが入力されると、負パルス検出回路４によりこれが検出されて出力端子Ｂ２から正負の状態を反転させて正パルスとして出力する。続く負のメモリ書込み／消去の電圧ＶＢＢが入力端子Ａに入力されると、負パルス検出回路４によりこれが検出されて、出力端子Ｂ２から連続的にハイレベルの信号が出力される。 When a negative pulse of data is input to the input terminal A, this is detected by the negative pulse detection circuit 4, and the positive / negative state is inverted from the output terminal B2 and output as a positive pulse. When the subsequent negative memory write / erase voltage VBB is input to the input terminal A, this is detected by the negative pulse detection circuit 4, and a high level signal is continuously output from the output terminal B2.
　このような第２実施形態によっても、第１実施形態と同様に、入力信号Ｖｉｎとして正および負のパルスおよびメモリ書込み／消去の電圧ＶＢＢを同じ入力端子Ａから入力することができる。 Also in the second embodiment, positive and negative pulses and the memory write / erase voltage VBB can be input from the same input terminal A as the input signal Vin as in the first embodiment.
　また、第２実施形態によれば、正パルス検出回路３の出力を出力端子Ｂ１に出力し、負パルス検出回路４の出力を出力端子Ｂ２に出力するように構成したので、テストモードの正および負のパルスを区別して検出し、別々に出力することができる。 Further, according to the second embodiment, the output of the positive pulse detection circuit 3 is output to the output terminal B1, and the output of the negative pulse detection circuit 4 is output to the output terminal B2. Negative pulses can be detected and output separately.
　（第３実施形態）
　図９は第３実施形態を示すもので、以下、第１実施形態と異なる部分について説明する。この実施形態では、半導体装置２０として、第１実施形態の図６にて外部接続した保護回路６と同様の保護回路１２を内部に設ける構成としたものである。 (Third embodiment)
FIG. 9 shows the third embodiment. Hereinafter, parts different from the first embodiment will be described. In this embodiment, the semiconductor device 20 has a configuration in which a protection circuit 12 similar to the protection circuit 6 externally connected in FIG. 6 of the first embodiment is provided inside.
　図９に示す構成では、半導体装置２０は、入力端子Ａから不揮発メモリの書込み／証拠電圧の入力経路とか電圧保護回路２への入力経路に保護回路２１を接続している。保護回路２１は、入力端子Ａの電位を固定するプルダウン抵抗２１ａおよびＥＳＤ保護回路２１ｂを備えている。 In the configuration shown in FIG. 9, the semiconductor device 20 has a protection circuit 21 connected to the input path from the input terminal A to the write / proof voltage of the nonvolatile memory or the input path to the voltage protection circuit 2. The protection circuit 21 includes a pull-down resistor 21a that fixes the potential of the input terminal A and an ESD protection circuit 21b.
　このような第３実施形態によれば、半導体装置２０の内部に保護回路２１を一体に設ける構成としたので、入力端子Ａに入力がない状態ではプルダウン抵抗２１ａにより電位をグランドレベルに固定することができるので、誤動作を防止できる。また、入力端子Ａに侵入するノイズに対してＥＳＤ保護回路２１ｂにより遮断することができるようになる。 According to the third embodiment, since the protection circuit 21 is integrally provided in the semiconductor device 20, the potential is fixed to the ground level by the pull-down resistor 21a when there is no input at the input terminal A. Therefore, malfunction can be prevented. Further, the ESD protection circuit 21b can block noise that enters the input terminal A.
　（第４実施形態）
　図１０および図１１は第４実施形態を示すもので、以下、第１実施形態と異なる部分について説明する。この実施形態では、半導体装置３０は、ＯＲ回路５の出力端子と出力端子Ｂとの間に出力回路３１を備えた構成である。 (Fourth embodiment)
FIG. 10 and FIG. 11 show the fourth embodiment, and only the parts different from the first embodiment will be described below. In this embodiment, the semiconductor device 30 includes an output circuit 31 between the output terminal of the OR circuit 5 and the output terminal B.
　図１０に示すように、出力回路３１は、ローパスフィルタ３２およびバッファ回路３３を備えている。ローパスフィルタ３２は、抵抗３２ａ、コンデンサ３２ｂを備え、ＯＲ回路５の出力端子から抵抗３２ａを介してバッファ回路３３の入力端子に接続されている。バッファ回路３３の出力端子は出力端子Ｂに接続されている。 As shown in FIG. 10, the output circuit 31 includes a low-pass filter 32 and a buffer circuit 33. The low-pass filter 32 includes a resistor 32a and a capacitor 32b, and is connected from the output terminal of the OR circuit 5 to the input terminal of the buffer circuit 33 via the resistor 32a. The output terminal of the buffer circuit 33 is connected to the output terminal B.
　これにより、ＯＲ回路５の出力信号が、ハイレベル状態から瞬時的にローレベルに変化してハイレベルに戻る場合や、その反対の変化をする場合などには、その瞬時的な変化は出力端子Ｂに伝わることなく、変化前の状態が保持されるようになる。 As a result, when the output signal of the OR circuit 5 instantaneously changes from the high level state to the low level and returns to the high level, or vice versa, the instantaneous change is output to the output terminal. The state before the change is maintained without being transmitted to B.
　図１１は、上記のパターンの一例を示すもので、入力端子Ａへの入力信号Ｖｉｎが、正パルスから正のメモリ書込み／読み出しの電圧ＶＰＰにかわり、その後、負のメモリ書込み／読み出しの電圧ＶＢＢに変化した場合である。正パルスから正のメモリ書込み／読み出しの電圧ＶＰＰに変化するときには、前述同様、正パルス検出回路３によりこれが検出されてパルスの信号に対応した出力から電圧ＶＰＰに対応してハイレベルの出力信号を得ることができる。 FIG. 11 shows an example of the above pattern. The input signal Vin to the input terminal A changes from the positive pulse to the positive memory write / read voltage VPP, and then the negative memory write / read voltage VBB. It is a case where it changes to. When the voltage VPP changes from the positive pulse to the positive memory write / read voltage VPP, as described above, this is detected by the positive pulse detection circuit 3, and the high level output signal corresponding to the voltage VPP is output from the output corresponding to the pulse signal. Obtainable.
　この後、図１１中に示す時刻ｔｘで、入力信号Ｖｉｎが、正のメモリ書込み／読み出しの電圧ＶＰＰから負のメモリ書込み／読み出しの電圧ＶＢＢに変化するときには、正パルス検出信号３から出力されているハイレベルの信号が一旦消失し、この後負パルス検出回路４により電圧ＶＢＢが検出されて再びハイレベルの出力信号となる。このとき、電圧が正から負に変化する際に、ＯＲ回路５の出力は瞬時的にローレベルに変化する。しかし、ローパスフィルタ３２ではこの変化が吸収され、若干の変動を伴うハイレベルの信号が保持される。バッファ回路３３は、閾値Ｖｔｈ＋を超える入力レベルであれば、出力端子Ｂへのハイレベルの信号出力状態が保持されるようになる。 After that, when the input signal Vin changes from the positive memory write / read voltage VPP to the negative memory write / read voltage VBB at time tx shown in FIG. The high level signal once disappears, and then the voltage VBB is detected by the negative pulse detection circuit 4 to become a high level output signal again. At this time, when the voltage changes from positive to negative, the output of the OR circuit 5 instantaneously changes to low level. However, this change is absorbed by the low-pass filter 32, and a high-level signal with slight fluctuation is held. If the buffer circuit 33 has an input level exceeding the threshold value Vth +, the high-level signal output state to the output terminal B is held.
　このような第４実施形態によれば、出力段にローパスフィルタ３２およびバッファ回路３３を設けた出力回路３１を設けたので、出力端子Ｂの出力をイネーブルのハイレベルに保持させたまま、書込み／消去電圧を正の電圧ＶＰＰから負の電圧ＶＢＢに切り替えることができるようになる。 According to the fourth embodiment, since the output circuit 31 provided with the low-pass filter 32 and the buffer circuit 33 is provided in the output stage, the write / read operation is performed while the output of the output terminal B is held at the enable high level. The erase voltage can be switched from the positive voltage VPP to the negative voltage VBB.
　（第５実施形態）
　図１２は第５実施形態を示すもので、第１実施形態と異なるところは、半導体装置４０として、負パルス検出回路４に代えて負パルス検出回路４１を設けたところである。図１２に示すように、負パルス検出回路４１は、入力端子ＡからＭＯＳＦＥＴ４ｂのソースに至る経路にダイオード４２が介在されている。ダイオード４２は、アノードがＭＯＳＦＥＴ４ｂのソースに接続され、カソードが入力端子Ａに接続されている。 (Fifth embodiment)
FIG. 12 shows the fifth embodiment. The difference from the first embodiment is that a negative pulse detection circuit 41 is provided as a semiconductor device 40 instead of the negative pulse detection circuit 4. As shown in FIG. 12, in the negative pulse detection circuit 41, a diode 42 is interposed in a path from the input terminal A to the source of the MOSFET 4b. The diode 42 has an anode connected to the source of the MOSFET 4 b and a cathode connected to the input terminal A.
　上記構成によれば、入力端子Ａへの入力信号Ｖｉｎが負のときに、ダイオード４２の順方向電圧ＶｆとＭＯＳＦＥＴ４ｂの閾値電圧との和の電圧に達した時にＭＯＳＦＥＴ４ｂがオンするようになる。換言すれば、ダイオード４２を設けることで負パルスを検出する場合の閾値電圧Ｖｔｈ－を調整することができるようになる。 According to the above configuration, when the input signal Vin to the input terminal A is negative, the MOSFET 4b is turned on when the sum of the forward voltage Vf of the diode 42 and the threshold voltage of the MOSFET 4b is reached. In other words, the provision of the diode 42 makes it possible to adjust the threshold voltage Vth− when detecting a negative pulse.
　このような第５実施形態によれば、第１実施形態と同様の作用効果を得ることができると共に、負パルス検出回路４１にダイオード４２を設けることで負パルスの検出の閾値電圧を調整することができるようになる。 According to the fifth embodiment, it is possible to obtain the same effect as that of the first embodiment, and to adjust the threshold voltage for detecting the negative pulse by providing the diode 42 in the negative pulse detection circuit 41. Will be able to.
　（他の実施形態）
　なお、本発明は、上述した実施形態のみに限定されるものではなく、その要旨を逸脱しない範囲で種々の実施形態に適用可能であり、例えば、以下のように変形または拡張することができる。 (Other embodiments)
In addition, this invention is not limited only to embodiment mentioned above, In the range which does not deviate from the summary, it is applicable to various embodiment, For example, it can deform | transform or expand as follows.
　第２実施形態で示した出力端子をＢ１、Ｂ２として設ける構成は、第３実施形態、第４実施形態、第５実施形態に適用することもできる。
　第３実施形態で示した保護回路２１を内蔵する構成は、第４実施形態、第５実施形態に適用することもできる。 The configuration in which the output terminals shown in the second embodiment are provided as B1 and B2 can also be applied to the third embodiment, the fourth embodiment, and the fifth embodiment.
The configuration incorporating the protection circuit 21 shown in the third embodiment can also be applied to the fourth embodiment and the fifth embodiment.
　第４実施形態で示した出力回路３１を設ける構成は、第５実施形態に適用することもできる。
　第５実施形態で、負パルス検出回路４１にダイオード４２を設ける構成では、閾値電圧を調整する目的で、２個以上のダイオードを直列に接続して設けることができる。 The configuration provided with the output circuit 31 shown in the fourth embodiment can also be applied to the fifth embodiment.
In the fifth embodiment, in the configuration in which the diode 42 is provided in the negative pulse detection circuit 41, two or more diodes can be connected in series for the purpose of adjusting the threshold voltage.
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (5)

  1. 　内部に不揮発性メモリ素子を備え、外部からテスト制御信号入力および書込み／消去の電圧の入力信号を受ける入力端子（Ａ）を備えた半導体装置であって、
    　テスト制御信号の出力端子（Ｂ）と、
    　前記テスト制御信号が正の場合にこれを検出して前記テスト制御信号出力端子に出力する正パルス検出回路（３）と、
    　前記テスト制御信号が負の場合にこれを検出して反転させた信号を前記テスト制御信号出力端子に出力する負パルス検出回路（４）とを備えた半導体装置。     A semiconductor device having a nonvolatile memory element therein and an input terminal (A) for receiving a test control signal input and a write / erase voltage input signal from the outside,
    An output terminal (B) of a test control signal;
    A positive pulse detection circuit (3) for detecting when the test control signal is positive and outputting it to the test control signal output terminal;
    A semiconductor device comprising: a negative pulse detection circuit (4) for outputting, to the test control signal output terminal, a signal that is detected and inverted when the test control signal is negative.
  2. 　前記正パルス検出回路の出力および前記負パルス検出回路の出力を入力して論理和を前記テスト制御信号出力端子（Ｂ）に出力するＯＲ回路（５）を備える請求項１に記載の半導体装置。 The semiconductor device according to claim 1, further comprising an OR circuit (5) that inputs an output of the positive pulse detection circuit and an output of the negative pulse detection circuit and outputs a logical sum to the test control signal output terminal (B).
  3. 　前記ＯＲ回路（５）の出力信号の低周波成分を通過させるローパスフィルタ（３２）と、
    　前記ローパスフィルタの出力信号を所定閾値で判定して出力するバッファ回路（３３）とを設けた請求項２に記載の半導体装置。     A low-pass filter (32) for passing a low-frequency component of the output signal of the OR circuit (5);
    The semiconductor device according to claim 2, further comprising a buffer circuit (33) that determines and outputs an output signal of the low-pass filter with a predetermined threshold.
  4. 　前記テスト制御信号出力端子は、前記正パルス検出回路の信号を出力する正出力端子（Ｂ１）と、前記負パルス検出回路の信号を出力する負出力端子（Ｂ２）とを備える請求項１に記載の半導体装置。 The test control signal output terminal includes a positive output terminal (B1) that outputs a signal of the positive pulse detection circuit and a negative output terminal (B2) that outputs a signal of the negative pulse detection circuit. Semiconductor device.
  5. 　前記入力端子とグランドとの間にプルダウン抵抗（２１ａ）を備える請求項１から４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, further comprising a pull-down resistor (21a) between the input terminal and the ground.
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