WO2018035054A1

WO2018035054A1 - Space transformers for probe cards, and associated systems and methods

Info

Publication number: WO2018035054A1
Application number: PCT/US2017/046791
Authority: WO
Inventors: Alistair Nicholas Sporck
Original assignee: Translarity, Inc.
Priority date: 2016-08-16
Filing date: 2017-08-14
Publication date: 2018-02-22
Also published as: TW201820575A; TWI743171B

Abstract

Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies of a semiconductor wafer includes a composite space transformer for contacting the dies. The composite space transformer has a first space transformer having a first side configured to face the wafer, and a second side facing away from the wafer. The first space transformer has a substrate made of ceramic. The composite space transformer also has a second space transformer having a first side configured to face the wafer, and a second side facing the first side of the first space transformer. The second space transformer has a substrate made of glass. The composite space transformer has a space transformer interconnect to electrically connect the first space transformer and the second space transformer.

Description

SPACE TRANSFORMERS FOR PROBE CARDS, AND ASSOCIATED SYSTEMS

AND METHODS

CROSS-REFERENCE(S) TO RELATED APPLICATION S) This application claims the benefit of U.S. Provisional Application No. 62/375552, filed August 16, 2016, which is hereby incorporated by reference in its entirety.

BACKGROUND

Integrated circuits are used in a wide variety of products. Integrated circuits have continuously decreased in price and increased in performance, becoming ubiquitous in modern electronic devices. These improvements in the performance/cost ratio are based, at least in part, on miniaturization, which enables more semiconductor dies to be produced from a wafer with each new generation of the integrated circuit manufacturing technology. Furthermore, the total number of the signal and power/ground contacts on a semiconductor die generally increases with new, more complex die designs.

Prior to shipping semiconductor dies to customers, the performance of the integrated circuits is tested, either based on a statistical sample or by testing each die. An electrical test of the semiconductor die typically includes powering the die through the power/ground contacts, transmitting signals to the input contacts of the die, and measuring the resulting signals at the output contacts of the die. Therefore, during the electrical test at least some contacts on the die must be contacted to connect the die to sources of power and test signals.

Figure 1A is a cross-sectional view of a probe card 10 for testing semiconductor wafers in accordance with prior art technology. In operation, the probe card 10 contacts a wafer 40 such that an array of probe pins 16 makes electrical contact with the corresponding array of die contacts 48 (e.g., pads or solderballs) on dies 45 (also referred to as "devices under test" or "DUTs") of the wafer. Next, a tester (not shown) sends electrical test sequences (e.g., test vectors) through cables 30 and the probe card 10 to the die contacts 48 of one or more dies 45 of the wafer 40. In response to these test sequences, the integrated circuits of the tested die generate output signals that are routed through the probe card 10 back to the wafer tester for analysis and determination whether a particular die passes the test. Next, the test contactor is stepped onto another die or group of dies 45 that are tested in parallel, and the testing continues till the entire wafer is tested. Once the entire wafer 40 is tested, the dies on the wafer are singulated along wafer streets 46, the dies that failed the test are discarded, and the dies that passed the test are packaged and shipped to the customers.

The probe card 10 provides a path for the signal/power between the tester and the DUTs 45 of the wafer 40. The signals/power pass through a printed circuit board (PCB) 14, through a contact structure 20 that connects the PCB 14 with a space transformer 12, through the routing layers 13 of the space transformer 12, and further to the probe pins 16 of the probe card 10, which, in operation, contact the DUTs. In some applications, electronic components 18 (e.g., capacitors, resistors, active components) are placed on the space transformer 12 and/or on the PCB 18 to improve the flow of signals and power between the tester and the DUTs.

The space transformer 12 is held in place by a holder 26. Screws 28 can adjust a relative position of the space transformer 12 with respect to the PCB 14. For example, the screws 28 can improve parallelism between the space transformer 12 and the PCB 14 to improve the contacts between the probe pins 16 and the DUTs 45.

In many applications, a reliable contact between the probe card 10 and the dies of the wafer 40 requires a relatively high contact force between the wafer and the probe card. In turn, this contact force may bend the probe card 10. Typically, the conventional space transformer 10 is less prone to bending than the PCB 14, because the space transformer is smaller than the PCB, and is also made of a stiffer material (e.g., ceramic) than the material of the PCB 14 (e.g., woven fiberglass cloth with an epoxy resin binder). Therefore, conventional probe cards include stiffeners 22a/22b and screws 24 to limit the bending of the PCB 14.

The ceramic space transformer 10 can have multiple routing layers with a dense routing of conductive traces 13. This relatively dense routing of the relatively thin conductive traces 13 in turn enables a fine pitch of the probe pins 16. Therefore, the conventional ceramic space transformer 12 can support relatively fine pitch/small size of the probe pins 16 for contacting the contacts 48. Therefore, the conventional ceramic space transformer can support newer wafer designs the have an increased number of contacts distributed over a decreasing area of the die, i.e., the dies that have dense arrays of fine pitch contacts 48.

However, the ceramic space transformer 12 can be very expensive (e.g., tens of thousands of dollars or more), and it generally requires long time to manufacture. The cost and lead time of the space transformer 12 scale up with the number of the routing layers 13. Furthermore, as the pitch/size of the contacts 48 decreases on the newer wafer designs, the number of routing layers 13 of the space transformer 12 increases. As a result, the cost/lead time of the conventional space transformer become higher with every new generation of the dies 45.

Accordingly, there remains a need for the space transformers that are cost effective and have short lead time, while being suitable for probing dies with small size/pitch of the contacts. DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of the inventive technology will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

Figure 1 A is cross-sectional view of a probe card for testing semiconductor wafers in accordance with prior art technology;

Figure IB is a partially-schematic, bottom view of the probe card shown in Figure 1A;

Figure 2A is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology;

Figure 2B is a partially-schematic, bottom view of the space transformer shown in Figure 2A;

Figure 3 is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology;

Figure 4 is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology;

Figure 5 is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology;

Figure 6A is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology;

Figure 6B is a partially-schematic, bottom view of the space transformer shown in Figure 6A; Figure 7 is a cross-sectional view of a space transformer in accordance with embodiments of the presently disclosed technology; and

Figure 8 is a flowchart of a method for making space transformers in accordance with embodiments of the presently disclosed technology.

DETAILED DESCRIPTION

Specific details of several embodiments of representative space transformers and associated methods for use and manufacture are described below. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to Figures 2A-8.

Briefly, the inventive technology is directed to testing dies on the semiconductor wafers. The semiconductor wafers can be produced in different diameters, e.g., 150 mm, 200 mm, 300 mm, 450mm, etc. The disclosed methods and systems enable testing the dies (devices under test or DUTs) that have contacts with small sizes and/or pitches. Examples of such contacts on the dies of the wafer are metal pads, solderballs, and/or other suitable contact elements on the DUTs. The wafers can be tested ("probed") by a sort card that includes a space transformer and a printed circuit board (PCB) for transferring signals and power between the tester and the DUTs. The space transformer carries probe pins that contact the corresponding contact elements on the DUTs.

In some embodiments of the inventive technology, a composite space transformer includes a ceramic space transformer and a glass space transformer. Generally, the ceramic space transformers can withstand significant mechanical loads, and can include densely routed metal traces in multiple layers. However, the ceramic space transformers are relatively expensive (e.g., tens of thousands of dollars), and take long time to manufacture. The glass space transformer may be significantly less expensive (sometimes by orders of magnitude), and can be manufactured relatively quickly. When the ceramic space transformer and the glass space transformer are used together in a composite space transformer, the number of routing layers of the ceramic space transformer may be reduced, because a portion of the routing layers can be transferred to the glass space transformer. As a result, the overall cost and lead time of the composite space transformer can be reduced. Furthermore, in at least some embodiments, the composite space transformer can withstand relatively high mechanical loads thanks to the relatively high load-carrying capability of the ceramic space transformer that compensates for the relatively low load-carrying capability of the glass space transformer.

In some embodiments, the ceramic space transformer and the glass space transformer are electrically connected with wirebonds, solderballs, copper pillars and/or other connecting structures. In some embodiments, the composite space transformer may include electrical components, for example, capacitors, resistors, and/or active components. In some embodiments, the ceramic space transformer and the glass space transformer are mechanically connected through a load interface, for example, an adhesive layer that may be peelable, by an underfill polymer material, or by other load bearing interface.

In some embodiments, the composite space transformer may be customizable. For example, if the layout of the contacts on the dies is changed, it may be sufficient to replace the glass space transformer of the composite space transformer, while the more expensive ceramic space transformer is reused. In some embodiments, the glass space transformer may be separated from the ceramic space transformer by removing the electrical contacts and the peelable load interface that connect the glass space transformer and the ceramic space transformer.

Figure 2A is a cross-sectional view of a space transformer 2000 in accordance with embodiments of the presently disclosed technology. In operation, the lower side of the composite space transformer 2000 faces a wafer, and the upper side faces the PCB 14 of the probe card, which is further connected to the tester.

The composite space transformer 2000 includes a ceramic space transformer 220 and a glass space transformer 230. In some embodiments, the ceramic space transformer 220 has a substrate 221 made of ceramic, for example, A1₂0₃ or other ceramic materials. In some embodiments, the ceramic space transformer 220 includes conductive traces 223 (also referred to as "routing traces") for signals/power transferred between contact pads 222 on one side of the ceramic space transformer 220 to contacts pads 224 on the opposite side. The conductive traces 223 can be distributed over multiple routing layers of the ceramic space transformer 220.

The glass space transformer 230 may have a substrate 231 made of glass, for example, S1O2 or other glass materials. In some embodiments, the glass space transformer 230 may carry probe pins 236 for contacting the DUTs on the wafer. In some embodiments, the probe pins 236 may be carried by a separate assembly attached to the glass space transformer 230.

In some embodiments, a load interface 240 attaches the ceramic space transformer 220 with the glass space transformer 230. The load interface 240 may be a polymer, for example an underfill material used in electronics packaging. In some embodiments, the load interface 240 may be peeled off the ceramic/glass space transformer 220/230, and the ceramic space transformer 220 and/or glass space transformer 230 may be reused. For example, the composite space transformer suitable for a new wafer design may be assembled by, for example, replacing the glass space transformer 230 with another glass space transformer, while reusing the ceramic space transformer 220. Additionally, the wirebonds 250 may also be replaced to route signals/power to the die contacts of the new wafer design.

Figure 2B is a partially-schematic, bottom view of the space transformer shown in Figure 2 A. The probe pins 236 of the glass space transformer may be electrically connected through traces 233 and contact pads 234 to the wirebonds 250, and further to the contacts pads 224 of the ceramic space transformer. In some embodiments, the extra contact pads 224 on the ceramic space transformer and extra contact pads 234 on the glass space transformer facilitate reusing the ceramic space transformer in another composite space transformer. Therefore, the composite space transformer 2000 can be modular.

In at least some embodiments, a relatively high mechanical load-bearing capability of the ceramic space transformer 220 compensates for a relatively low mechanical load-bearing capability of the glass space transformer 230. Furthermore, the number of routing layers of the ceramic space transformer 220 may be reduced because of the routing capability of the glass space transformer 230, therefore reducing relatively high cost and long lead time of the ceramic space transformer 230.

Figure 3 is a cross-sectional view of a composite space transformer 3000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the ceramic space transformer 220 includes through-ceramic vias (TCVs) 228 and the glass space transformer 230 may include through-glass vias (TGVs) 238. In some embodiments, the TCVs 228 and the TGVs 238 are made by first making through-holes in the substrates 221/231 with, for example, mechanical drill, laser beams or directional etching, followed by plating the holes with electrical conductors, for example, copper or aluminum. In some embodiments, solderballs 242 electrically connect the TCVs 228 and the TGVs 238. Furthermore, in at least some embodiments, the solderballs 242 provide a load-bearing function to the composite space transformer 3000 instead-of or in addition-to the load interface 240. In some embodiments, the solderballs 232 can be reheated to their melting point to separate the ceramic space transformer 220 from the glass space transformer 230.

Figure 4 is a cross-sectional view of a composite space transformer 4000 in accordance with embodiments of the presently disclosed technology. In some embodiments, copper pillars 244 electrically and mechanically connect the ceramic space transformer 220 with the glass space transformer 230. In some applications, the copper pillars 244 may be smaller than the solderballs 242, therefore enabling smaller pitch/pad size of the contacts of the space transformer.

Figure 5 is a cross-sectional view of a composite space transformer 5000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the wirebonds 250 connect the periphery of the ceramic space transformer 220 with the periphery of the glass space transformer 230, while the solderballs 242 connect the central areas of the glass and ceramic space transformers. In some embodiments, the combination of the wirebonds 250 and the solderballs 242 (and/or the copper pillars 244) improves signal/power routing. For example, in some embodiments, the number of routing layers in the ceramic space transformer 220 may be reduced because both the wirebonds 250 and the solderballs 242 electrically connect the ceramic space transformer 220 with the glass space transformer 230.

Figure 6A is a cross-sectional view of a composite space transformer 6000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the composite space transformer 6000 includes electronic components 260 placed in an opening in the ceramic space transformer 220. The electronic components 260 may be passive components (e.g., capacitors, resistors), active components (e.g., operational amplifiers, processors with memory banks, etc.), or a combination of passive and active components. In some embodiments, the electronic components 260 may be carried by either side of the glass space transformer 230.

Figure 6B is a partially-schematic, bottom view of the space transformer shown in Figure 6A. In the illustrated view, the electronic components 260 are located inside the opening in the ceramic space transformer 220. In at least some embodiments, the load- bearing capacity of the composite space transformer remains sufficient for probing the wafers even when the ceramic space transformer includes an opening.

Figure 7 is a cross-sectional view of a space transformer 7000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the composite space transformer 7000 may include multiple ceramic space transformers, for example, a lower ceramic space transformer 220b and an upper ceramic space transformer 220a. In some embodiments, the electronic components 260 are carried by the glass space transformer 230 in an area corresponding to the opening in the lower ceramic space transformer 220b. The presence of multiple ceramic space transformers may improve the load bearing capability and/or routing capability of the composite space transformer 7000. Furthermore, in some embodiments, the lead time and product cost for two ceramic space transformers, each having a relatively small number of routing layers, may be lower than the lead time and/or cost of a single ceramic space transformer with a relatively large number of routing layers.

Figure 8 is a flowchart of a method 8000 for making space transformers in accordance with embodiments of the presently disclosed technology. In some embodiments, the method 8000 is directed to a modular design of a composite space transformer that, for example, includes replacing the glass space transformer when the wafer design changes. In some embodiments, the method may include additional steps or may be practiced without all steps illustrated in the flow chart.

The method starts in step 810, and continues to step 815. In step 815, the ceramic space transformer and the glass space transformer are selected based on, for example, a layout of the die contacts on the dies of the wafer, a load-bearing capability of the composite space transformer, number of dies to be probed in parallel, etc.

In step 820, a load interface is applied between the ceramic space transformer and the glass space transformer. In some embodiments, the load interface may be an adhesive polymer. In some embodiments, the load interface may be peelable, therefore facilitating replacement of the glass space transformer of the composite space transformer. In some embodiments, the load interface may be an underfill material that is applied as a liquid phase that subsequently solidifies.

In step 825, the ceramic space transformer and the glass space transformer are electrically connected using, for example, the solderballs 242, the copper pillars 244, the wirebonds 250, or their combinations. In step 830, the composite space transformer probes the dies on the wafer. In operation, the composite space transformer can be included in a probe card having the PCB, the stiffener, cables for connecting to the tester, etc.

In step 835, a determination is made whether the probe card needs to test wafers having new layout of the die contacts. If the wafer layout does not change, the probe card may continue to test the wafers in step 830.

If the layout of the die contacts (or other attributes of the die design) have changed, the method proceeds to step 840 where the ceramic space transformer and the glass space transformer are separated. In some embodiments, the load interface 240 may be removed by, for example, peeling it off. Furthermore, the electrical contacts between the ceramic space transformer and the glass space transformer are removed, for example, by cutting the wirebonds 250, or by reheating the solderballs 242 or the copper pillars 244.

In step 845, another glass space transformer is selected for the attachment with the ceramic space transformer. The new composite space transformer may be selected based on, for example, the load-bearing requirements, signal/power routing requirements, layout of the die contacts, etc.

In step 850, the ceramic space transformer and the glass space transformer can be mechanically and electrically connected into an updated composite probe card. In step 855, the wafer is probed by the probe card that includes the updated composite space transformer. The method may end in step 860.

Many embodiments of the technology described above may take the form of computer-executable or controller-executable instructions, including routines executed by a programmable computer or controller. Those skilled in the relevant art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described above. The technology can be embodied in a special-purpose computer, application specific integrated circuit (ASIC), controller or data processor that is specifically programmed, configured or constructed to perform one or more of the computer-executable instructions described above. Of course, any logic or algorithm described herein can be implemented in software or hardware, or a combination of software and hardware.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.

Claims

CLAIMS We claim:

1. An apparatus for testing dies of a semiconductor wafer, comprising:

a composite space transformer for contacting the dies, comprising:

a first space transformer having a first side configured to face the wafer, and a second side facing away from the wafer, wherein the first space transformer has a substrate made of ceramic;

a second space transformer having a first side configured to face the wafer, and a second side facing the first side of the first space transformer, wherein the second space transformer has a substrate made of glass; and

a space transformer interconnect configured to electrically connect the first space transformer and the second space transformer.

2. The apparatus of Claim 1, further comprising a load interface between the first space transformer and the second space transformer.

3. The apparatus of Claim 2, wherein the load interface is an adhesive material having a first adhesive surface attached to the first side of the first space transformer, and a second adhesive surface attached to the second side of the second space transformer.

4. The apparatus of Claim 2, wherein the load interface is an underfill material in contact with the first side of the first space transformer, and the second side of the second space transformer.

5. The apparatus of Claim 2, wherein the load interface is peelable.

6. The apparatus of Claim 1, wherein the space transformer interconnect comprises wirebonds connecting the first side of the first space transformer and the first side of the second space transformer.

7. The apparatus of Claim 6, wherein the space transformer interconnect further comprises solderballs connecting the first side of the first space transformer and the second side of the second space transformer.

8. The apparatus of Claim 1, wherein the space transformer interconnect comprises solderballs or copper pillars connecting the first side of the first space transformer and the second side of the second space transformer.

9. The apparatus of Claim 8, wherein the first space transformer includes at least one through-ceramic via (TCV) electrically connected to at least one solderball or copper pillar at the first side of the first space transformer, and the second space transformer includes at least one through-glass via (TGV) electrically connected to the at least one solderball or copper pillar at the second side of the second space transformer.

10. The apparatus of Claim 1, further comprising a plurality of probe pins at the first side of the second space transformer, wherein the probe pins are configured to contact the dies of the semiconductor wafer.

11. The apparatus of Claim 1, further comprising a plurality of electronic components carried by the second side of the second space transformer in a cavity formed by an opening in the first space transformer.

12. The apparatus of Claim 11, wherein the electronic components are capacitors.

13. The apparatus of Claim 11, wherein the first space transformer is a first lower space transformer, the apparatus further comprising:

a first upper space transformer having a substrate made of ceramic, wherein the first upper space transformer contacts the second side of the first lower space transformer.

14. The apparatus of Claim 1, further comprising a printed circuit board (PCB) electrically connected to the second side of the first space transformer.

15. The apparatus of Claim 1, further comprising the wafer in contact with a plurality of probe pins at the first side of the second space transformer.

16. A method for testing a semiconductor wafer, comprising:

contacting a die on the semiconductor wafer with a plurality of probe pins attached to a composite space transformer, wherein the composite space transformer includes: a first space transformer having a first side configured to face the wafer, and a second side facing away from the wafer, wherein the first space transformer has a substrate made of ceramic;

17. The method of Claim 16, wherein the composite space transformer includes a load interface between the first space transformer and the second space transformer.

18. The method of Claim 17, wherein the load interface is peelable, the method further comprising:

peeling off the load interface between the first space transformer and the second space transformer, wherein the second space transformer is replaceable;

replacing the second space transformer with another second space transformer having a different design than the replaced second space transformer; and

electrically connecting the first space transformer and the another second space transformer.

19. The method of Claim 16, wherein the second space transformer is replaceable, the method further comprising:

20. The method of Claim 19, wherein electrically connecting the first space transformer and the another second space transformer includes connecting a periphery of the first space transformer with a periphery of the another second space transformer with wirebonds.

21. The method of Claim 20, wherein electrically connecting the first space transformer and the another second space transformer includes connecting a first side of the first space transformer with the another second space transformer through solderballs.

22. The method of Claim 19, wherein electrically connecting the first space transformer and the another second space transformer includes connecting a first side of the first space transformer with the another second space transformer through solderballs or copper pillars.

23. The method of Claim 16, wherein the space transformer interconnect comprises wirebonds connecting the first side of the first space transformer and the first side of the second space transformer.

24. The method of Claim 16, wherein the space transformer interconnect comprises solderballs connecting the first side of the first space transformer and the first side of the second space transformer.

25. The method of Claim 16, wherein the space transformer interconnect comprises copper pillars connecting the first side of the first space transformer and the first side of the second space transformer.