WO2018033771A1

WO2018033771A1 - Power converter to produce a reference voltage and method of operating the same

Info

Publication number: WO2018033771A1
Application number: PCT/IB2016/054910
Authority: WO
Inventors: Magnus Karlsson; Oscar Persson
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2016-08-16
Filing date: 2016-08-16
Publication date: 2018-02-22

Abstract

A power converter for producing a reference voltage and method of operating the same. In one embodiment, the power converter is configured to receive an input voltage and includes a power train configured to produce a scaled voltage at a first voltage level being a scaled value of the input voltage. The power converter also includes a buffer amplifier having a slew resistive element coupled at a circuit node to a timing capacitive element and configured to receive the scaled voltage and provide a reference voltage as a function of a second voltage level at the circuit node and the scaled voltage.

Description

POWER CONVERTER TO PRODUCE A REFERENCE VOLTAGE

AND METHOD OF OPERATING THE SAME

TECHNICAL FIELD

The present invention is directed, in general, to the field of power electronics and, more specifically, to a power converter for producing a reference voltage and method of operating the same.

BACKGROUND

A switched-mode power converter is a type of power converter having a diverse range of applications by virtue of its small size, weight and high efficiency. For example, switched-mode power converters are widely used in personal computers and portable electronic devices such as cellphones. A switching device (e.g., a metal-oxide semiconductor field-effect transistor ("MOSFET")) of a power train of the switched-mode power converter is controlled to convert an input voltage to a desired output voltage. A frequency (also referred to as a "switching frequency") and duty cycle of the switching device is adjusted using a feedback signal to convert the input voltage to the desired output voltage. A feedback loop (also referred to as a

"compensation loop" or "feedback circuit") of the power converter that provides the feedback signal may be monitored and adjusted to enhance the regulation of an output characteristic such as the output voltage. The feedback loop typically includes a controller that regulates the switching frequency and/or the duty cycle to regulate the output voltage.

Increasing dynamic requirements, such as a monotonic increase in the output voltage at start-up, recovery after a short circuit, and load transient performance have led to relocation of the controller, or portions thereof, from a primary side to a secondary side of a transformer of the power converter. When the controller is on the secondary side of an isolation barrier of the transformer, the controller (often powered from the primary side) monitors the input voltage to the power converter on the secondary side to control the output voltage of the power converter. That being said, a circuit configured to generate a reference voltage related to the input voltage for control of the power converter would be beneficial.

SUMMARY

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention for a power converter for producing a reference voltage and method of operating the same. In one embodiment, the power converter is configured to receive an input voltage and includes a power train configured to produce a scaled voltage at a first voltage level being a scaled value of the input voltage. The power converter also includes a buffer amplifier having a slew resistive element coupled at a circuit node to a timing capacitive element and configured to receive the scaled voltage and provide a reference voltage as a function of a second voltage level at the circuit node and the scaled voltage.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGURE 1 and 2 illustrate block diagrams of embodiments of power converters;

FIGURES 3 to 12 illustrate diagrams of embodiments of auxiliary power converters;

FIGURE 13 illustrates a block diagram of an embodiment of a communication device; and

FIGURE 14 illustrates a flow diagram of an embodiment of a method of operating a power converter.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated, and may not be redescribed in the interest of brevity after the first instance. The FIGUREs are drawn to illustrate the relevant aspects of exemplary embodiments.

DETAILED DESCRIPTION

The making and using of the present exemplary embodiments are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the systems, subsystems, and modules associated with producing a reference voltage for a power converter.

A process will be described herein with respect to exemplary embodiments in a specific context, namely, a system and method of providing a trimmable, safety-isolated reference voltage on the secondary side of a power converter that is a scaled value of the input voltage. While the principles will be described in the environment of a power converter, any environment such as a motor controller or audio amplifier that may benefit from such a system and method that enables these functionalities is well within the broad scope of the present disclosure.

The controller of an isolated power converter may be powered via an auxiliary (or "housekeeping") power converter or converter stage. A design consideration for the auxiliary converter stage is to supply bias voltages on primary and secondary sides of a transformer to power, for example, operational amplifiers and drivers for power switches therein. A further design consideration is providing information about an input voltage of the power converter to the secondary side with a level of safety isolation. The information can be used for voltage feedforward control in a secondary-side controlled power converter, or for setting a reference voltage in a regulated ratio or hybrid regulated ratio ("HRR") controlled power converter.

Fly-back circuit solutions exist, but the high voltage safety isolation requirement of "basic isolation" and 2250 volt isolation causes challenges when producing the fly-back transformer, as described by Mikael Appelberg in U.S. Patent Application Publication No. 2011/0090724, entitled "Power Converter," published April 21, 2011, which is incorporated herein by reference. To supply regulated housekeeping power on the primary side of the power converter, the transformer may incorporate three windings. An auxiliary winding of the main transformer may be used to facilitate the housekeeping power for the power converter. The use of an auxiliary winding, however, requires that main power switches (also referred to as

"switching elements") in the power converter are actively switched. Such a configuration can cause difficulties, particularly, during pre-bias start-up and during fault handling when the output of the power converter is turned off. Nonetheless, the housekeeping bias power on the secondary side of the power converter is generally necessary.

A housekeeping bias power supply is introduced herein that can supply bias power to the primary and secondary sides of the power converter with a level of isolation and that can provide information about an input voltage of the power converter to the secondary side thereof. Again, this information can be used for voltage feed-forward control in a secondary-side controlled power converter, or for setting a reference voltage in a regulated ratio or hybrid regulated ratio ("HRR") controlled power converter.

In an HRR controlled power converter, in a normal mode of operation when the input voltage to the power converter is above a threshold level, the output voltage is fully regulated to a voltage level. At input voltages less than the threshold level, the power converter operates in a regulated ratio mode wherein a reference voltage that controls the output voltage is set proportional to the input voltage that may include a voltage offset. The result is a fully regulated power converter with a high level of power conversion efficiency with a need for a relatively small output filter inductor. Such designs are advantageous, as an example, for power systems that employ an intermediate bus voltage architecture. The housekeeping bias power supply introduced herein is buffered to yield enhanced accuracy in the regulated ratio mode as well as better control of time constants in

charging/discharging a reference voltage therein. The buffering is achieved by employing an operational amplifier with a high input impedance to isolate a following circuit portion from an input voltage signal. It also allows a standard output voltage trim process, sometimes referred to as "lucent output voltage trim" to be applied. The circuit may also include overvoltage protection to protect against trimming the output voltage of the power converter too high.

Accurate sensing of the input voltage on the secondary side of the power converter and the capability of controlling slew rates (up and down) of a reference voltage allows for improved control of the power converter.

Turning now to FIGURE 1, illustrated is a block diagram of an embodiment of a power converter 100. The power converter 100 includes a main converter stage 1 10, an auxiliary converter stage 150 and a controller 120 including a processor ("PR") 130 and memory ("M") 140. The controller 120 provides control signals Cs to the main converter stage 110 to control a duty cycle D (and a complimentary duty cycle 1-D) and/or a switching frequency of one or more power switches or switching elements (e.g., field-effect transistors ("FETs")) to convert an input voltage V_m to a regulated output voltage V_out.

The auxiliary converter stage 150 receives the input voltage V_m and control signals Cs from the controller 120 and provides a supply bias power (e.g., a bias voltage V s) for powering the controller 120. The auxiliary converter stage 150 may also supply the bias voltage V s to primary side circuits of the power converter 100 and also provide an isolated power source to secondary-side circuits of the power converter 100. The auxiliary converter stage 150 may also provide a reference voltage VR related to the input voltage V_M to secondary-side circuits (such as secondary-side circuits in the controller 120) to facilitate a voltage feed-forward control for the power converter 100. The reference voltage VR (which may be of a level proportional to the input voltage V_m and may include an offset level such as due to diode rectification) may be used in the regulated ratio ("RR") mode or the hybrid regulated ratio ("HRR") mode, as described in U.S. Patent Application Publication No. 2013/0343094, entitled "Controlling a Switched Mode Power Supply with Maximsed Power Efficiency," published December 26, 2013 and U.S. Patent Application Publication No. 2015/0055375, entitled "Controlling a Switched Mode Power Supply with Maximsed Power Efficiency," published February 26, 2015, which are incorporated herein by reference. The controller 120 employs the reference voltage VR and senses the output voltage V_out to control the output voltage V_out of the power converter 100. Alternatively, the reference voltage VR generated by the auxiliary converter stage 150 may be provided to a sample and hold circuit that extracts data representative of the input voltage V_m, which may then be used by the controller 120, or for other purposes.

The main converter stage 110 is an isolated dc-dc power converter, typically down- converting the input voltage V_m to a suitable output voltage V_ou^ for powering a load coupled to the power converter 100. The main converter stage 110 may typically operate with an input or output voltage range of 10-100 volts. The auxiliary stage converter 150 may be provided, without limitation, in the form of a fly-buck power converter. Again, the auxiliary converter stage 150 supplies the bias voltage Vbias to the controller 120. The bias voltage Vbias may be a primary-side or secondary-side bias voltage Vp, Vs illustrated and described hereinbelow.

The controller 120 including processor ("PR") 130 and memory ("M") 140 receives the output voltage Vout and the reference voltage VR from the auxiliary converter 150 and generates control signals Cs to the switching elements in the main converter stage 110 to regulate the output voltage Wt (an output characteristic of the power converter). The processor 130 may be embodied as any type of processor and associated circuitry configured to perform one or more of the functions described herein. For example, the processor 130 may be embodied as or otherwise include a single or multi-core processor, an application specific integrated circuit, a collection of logic devices, or other circuits. The memory 140 may be embodied as read-only memory devices and/or random access memory devices. For example, the memory 140 may be embodied as or otherwise include dynamic random access memory devices ("DRAM"), synchronous dynamic random access memory devices ("SDRAM"), double-data rate dynamic random access memory devices ("DDR SDRAM"), and/or other volatile or non-volatile memory devices. The memory 140 may have stored therein programs including a plurality of instructions or computer program code for execution by the processor 130 to control particular functions of the power converter as discussed in more detail below.

Turning now to FIGURE 2, illustrated is a block diagram of an embodiment of a power converter 200. The power converter 200 includes a main converter stage 210, an auxiliary converter stage 220, a pulse- width modulator ("PWM") controller 230, a compensator 240 and an auxiliary controller 250. The PWM controller 230 resides on a primary side of an isolation boundary of the main and auxiliary converter stages 210, 220, and the compensator 240 resides on a secondary side of the isolation boundary of the main and auxiliary converter stages 210, 220.

The compensator 240 (see, e.g., "Demystifying Type II and Type III Compensators Using Op- Amp and OTA for DC/DC Converters," Texas Instruments Application Report, SLVA662, by SW Lee, July 2014, which is incorporated herein by reference) receives a reference voltage VR from the auxiliary converter stage 220 and an output voltage Wt of the power converter 200 and provides a control signal CNTL to the PWM controller 230. The auxiliary converter stage 220 receives the input voltage Vin and also provides a primary-side bias voltage Vp, a secondary- side bias voltage Vs and a trim voltage Vtrfm as described below. The aforementioned voltages and the reference voltage VR are related to the input voltage Vin

The PWM controller 230 receives the control signal CNTL from the compensator 240 and provides control signals Csp, Css to the primary and secondary-sides of the main converter stage 210 to control a duty cycle D (and a complimentary duty cycle 1-D) and/or a switching frequency of one or more power switches or switching elements (e.g., field-effect transistors ("FETs")) to convert the input voltage Vin to a regulated output voltage Vout.

Analogous to the power converter 100 of FIGURE 1 , the main converter stage 210 may be an isolated dc-dc power converter, typically down-converting the input voltage Vin to a suitable output voltage Vout for powering a load coupled to the power converter 200. The main converter stage 210 may typically operate with an input or output voltage range of 10-100 volts. The auxiliary stage converter 220 may be provided, without limitation, in the form of a fly-buck power converter. Again, the auxiliary converter stage 220 supplies the primary-side or secondary-side bias voltages Vp, Vs illustrated and described hereinbelow. The auxiliary controller 250 provides control signals Cs to the auxiliary stage converter 220 to regulate the primary-side bias voltage VP in a voltage control feedback loop and control of the secondary-side bias voltage Vs is open loop following the primary-side bias voltage Vp.

Turning now to FIGURE 3, illustrated is a schematic diagram of an embodiment of an auxiliary power converter. The auxiliary power converter may be employed as the auxiliary stage converter 150, 220 of FIGURES 1 and 2. The auxiliary power converter includes first and second power switches Qi, Q2, a transformer Tl having a primary winding Xi and a secondary winding X2 (with a turns ratio of 1 :n), a diode Di, and first and second capacitive elements Cp, Cs. The auxiliary power converter produces primary-side and secondary-side bias voltages Vp, Vs across the first and second capacitors CP, CS, respectively.

A controller (e.g., controller 120 of FIGURE 1 or the auxiliary controller 250 of FIGURE 2) provides control signals to control a duty cycle D (and a complimentary duty cycle 1-D) and/or a switching frequency of the first and second power switches Qi, Q2, respectively, to produce (via a buck converter topology) the primary-side bias voltage V_P proportional to an input voltage Vin. The auxiliary power converter is also formed with a secondary-side fly-buck converter that produces an isolated, secondary-side voltage Vs also proportional (with an offset due to the diode Di) to the input voltage Vin. The duty cycle D employed for the auxiliary power converter may be equivalent to the duty cycle D of a main power converter forming the main converter stage (see, e.g., main converter stage 110, 210 of FIGURES 1 and 2). While isolated fly-buck converters typically have a transformer turns ratio between the primary winding Xi and the secondary winding X2 of 1 : 1, field-effect transistors, which may be used in a controller (see, e.g., FIGURES 1 and 2), usually require lower voltages. Therefore, a suitable transformer turns ratio for the isolated fly-buck converter may, in some applications, be 1 :0.75.

The first capacitive element Cp is connected in series with the primary winding Xi of the transformer Tl and the first and second power switches Qi, Q2 arranged in the primary-side circuit. The first and second power switches Qi, Q2 are configured to switch such that, during a forward phase of operation of the isolated fly-buck converter, the primary winding Xi and the first capacitive element Cp are connected to the input voltage V_m and, during a fly-buck phase of operation of the isolated fly-buck converter, the primary winding Xi and the first capacitive element Cp are disconnected from the input voltage V_m and are connected to one another in a closed circuit employing the second power switch Q2.

The secondary winding X2 is electromagnetically coupled to the primary winding Xi of the transformer Tl. The second capacitive element Cg is connected across the secondary winding X2. The diode Di (a rectifier) is connected to the secondary winding X2 and the second capacitive element Cg so as to prevent current from flowing through the secondary winding X2 to charge/discharge the second capacitive element Cg during the forward phase of operation of the fly-buck converter. The secondary-side bias voltage Vg of the fly-buck converter corresponds to the voltage produced across the second capacitive element Cg.

Turning now to FIGURES 4 to 6, illustrated are schematic diagrams of another embodiment of an auxiliary power converter. The auxiliary power converter allows for a measurement of the input voltage Vin to be performed on the secondary side thereof. (See, e.g., U.S. Patent Application Publication No. 2015/0340959, entitled "Isolated Fly-Buck Converter, Switched Mode Power Supply, and Method of Measuring Voltage on a Secondary Side of an Isolated Fly-Buck Converter," published November 26, 2015, which is incorporated herein by reference.) The auxiliary power converter includes a buck converter 410 on the primary side, and isolated fly-buck converter topologies 420, 430 on the secondary side.

With continuing reference to FIGURE 3, the modified fly-buck converter of FIGURE 4 also includes an input voltage sensing circuit for generating a sense voltage V_sense that is indicative of and a function of a voltage level of the input voltage V_m by stacking the isolated fly-buck converter topologies 420, 430 to produce the sense voltage Vsense proportional to the input voltage Vin independently of the duty cycle D of the power switch Ql . The input voltage sensing circuit includes a third capacitive element Cp and a second diode D2 (a rectifier) that are connected in series. The input voltage sensing circuit is connected over the secondary winding X2 such that the second diode D2 prevents current from flowing through the input voltage sensing circuit during the fly-buck phase of operation. The sum of a second secondary-side bias voltage Vp across the third capacitive element Cp and the secondary-side bias voltage Vg is the sensed voltage V_sense on the secondary side, which is indicative of a level of the input voltage

V_m of the auxiliary power converter on the primary side. The input voltage sensing circuit may, as in the example illustrated in FIGURE 4, include a resistive element R3 connected in series with the second capacitive element Cp and the second diode D2, the resistive element R3 serving to reduce current spikes (circuit noise content) during charging of the third capacitive element Cp, thereby producing a less noisy voltage across third capacitive element Cp. For the remaining elements of the auxiliary power converter of FIGURE 4, see the description above with respect the auxiliary power converter of FIGURE 3.

An explanation of the auxiliary power converter of FIGURE 4 will be performed with reference to the partial schematic diagrams of FIGURES 5 and 6. The relationship between the sensed voltage V_sense and the input voltage V_m will be derived in the case where the primary winding Xi of transformer Tl has one turn and the secondary winding X2 has n turns. Steady- state switching with a duty cycle D, a small ripple current in the windings, and a small voltage ripple in the capacitances (such as the third capacitive element Cp) are also assumed.

During the forward phase of operation, the first power switch Qi is conducting and the second power switch Q2 is not conducting as depicted in FIGURE 5. The diode Di is not conducting and the resistive element R3 is removed during the following analysis. A voltage VL across the primary winding Xi is:

v_L = v_in - v_P, Equation 1

or, using the reflected voltage over the third capacitive element Vp on the primary side, as:

V -, Equation 2

n

wherein the voltage Vpj is the voltage across the second diode >2 in the forward direction.

During the fly-buck phase of operation, the auxiliary power converter of FIGURE 4 can be simplified to the schematic diagram shown in FIGURE 6. The voltage VL across the primary winding Xi can be stated directly on the primary side as:

V , = —Vp, Equation 3

or, using the reflected secondary-side bias voltage V§ on the primary side, as:

V_s + V_{D r}

V = -— -, Equation 4

n

wherein the voltage Vpj is the voltage drop over the diode Di in the forward direction. For the primary-side bias voltage Vp, the volt-second balance using Equations 1 and 3 becomes:

D(V_in - V_P) + D'(-V_P)

Equation 5

= 0,

wherein the forward phase duration is equal to the duty cycle D, and the fly-buck phase duration is (1 -D) = D'. Solving Equation 5 for primary-side bias voltage Vp yields:

V_P = DV_in. Equation 6

For the isolated fly-buck converter topology, the volt-second balance using Equations 1 and 4 becomes:

V_s + V_D\

D(V_in - V_P) + D' ί— j = 0. Equation 7

Collecting terms on each side yields:

DV_in = DV_P + D'

n

and using Equation 6 yields:

, V_S + V_D

DV_P + D

n Collecting the primary-side bias voltage Vp on the left-hand side and using (1 - D) = D' yields:

Dividing the result by D' on both sides and solving for the secondary-side bias voltage V§ yields:

V_s = nVp - V_l Equation 8

For the isolated forward-buck converter topology, the volt-second balance using Equations 2 and 3 becomes:

D + D'(-Vp) = 0. Equation 9 n

Solving Equation 1 for D'(-Vp) and replacing the term in Equation 9 yields:

V_F + V_D

D - + D(V_in - V_P) = 0.

n

Solving for the second secondary-side bias voltage Vp yields:

V_F = n(V_in— Vp)— V_D. Equation 10 The sensed voltage V_sense indicative of the input voltage V_m is the sum of the secondary-side bias voltages V§, Vp, and using Equations 8 and 10 yields:

Vsense = V_s + V_F = nV_P - V_D + n(V_in - V_P) - V_D, and collecting terms yields:

Vsense = nV_in - 2V_D . Equation 11

Hence, the sensed voltage V_sense is a scaled, linear value of the input voltage V_m and offset by two diode forward voltages Vpj. Since the input voltage V_m times the transformer turns ratio n is much greater than 2^»VTJ, Equation 11 can be simplified to:

Vsense ~ nV_in. Equation 12

The diode voltage drops Vpj.can be reduced using Schottky diodes or can be substantially eliminated by using synchronous rectification.

The sensed voltage V_sense is thus indicative of (i.e., a function of) the level of the input voltage V_m and is sensed on the isolated, secondary side. The sensed voltage V_sense (or a reference voltage VR proportional thereto as described hereinbelow with reference to FIGURE 7) can be used in the control of the main power converter of the main converter stage 110, 210 of the power converter 100, 200 of FIGUREs 1 and 2. The sensed voltage V_sense (and the corresponding reference voltage VR) is independent of the duty cycle D as illustrated by Equation 12.

Again referring to FIGURE 1 , the controller 120 of the power converter 100 (or control system including the compensator 240 of FIGURE 2) may thus be configured to receive the sensed voltage V_sense (or the corresponding reference voltage VR) from the isolated secondary side of the auxiliary power converter to control the power train of the main power converter of the main converter stage 1 10 (or the main converter stage 210 of FIGURE 2). The sensed voltage V_sense (or the corresponding reference voltage VR) as measured on the secondary side, may then be used for input voltage feedforward control in a secondary-side controlled switched- mode power converter. Alternatively or additionally, the sensed voltage V_sense (or the corresponding reference voltage VR) may be used for setting a reference voltage in a regulated ratio or hybrid regulated ratio controlled power converter.

Turning now to FIGURE 7, illustrated is a schematic diagram of another embodiment of an auxiliary power converter. The auxiliary power converter (employable in the auxiliary converter stage 150, 220) may be used for a hybrid regulated ratio ("HRR") control in the power converter 100, 200 of FIGURES 1 and 2. The auxiliary power converter employs a transformer Tl with an added isolated fly-buck converter topology on the secondary side to produce a reference voltage VR related to (e.g., proportional to with an offset) a voltage level of the input voltage Vin that can be employed to regulate an output voltage Vout of a hybrid regulated ratio power converter. As described previously hereinabove, by adding the second diode D₂, the third capacitive element CF, and the resistive element R3 on the secondary side of the circuit utilizing the forward phase (when power switch Ql is conducting), the input voltage Vin to the power converter 100, 200 can be sensed by sensing the second secondary-side bias voltage VF across the third capacitive element CF. The reference voltage VR is formed with resistive elements Ri, R2 and a fourth capacitive element Ci, and controlled/clamped with a Zener diode D_ref. By adding the Zener diode Dref in parallel with resistive element Ri, a simple overvoltage protection ("OVP") circuit arrangement is obtained to prevent trimming the output voltage Wt of the power converter 100, 200 too high. It also limits the effect of a high second secondary-side bias voltage VF. The Zener diode Dref implements the constant part of the reference voltage VR used in hybrid regulated ratio control. By removing the voltage reference produced by Zener diode Dref, one obtains a controllably varied reference voltage VR for regulated ratio operation of the power converter 100.

Continuing with a further description of the auxiliary power converter illustrated in FIGURE 7, on the secondary side is a voltage divider including the two series-connected resistive elements, Ri , R2 that are connected in parallel with the second and third capacitive elements C§, Cp to divide the sensed voltage V_SENSE to produce the reference voltage VR. The fourth capacitive element Ci , and a voltage limiting circuit element (the Zener diode D_ref) are connected in parallel with one of the resistive elements of the voltage divider (such as the resistive element Ri ), wherein the reference voltage VR changes with a time constant that is dependent upon the fourth capacitive element Ci and is limited by a breakdown voltage of the

Zener diode Dref. Again, the reference voltage VR is usable as a hybrid regulated ratio reference in hybrid regulated ratio ("HRR") control of the main power converter of the main converter stage 110, 210.

In the auxiliary power converter, the sense voltage V_SENSE ~ n^»V_M is divided using the voltage divider formed with the resistive elements Ri , R2, and a time constant set by the fourth capacitive element C\ . The reference voltage VR is saturated using a high precision voltag reference with voltage formed with the Zener diode D_ref, yielding the reference voltage VR for hybrid regulated ratio as:

V_R

Equation 13 mm

wherein s is complex frequency, the regulated ratio input voltage part has a gain GRR of:

Ri

GRR = n———— Equation 14

«1 + ^K2

and a time constant T_rr becomes:

^{Trr = Cl} R^+ Rz Equatⁱon 15

Accurate sensing of, and the ability to configure increasing and decreasing slew rates of, the reference voltage VR is important for control of the power converter 100, 200.

More particularly, for a given value of the fourth capacitive element Cj , it is difficult to configure a slew rate of the reference voltage VR without also having to modify the gain GRR for generating the reference voltage VR. Therefore, where the voltage range of the reference voltage VR is defined by a recipient circuit of the reference voltage VR, it is impractical to configure the slew rate of the reference voltage VR. Furthermore, the increasing and decreasing slew rates of the reference voltage VR are both defined by the voltage divider formed with the resistive elements Ri , R2, and the fourth capacitive element Ci , and so increasing and decreasing slew rates are not independently configured.

Turning now to FIGURES 8 to 12, illustrated are diagrams of another embodiment of an auxiliary power converter 800, or portions thereof. The auxiliary power converter 800 includes a power train 810 including a resistor divider 820 and a reference voltage generator 830. The power train 810 produces the sensed voltage Vsense akin to the auxiliary power converter of FIGURE 7. The auxiliary power converter 800 may form the auxiliary converter stage 150, 220 of the power converter 100, 200 of FIGURES 1 and 2.

The auxiliary power converter 800 is configured to convert an input voltage V_m to a primary-side bias voltage Vp and a secondary-side bias voltage Vs, and generate a reference voltage VR that is a function of a level of the input voltage V_m. The auxiliary power converter

800 includes primary-side circuit formed with a first capacitive element Cp coupled to a primary winding Xi of transformer Tl and a non-isolated buck connected in series, with first and second power switches Qi, Q2 in the primary-side circuit. The first and second power switches Qi, Q2 are configured to switch such that, during a forward phase of operation of the isolated fly-buck converter, the primary winding Xi of transformer Tl and the non-isolated buck are connected to the input voltage Vin and, during a fly-buck phase of operation of the isolated fly-buck converter, the primary winding Xi of transformer Tl and the non-isolated buck are disconnected from the input voltage Vin and are connected by the second power switch Q2 to one another in a closed circuit. The primary-side bias voltage Vp is the voltage across the first capacitive element Cp. The auxiliary power converter 800 is also formed with a secondary-side circuit including a secondary winding X2 of the transformer Tl magnetically coupled to the primary winding Xi, a second capacitive element Cs connected across the secondary winding X2, and a diode Di (a rectifier) that is connected to the secondary winding X2 so as to prevent current flowing through the secondary winding X2 during the forward phase, wherein the secondary-side bias voltage Vs is the voltage across the second capacitive element Cs (referenced to local circuit ground).

The secondary-side circuit further includes an input voltage sensing circuit for generating a sensed voltage Vsense and a scaled value Vin-div thereof that are functions of a level of the input voltage Vin, the input voltage sensing circuit including a third capacitive element CF and a second diode D2 (a rectifier) connected in series. The input voltage sensing circuit is connected across the secondary winding X2 of the transformer Tl such that the diode D2 prevents current from flowing through the input voltage sensing circuit during the fly-buck phase of operation. The input voltage sensing circuit further includes a buffer amplifier 840 formed with operational amplifier 850 and arranged to buffer the scaled voltage Vin-div that is a function of a sum of the second secondary-side bias voltage VF across the third capacitive element CF and the secondary- side bias voltage Vs across the second capacitive element Cs, and to output the reference voltage VR that is a function of a voltage level of the input voltage Vin. The reference voltage VR is proportional to the input voltage Vin and may have an offset level such as due to a diode forward voltage drop. The output of the buffer amplifier 840 is connected to local circuit ground via a slew resistive element Rsiew in series with a parallel combination of a timing resistive element Rt and a timing capacitive element Ct. The timing capacitive element Ct limits a slew rate of the reference voltage VR. The buffer amplifier 840 with a high input impedance is added between a resistor divider 820 formed with resistive elements Ri, R2 and a Zener diode D_ref. By adding the Zener diode Dref in parallel with the timing resistive element Rt an overvoltage protection structure is obtained that can prevent trimming the output voltage Vout of the power converter 100, 200 of FIGUREs 1 and 2. It also limits a maximum voltage level of the sense voltage Vsense. The buffer amplifier 840 with its high input impedance makes it possible to control the slew rate of charging/discharging voltage produced across the timing capacitive element Ct that is in parallel with the Zener diode D_ref through the slew resistive element Rsiew when the input voltage Vin changes. This also enables control over the initial ramp-up time of the reference voltage VR via a ramp resistive element Rramp. The purpose of a diode D3 is to limit current through the Zener diode Dref. The buffer amplifier 840 should sink the reference voltage VR, not increase it, which functionality is provided by the diode D3 in series with the output of operational amplifier 850. As a result, the buffer amplifier 840 is configured to prevent the reference voltage VR from being greater than the scaled voltage Vin-div. The resistor r is included to limit an offset of the operational amplifier 850. The timing resistive element Rt is included for discharging the timing capacitive element Ct when the auxiliary power converter 800 is disabled.

The buffer amplifier 840 may, as in the present embodiment, be formed with the operational amplifier 850 provided with a feedback circuit (including the resistor r) that is arranged to feed back an output voltage thereof to an inverting input of the operational amplifier 850. The resistor r serves to prevent, or at least mitigate, voltage offset problems which may arise. The non-inverting input of the operational amplifier 850 is arranged to receive the scaled voltage Vin-div being a scaled value of the sense voltage Vsense set by the values of resistive elements Ri, R2 forming resistor divider 820. The output of the buffer amplifier 840 is connected to ground via the slew resistive element Rsi_ew in series with a parallel combination of the timing resistive element R^ and the timing capacitive element C^. The rate of charging and discharging of the timing capacitive element C_† through the slew and timing resistive elements Rslew defines slew rates for the reference voltage VR. When the auxiliary power converter 800 is inactive, the timing resistive element R^ provides a discharge path for the timing capacitive element C_†.

The buffer amplifier 840 may further include the diode D3 arranged to connect the output of the operational amplifier 850 to the slew resistive element Rsi_ew so as to prevent current from flowing from the buffer amplifier 840 to the slew resistive element Rsi_ew. In this embodiment, the diode D3 is arranged between the output of the operational amplifier 850 and a terminal for reading the reference voltage VR. When the diode D3 is biased to prevent current from flowing through the slew resistive element Rsi_ew, the reference voltage VR does not depend on the sense voltage V_sense, but on a voltage across the timing capacitive element C . When the diode D3 (as part of the feedback circuit of the buffer amplifier 840) is reverse biased to prevent current flow, there is no feedback in the buffer amplifier 840 and the non-conducting state is maintained until the reference voltage VR becomes equal to or greater than the scaled voltage V^.^iv through the charging of timing capacitive element C_†.

With the combined effects of the buffer amplifier 840 and the slew and timing resistive elements Rslew ¾ ^me reference voltage VR follows the scaled voltage V_m_di_v with a regulated ratio response according to the following equation (neglecting the small offset over the slew resistive element Rsi_ew):

' Equation 16

t R_t + R_si_ew wherein the time constant

t _{p i p} ■ Equation 17

The diode D3 prevents the timing capacitive element C_† from being charged by the buffer amplifier 840. Thus, when the diode D3 is included in the input voltage sensing circuit, it may be necessary to introduce an alternative means for charging the timing capacitive element C_†. This may be achieved by arranging the timing resistive element R^ and the timing capacitive element C_† such that they are connected to ground in parallel with the second capacitive element C§. This connection may be achieved by the input voltage sensing circuit further comprising the ramp resistive element R_ramp connecting the second capacitive element C§ to the slew resistive element Rsi_ew, the timing resistive element R^ and the timing capacitive element C_†.

When the charge in timing capacitive element C^, and therefore the reference voltage VR, decrease following a decrease of the input voltage V_M, current flows through both the slew resistive element Rsi_ew and the ramp resistive element R_ramp, and so the timing capacitive element C_† discharges with a time constant that is dependent on both the slew and ramp resistive elements Rsiew ^ramp- O^{n me} other hand, due to diode D3, when the timing capacitive element charges following an increase in the input voltage V_M, current flows through the ramp resistive element R_ramp but not through the slew resistive element R_si_ew, and so the timing capacitive element C^ charges with a time constant that is dependent upon the ramp resistive element R_ramp but not dependent upon the slew resistive element R_si_ew. Therefore, by choosing appropriate resistance values for the slew and ramp resistive elements Rsiew ^ramp' the auxiliary power converter 800 may be configured such that the reference voltage VR responds to changes in a level of the input voltage V_m with different rising and falling slew rates that may be set independently of one another.

Additionally, the ramp resistive element R_ramp may be adjusted to control an initial charging time of the timing capacitive element C^, which is dependent upon the ratio between the resistances of the ramp resistive element R_ramp and slew resistive element Rsi_ew. The value of the ramp resistive element R_ramp may therefore be set to achieve an initial ramp-up time of the reference voltage VR.

The auxiliary power converter 800 may include the Zener diode Dref D_ref connected in parallel with the timing resistive element R^ and the timing capacitive element C_†. The Zener diode Dref functions as a voltage-limiting element. The auxiliary power converter 800 with the Zener diode D_ref may, for example, be used in order to operate a power converter in a Hybrid Regulated Ratio ("HRR") mode. The output voltage V_out of the power converter is provided with a regulated ratio between the input voltage V_m and output voltage V_out when the input voltage V_m is in a first voltage range, and is provided independently from the input voltage V_m when the input voltage V_m is in a second, higher voltage range. When input voltage V_m is in the second voltage range, the diode D3 limits the current through the Zener diode D_ref. Operating in HRR mode (and neglecting the ramp resistive component R_ramp and the offset across the slew resistive component R_si_ew), the reference voltage VR will follow the input voltage V_m in a regulated ratio mode until it reaches the reference voltage V_ref, which is defined by the Zener diode D_ref. If the input voltage V_m increases beyond this level, the reference voltage VR will not vary in regulated ratio mode but will instead remain at the reference voltage V_ref until the input voltage V_m falls below this level again. This variation of the reference voltage VR may be expressed as follows:

, V_ref J. Equation 18

s^Ct R_t + R slew

The scaled voltage V^.^iv is indicative of the sensed voltage V_sense via the resistor divider 820. With this potential divider, the reference voltage VR is defined by the following formula:

V_R

\ Equation 19

Rl

min nV_ir ref

slew

+ R slew

wherein s is complex frequency, the regulated ratio input voltage part has a gain GRR of: GRR = n——— - , Equation 20

and a time constant T_rr becomes:

¾_R = Q . Equation 21

This embodiment differs from the converter of FIGURE 7 (which follows Equations 13 to 15) at least by the gain GRR and time constant being independently configurable for a given timing capacitive element C_†. So the gain and time constant may be set to values employed by a recipient circuit of the reference voltage VR, such as the controller 120 of the power converter 100 illustrated in FIGURE 1 (or the control system including the compensator 240 of the power converter 200 illustrated in FIGURE 2).

Turning now to FIGURE 9, the auxiliary power converter 800 of FIGURE 8 also includes a trim resistive element RL configured to provide a trim voltage Vtrim as a function of the reference voltage VR. The trim voltage Vtrim enables operation with a Lucent output voltage trim. The trim voltage Vtrim is coupleable to an external resistor R as shown in FIGURES 10 and 1 1. The voltage at a circuit node 910 retains a voltage level with a component scaled to the input voltage Vin. FIGURE 10 illustrates the external resistor R that is coupled to a positive output voltage terminal V+ of a power converter (see FIGURES 1 and 2) that is employed to trim up the output voltage Vout. FIGURE 1 1 illustrates the external resistor R that is coupled to a negative output voltage terminal V- of a power converter (see FIGURES 1 and 2) that is employed to trim up the output voltage Vout. In order to accommodate Lucent output voltage trim, the external resistor R with a resistance value of, for instance, 5.11 kilo-ohms ("kQ") are often used. This limits slew-rate control somewhat, but the value of timing capacitance element Ct still makes use of the Lucent output voltage trim possible.

Turning now to FIGURE 12, the auxiliary power converter 800 of FIGURE 8 also includes a second Zener diode Z that limits a maximum value of the scaled voltage V^^i_y Thus, the auxiliary power converter is operable with the Lucent output voltage trim and can provide output overvoltage protection.

Turning now to FIGURE 13, illustrated is a block diagram of an embodiment of a communication device 1300. The power converter as described herein may be employed in a communication device 1300 such as a base station in a telecommunications network.

Turning now to FIGURE 14, illustrated is a flow diagram of an embodiment of a method of operating a power converter. The method begins at a start step or module 1400. At a step or module 1405, the method includes receiving an input voltage at a main converter stage and an auxiliary converter stage. At a step or module 1410, the method includes producing a primary- side bias voltage with a first capacitive element series-coupled with a primary winding of an isolation transformer of a power train of the auxiliary converter stage. At a step or module 1415, the method includes providing a secondary-side bias voltage during a complementary duty cycle (1-D) with a second capacitive element of the auxiliary converter stage coupled in series with a first diode to a secondary winding of the isolation transformer. At a step or module 1420, the method includes providing a second secondary-side bias voltage during a duty cycle (D) with a third capacitive element of the auxiliary converter stage coupled in series with a second diode to the secondary winding. At a step or module 1425, the method includes reducing a noise content of the second secondary-side bias voltage with a first resistive element series-coupled with the second diode of the power train.

At a step or module 1430, the method includes producing a scaled voltage at a first voltage level being a scaled value of the input voltage with a power train of the auxiliary converter stage. In an embodiment, the first voltage level is independent of a duty cycle (D) of the power train. The scaled voltage is a function of the secondary-side bias voltages across the second and third capacitive elements. The scaled voltage is isolated from the input voltage via the isolation transformer of the auxiliary converter stage including the primary winding and the secondary winding.

At a step or module 1435, the method includes limiting the scaled voltage with a Zener diode parallel-coupled to a first resistive element of a resistor divider of the auxiliary converter stage. At a step or module 1440, the method includes receiving the scaled voltage at a buffer amplifier of the auxiliary converter stage including a slew resistive element coupled at a circuit node to a timing capacitive element.

At a step or module 1445, the method includes providing a reference voltage as a function of a second voltage level at the circuit node and the scaled voltage. At a step or module 1450, the method includes limiting the second voltage level at the circuit node via a Zener diode of the auxiliary converter stage parallel-coupled with the timing capacitive element. At a step or module 1455, the method includes controlling a ramp-up time of the reference voltage with, for instance, a ramp resistive element. At a step or module 1460, the method includes preventing the reference voltage from being greater than the scaled voltage with a diode coupled to an operational amplifier of the buffer amplifier.

At a step or module 1465, the method includes providing a trim voltage via a trim resistive element of the buffer amplifier coupled to the slew resistive element. At a step or module 1470, the method includes providing an output voltage from the main converter stage as a function of the reference voltage. The method ends at a step or module 1475.

Thus, a power converter for producing a reference voltage and method of operating the same has been introduced herein. In one embodiment, the power converter (100, 200) includes a main converter stage (110, 210) configured to receive an input voltage (Vin) and provide an output voltage (Vout) therefrom. The power converter (100, 200) also includes an auxiliary converter stage (150, 220, 800) configured to receive the input voltage (Vin) and comprises a power train (810) configured to produce a scaled voltage (Vin-div) at a first voltage level being a scaled value of the input voltage (Vin). The first voltage level may be independent of a duty cycle (D) of the power train (810). The auxiliary converter stage (150, 220, 800) also includes a buffer amplifier (840) including a slew resistive element (Rsiew) coupled at a circuit node (910) to a timing capacitive element (Ct) and configured to receive the scaled voltage (Vin-div) and provide a reference voltage (VR) as a function of a second voltage level at the circuit node (910) and the scaled voltage (Vin-div).

The power train (810) further includes an isolation transformer (Tl) including a primary winding (Xi) and a secondary winding (X₂) configured to isolate the scaled voltage (Vin-div) from the input voltage (Vin), a first capacitive element (Cp) series-coupled with the primary winding (Xi) configured to produce a primary-side bias voltage (Vp), a second capacitive element (C_s), coupled in series with a first diode (Di) to the secondary winding (X₂), configured to store a secondary-side bias voltage (Vs) during a complementary duty cycle (1 -D), and a third capacitive element (CF), coupled in series with a second diode (D₂) to the secondary winding (X₂), configured to store a second secondary-side bias voltage (VF) during a duty cycle (D). The second and third capacitive elements (Cs, CF) are series-coupled to provide the scaled voltage (Vin-div) as a function of the secondary-side bias voltages (Vs, VF). The power train (810) further includes a first resistive element (R3) series-coupled with the second diode (D2) configured to reduce a noise content of the second secondary-side bias voltage (VF).

The auxiliary converter stage (1 50, 220, 800) further includes a resistor divider including first and second resistive elements (Ri, R2) coupled to the scaled voltage (Vin-div), and a Zener diode (Z) parallel-coupled to the first resistive element (Ri) configured to limit the scaled voltage (Vin-div). The auxiliary converter stage (150, 220, 800) further includes a ramp resistive element (Rramp) configured to control a ramp-up time of the reference voltage (VR).

The auxiliary converter stage (150, 220, 800) further includes a Zener diode (D_ref) parallel-coupled with the timing capacitive element (Ct) configured to limit the second voltage level at the circuit node (910). The buffer amplifier (840) includes a diode (D3) coupled to an operational amplifier (850) configured to prevent the reference voltage (VR) from being greater than the scaled voltage (Vin-div). The buffer amplifier (840) further includes a trim resistive element (RL) coupled to the slew resistive element (Rsiew) configured to provide a trim voltage

(Vtrim).

Many modifications and variations can be made to the embodiments described hereinabove without departing from the scope of the presently introduced solution. For example, generally, a circuit for a control process as introduced herein can be implemented using either analog or digital electronics, with no loss of performance. In a digital implementation of the circuit, the components of the circuit may be implemented as software components of that may form at least a part of a computer program, module, object or sequence of instructions executable by a programmable signal processing apparatus such as a microprocessor, for example the controller 120 as shown schematically in FIGURE 1, which is an example of a general kind of programmable signal processing apparatus in which the proposed solution may be implemented.

The foregoing description of embodiments of the present proposed solution has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the proposed solution to the present form disclosed. Alternations, modifications and variations can be made without departing from the spirit and scope of the present proposed solution.

As described above, the exemplary embodiment provides both a method and

corresponding apparatus consisting of various modules providing functionality for performing the steps of the method. The modules may be implemented as hardware (embodied in one or more chips including an integrated circuit such as an application specific integrated circuit), or may be implemented as software or firmware for execution by a processor. In particular, in the case of firmware or software, the exemplary embodiment can be provided as a computer program product including a computer readable storage medium embodying computer program code (i.e., software or firmware) thereon for execution by the computer processor. The computer readable storage medium may be non-transitory (e.g., magnetic disks; optical disks; read only memory; flash memory devices; phase-change memory) or transitory (e.g., electrical, optical, acoustical or other forms of propagated signals-such as carrier waves, infrared signals, digital signals, etc.). The coupling of a processor and other components is typically through one or more busses or bridges (also termed bus controllers). The storage device and signals carrying digital traffic respectively represent one or more non-transitory or transitory computer readable storage medium. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device such as a controller.

Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope thereof as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof. Also, many of the features, functions, and steps of operating the same may be reordered, omitted, added, etc., and still fall within the broad scope of the various embodiments.

Moreover, the scope of the various embodiments is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized as well. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

CLAIMS:

1. A power converter (800) configured to receive an input voltage (Vm), comprising: a power train (810) configured to produce a scaled voltage (Vin-div) at a first voltage level being a scaled value of said input voltage (Vm); and

a buffer amplifier (840) including a slew resistive element (Rsiew) coupled at a circuit node (910) to a timing capacitive element (Ct) and configured to receive said scaled voltage (Vin- div) and provide a reference voltage (VR) as a function of a second voltage level at said circuit node (910) and said scaled voltage (Vin-div).

2. The power converter (800) as recited in Claim 1 wherein said first voltage level is independent of a duty cycle (D) of said power train (810).

3. The power converter (800) as recited in Claim 1 wherein said buffer amplifier (840) further comprises a trim resistive element (RL) coupled to said slew resistive element (Rsiew) configured to provide a trim voltage (Vtrim).

4. The power converter (800) as recited in Claim 1 further comprising a Zener diode (Dref) parallel-coupled with said timing capacitive element (Ct) configured to limit said second voltage level at said circuit node (910).

5 The power converter (800) as recited in Claim 1 wherein said buffer amplifier (840) includes a diode (D3) coupled to an operational amplifier (850) configured to prevent said reference voltage (VR) from being greater than said scaled voltage (Vin-div).

6. The power converter (800) as recited in Claim 1 , further comprising:

a resistor divider including first and second resistive elements (Ri, R2) coupled to said scaled voltage (Vin-div); and a Zener diode (Z) parallel-coupled to said first resistive element (Ri) configured to limit said scaled voltage (Vin-div).

7. The power converter (800) as recited in Claim 1 wherein said power train (810) further comprises:

an isolation transformer (Tl) including a primary winding (Xi) and a secondary winding (X₂) configured to isolate said scaled voltage (Vin-div) from said input voltage (Vm);

a first capacitive element (C_s), coupled in series with a first diode (Di) to said secondary winding (X₂), configured to store a secondary-side bias voltage (Vs) during a complementary duty cycle (1 -D); and

a second capacitive element (CF), coupled in series with a second diode (D₂) to said secondary winding (X₂), configured to store a second secondary-side bias voltage (VF) during a duty cycle (D), said first and second capacitive elements (Cs, CF) series-coupled to provide said scaled voltage (Vin-div) as a function of said secondary-side bias voltages (Vs, VF).

8. The power converter (800) as recited in Claim 7 wherein said power train (810) further comprises a first resistive element (R3) series-coupled with said second diode (D₂) configured to reduce a noise content of said second secondary-side bias voltage (VF).

9. The power converter (800) as recited in Claim 1 further comprising a ramp resistive element (Rramp) configured to control a ramp-up time of said reference voltage (VR).

10. The power converter (800) as recited in Claim 1 wherein said power train (810) further comprises a first capacitive element (Cp) series-coupled with a primary winding (Xi) of an isolation transformer (Tl) configured to produce a primary-side bias voltage (Vp) for said power train (810).

11. A power converter (100, 200), comprising: a main converter stage (1 10, 210) configured to receive an input voltage (Vin) and provide an output voltage (Wt) therefrom; and

an auxiliary converter stage (150, 220, 800) configured to receive said input voltage (Vin), comprising:

a power train (810) configured to produce a scaled voltage (Vin-div) at a first voltage level being a scaled value of said input voltage (Vin), and

a buffer amplifier (840) including a slew resistive element (Rsiew) coupled at a circuit node (910) to a timing capacitive element (Ct) and configured to receive said scaled voltage (Vin-div) and provide a reference voltage (VR) as a function of a second voltage level at said circuit node (910) and said scaled voltage (Vin-div).

12. The power converter (100, 200) as recited in Claim 1 1 wherein said first voltage level is independent of a duty cycle (D) of said power train (810).

13. The power converter (100, 200) as recited in Claim 1 1 wherein said buffer amplifier (840) further comprises a trim resistive element (RL) coupled to said slew resistive element (Rsiew) configured to provide a trim voltage (Vtrim).

14. The power converter (100, 200) as recited in Claim 1 1 wherein said auxiliary converter stage (150, 220, 800) further comprises a Zener diode (D_ref) parallel-coupled with said timing capacitive element (Ct) configured to limit said second voltage level at said circuit node (910).

15 The power converter (100, 200) as recited in Claim 1 1 wherein said buffer amplifier (840) includes a diode (D3) coupled to an operational amplifier (850) configured to prevent said reference voltage (VR) from being greater than said scaled voltage (Vin-div).

16. The power converter (100, 200) as recited in Claim 11 wherein said auxiliary converter stage (150, 220, 800) further comprises:

a resistor divider including first and second resistive elements (Ri, R2) coupled to said scaled voltage (Vin-div); and

a Zener diode (Z) parallel-coupled to said first resistive element (Ri) configured to limit said scaled voltage (Vin-div).

17. The power converter (100, 200) as recited in Claim 11 wherein said power train (810) further comprises:

an isolation transformer (Tl) including a primary winding (Xi) and a secondary winding (X2) configured to isolate said scaled voltage (Vin-div) from said input voltage (Vin);

a first capacitive element (C_s), coupled in series with a first diode (Di) to said secondary winding (X2), configured to store a secondary-side bias voltage (Vs) during a complementary duty cycle (1 -D); and

a second capacitive element (CF), coupled in series with a second diode (D2) to said secondary winding (X2), configured to store a second secondary-side bias voltage (VF) during a duty cycle (D), said first and second capacitive elements (Cs, CF) series-coupled to provide said scaled voltage (Vin-div) as a function of said secondary-side bias voltages (Vs, VF).

18. The power converter (100, 200) as recited in Claim 17 wherein said power train (810) further comprises a first resistive element (R3) series-coupled with said second diode (D2) configured to reduce a noise content of said second secondary-side bias voltage (VF).

19. The power converter (100, 200) as recited in Claim 1 1 further comprising a ramp resistive element (Rramp) configured to control a ramp-up time of said reference voltage (VR).

20. The power converter (100, 200) as recited in Claim 1 1 wherein said power train (810) further comprises a first capacitive element (Cp) series-coupled with a primary winding (Xi) of an isolation transformer (Tl) configured to produce a primary-side bias voltage (VP) for said power train (810).

21. A method of operating a power converter (100, 200), comprising:

receiving (1405) an input voltage (Vin) at a main converter stage (1 10, 210) and an auxiliary converter stage (150, 220, 800);

producing (1430) a scaled voltage (Vin-div) at a first voltage level being a scaled value of said input voltage (Vin) with a power train (810) of said auxiliary converter stage (150, 220, 800);

receiving (1440) said scaled voltage (Vin-div) at a buffer amplifier (840) of said auxiliary converter stage (150, 220, 800) including a slew resistive element (Rsiew) coupled at a circuit node (910) to a timing capacitive element (Ct);

providing (1445) a reference voltage (VR) as a function of a second voltage level at said circuit node (910) and said scaled voltage (Vin-div); and

providing (1470) an output voltage (Vout) from said main converter stage (1 10, 210) as a function of said reference voltage (VR).

22. The method as recited in Claim 21 wherein said first voltage level is independent of a duty cycle (D) of said power train (810).

23. The method as recited in Claim 21 further comprising providing (1465) a trim voltage (Vtrim) via a trim resistive element (RL) of said buffer amplifier (840) coupled to said slew resistive element (Rsiew).

24. The method as recited in Claim 21 further comprising limiting (1450) said second voltage level at said circuit node (910) via a Zener diode (D_ref) of said auxiliary converter stage (150, 220, 800) parallel-coupled with said timing capacitive element (Ct).

25 The method as recited in Claim 21 further comprising preventing (1460) said reference voltage (VR) from being greater than said scaled voltage (Vin-div) with a diode (D3) coupled to an operational amplifier (850) of said buffer amplifier (840).

26. The method as recited in Claim 21 further comprising limiting (1435) said scaled voltage (Vin-div) with a Zener diode (Z) parallel-coupled to a first resistive element (Ri) of a resistor divider of said auxiliary converter stage (150, 220, 800).

27. The method as recited in Claim 21, further comprising:

isolating said scaled voltage (Vin-div) from said input voltage (Vin) with an isolation transformer (Tl) of said auxiliary converter stage (150, 220, 800) including a primary winding (Xi) and a secondary winding (X₂);

providing (1415) a secondary-side bias voltage (Vs) during a complementary duty cycle (1-D) with a first capacitive element (C_s) of said auxiliary converter stage (150, 220, 800) coupled in series with a first diode (Di) to said secondary winding (X2); and

providing (1420) a second secondary-side bias voltage (VF) during a duty cycle (D) with a second capacitive element (CF) of said auxiliary converter stage (150, 220, 800) coupled in series with a second diode (D2) to said secondary winding (X2), said first and second capacitive elements (Cs, CF) series-coupled to provide said scaled voltage (Vin-div) as a function of said secondary-side bias voltages (Vs, VF).

28. The method as recited in Claim 27 further comprising reducing (1425) a noise content of said second secondary-side bias voltage (VF) with a first resistive element (R3) series- coupled with said second diode (D2) of said power train (810).

29. The method as recited in Claim 27 further comprising controlling (1455) a ramp- up time of said reference voltage (VR) with a ramp resistive element (Rramp).

30. The method as recited in Claim 21 further comprising producing (1410) a primary-side bias voltage (Vp) with a first capacitive element (Cp) series-coupled with a primary winding (Xi) of an isolation transformer (Tl) of said power train (810).