WO2018006091A1

WO2018006091A1 - Soc supply droop compensation

Info

Publication number: WO2018006091A1
Application number: PCT/US2017/040597
Authority: WO
Inventors: Hassan Ihs
Original assignee: Endura Technologies LLC
Priority date: 2016-07-01
Filing date: 2017-07-03
Publication date: 2018-01-04
Also published as: CN109564440B; US10749513B2; CN109564440A; US10320375B2; US20180062628A1; EP3479185A1; US20190267977A1; EP3479185A4

Abstract

Droop monitors spread across a system-on-chip (SoC) monitor for voltage droops in regulated supply voltage supplied to logic circuitry of the SoC. In the event of a voltage droop, a clock signal supplied to the logic circuitry is stretched, to temporarily increase a period of the clock signal. The droop monitors may include a sensing delay line provided voltage at the regulated supply voltage, and a reference delay line supplied with a reference voltage, with operations of the delay lines monitored to determine a voltage droop.

Description

SOC SUPPLY DROOP COMPENSATION

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to supply of power to integrated circuits, and more particularly to detecting and/or compensating for power supply droops to integrated circuits.

[0002] Integrated circuits may be largely quiescent at times, drawing little power, while at other times may in whole or in part require large amounts of power. The changes in utilized power may present difficulties in providing stable power to the circuitry, and voltage supplied may decrease, or droop, when power regulation circuits are faced with rapid increases in power demands. These voltage droops may result in slower operation of integrated circuitry, and may result in combinatorial logic failures, particularly for system on chip (SoC) devices, in which voltage droops may not be uniform over the device.

[0003] FIGs. 10A and 10B illustrate a load current transient, in which load current rapidly increases, and a corresponding voltage droop. In the example of FIGs. 10A and 10B, timing failures for combinatorial logic may occur once the supply voltage decreases below 0.9 Volts, which is shown as occurring. In other words, temporary mismatch between load current and voltage regulator current delivery leads to power supply droop.

[0004] The effect of supply droops in SoC is to lead to failure in sampled combinational paths. Supply droops increase the delay in logic paths. Supply droops are mainly caused by fast SoC load current transients. BRIEF SUMMARY OF THE INVENTION

[0005] Prevention of logic failures comprises either or both preventing a supply voltage droop from taking place and/or allow more clock delay to logic to resolve failure-free. A way of detecting a supply droop is to mimic the mechanism of logic path failure with a delay line monitor tuned to fail earlier than the most critical path of a System-on-Chip (SoC) during a supply droop transient. A supply droop transient may be detected using a droop detector, for example the droop detector(s) discussed hereon. Clock stretching comprises, upon droop detection, temporarily stretching a clock period of a clock signal used by logic circuitry of the SoC to prevent critical paths failure. Stretching temporarily the clock period during a load transient, inherently reduces the load current (CVF) and thus reduces the droop amplitude. The benefits of clock stretching may be twofold. Clock pulse skipping is more aggressive in creating large voltage ripple and sever performance throttling. Clock stretching with finer timing resolution keeps voltage ripple and performance throttling under control.

[0006] In some embodiments, novel and inventive aspects include one, some, or all of:

[0007], A clock stretcher scheme to prevent logic failure in presence of supply voltage droop.

[0008] Distributed droop monitors across sensitive areas of an SoC die.

[0009] A wheel having a turning needle to stretch the SoC clock.

[0010] An analog implementation of a droop monitor using analog calibrated delay lines.

[0011] A digital implementation of a droop monitor using digitally calibrated delay lines.

[0012] Some embodiments provide a system for compensating for voltage droops in power supplied to integrated circuitry, comprising: a plurality of droop monitors within an integrated circuit, the droop monitors configured to detect occuiTence of a droop in voltage level below a specified level of a regulated supply voltage; and clock adjustment circuitry configured to stretch a period of a clock signal supplied to portions of the integrated circuit in response to detection of the occurrence of the droop in voltage level below the specified level.

[0013] Some embodiments provide a method for compensating for voltage droops in power supplied to integrated circuitry, comprising: Operating integrated circuitry of a system-on-chip (SoC) using a first clock signal at a first clock frequency, the integrated circuitry of the SoC including SoC logic circuitry, first integrated circuitry, and second integrated circuitry; monitoring speed of operation of first integrated circuitry supplied with a regulated supply voltage with respect to speed of operation of second integrated circuitry supplied with a first voltage level; and transitioning operation of the integrated circuitry of the SoC to use of a second clock signal of a plurality of clock signals, the plurality of clock signals including the first clock signal, each of the plurality of clock signals having a same frequency but having differing phases, with the transitioning of operation of the integrated circuitry of the SoC to use of the second clock signal resulting in stretching of a clock period of a clock signal provided to the integrated circuitry of the SoC.

[0014] These and other aspects of the invention are more fully comprehended upon review of this disclosure.

BRIEF DESCRIPTION OF THE FIGURES

[0015] FIG. 1 is a block diagram of a system in accordance with aspects of the invention.

[0016] FIG. 2 illustrates a timing diagram of example clock signals generated by the PLL of FIG. 1.

[0017] FIG. 3 illustrates a timing diagram showing example clock signals in accordance with aspects of the invention. [0018] FIG. 4 is a block diagram of a monitor block in accordance with aspects of the invention.

[0019] FIG. 5 illustrates an embodiment of an analog delay line, which may be used as the sensing delay line and the reference delay line of the embodiment of FIG. 4.

[0020] FIG. 6 is a block diagram of a further embodiment of a monitor block in accordance with aspects of the invention.

[0021] FIGs. 7 A and 7B illustrate an embodiment of digitally controlled delayed lines, for example for use in the monitor block of FIG. 6.

[0022] FIGs. 8A and 8B illustrate benefits of operation of a system such as the system of FIG. 1.

[0023] FIG. 9 is a flow diagram of logic operations which may be used to select a clock signal for use by logic circuitry.

[0024] FIGs. 10A and 10B illustrate a load current transient, in which load current rapidly increases, and a corresponding voltage droop.

[0025] FIG. 11 is a graph of delay time versus voltage.

DETAILED DESCRIPTION

[0026] Some embodiments in accordance with aspects of the invention include a plurality of droop monitors within an integrated circuit, the droop monitors configured to detect occurrence of a droop in voltage level below a specified level of a regulated supply voltage, and clock adjustment circuitry configured to stretch a period of a clock signal supplied to portions of the integrated circuit in response to detection of the occurrence of the droop in voltage level below the specified level. [0027] In some embodiments the droop monitors monitor a speed of execution of sensing integrated circuitry compared to speed of execution of reference integrated circuitry. In some embodiments the sensing integrated circuitry and the reference integrated circuitry each comprise a delay line. In some embodiments the reference integrated circuitry is provided power at a first voltage level and the sensing integrated circuitry is provided power at the regulated supply voltage level.

[0028] In some embodiments the clock adjustment circuitry selects a system clock signal at a particular phase from a plurality of clock signals each having different phases. In some embodiments the clock adjustment circuitry stretches the period of the system clock signal supplied to portions of the integrated circuit by selecting a next to be used clock signal that is phase delayed compared to a currently used clock signal.

[0029] FIG. 1 is a block diagram of a system in accordance with aspects of the invention. A clock tree 1 1 1 distributes a system clock signal generated by a PLL 1 12 to areas of an integrated circuit for clocking operations of circuitry of the integrated circuit. A power mesh 113 similarly distributes regulated power to the circuitry of the integrated circuit. The regulated power is provided by a voltage regulator (not shown). In some embodiments the voltage regulator is part of a chip of the integrated circuit, and may be considered an embedded voltage regulator, and in some embodiments the voltage regulator is provided in some other chip. In most embodiments the voltage regulator is a DC-DC switching converter.

[0030] A plurality of monitor blocks 1 15a-c receive power from the power mesh and the clock signal from the clock tree. The monitor blocks are generally distributed in different areas of the integrated circuit. The monitor blocks determine if the regulated power from the voltage regulator drops below a predefined level. In some embodiments the monitor blocks determine if the regulated power from the voltage regulator drops below the predefined level by comparing speed of operation of reference integrated circuitry with speed of operation of sensing integrated circuitry. In some embodiments the sensing integrated circuitry and the reference integrated circuitry each comprise a delay line. In some embodiments the sensing regulated circuitry is provided the regulated power from the voltage regulator and the reference integrated circuitry is provided power from a different power regulator. In some embodiments the power from a different power regulator is regulated to be at a voltage less than a nominally expected voltage from the voltage regulator, but also at a voltage greater than a voltage at which a failure of expected operation of combinatorial logic circuitry is expected to occur.

[0031] In operation, if any of the monitor blocks determine that the regulated power from the voltage regulator drops below the predefined level, indicative of a power droop, then the system clock signal for clocking operations of the circuitry of the integrated circuit is stretched. In most embodiments the clock signal is stretched by replacing a then currently selected clock signal with a clock signal at the same frequency, but phase shifted so as to transition at a slightly later time. In some embodiments, however, clock stretching may be performed by adjusting operation of a voltage controlled oscillator (VCO), for example by first slowing operation of the VCO to lengthen a clock period and then speeding operation of the VCO so as to return the frequency of the clock signal to the frequency prior to slowing of the VCO.

[0032] In the embodiment of FIG. 1 , each of the monitor blocks provides a signal indicating a power droop to an OR block 1 17. An output of the OR block is provided to a sync block 1 19, which provides a clock selection signal to a clock phase wheel 121. The clock phase wheel receives a plurality of clock signals at a same frequency, but differing in phase, from the PLL 1 12, and outputs a selected one of the clock signals as the system clock signal. In some embodiments the clock phase wheel is implemented using multiplexer circuitry, or circuitry providing for similar operations. In some embodiments the sync block additionally receives a leap size adjustment signal, which indicates to the sync block an amount to stretch the system clock signal.

[0033] FIG. 2 illustrates a timing diagram of example clock signals generated by the PLL of FIG. 1. FIG. 2 shows eight clock signals, each phase shifted with respect to each other, with the clock signals labeled from Clkp0-Clkp7.

[0034] FIG. 3 illustrates a timing diagram showing example clock signals in accordance with aspects of the invention. The clock signals, for example, may be clock signals of the embodiment of FIG. 1. The clock signals include a clock signal Clkp_n, which is an initially selected clock signal, a clock signal Clkp_n+i, which is a subsequently selected clock signal, a clock signal Clksoc, which is a clock signal for use by logic circuitry of an integrated circuit (at a point of initial distribution of the clock signal), and a clock signal Clkieaf, which is the clock signal Clksoc after passage through a clock tree (and where actually utilized by the logic circuitry).

[0035] The clock signal Clkp_n and Clkp_n+i both have the same frequency, but differ in phase, and both clock signals may be generated by a PLL. At a time tl it may be seen that the clock signal Clksoc and the clock signal Clkp_n both transition from a low to high state, indicating that the clock signal Clkp_n is currently selected as the clock signal for use by the logic circuitry. At a time t2, subsequent to time tl , it may be seen that the clock signal Clkieaf transitions from a low to high state, with the time t2-tl indicating a propagation delay as the clock signal Clksoc travels through the clock tree.

[0036] At a time t3 the clock signal Clkp_n once again transitions from a low to high state. The clock signal Clksoc, however, does not transition from a low to high state at time t3, indicating that the clock signal Clkpn is no longer selected for use by the logic circuitry. Instead, for example due to a monitor block indicating detection of a voltage droop, the clock signal Clkpn+1 has been selected for use by the logic circuitry. This may be seen with the clock signal Clksoc transitioning from a low to high state concurrently with the clock signal Clkp_n+i at a time subsequent to time t3, indicating that the clock signal Clkp_n+i has been selected for use by the logic circuitry. Effectively, therefore, a clock period of the clock signal Clksoc has been stretched, or extended in time.

[0037] At a time t4 the clock signal Clkieaf would transition from a low state to a high state, if Clkp_n were still the selected clock signal. Due to the detected voltage droop, a logic failure would have been expected at that time. However, as Clksoc has transitioned to the clock signal Clkpn+i , the rising edge of Clkieaf has been delayed to time t5, providing sufficient time for the logic operations of the logic circuitry to complete.

[0038] With respect to FIGs. 1-3, in various embodiments:

[0039] n clock phases are obtained from VCO cells. They are available at no cost as traditional VCOs align more than 8 cells.

[0040] The phases are placed in a fixed wheel, and only one phase is selected as the SOC clock by a turning needle.

[0041] Several monitors distributed through the SoC sense the supply droop about to create a timing failure.

[0042] Any of these alarms moves clockwise forward the wheel pointer by a predefined step.

[0043] Depending on the severity of the droops, it might be decided using logic means, for example logic circuitry, to move the pointer 1, 2, or as needed or desired steps to prevent timing failure. [0044] The monitors are translate power droop into delay that is compared to a predefined delay reference.

[0045] Fine granularity of clock phase may put performance throttling under control.

[0046] FIG. 4 is a block diagram of an example monitor block in accordance with aspects of the invention. In some embodiments the monitor block of FIG. 4, or portions thereof, is used as the monitor block of FIG. 1. The monitor block effectively compares a delay of a sensing delay line 41 1 with a delay of a reference delay line 413 to determine if a regulated supply voltage droop has occurred. In various embodiments, and as shown in FIG. 4, the monitor block additionally includes circuitry to effectively set a delay length for the sensing delay line, circuitry to match the delay of the reference delay line to that of the sensing delay line, and circuitry to provide a predefined or definable set voltage to supply the reference delay line. In some embodiments the additionally included circuitry is included in whole, as shown in FIG. 4, or in part, or not at all.

[0047] The sensing delay line 41 1 and the reference delay line each receive a clock signal CLKsoc The clock signal CLKsoc may be for example, the Clksoc signal or the Clkieaf signal of FIG. 3. The delay lines provide delayed versions of the signal to comparison circuitry, which in the embodiment of FIG. 4 is a latch 415. The latch sets it output to the value of the output of the reference delay line on rising edges of the output of the sensing delay line. The delay of the reference delay line set so as to be greater than the delay of the sensing delay line under nominal regulated voltage supply conditions, with the reverse true if the regulated voltage supply level drops below a voltage expected to result in combinatorial logic failures. Accordingly, the output of the latch will be zero until the regulated voltage supply level drops below the voltage expected to result in combinatorial logic failures, and the output of the latch may be considered to be a voltage droop alarm signal.

[0048] In the embodiment of FIG. 4, the sensing delay line receives power from the regulated voltage supply, which for example may be a DC-DC switching converter (not shown). The reference delay line receives power from reference power supply circuitry 416. The reference power supply circuitry supplies power at a voltage at, about, or a safety margin above a voltage level at which combinatorial logic failures would be expected. In the embodiment of FIG. 4, the reference power supply circuitry comprises a low dropout (LDO) regulator 417. The LDO regulator receives power from a power supply source other than the regulated voltage supply, and in many embodiments the LDO regulator receives power from the same power source providing power to the DC-DC switching converter providing the regulated voltage supply. Also in the embodiment of FIG. 4, the LDO regulator sets its output voltage at a level determined by a digital-to-analog converter (DAC) 419, allowing for system setting of a desired output voltage.

[0049] The embodiment of FIG. 4 additionally includes a lock loop to set a delay of the sensing delay line to a predetermined delay, in the case of FIG. 4 a delay that covers a clock cycle, and a tuning loop to tune a delay of the reference delay line to that of the sensing delay line, under the same supply voltage conditions. In the embodiment of FIG. 4, both the lock loop and the tuning loop are operational during a calibration mode, and non-operational during an operational mode in which the monitor block monitors for a voltage droop.

[0050] The lock loop includes a phase and frequency detector (PFD) 423 which operates on the output of the sensing delay line and the clock signal CLKSOC. The PFD provides up/down signals to a first charge pump 431, the output of which, in calibration mode, charges a lock capacitor 433 with a voltage Vlock. The voltage Vlock is used to modify speed of operation of the sensing delay line, with the voltage Vlock varying during calibration until the output of the sensing delay line is phase and frequency locked to the clock signal CLKSOC.

[0051] The tuning loop utilizes the alarm signal to operate a second charge pump 441, the output of which, in calibration mode, charges a tuning capacitor 443 with a voltage Vtune. The voltage Vtune is used to modify speed of operation of the reference delay line. When delay of the reference delay line does not approximate delay of the sensing delay line, the alarm signal will generally either be high or be low, depending on the offset between the two delay lines. Once the delays are closing to matching, with the relative delays effectively slightly toggling in comparative length with respect to each other, the alarm signal will also generally toggle between a high and low state, indicating the delay lines substantially match.

[0052] In summary, operation of the monitor block of FIG. 4 may be as indicated in Table I:

[0053]

Reference delay line locks on the The chain of delay elements detects the sensing delay line to provide matching, effect of supply variation on timings.

in some embodiments near perfect,

between the two delay lines

Lock is obtained when Alarm is

toggling

Table I

[0054] FIG. 5 illustrates an embodiment of an analog delay line, which may be used as the sensing delay line and the reference delay line of the embodiment of FIG. 4. The analog delay line includes a series of inverters 51 la-n, with capacitors 513a-n coupled to ground between the inverters (and after the ultimate inverter in the series of inverters). In the embodiment of FIG. 5, the capacitors are variable capacitors, with a capacitance set by Vtune, for the reference delay line, or Vlock, for the sensing delay line. Adjustment of the capacitance of the variable capacitors adjusts speed of operation of the delay line. [0055] In various embodiments: [0056] As the delay line is used to sense supply variations and convert it to delay, the tuning is preferably performed on the capacitor (PSRR=1).

[0057] Current starving inverters have a high PSRR and may not be as suitable to supply monitoring.

[0058] Delay versus supply is decently linear within useful range, as may be seen in FIG. 11, which graphs delay time versus voltage.

[0059] As failure mechanism is related to delay in critical paths, the delay line senses the effect of a supply voltage droop.

[0060] FIG. 6 is a block diagram of a further embodiment of a monitor block in accordance with aspects of the invention. In some embodiments the monitor block of FIG. 6 is used for the monitor block of FIG. 1. [0061] The monitor block of FIG. 6 is similar to the monitor block of FIG. 4, with the monitor block of FIG. 6 including a sensing delay line 611 , a reference delay line 613, a latch 615, reference power supply circuitry 616 comprised of an LDO 617 setting an output voltage in accordance with output of a DAC 619, and a PFD 623, with all arranged as discussed with respect to the embodiment of FIG. 4. The embodiment of FIG. 6 also includes a lock loop and a tuning loop.

[0062] In the embodiment of FIG. 6, however, the delay lines, lock loop, and tuning loop are implemented with digital components. The lock loop includes a first up/down counter 631 in place of a charge pump, with an output of the first up/down counter provided, in calibration mode, to a first thermocoder 635. The first thermocoder provides a multibit output to the sensing delay line, for adjusting a delay of the sensing delay line. Similarly, the tuning loop includes a second up/down counter 641 , in place of a charge pump, with an output of the second up/down counter provided, in calibration mode, to a second thermocoder 645. The second thermocoder provides a multibit output to the reference delay line, for adjusting a delay of the reference delay line.

[0063] In summary, for the embodiment of FIG. 6:

[0064] Fully digital concept

[0065] Digital charge pump, integrator, up down counter

[0066] Delay line implemented in switchable logic gates or tristate logic gates

[0067] Suitable to FPGA implementation for concept validation

[0068] FIGs. 7A and 7B illustrate an embodiment of digitally controlled delayed lines, for example for use in the monitor block of FIG. 6. The embodiment of FIG. 7A utilizes a series of switchable logic gates 711a-n, controlled by control signals from the first and second thermocoders, for the sensing delay line and the reference delay line, respectively. The embodiment of FIG. 7B utilizes a series of tristate logic gates, again controlled by control signals from the first and second thermocoders, for the sensing delay line and the reference delay line, respectively.

[0069] FIGs. 8A and 8B illustrate possible benefits of operation of a system such as the system of FIG. 1. FIG. 8 A is a graph showing regular operation of a clock signal over a time period, regulated supply voltage Vddsoc over the same time period, and current load lload again over the same time period. During operation, Vddsoc experiences a voltage droop, shown as well below 0.9 Volts, at a time when lload increases substantially, indicating increased current draw by circuitry of an SoC. By comparison, FIG. 8B, showing operation of an integrated circuit including a system such as the system of FIG. 1, illustrates clock stretching of the clock signal, with a reduced voltage droop and less rapid increase in lload.

[0070] In summary:

[0071] Droop effect is compensated twofold.

[0072] Clock stretching prevents critical logic paths from failing.

[0073] Clock stretching temporally reduces switching frequency that translates into load current reduction.

[0074] FIG. 9 is a flow diagram of logic operations which may be used to select a clock signal for use by logic circuitry. In some embodiments the logic operations of FIG. 9 are implemented by the sync circuitry of FIG. 1. In block 91 1 a clock with a first clock phase, for example Clkpo of the clock phases of FIG. 2, is selected for use as a system clock signal. If an alarm signal, for example from a monitor block, goes high, a next clock signal, with delayed phase, is selected for use as the system clock signal. This effectively stretches a period of the system clock signal. If the alarm signal again goes high or, in some embodiments remains high over a predefined time period, a further next clock signal, Clkpo+i, i a non-zero integer, is selected for use as the system clock signal, again effectively stretching a period of the system clock signal.

[0075] Although the invention has been discussed with respect to various embodiments, it should be recognized that the invention comprises the novel and non-obvious claims supported by this disclosure.

Claims

What is claimed is:

1. A system for compensating for voltage droops in power supplied to integrated circuitry, comprising: a plurality of droop monitors within an integrated circuit, the droop monitors configured to detect occurrence of a droop in voltage level below a specified level of a regulated supply voltage; and clock adjustment circuitry configured to stretch a period of a clock signal supplied to portions of the integrated circuit in response to detection of the occurrence of the droop in voltage level below the specified level.

2. The system of claim 1 , wherein the droop monitors are configured to monitor a speed of execution of sensing integrated circuitry compared to speed of execution of reference integrated circuitry.

3. The system of claim 2, wherein the sensing integrated circuitry comprises a sensing delay line and the reference integrated circuitry comprises a reference delay line.

4. The system of claim 3 wherein the sensing delay line and the reference delay line each include a series of inverters with variable capacitors coupled to ground between inverters in the series of inverters.

5. The system of claim 3, wherein the sensing delay line and the reference delay line each comprise a digital delay line.

6. The system of claim 3, wherein the droop monitors include a lock loop to set a delay of the sensing delay line to a predetermined delay.

7. The system of claim 6, wherein the predetermined delay covers a clock cycle of a system clock signal.

8. The system of claim 3, wherein the droop monitors include a tuning loop to tune a delay of the reference delay line to a delay of the sensing delay line.

9. The system of claim 2, further comprising a low dropoff regulator to provide power to the reference integrated circuitry at a first voltage level and a DC-DC switching regulator to provide power to the sensing integrated circuitry is provided power at a regulated supply voltage level.

10. The system of claim 1, wherein the clock adjustment circuitry is configured to select a system clock signal at a particular phase from a plurality of clock signals each having different phases.

1 1. The system of claim 10, wherein the clock adjustment circuitry is configured to stretch a period of the system clock signal supplied to portions of the integrated circuit by selecting a next to be used clock signal that is phase delayed compared to a currently used clock signal.

12. A method for compensating for voltage droops in power supplied to integrated circuitry, comprising: operating integrated circuitry of a system-on-chip (SoC) using a first clock signal at a first clock frequency, the integrated circuitry of the SoC including SoC logic circuitry, first integrated circuitry, and second integrated circuitry; monitoring speed of operation of first integrated circuitry supplied with a regulated supply voltage with respect to speed of operation of second integrated circuitry supplied with a first voltage level; and transitioning operation of the integrated circuitry of the SoC to use of a second clock signal of a plurality of clock signals, the plurality of clock signals including the first clock signal, each of the plurality of clock signals having a same frequency but having differing phases, with the transitioning of operation of the integrated circuitry of the SoC to use of the second clock signal resulting in stretching of a clock period of a clock signal provided to the integrated circuitry of the SoC.

13. The method of claim 12, wherein the first integrated circuitry includes a sensing delay line and the second integrated circuitry includes a reference delay line.

14. The method of claim 13, further comprising calibrating the sensing delay line and the reference delay line, the calibrating including supplying the sensing delay line with the first voltage level instead of the regulated supply voltage.

15. The method of claim 12, wherein the first voltage level is provided by a low dropoff regulator and the regulated supply voltage is provided by a DC-DC switching converter.

16. The method of claim 15, wherein the first voltage level is a voltage at a safety margin above a voltage level at which combinatorial logic failures of the SoC logic circuitry would be expected.

17. The method of claim 15, wherein the first voltage level is a voltage at which

combinatorial logic failures of the SoC logic circuitry would be expected.