WO2017217248A1

WO2017217248A1 - Power converter unit

Info

Publication number: WO2017217248A1
Application number: PCT/JP2017/020540
Authority: WO
Inventors: 和則津田
Original assignee: 株式会社村田製作所
Priority date: 2016-06-13
Filing date: 2017-06-02
Publication date: 2017-12-21
Also published as: CN209267450U

Abstract

A power converter unit (1) is provided with a capacitive power converter (10) and an inductive power converter (20) that are connected in a cascade arrangement, and a charging circuit (30). The capacitive power converter (10) comprises a plurality of capacitors (C11, C12, C13) connected in parallel to a terminal (101) to which a DC voltage is input, and a plurality of switch elements (S11-S17). The capacitive converter (10) steps the voltage up or down by switching the state of the switch elements (S11-S17) to charge or discharge the capacitors (C11, C12, C13). The charging circuit (30) comprises a switch element (S31) that connects or cuts off the capacitive power converter (10) and a constant current source (31) for supplying a constant current to the capacitive power converter (10).

Description

Power converter unit

The present invention relates to a power converter unit in which two power conversion units are connected in cascade.

Generally, the power supply capability of a capacitive power converter such as a switched capacitor (also referred to as a charge pump circuit) depends on the product of the drive frequency, the capacitance of the capacitor, and the voltage applied to the capacitor. When there is a demand exceeding the supply capacity, the output of the capacitive power converter decreases. This decrease is mainly caused by capacitor overdischarge. In such a state, an inrush current corresponding to the voltage drop occurs at the start of the charging period for the capacitor. This inrush current causes noise and has an adverse effect such as destruction of the element.

Patent Document 1 discloses a capacitive power converter including a precharge circuit for preventing an inrush current to a capacitor. The precharge circuit described in Patent Literature 1 includes a switch element connected to each capacitor and a resistor. Then, by turning on the switch element, an inrush current to the capacitor is prevented.

US Pat. No. 8,503,203

In the precharge circuit described in Patent Document 1, the capacitor charging time is determined by the size of the resistor. For this reason, if the resistance value is increased in order to prevent an inrush current when the power supply voltage is high, it takes time to precharge the capacitor. On the other hand, if the resistance value is reduced to shorten the precharge time, inrush current cannot be prevented when the power supply voltage is high.

Therefore, an object of the present invention is to provide a safe power converter unit that can prevent an inrush current without taking time.

A power converter unit according to the present invention includes an input unit to which a DC voltage is input, an output unit to which a DC voltage is output, a plurality of capacitors connected in parallel to the input unit, and a plurality of capacitive switching elements And a capacitive side control unit that controls the switching of the plurality of capacitive side switch elements, and changes the state of the plurality of capacitive side switch elements to charge and discharge the plurality of capacitors to increase and decrease the voltage. A capacitive power converter that compresses, and is connected to the input unit or the output unit, and includes an inductor, an inductive side switch element, and an inductive side control unit that performs switching control of the inductive side switch element. An inductive power converter that switches the state of the inductive side switch element and discharges energy to the inductor, and a constant current source. The supplies a constant current from the constant current source to the connection point of said plurality of capacitors, or, characterized in that it comprises a charging circuit for interrupting the supply.

In this configuration, inrush current to the capacitor can be prevented by charging the capacitor of the capacitive power converter with a constant current by the charging circuit. At this time, since a constant current is supplied to a plurality of capacitors connected in parallel, it is possible to charge each capacitor in a lump, and charging does not take time.

The power converter unit includes a voltage detection unit that detects a charging voltage to any of the plurality of capacitors, and an abnormality determination unit that compares the detection value detected by the voltage detection unit with a target value to determine an abnormality. And may be provided.

In this configuration, it is possible to determine an abnormality of the capacitive power converter such as an abnormality of the capacitor or an abnormality of the switch element by comparing the charging voltage of the capacitor with the target value.

The abnormality determination unit may operate within a predetermined time after the capacitive power converter is activated.

In this configuration, it is possible to suppress the possibility of causing further problems by continuing to drive the power converter unit in the presence of an abnormality by determining the presence or absence of the abnormality immediately after the power converter unit is started.

The power converter unit may include a power conversion limiting unit that limits power conversion by the capacitive power converter when the abnormality determination unit determines that an abnormality has occurred.

In this configuration, the drive of the power converter unit can be stopped when there is an abnormality.

According to the present invention, inrush current to the capacitor can be prevented by charging the capacitor of the capacitive power converter with a constant current by the charging circuit. At this time, since a constant current is supplied to a plurality of capacitors connected in parallel, it is possible to charge each capacitor in a lump, and charging does not take time.

FIG. 1 is a block diagram of a power converter unit according to the first embodiment. FIG. 2 is a circuit diagram of the power converter unit according to the first embodiment. FIGS. 3A and 3B are diagrams for explaining switching control in the capacitive power converter. FIG. 4 is a diagram for explaining the operation at the time of precharging by the charging circuit. FIG. 5 is a circuit diagram of the charging circuit. FIG. 6 is a diagram illustrating the output of each element of the failure determination circuit when the capacitive power converter is normal. FIG. 7 is a diagram illustrating the output of each element of the failure determination circuit when the capacitive power converter is abnormal. FIG. 8 is a circuit diagram of another example of the charging circuit. FIG. 9 is a block diagram of a failure determination unit that performs abnormality determination of the capacitive power converter. FIG. 10 is a circuit diagram of the capacitive power converter according to the second embodiment. FIG. 11 is a diagram for explaining the operation at the time of precharging by the charging circuit.

FIG. 1 is a block diagram of a power converter unit 1 according to this embodiment.

The power converter unit 1 includes an input unit including a pair of terminals In1 and In2, and an output unit including a terminal Out1 and a terminal Out2. A DC power supply is connected to the terminals In1 and In2. A load is connected to the terminal Out1 and the terminal Out2. The power converter unit 1 steps down a DC voltage V1 (hereinafter referred to as an input voltage V1) input from the terminal In1 and the terminal In2 to a voltage V3 (hereinafter referred to as an output voltage V3), and outputs the voltage from the terminal Out1 and the terminal Out2. .

The power converter unit 1 includes a capacitive power converter 10, an inductive power converter 20, a charging circuit 30, a failure determination circuit 40, and a control circuit 50. The capacitive power converter 10 and the inductive power converter 20 are cascade-connected between the terminal In1 and the terminal In2 and the terminal Out1 and the terminal Out2 so that the capacitive power converter 10 is on the input side. .

Capacitive power converter 10 steps down input voltage V1 to voltage V2 (hereinafter referred to as intermediate voltage V2). The capacitive power converter 10 is a switched capacitor, for example, and steps down the input voltage V1 by switching the switch element to charge and discharge the capacitor.

The inductive power converter 20 receives the intermediate voltage V2 and steps down the intermediate voltage V2 to the output voltage V3. The output voltage V3 is supplied to a load connected to the terminal Out1 and the terminal Out2.

The charging circuit 30 has a constant current source. The charging circuit 30 charges the capacitor of the capacitive power converter 10 immediately after the power converter unit 1 is started and before the step-down operation by the capacitive power converter 10 and the inductive power converter 20 is performed. Hereinafter, this charging is referred to as “pre-charging”. Immediately after the power converter unit 1 is started, the capacitor of the capacitive power converter 10 is not charged. In this state, when a capacitor is charged from a DC power source connected to the terminal In1 and the terminal In2, an inrush current flows through each capacitor, and each capacitor or switch element may be damaged.

Therefore, immediately after the power converter unit 1 is started, the charging circuit 30 interrupts the current flowing from the DC power source connected to the terminal In1 and the terminal In2 to the capacitive power converter 10. Then, the charging circuit 30 supplies a constant current to the capacitive power converter 10 from a constant current source that the charging circuit 30 has. When the capacitor is charged with a constant current, the charging voltage of the capacitor increases in proportion to the charging time. For this reason, immediately after the power converter unit 1 is activated, the charging circuit 30 charges the capacitor with a constant current, thereby preventing an inrush current from flowing into the capacitor of the capacitive power converter 10. As a result, failure of the capacitor can be prevented.

The failure determination circuit 40 determines whether or not the capacitive power converter 10 has failed. Failure determination circuit 40 detects the charging voltage of the capacitor of capacitive power converter 10 during the period of precharging by charging circuit 30 or after the end of precharging. Then, the failure determination circuit 40 compares the detected charging voltage with the target value to determine whether there is a failure.

Note that the failure of the capacitive power converter 10 includes short-circuit breakdown or open breakdown of the capacitor, excess or insufficient capacity, formation of an unexpected current path, and the like.

The control circuit 50 detects the input voltage V1, the intermediate voltage V2, and the output voltage V3. The control circuit 50 compares the intermediate voltage V2 and the output voltage V3 with each target voltage value, and outputs a command signal to the capacitive power converter 10 and the inductive power converter 20 according to the comparison result. The capacitive power converter 10 and the inductive power converter 20 change the driving frequency, for example, according to the command signal. The control circuit 50 stops driving the power converter unit when the failure determination circuit 40 determines that there is an abnormality. The control circuit 50 is an example of the “power conversion limiting unit” according to the present invention.

FIG. 2 is a circuit diagram of the power converter unit 1 according to the present embodiment. 2, illustration of the control circuit 50 shown in FIG. 1 is omitted.

The capacitive power converter 10 has an input unit composed of a terminal 101 and a terminal 102 and an output unit composed of a terminal 103 and a terminal 104. Terminal 101 is connected to terminal In1. Terminal 102 is connected to terminal In2. The terminal 103 is connected to a terminal 201 of the inductive power converter 20 described later. The terminal 104 is connected to a terminal 202 of the inductive power converter 20 described later.

The capacitive power converter 10 includes a switch element S11, a switch element S12, a switch element S13, a switch element S14, a switch element S15, a switch element S16, a switch element S17, a capacitor C11, and a capacitor C12. And a capacitor C13 and a switching control circuit 111. The switching control circuit 111 performs switching control of the switch elements S11 to S17.

The switching control circuit 111 is an example of the “capacitive side control unit” according to the present invention. The switch elements S11 to S17 are examples of the “capacitive side switch element” according to the present invention.

The switch element S11 and the switch element S12 are connected in series between the terminal 101 and the terminal 103. A capacitor C11 and a switch element S14 are sequentially connected in series to a connection point between the switch element S11 and the switch element S12. The terminal 103 is connected in series with a switch element S16, a capacitor C12, and a switch element S15. A switch element S13 is connected between a connection point between the capacitor C11 and the switch element S14 and a connection point between the switch element S16 and the capacitor C12. Further, the switch element S17 is connected between the connection point between the capacitor C12 and the switch element S15 and the terminal 103. The capacitor C13 is connected between the terminal 103 and the terminal 104. Capacitor C11, capacitor C12, and capacitor C13 each have the same capacitance.

Hereinafter, the step-down operation in the capacitive power converter 10 will be described.

FIGS. 3A and 3B are diagrams for explaining switching control in the capacitive power converter 10. 3A and 3B, the charging circuit 30 is not shown. In this example, consider the case where the capacitive power converter 10 steps down the input voltage V1 of 3.0V to the intermediate voltage V2 of 1.0V.

In the first state, the switching control circuit 111 (see FIG. 2) turns on the switch element S11, the switch element S13, and the switch element S17 as shown in FIG. The element S14, the switch element S15, and the switch element S16 are turned off. In this case, as shown by an arrow in FIG. 3A, the terminal 101 is connected to a series circuit of a capacitor C11, a capacitor C12, and a capacitor C13. In this case, since the input voltage V1 is 3.0V, the capacitor C11, the capacitor C12, and the capacitor C13 are each charged with a voltage of 1.0V.

Next, in the second state, the switching control circuit 111 turns off the switch element S11, the switch element S13, and the switch element S17 as shown in FIG. 3B, and switches the switch element S12 and the switch element S14. Then, the switch element S15 and the switch element S16 are turned on. In this case, as shown in FIG. 3B, the terminal 103 has a configuration in which a capacitor C11, a capacitor C12, and a capacitor C13 are connected in parallel. In this case, since the capacitor C11, the capacitor C12, and the capacitor C13 are each charged with a voltage of 1.0 V, an intermediate voltage V2 of 1.0 V is output from the terminal 103 and the terminal 104.

Thus, in the capacitive power converter 10, the input voltage V1 is stepped down to the intermediate voltage V2 by alternately switching between the first state of FIG. 3A and the second state of FIG. 3B. The

Returning to FIG. 2, the inductive power converter 20 includes an input unit including a terminal 201 and a terminal 202 and an output unit including a terminal 203 and a terminal 204. Terminal 201 is connected to terminal 103 of capacitive power converter 10. Terminal 202 is connected to terminal 104 of capacitive power converter 10. The terminal 203 is connected to the terminal Out1. Terminal 204 is connected to terminal Out2.

The inductive power converter 20 is a step-down converter. Inductive power converter 20 includes switch element Q11, switch element Q12, inductor L1, capacitor C2, and driver 21. The switch element Q11 is a p-type MOS-FET. The switch element Q12 is an n-type MOS-FET. The driver 21 performs switching control of the switch element Q11 and the switch element Q12. Inductive power converter 20 turns on and off switch element Q11 and switch element Q12 to step down intermediate voltage V2 to output voltage V3.

The switch element Q11 and the switch element Q12 are examples of the “inductive side switch element” according to the present invention. The driver 21 is an example of the “inductive side control unit” according to the present invention.

Thus, the power converter unit 1 steps down the input voltage V1 to the intermediate voltage V2 by the capacitive power converter 10. Then, the inductive power converter 20 further reduces the intermediate voltage V2 to the output voltage V3. That is, the power converter unit 1 steps down the voltage in two stages. Compared with the case where the input voltage V1 is stepped down to the output voltage V3 with only one power conversion unit, for example, the inductive power converter 20, the input / output at the capacitive power converter 10 and the inductive power converter 20 respectively. The voltage difference is small. For this reason, the power conversion loss in the power converter unit 1 can be reduced.

The charging circuit 30 includes a constant current source 31 and a switch element S31. The constant current source 31 and the switch element S31 are connected in series. This series circuit is connected between the terminal In1 and a connection point between the switch element S11 and the capacitor C11. The charging circuit 30 turns on the switch element S31 when starting up the power converter unit 1 and supplies a constant current to the capacitive power converter 10. Capacitor C11, capacitor C12, and capacitor C13 of capacitive power converter 10 are charged by this constant current.

FIG. 4 is a diagram for explaining the operation at the time of precharging by the charging circuit 30.

When performing precharging, the charging circuit 30 turns on the switch element S31. The switching control circuit 111 (see FIG. 2) of the capacitive power converter 10 turns on the switch element S12, the switch element S14, the switch element S15, and the switch element S16, and switches the switch element S11 and the switch element. S13 and the switch element S17 are turned off. Accordingly, the capacitor C11, the capacitor C12, and the capacitor C13 are configured to be connected in parallel to the charging circuit 30. That is, since a constant current is supplied from the charging circuit 30 to a connection point between the capacitor C11, the capacitor C12, and the capacitor C13 that are connected in parallel, the constant current is supplied to the capacitor C11, the capacitor C12, and the capacitor C13. Supplied at the same time.

The charging circuit 30 stops charging with a constant current when each of the capacitor C11, the capacitor C12, and the capacitor C13 is charged to a reference voltage that is a target value. The capacitances of the capacitor C11, the capacitor C12, and the capacitor C13 are the same. Therefore, the same voltage is charged in each of the capacitor C11, the capacitor C12, and the capacitor C13.

FIG. 5 is a circuit diagram of the charging circuit 30. FIG. 5 shows a simplified state of the capacitive power converter 10 at the time of precharging. That is, the capacitive power converter 10 turns on the switch element S12, the switch element S14, the switch element S15, and the switch element S16, and turns off the switch element S11, the switch element S13, and the switch element S17. It is in the state.

The charging circuit 30 includes a constant current source (constant current circuit) 31, a switch element S31, a switch element S32, a switch element S33, a comparator 32, and a reference voltage power supply 33. The series circuit of the constant current source 31 and the switch element S32 and the switch element S33 are connected in parallel to form a current mirror circuit and connected to the terminal In1. The switch element S31 is connected in series to the switch element S33. The switch element S31 is an n-type MOS-FET, and the output of the comparator 32 is input to the gate and turned on / off.

The comparator 32 receives and compares the detection result of the charging voltage of the capacitor C11, the capacitor C12, and the capacitor C13 and the reference voltage from the reference voltage power source 33. Note that the charging voltages of the capacitor C11, the capacitor C12, and the capacitor C13 are the same. Therefore, by providing a voltage dividing circuit in parallel with the capacitor C13, the charging voltages of the capacitor C11, the capacitor C12, and the capacitor C13 can be detected. In the following description, it is expressed that the detection result of the charging voltage of the capacitor C13 is input to the comparator 32.

The comparator 32 outputs an H level signal when the charging voltage of the capacitor C13 is lower than the reference voltage, and outputs an L level signal when the charging voltage of the capacitor C13 is higher than the reference voltage. That is, when the charging voltage of the capacitor C13 is lower than the reference voltage, the switch element S31 is turned on. Thereby, a constant current is supplied to the capacitor C11, the capacitor C12, and the capacitor C13, and precharging is started. When the charging voltage of the capacitor C13 becomes higher than the reference voltage, the switch element S31 is turned off. As a result, the supply of constant current to the capacitor C11, the capacitor C12, and the capacitor C13 is cut off, and the precharge ends.

Thus, for precharging, the capacitors C11, C12, and C13 are connected in parallel, and a constant current is supplied, so that it is possible to charge the capacitors all at once. For this reason, time is not required for charge. In addition, when the capacitor C11, the capacitor C12, and the capacitor C13 are connected in series and precharged, if a short circuit failure occurs in one capacitor, the voltage applied to the other capacitor increases, and the other capacitor also fails. There is a risk. For this reason, the voltage applied to each capacitor can be suppressed by connecting the capacitor C11, the capacitor C12, and the capacitor C13 in parallel. Further, when normal, the output voltage of the capacitive power converter 10 is the same as the charging voltage of each capacitor. Therefore, it is not necessary to provide a plurality of charging voltage detection circuits, and space can be saved.

The failure determination circuit 40 determines the failure of the capacitive power converter 10 by comparing the output voltage of the capacitive power converter 10 with a target value after the charging circuit 30 starts precharging. As described above, at the time of precharging, the capacitor C11, the capacitor C12, and the capacitor C13 are connected in parallel, and the respective capacitances are the same (may be different capacitances). That is, if the capacitive power converter 10 is normal, the output voltage of the capacitive power converter 10 is the same as the charging voltages of the capacitor C11, the capacitor C12, and the capacitor C13. Therefore, by detecting the output voltage of the capacitive power converter 10, an abnormality of the entire capacitive power converter 10 such as an abnormality of a plurality of capacitors or an abnormality of a plurality of switch elements can be determined.

The constant current supplied from the charging circuit 30 is known. The capacitances of the capacitor C11, the capacitor C12, and the capacitor C13 of the capacitive power converter 10 are also known because they are design values or recommended values. Since the charging voltage of the capacitor increases in proportion to the charging time, the time until the target voltage is charged in the capacitor can be calculated in advance. The failure determination circuit 40 determines the presence / absence of an abnormality based on whether the output voltage of the capacitive power converter 10 after the elapse of the calculated time from the start of precharge is within the range including the target value and its error. To do.

In the following, the determination range is a range of the reference voltage REFL or more and the reference voltage REFH or less. Further, the output voltage of the capacitive power converter 10 at the time of precharging is represented by VM. The output voltage VM can be detected by providing a voltage dividing circuit of resistors R11 and R12 on the output side of the capacitive power converter 10. The voltage dividing circuit of the resistor R11 and the resistor R12 is an example of the “voltage detection unit” according to the present invention.

The failure determination circuit 40 includes a comparator 41, a comparator 42, an AND gate 43, a NOT circuit 44, and an AND gate 45. The failure determination circuit 40 is an example of the “abnormality determination unit” according to the present invention.

The detection voltage VMd of the output voltage VM of the capacitive power converter 10 is input to the inverting input of the comparator 41. A reference voltage REFH is input to the non-inverting input of the comparator 41. The detection voltage VMd of the output voltage VM of the capacitive power converter 10 is input to the non-inverting input of the comparator 42. The reference voltage REFL (<reference voltage REFH) is input to the inverting input of the comparator 42.

The AND gate 43 receives an output signal DETH from the comparator 41 and an output signal DETL from the comparator 42. The NOT circuit 44 inverts the output signal DET of the AND gate 43.

The AND gate 45 receives the output signal DETX from the NOT circuit 44 and the clock counter CTR. The clock counter CTR is a signal output from the counter 46. The counter 46 counts the clock signal from the beginning of the precharge, and outputs an H level signal for a time corresponding to one clock when a predetermined time has elapsed. The AND gate 45 outputs an H level signal when the capacitive power converter 10 has an abnormality. The AND gate 45 outputs an L level signal when there is no abnormality in the capacitive power converter 10.

The position where the failure determination circuit 40 is connected can be changed as appropriate. For example, the failure determination circuit 40 may be connected to a connection point between the capacitor C11 and the switch element S12, a connection point between the capacitor C12 and the switch element S16, or the like.

FIG. 6 is a diagram showing the output of each element of the failure determination circuit 40 when the capacitive power converter 10 is normal.

As described above, when a constant current is supplied to the capacitor, the charging voltage of the capacitor increases in proportion to the charging time. Therefore, the output voltage VM of the capacitive power converter 10 also increases in proportion to time. In this example, the output voltage VM becomes the reference voltage REFL when the time T1 has elapsed since the start of precharge, and becomes the reference voltage REFH when the time T2 has elapsed.

The output voltage VM is lower than the reference voltage REFL and the reference voltage REFH until the time T1 elapses after the precharge is started. In this case, the output signal DETH of the comparator 41 becomes H level, and the output signal DETL of the comparator 42 becomes L level.

The output voltage VM is higher than the reference voltage REFL and lower than the reference voltage REFH until the time T2 elapses after the elapse of time T1 from the start of precharge. In this case, the output signal DETH of the comparator 41 becomes H level, and the output signal DETL of the comparator 42 becomes L level. Then, the output signal DET of the AND gate 43 becomes H level. The output signal DETX of the NOT circuit 44 outputs an inverted signal of the signal DET. That is, the output signal DETX is at the L level during the period from time T1 to time T2.

As described above, if the capacitive power converter 10 is normal, the target voltage is charged to the capacitor C11, the capacitor C12, and the capacitor C13 within the period from the time T1 to the time T2. I know. Therefore, the clock counter CTR is set to be input to the AND gate 45 during the period from the time T1 to the time T2. When the capacitive power converter 10 is normal, the output signal DETX input to the AND gate 45 is at L level during the period from time T1 to time T2. Therefore, the output signal FLT of the AND gate 45 remains at the L level.

FIG. 7 is a diagram showing the output of each element of the failure determination circuit 40 when the capacitive power converter 10 is abnormal.

For example, if the capacity of the capacitor is too large, or if a short circuit failure or a short circuit path is formed and a leak occurs, the charging time of the capacitor is delayed. For this reason, the inclination of the detection voltage VMd becomes gentler than in the case of FIG. In this example, it is assumed that the detection voltage VMd becomes higher than the reference voltage REFL when the time T3 (> T2) has elapsed after the start of precharging.

The detection voltage VMd is lower than the reference voltage REFL and the reference voltage REFH until the time T3 elapses after the precharge is started. In this case, the output signal DETH of the comparator 41 is at the H level, and the output signal DETL of the comparator 42 is at the L level. Then, the output signal DET of the AND gate 43 becomes L level, and the signal DETX becomes H level. In other words, during the period from time T1 to time T2, the signal DETX is at the H level. Therefore, a period in which the output signal FLT of the AND gate 45 is at the H level occurs.

It should be noted that an abnormality can be detected even when the slope of the detection voltage VMd is greater than by limiting the charge upper limit potential without stopping the charge upon completion of the charge. In this case, as in FIG. 7, there is a period in which the output signal FLT of the AND gate 45 is at the H level. Further, the lack of capacity can be easily detected from the point where the charge completion detection signal is earlier than expected. For example, as another means for detecting the charging completion time, a method of comparing the timing of the charging completion detection signal with the count number of the counter can be considered.

In this description, the timing of outputting the clock counter CTR, the values of the reference voltage REFL, the reference voltage REFH, and the like can be changed as appropriate.

Thus, the failure determination circuit 40 outputs an H level signal when the capacitive power converter 10 is abnormal. When an H level signal is output from the failure determination circuit 40, for example, the control circuit 50 does not drive the capacitive power converter 10. Thereby, it is possible to suppress the possibility that the abnormal power converter unit 1 continues to drive and causes further problems. Further, when there is an abnormality, the failure may be notified to the outside.

As described above, the power converter unit 1 steps down the input voltage V1 to the intermediate voltage V2 by the capacitive power converter 10. Then, the inductive power converter 20 further reduces the intermediate voltage V2 to the output voltage V3. For this reason, when there is an abnormality in the capacitive power converter 10, an overvoltage equal to or higher than the intermediate voltage V2 is applied to the inductive power converter 20, and the inductive power converter 20 may fail. Therefore, failure of the inductive power converter 20 can be prevented by determining the abnormality of the capacitive power converter 10 by the failure determination circuit 40 and not driving the capacitive power converter 10.

Also, assuming that an overvoltage is applied, it is not necessary to configure the inductive power converter 20 with an element having a high withstand voltage. In particular, by reducing the breakdown voltage of the switch elements Q11 and Q12, which are FETs, the gate capacitance is reduced and the on-resistance is also reduced. For this reason, the switching frequency can be increased. Further, the inductor L1 can be reduced, and the power converter unit 1 can be reduced in size.

Note that the circuit configuration of the charging circuit 30 can be changed as appropriate.

FIG. 8 is a circuit diagram of another example of the charging circuit 30A.

8 is different from the charging circuit 30 of FIG. 5 in that the reference voltage power supply 34 is connected to the gate of the switch element S31 and no comparator is used. When the capacitor C11 is fully charged, the source potential of the switch element S31 rises and the switch element S31 is turned off. Then, the constant current is not supplied to the capacitor C11, the capacitor C12, and the capacitor C13.

Further, abnormality determination of the capacitive power converter 10 may be performed by digital processing.

FIG. 9 is a block diagram of the failure determination unit 40A that performs abnormality determination of the capacitive power converter 10.

The failure determination unit 40A includes an AD converter (ADC) 401, an arithmetic processing unit 402, a counter 403, and a storage unit 404. The ADC 401 converts the detection result of the output voltage VM of the capacitive power converter 10 into a digital value. The storage unit 404 is an EEPROM or the like, and stores a target value for comparison with the output voltage VM. The storage unit 404 can be rewritten from the outside. The counter 403 outputs a clock counter to the arithmetic processing unit 402 at a preset timing. The arithmetic processing unit 402 is, for example, a microcomputer, and performs failure determination by comparing the output voltage VM of the capacitive power converter 10 with the target value stored in the storage unit 404 at the timing of the clock counter.

(Embodiment 2)
The power converter unit according to the second embodiment will be described below. In the present embodiment, the configuration of the capacitive power converter is different from that of the first embodiment.

FIG. 10 is a circuit diagram of the capacitive power converter 60 according to the second embodiment.

The capacitive power converter 60 has an input unit composed of

terminals

601 and 602 and an output unit composed of

terminals

603 and 604. The capacitive power converter 60 includes a switch element S41, a switch element S42, a switch element S43, a switch element S44, a switch element S45, a switch element S46, a switch element S47, a capacitor C31, and a capacitor. C32, a capacitor C33, and a switching control circuit 112. The switching control circuit 112 performs switching control of the switch elements S41 to S47.

The switching control circuit 112 is an example of a “capacitive side control unit” according to the present invention. The switch elements S41 to S47 are examples of the “capacitive side switch element” according to the present invention.

The switch element S41, the switch element S42, and the switch element S43 are connected in series between the terminal 601 and the terminal 603. A capacitor C31 and a switch element S45 are sequentially connected in series to a connection point between the switch element S41 and the switch element S42. A capacitor C32 and a switch element S46 are sequentially connected in series to a connection point between the switch element S42 and the switch element S43. The switch element S44 is connected between a connection point between the capacitor C31 and the switch element S45 and the terminal 603. The switch element S47 is connected between a connection point between the capacitor C32 and the switch element S46 and the terminal 603. The capacitor C33 is connected between the terminal 603 and the terminal 604.

In this configuration, the potential difference between both ends of the capacitor C31 is larger than the potential difference between both ends of the capacitor C32 and the potential difference between both ends of the capacitor C33.

The switching control circuit 112 turns on the switch element S41, the switch element S44, the switch element S43, and the switch element S46, and turns off the switch element S42, the switch element S45, and the switch element S47 (the first element). Configuration). As a result, a power supply voltage potential is applied to the positive electrode of the capacitor C31, an output voltage potential is applied to the negative electrode, and a potential difference of 2/3 of the power supply voltage is applied to both electrodes of the capacitor C31.

Next, the switching control circuit 112 turns off the switch element S41, the switch element S44, the switch element S43, and the switch element S46, and turns on the switch element S42, the switch element S45, and the switch element S47. (Second configuration). As a result, a voltage 2/3 of the power supply voltage appears at the positive electrode of the capacitor C31, a GND potential appears at the negative electrode, a voltage 2/3 of the power supply voltage appears at the positive electrode of the capacitor C32, and an output voltage (= 1/3 of the power supply voltage is applied to both electrodes of the capacitor C32. When returning from the second configuration to the first configuration, the negative electrode of the capacitor C32 becomes the GND potential, and the positive electrode becomes 1/3 of the power supply voltage, which is supplied to the output.

Thus, in the capacitive power converter 60, by switching each switch element, the input voltage is stepped down to an intermediate voltage.

FIG. 11 is a diagram for explaining the operation at the time of precharging by the charging circuit 30.

When precharging by the charging circuit 30 is performed, the switching control circuit 112 of the capacitive power converter 60 turns on the switch element S42, the switch element S43, the switch element S45, and the switch element S46, The switch element S44 and the switch element S47 are turned off. Thereby, the capacitor C31, the capacitor C32, and the capacitor C33 are configured to be connected in parallel to the charging circuit 30. A constant current is supplied from the constant current source 31 to the capacitor C31, the capacitor C32, and the capacitor C33.

As in the first embodiment, the charging circuit 30 stops charging with a constant current when each of the capacitor C31, the capacitor C32, and the capacitor C33 is charged to the reference voltage that is a target value.

Note that, in the configuration of the capacitive power converter 60 according to the present embodiment, the charging voltages of the capacitor C31, the capacitor C32, and the capacitor C33 are not common. For this reason, when charging by supplying a constant current, the voltages charged in the capacitor C31, the capacitor C32, and the capacitor C33 are different. However, in the same manner as in the above-described embodiment, the inrush current is suppressed by precharging the capacitor C31, the capacitor C32, and the capacitor C33 to appropriate voltages.

Further, the on / off states of the switch elements S41 to S47 of the capacitive power converter 60 at the time of precharging can be changed as appropriate. For example, the switch elements S31, S45, S42, S46, and S43 may be turned on to precharge the capacitors C31, C32, and C33, and then the switch element S42 may be turned off to additionally charge the capacitor C31.

Further, when the capacitances of the capacitor C32 and the capacitor C33 are the same and the target voltages of the capacitor C32 and the capacitor C31 are V _C32 and V _C31 = 2 * V _C32 , the switch element S45, the switch element S42, Alternatively, the switch element S47 may be turned on and the others may be turned off to perform precharge. In this case, the capacitor C31 and the series circuit of the capacitor C32 and the capacitor C33 are connected to the charging circuit 30 in parallel.

Further, in the present embodiment, since the capacitances of the capacitor C31, the capacitor C32, and the capacitor C33 are different, the failure determination circuit detects a charging voltage of at least one of the capacitor C31, the capacitor C32, and the capacitor C33. Then, the abnormality is determined by comparing with the target value. In this case, the timing of outputting the clock counter CTR described in the first embodiment, the values of the reference voltage REFL, the reference voltage REFH, and the like are appropriately changed according to the capacitor that detects the charging voltage.

The capacitances of the capacitor C31, the capacitor C32, and the capacitor C33 can be set arbitrarily and may be the same. Furthermore, each capacitance may be charged one by one, or a plurality may be charged together.

Thus, the configuration at the time of charging can be changed as appropriate. On the other hand, in any case, the charging time can be calculated from the charging current, the combined capacity of the capacitors, the target voltage, and the like. In other words, regardless of the configuration, if there is a charging circuit with a known current rate, a capacitor to be charged, a detection circuit that detects the completion of charging, and a timer that monitors the time, failure detection is possible while precharging. It is. Regarding failure detection, each capacitor may be detected, or a plurality of capacitors may be detected as a group. Further, only some representative parts may be detected.

In the first and second embodiments, the step-down power converter unit has been described, but the power converter unit may be used for step-up. In this case, the terminal Out1 and the terminal Out2 shown in FIG. 1 are input units, and the terminal In1 and the terminal In2 are output units. Then, the voltage input from the input portions of the terminal Out1 and the terminal Out2 is boosted and output from the output portion of the terminals In1 and In2. In this configuration, the charging circuit is provided between the inductive power converter and the capacitive power converter. When precharging is performed, the inductive power converter and the capacitive power converter are disconnected from each other. , Supplying a constant current to the capacitive power converter. Thereby, the inrush current to the capacitive power converter can be prevented.

C11, C12, C13 ... Capacitor C2 ... Capacitors C31, C32, C33 ... Capacitor In1, In2 ... Terminal L1 ... Inductor Out1, Out2 ... Terminals Q11, Q12 ... Switch elements (inductive side switch elements)
R11, R12 ... Resistance (Voltage detector)
S11, S12, S13, S14, S15, S16, S17 ... switch element (capacitive side switch element)
S31 ... Switch elements S32, S33 ... Switch elements S41, S42, S43, S44, S45, S46, S47 ... Switch elements (capacitive side switch elements)
V1 ... input voltage V2 ... intermediate voltage V3 ... output voltage VM ... output voltage 1 ... power converter unit 10 ... capacitive power converter 20 ... inductive power converter 21 ... driver (inductive side controller)
30, 30A ... charging circuit 31 ... constant current source 32 ... comparator 33 ... reference voltage power source 34 ... reference voltage power source 40 ... failure determination circuit (failure determination unit)
40A ...

Failure determination unit

41, 42 ... Comparator 43 ... AND gate 44 ... NOT circuit 45 ... AND gate 46 ... Counter 50 ... Control circuit (power conversion limiting unit)
60 ...

Capacitive power converters

101, 102, 103, 104 ...

Terminals

111, 112 ...

Switching control circuits

201, 202, 203, 204 ... Terminal 402 ... Arithmetic processing unit 403 ... Counter 404 ...

Storage units

601, 602, 603 604 ... Terminal

Claims

An input unit to which a DC voltage is input, an output unit to which a DC voltage is output, a plurality of capacitors connected in parallel to the input unit, a plurality of capacitive side switch elements, and the plurality of capacitive side switches A capacitive side control unit that performs switching control of the element, and a capacitive power converter that steps up and down the voltage by charging and discharging the plurality of capacitors by switching the state of the plurality of capacitive side switch elements;
The inductive side switch element is connected to the input unit or the output unit, and includes an inductor, an inductive side switch element, and an inductive side control unit that controls the switching of the inductive side switch element. An inductive power converter that steps up and down the voltage by switching the state and discharging the energy to the inductor;
A charging circuit having a constant current source, supplying a constant current from the constant current source to a connection point of the plurality of capacitors, or cutting off the supply;
Power converter unit with
A voltage detector for detecting a charging voltage to any of the plurality of capacitors;
An abnormality determination unit that compares the detection value detected by the voltage detection unit with a target value to determine abnormality,
A power converter unit according to claim 1.
The abnormality determination unit operates within a predetermined time after the capacitive power converter is activated.
The power converter unit according to claim 2.
A power conversion limiting unit that limits power conversion by the capacitive power converter when the abnormality determination unit determines that an abnormality has occurred;
A power converter unit according to claim 2 or 3.