WO2017215837A1 - Power semiconductor subassembly - Google Patents

Power semiconductor subassembly Download PDF

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Publication number
WO2017215837A1
WO2017215837A1 PCT/EP2017/060789 EP2017060789W WO2017215837A1 WO 2017215837 A1 WO2017215837 A1 WO 2017215837A1 EP 2017060789 W EP2017060789 W EP 2017060789W WO 2017215837 A1 WO2017215837 A1 WO 2017215837A1
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WO
WIPO (PCT)
Prior art keywords
carrier plate
carrier
circuit board
conducting
subassembly according
Prior art date
Application number
PCT/EP2017/060789
Other languages
French (fr)
Inventor
Ronald Eisele
Aylin BICAKCI
Frank Osterwald
Original Assignee
Danfoss Silicon Power Gmbh
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Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2017215837A1 publication Critical patent/WO2017215837A1/en

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
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    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • Power semiconductor subassembly The invention relates to a power semiconductor subassembly.
  • the invention relates to a power semiconductor subassembly comprising a "bare die" semiconductor.
  • the "bare die” technique is usually used for mounting power semiconductors on ceramic-core circuit carriers such as Directly Bonded Copper (DBC) substrates.
  • ceramic-core circuit carriers are labour-intensive to produce and therefore also costly and the possibilities for patterning the thick-copper layers using an etching technique result in much larger- scale patterns than are needed for the mounting of SMD technology components.
  • the prior art describes the use of classic laminated circuit boards and ceramic-core circuit boards as a macroscopic mounting task, with partly sprung contact strips to compensate for the expansion of the ceramic (thermal expansion 4-8 ppm/K) and laminated epoxy -resin circuit boards (thermal expansion 18-22 ppm/K in the x and y directions).
  • a known technique is to mount power semiconductors using a "bare die” technique on copper lead frames with a spatially separate arrangement of conventional circuit boards for logic and sensor components and which are interconnected by plug-in connectors and cables.
  • IMS Insulated Metal Substrate
  • this type of circuit carrier having copper conductor tracks up to a maximum thickness of 105 ⁇ , which can also be finely structured by an etching technique.
  • the reflow technique is used for mounting SMD components and power semiconductors together in discrete packages.
  • the small thickness of up to max. 105 ⁇ of the copper layer is decisive for the restricted current utilization of the power semiconductors, and therefore predominantly discretely packaged transistors are mounted by the soldering technique.
  • the low current-carrying capacity of the copper conducting areas is compensated by a greater area requirement - about 3 to 4 times greater than in the case of ceramic-core circuit boards and up to 10 times greater than in the case of lead frame substrates.
  • At least one metallic conducting carrier with at least one "bare die” semiconductor arranged thereon
  • circuit board with at least one active or passive electrical component arranged thereon
  • the basic concept of the invention is that of providing a large- scale-integrated subassembly with, on the one hand, power semiconductors based on the "bare die” technique and, on the other hand, active or passive components for driving the power components for logic and sensor functions in classic circuit board mounting in a low-cost way, wherein the subassembly is in particular a power module.
  • the substrate used for this consists essentially of a one-piece carrier plate, e.g. of copper, at least partially covered on one side with an electrically insulating film or layer, which is covered in certain portions with conductor tracks or conductor areas forming a conducting carrier.
  • a one-piece carrier plate e.g. of copper
  • an electrically insulating film or layer which is covered in certain portions with conductor tracks or conductor areas forming a conducting carrier.
  • the conducting carrier carries "bare die” semiconductor components, in particular
  • the conducting carrier, the insulating layer and the carrier plate are in form-fitting, preferably material- bonding contact.
  • the component side of the carrier plate has, in addition to portions having the conducting carrier, portions with preferably organic (e.g. epoxy-resin) circuit boards.
  • These circuit board elements are loaded with active and/or passive components for forming the functions of logic drivers for the power semiconductors and/or sensor-related tasks. These are, for example, series resistors, sensors or control and driver circuits that are suitable for driving power semiconductors.
  • the circuit boards are in this case preferably in form-fitting contact with the carrier plate.
  • the form-fitting contact of the circuit board may in this case be brought about, for example, by a suitable epoxy-resin-containing or silicone-containing adhesive.
  • the invention therefore provides a subassembly comprising at least one metallic conducting carrier with at least one "bare die” semiconductor arranged thereon, at least one circuit board with at least one active or passive electrical component arranged thereon, and a carrier plate with high thermal conductivity, wherein the at least one conducting carrier and the at least one circuit board are fixed adjacent to one another on the carrier plate.
  • the conducting carrier is fixed on the carrier plate through the provision of an insulating layer, it being particularly preferable that the conducting carrier, the insulating layer and the carrier plate are connected to one another in a material-bonding manner.
  • the conducting carrier itself is in particular metallic, for example formed from copper.
  • the insulating layer used between the carrier plate and the conducting carrier specifically has a high thermal conductivity.
  • the circuit board is preferably fastened on the carrier plate by the provision of an adhesive, the adhesive in particular containing resin or silicone.
  • the circuit board can also be fastened on the carrier plate by the provision of the insulating layer used for the conducting carrier.
  • the insulating layer can at least partially cover the carrier plate and serve as an adhesion promoter both for the conducting carrier and for the circuit board, such that overall a very simple structure is achieved.
  • a conductor connects the gate terminal of a semiconductor to a circuit board, in particular if the electrical component arranged on the circuit board is a component part of a logic circuit controlling the semiconductor.
  • the carrier plate is preferably formed from copper, aluminium or a copper alloy or an aluminium alloy.
  • circuit board by contrast, is preferably formed from a synthetic resin.
  • the invention will be explained in more detail hereinbelow with reference to an exemplary embodiment of particularly preferred configuration which is shown in the accompanying drawings, in which: Figure 1 shows a schematic side view of a first exemplary embodiment
  • Figure 2 shows a schematic side view of a second exemplary embodiment
  • Figure 3 shows a schematic side view of a third exemplary embodiment
  • Figure 1 shows a schematic side view of a first exemplary embodiment according to the invention.
  • Figure 1 shows a one-piece mounting or carrier plate 10, which is produced, for example, from material with good thermal conductivity such as copper or aluminium or the alloys thereof.
  • the carrier plate 10 is at least partially covered on one side with an electrically insulating layer or film 30 which has a high thermal conductivity (in particular > 2 W/mK).
  • the area of the insulating layer 30 is covered with conductor tracks or conductor areas, forming a conducting carrier 20, made of a material with good thermal conductivity, e.g. such as copper or aluminium or the alloys thereof, and which are preferably 0.5 mm to 5 mm thick, and particularly preferably 1 to 2 mm thick.
  • the conducting carrier 20 carries "bare die" semiconductor components 21; in particular, these are components with increased power loss dissipation, for which it is essential to remove heat via the conducting carrier 20, the insulating layer 30 and the carrier plate 10.
  • Each semiconductor 21 is connected to the conducting carrier 20 here by means of a fastening means 22, for example a sintered layer.
  • the conducting carrier 20, the insulating layer 30 and the carrier plate 10 are in form-fitting, preferably material-bonding, and consequently optimally thermally conductive, contact.
  • the "bare die” semiconductor components 21 are connected by way of bonding wires or low- inductance high-frequency ribbon cables 23.
  • the component side of the substrate 10, in addition to the areas free of the conducting carrier, has elements of preferably organic (e.g. epoxy-resin) circuit boards 40. These circuit board elements 40 are loaded with active and/or passive components 41 for forming the functions of logical drives of the power semiconductors 21 and/or sensor-related and/or other tasks. These are, for example, series resistors, sensors or control and driver circuits for driving power semiconductors 21.
  • the circuit boards 40 are in this case preferably in form-fitting or material-bonding contact with the carrier plate 10.
  • the contact of the circuit board 40 may in this case be brought about for example by a suitable adhesive 50 (e.g. containing resin or silicone).
  • the electrical connection e.g. from the driver circuit 41 to the "bare die” semiconductor component 21, takes place likewise by way of bonding wires or low-inductance high-frequency ribbon cables 42.
  • circuit board 40 takes place in the greatest possible proximity to the "bare die" conductor area 20, in order to ensure that conductor routing from the driver to the semiconductor 21 has the smallest-possible low-inductance configuration.
  • Figure 2 shows an exemplary embodiment of particularly preferred configuration, in which a plurality of conducting carriers 20 and circuit boards 40 are arranged in alternating fashion.
  • the circuit board area is both the origin and the area for the distribution of the gate potentials to the locations of the spatially closest gate connection 42 with respect to the power semiconductor 21 concerned.
  • FIG 3 shows an exemplary embodiment of another particularly preferred configuration, similar to the embodiment shown in Figure 1.
  • the circuit board 40 is here fastened to the carrier plate 10 by the insulating layer 30. This is a great advantage in the manufacturing process of the subassembly since a single material is used for fixing the conducting carriers 20 and the circuit board 40. This enables the fixing to take place in a single step in the assembly process, saving time and hence cost.
  • the electrical connection e.g. from the driver circuit 41 to the "bare die” semiconductor component 21, takes place, as in the above embodiments, by way of bonding wires or low-inductance high-frequency ribbon cables 42.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

Power module comprising at least one metallic conducting carrier (20) with at least one "bare die" semiconductor (21) arranged thereon, at least one circuit board (40) with at least one active or passive electrical component (41) arranged thereon, and a carrier plate (10) with high thermal conductivity, wherein the at least one conducting carrier (20) and the at least one circuit board (40) are fastened adjacent to one another on the carrier plate (10).

Description

Power semiconductor subassembly The invention relates to a power semiconductor subassembly. In particular, the invention relates to a power semiconductor subassembly comprising a "bare die" semiconductor.
The "bare die" technique is usually used for mounting power semiconductors on ceramic-core circuit carriers such as Directly Bonded Copper (DBC) substrates. Such ceramic-core circuit carriers are labour-intensive to produce and therefore also costly and the possibilities for patterning the thick-copper layers using an etching technique result in much larger- scale patterns than are needed for the mounting of SMD technology components.
Therefore, the prior art describes the use of classic laminated circuit boards and ceramic-core circuit boards as a macroscopic mounting task, with partly sprung contact strips to compensate for the expansion of the ceramic (thermal expansion 4-8 ppm/K) and laminated epoxy -resin circuit boards (thermal expansion 18-22 ppm/K in the x and y directions).
Alternatively, a known technique is to mount power semiconductors using a "bare die" technique on copper lead frames with a spatially separate arrangement of conventional circuit boards for logic and sensor components and which are interconnected by plug-in connectors and cables.
The main disadvantage of this procedure is that there can be no integration of the power semiconductors based on the "bare die" technique with the required logic and sensor components in any great spatial proximity. Specifically, ceramic-core circuit boards have a very low coefficient of thermal expansion and this necessitates expansion compensation measures, e.g. by means of spring pins, extended solder pins, or cable or bar connections. A low-inductance and dense-power arrangement of the control circuit and the bare die power semiconductor cannot be achieved in this way. Especially fast-switching components of the wide-band-gap class (SiC or GaN power components) must be connected in the greatest spatial proximity with minimal line inductances. Metal-core circuit boards (IMS = Insulated Metal Substrate) are also known as a further alternative, this type of circuit carrier having copper conductor tracks up to a maximum thickness of 105 μιη, which can also be finely structured by an etching technique. Here, the reflow technique is used for mounting SMD components and power semiconductors together in discrete packages.
Although a relatively good spatial compacting of power and logic components is possible in this configuration, the maximum integration of these components suffers under the low copper layer thickness for the power semiconductors and the only single-layered copper conductor configuration for the logic components.
The small thickness of up to max. 105 μιη of the copper layer is decisive for the restricted current utilization of the power semiconductors, and therefore predominantly discretely packaged transistors are mounted by the soldering technique. The low current-carrying capacity of the copper conducting areas is compensated by a greater area requirement - about 3 to 4 times greater than in the case of ceramic-core circuit boards and up to 10 times greater than in the case of lead frame substrates. This considerable disadvantage together with the area-intensive, single-layered arrangement of the logic components in turn produces the disadvantages of increased line inductances and a large area requirement.
It is therefore an object of the invention to provide specifically power semiconductors based on the "bare die" technique and the required logic and sensor components in an integrated subassembly. This object is achieved according to the invention by the subassembly comprising
at least one metallic conducting carrier with at least one "bare die" semiconductor arranged thereon,
at least one circuit board with at least one active or passive electrical component arranged thereon, and
a carrier plate with high thermal conductivity,
wherein the at least one conducting carrier and the at least one circuit board are fastened adjacent to one another on the carrier plate. The basic concept of the invention is that of providing a large- scale-integrated subassembly with, on the one hand, power semiconductors based on the "bare die" technique and, on the other hand, active or passive components for driving the power components for logic and sensor functions in classic circuit board mounting in a low-cost way, wherein the subassembly is in particular a power module.
In particular, the substrate used for this consists essentially of a one-piece carrier plate, e.g. of copper, at least partially covered on one side with an electrically insulating film or layer, which is covered in certain portions with conductor tracks or conductor areas forming a conducting carrier.
The conducting carrier carries "bare die" semiconductor components, in particular
components with increased power loss dissipation, for which it is essential to remove heat via the conducting carrier. For the best-possible power loss thermal conductivity, the conducting carrier, the insulating layer and the carrier plate are in form-fitting, preferably material- bonding contact.
The component side of the carrier plate has, in addition to portions having the conducting carrier, portions with preferably organic (e.g. epoxy-resin) circuit boards. These circuit board elements are loaded with active and/or passive components for forming the functions of logic drivers for the power semiconductors and/or sensor-related tasks. These are, for example, series resistors, sensors or control and driver circuits that are suitable for driving power semiconductors. The circuit boards are in this case preferably in form-fitting contact with the carrier plate. The form-fitting contact of the circuit board may in this case be brought about, for example, by a suitable epoxy-resin-containing or silicone-containing adhesive.
The invention therefore provides a subassembly comprising at least one metallic conducting carrier with at least one "bare die" semiconductor arranged thereon, at least one circuit board with at least one active or passive electrical component arranged thereon, and a carrier plate with high thermal conductivity, wherein the at least one conducting carrier and the at least one circuit board are fixed adjacent to one another on the carrier plate. It is preferable that the conducting carrier is fixed on the carrier plate through the provision of an insulating layer, it being particularly preferable that the conducting carrier, the insulating layer and the carrier plate are connected to one another in a material-bonding manner. The conducting carrier itself is in particular metallic, for example formed from copper.
The insulating layer used between the carrier plate and the conducting carrier specifically has a high thermal conductivity. Similarly, the circuit board is preferably fastened on the carrier plate by the provision of an adhesive, the adhesive in particular containing resin or silicone.
Alternatively, the circuit board can also be fastened on the carrier plate by the provision of the insulating layer used for the conducting carrier. As a result, the insulating layer can at least partially cover the carrier plate and serve as an adhesion promoter both for the conducting carrier and for the circuit board, such that overall a very simple structure is achieved.
It is particularly advantageous, in the case of a plurality of conducting carriers and circuit boards arranged on the carrier plate, for there to be an alternating arrangement of conducting carriers and circuit boards, such that an optimum distribution of heat over the carrier plate can be achieved.
It is further advantageous if - as will be described further hereinbelow - a conductor connects the gate terminal of a semiconductor to a circuit board, in particular if the electrical component arranged on the circuit board is a component part of a logic circuit controlling the semiconductor.
A good distribution of heat and removal of heat from the electrical components is achieved when the thickness of the conducting carrier is at least 1.5 times greater than the thickness of the carrier plate. In this case, the carrier plate is preferably formed from copper, aluminium or a copper alloy or an aluminium alloy.
The circuit board, by contrast, is preferably formed from a synthetic resin. The invention will be explained in more detail hereinbelow with reference to an exemplary embodiment of particularly preferred configuration which is shown in the accompanying drawings, in which: Figure 1 shows a schematic side view of a first exemplary embodiment
according to the invention;
Figure 2 shows a schematic side view of a second exemplary embodiment
according to the invention, and
Figure 3 shows a schematic side view of a third exemplary embodiment
according to the invention.
Figure 1 shows a schematic side view of a first exemplary embodiment according to the invention.
In particular, Figure 1 shows a one-piece mounting or carrier plate 10, which is produced, for example, from material with good thermal conductivity such as copper or aluminium or the alloys thereof. The carrier plate 10 is at least partially covered on one side with an electrically insulating layer or film 30 which has a high thermal conductivity (in particular > 2 W/mK).
In certain portions, the area of the insulating layer 30 is covered with conductor tracks or conductor areas, forming a conducting carrier 20, made of a material with good thermal conductivity, e.g. such as copper or aluminium or the alloys thereof, and which are preferably 0.5 mm to 5 mm thick, and particularly preferably 1 to 2 mm thick. The conducting carrier 20 carries "bare die" semiconductor components 21; in particular, these are components with increased power loss dissipation, for which it is essential to remove heat via the conducting carrier 20, the insulating layer 30 and the carrier plate 10. Each semiconductor 21 is connected to the conducting carrier 20 here by means of a fastening means 22, for example a sintered layer.
For the best-possible removal of power loss heat, the conducting carrier 20, the insulating layer 30 and the carrier plate 10 are in form-fitting, preferably material-bonding, and consequently optimally thermally conductive, contact. The "bare die" semiconductor components 21 are connected by way of bonding wires or low- inductance high-frequency ribbon cables 23. The component side of the substrate 10, in addition to the areas free of the conducting carrier, has elements of preferably organic (e.g. epoxy-resin) circuit boards 40. These circuit board elements 40 are loaded with active and/or passive components 41 for forming the functions of logical drives of the power semiconductors 21 and/or sensor-related and/or other tasks. These are, for example, series resistors, sensors or control and driver circuits for driving power semiconductors 21.
The circuit boards 40 are in this case preferably in form-fitting or material-bonding contact with the carrier plate 10. The contact of the circuit board 40 may in this case be brought about for example by a suitable adhesive 50 (e.g. containing resin or silicone). The electrical connection, e.g. from the driver circuit 41 to the "bare die" semiconductor component 21, takes place likewise by way of bonding wires or low-inductance high-frequency ribbon cables 42.
The placement of the circuit board 40 takes place in the greatest possible proximity to the "bare die" conductor area 20, in order to ensure that conductor routing from the driver to the semiconductor 21 has the smallest-possible low-inductance configuration.
Figure 2 shows an exemplary embodiment of particularly preferred configuration, in which a plurality of conducting carriers 20 and circuit boards 40 are arranged in alternating fashion. In particular, in this example, the circuit board area is both the origin and the area for the distribution of the gate potentials to the locations of the spatially closest gate connection 42 with respect to the power semiconductor 21 concerned.
Figure 3 shows an exemplary embodiment of another particularly preferred configuration, similar to the embodiment shown in Figure 1. The circuit board 40 is here fastened to the carrier plate 10 by the insulating layer 30. This is a great advantage in the manufacturing process of the subassembly since a single material is used for fixing the conducting carriers 20 and the circuit board 40. This enables the fixing to take place in a single step in the assembly process, saving time and hence cost. The electrical connection, e.g. from the driver circuit 41 to the "bare die" semiconductor component 21, takes place, as in the above embodiments, by way of bonding wires or low-inductance high-frequency ribbon cables 42.

Claims

Subassembly comprising at least one metallic conducting carrier with at least one "bare die" semiconductor arranged thereon, at least one circuit board with at least one active or passive electrical component arranged thereon, and a carrier plate with high thermal conductivity, wherein the at least one conducting carrier and the at least one circuit board are fixed adjacent to one another on the carrier plate.
2. Subassembly according to Claim 1, characterized in that the conducting carrier is fixed on the carrier plate through the provision of an insulating layer.
3. Subassembly according to Claim 2, characterized in that the conducting carrier, the insulating layer and the carrier plate are connected to one another in a material- bonding manner.
4. Subassembly according to one of the preceding claims, characterized in that the circuit board is fastened on the carrier plate by the provision of an adhesive.
5. Subassembly according to one of the preceding claims, characterized by a plurality of conducting carriers and circuit boards arranged in alternating fashion on the carrier plate. - 2 -
6. Subassembly according to one of the preceding claims, characterized by a conductor connecting the gate terminal of a semiconductor to a circuit board.
7. Subassembly according to one of the preceding claims, characterized in that the
electrical component is a component part of a logic circuit controlling the
semiconductor.
8. Subassembly according to one of the preceding claims, characterized in that the
thickness of the conducting carrier is at least 1.5 times greater than the thickness of the carrier plate.
9. Subassembly according to one of the preceding claims, characterized in that the carrier plate is formed from copper, aluminium or a copper alloy or aluminium alloy.
10. Subassembly according to one of the preceding claims, characterized in that the circuit board is formed from a synthetic resin.
11. Subassembly according to one of the preceding claims, characterized in that the
conducting carrier and the circuit board are both fixed on the carrier plate through the provision of the same insulating layer.
PCT/EP2017/060789 2016-06-14 2017-05-05 Power semiconductor subassembly WO2017215837A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016110889.8 2016-06-14
DE102016110889 2016-06-14

Publications (1)

Publication Number Publication Date
WO2017215837A1 true WO2017215837A1 (en) 2017-12-21

Family

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Application Number Title Priority Date Filing Date
PCT/EP2017/060789 WO2017215837A1 (en) 2016-06-14 2017-05-05 Power semiconductor subassembly

Country Status (1)

Country Link
WO (1) WO2017215837A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144571A (en) * 1999-02-22 2000-11-07 Hitachi, Ltd. Semiconductor module, power converter using the same and manufacturing method thereof
JP2002203940A (en) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp Semiconductor power module
EP2814060A1 (en) * 2012-06-13 2014-12-17 Fuji Electric Co., Ltd. Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144571A (en) * 1999-02-22 2000-11-07 Hitachi, Ltd. Semiconductor module, power converter using the same and manufacturing method thereof
JP2002203940A (en) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp Semiconductor power module
EP2814060A1 (en) * 2012-06-13 2014-12-17 Fuji Electric Co., Ltd. Semiconductor device

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