WO2017208790A1 - Variable capacitor - Google Patents

Variable capacitor Download PDF

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Publication number
WO2017208790A1
WO2017208790A1 PCT/JP2017/018127 JP2017018127W WO2017208790A1 WO 2017208790 A1 WO2017208790 A1 WO 2017208790A1 JP 2017018127 W JP2017018127 W JP 2017018127W WO 2017208790 A1 WO2017208790 A1 WO 2017208790A1
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Prior art keywords
layer
capacitor
thin film
electrode
substrate
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PCT/JP2017/018127
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French (fr)
Japanese (ja)
Inventor
直樹 牛山
古本 憲輝
純弘 大塚
剛 國仲
Original Assignee
パナソニックIpマネジメント株式会社
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Publication of WO2017208790A1 publication Critical patent/WO2017208790A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G7/00Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
    • H01G7/04Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture having a dielectric selected for the variation of its permittivity with applied temperature

Definitions

  • the present invention relates to a variable capacitor, and more particularly to a variable capacitor that can change capacitance.
  • the variable capacitor system described in Patent Document 1 includes a variable capacitor having a drive mechanism that makes the capacitance variable, and a plurality of switches that electrically connect the plurality of fixed capacitors.
  • the variable capacitor system changes the overall capacitance by changing the combination of a variable capacitor and a plurality of fixed capacitors by controlling the opening and closing of the plurality of switches.
  • the capacitance is changed by a driving mechanism, or the overall capacitance is changed by a combination with a fixed capacitor. Therefore, there is a possibility that the capacitance cannot be changed to a desired capacitance when foreign matter or the like is mixed into the drive mechanism. Further, even when a switch is used, if the operation reliability of the contact is low, there is a possibility that it cannot be changed to a desired capacitance. Therefore, it is desired to change the capacitance by a method different from that of the conventional variable capacitor.
  • the present invention has been made in view of the above reasons, and an object thereof is to provide a variable capacitor capable of changing the capacitance without using a drive mechanism and a switch.
  • the variable capacitor according to the first aspect of the present invention includes a substrate, a capacitor portion, a thin film layer, and a temperature adjustment element.
  • the capacitor unit includes a first electrode, a second electrode, and a dielectric layer provided between the first electrode and the second electrode, and is provided on the substrate.
  • the thin film layer covers the capacitor portion.
  • the temperature adjusting element adjusts the temperature of the dielectric layer to change the capacitance of the capacitor unit.
  • the substrate has a gap.
  • the thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit.
  • a surface opposite to the surface on which the capacitor portion is laminated is exposed from the gap.
  • the substrate has a porous layer.
  • the thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit.
  • the surface opposite to the surface on which the capacitor portion is laminated is in contact with the porous layer.
  • the substrate is a semiconductor substrate.
  • variable capacitor of the fifth aspect in any of the first to fourth aspects, the temperature adjusting element is provided in the thin film layer.
  • the temperature adjustment element is a resistance heating element.
  • the dielectric layer is a ferroelectric.
  • the temperature adjusting element is controlled so that the temperature of the dielectric layer is adjusted to be equal to or higher than a Curie temperature at which the dielectric layer changes from a ferroelectric material to a paraelectric material. Change.
  • variable capacitor of the eighth aspect according to the present invention further comprises a temperature sensor for detecting the temperature of the capacitor part in any one of the first to seventh aspects.
  • the dielectric constant of the dielectric layer can be changed by changing the temperature of the dielectric layer, and as a result, the capacitance of the capacitor unit can be changed.
  • FIG. 1A is a plan view of a variable capacitor according to Embodiment 1 of the present invention
  • FIG. 1B is a cross-sectional view taken along line AA of the same variable capacitor.
  • 2A to 2I are cross-sectional views for explaining a manufacturing process of the variable capacitor described above.
  • 3A and 3B are cross-sectional views for explaining a modification of the variable capacitor described above.
  • FIG. 4A is a plan view of a variable capacitor according to Embodiment 2 of the present invention
  • FIG. 4B is a cross-sectional view taken along the line BB of the variable capacitor of the above.
  • FIG. 5A to FIG. 5F are cross-sectional views for explaining the manufacturing process of the variable capacitor described above.
  • FIG. 6A is a plan view of a variable capacitor according to Embodiment 3 of the present invention
  • FIG. 6B is a cross-sectional view taken along the line CC of the variable capacitor according to the third embodiment.
  • FIG. 7A to FIG. 7I are cross-sectional views for explaining the manufacturing process of the variable capacitor described above.
  • FIG. 8A is a plan view of a variable capacitor according to Embodiment 4 of the present invention
  • FIG. 8B is a cross-sectional view of the variable capacitor taken along the line DD of the same.
  • 9A to 9D are cross-sectional views for explaining a manufacturing process of the variable capacitor described above.
  • each drawing to be described is a schematic diagram, and the ratio of the size and thickness of each component in the drawing necessarily reflects the actual dimensional ratio. Is not limited.
  • variable capacitor 10 of the present embodiment changes the capacitance of the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16 by adjusting the temperature of the dielectric layer 16.
  • variable capacitor 10 is used for impedance adjustment of, for example, a non-contact communication device, a wireless power feeding system, a resonance circuit, and the like.
  • the variable capacitor 10 includes a substrate 11, a support layer 12, an interlayer insulating film 18, a surface protective layer 19, and a thin film heater 21 (temperature adjustment element) in addition to the capacitor element 20. ing.
  • the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
  • the substrate 11 is the bottom, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, the thin film heater 21, and the surface protection layer 19. Are stacked in this order.
  • a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19.
  • the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19, that is, the thickness of the thin film layer 50 is several ⁇ m.
  • the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined.
  • FIGS. 1A and 1B arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10 of the present embodiment.
  • the substrate 11 is a semiconductor substrate, for example, a single crystal Si substrate.
  • the main surface 111 of the substrate 11 is a (100) plane.
  • the substrate 11 is formed in a rectangular plate shape.
  • the thickness of the substrate 11 is, for example, 500 to 600 ⁇ m.
  • the central part of the substrate 11 has a rectangular gap 30 penetrating in the thickness direction.
  • the support layer 12 is a laminated film of a SiO 2 film (silicon oxide film) on the substrate 11 and a Si 3 N 4 film (silicon nitride film) on the SiO 2 film, and is formed on one main surface 111 of the substrate 11. Is provided. In the substrate 11 described above, the air gap 30 is formed so that the surface (back surface 121 described above) opposite to the surface on which the capacitor element 20 is provided in the support layer 12 is exposed.
  • the first adhesion layer 13 is made of a Ti film.
  • the first adhesion layer 13 is laminated on the support layer 12 and enhances the adhesion between the support layer 12 and the first electrode 14.
  • the first adhesion layer 13 is not limited to the Ti film, and may be formed of, for example, a BST film ((Ba, Sr) TiO 3 film: barium strontium titanate film).
  • the first electrode 14 is laminated on the first adhesion layer 13.
  • a dielectric layer 16 made of a dielectric material (here, a ferroelectric material) is laminated on the first electrode 14.
  • a second electrode 15 is laminated on the dielectric layer 16.
  • the first electrode 14 is formed of a Pt film.
  • the dielectric layer 16 is formed of a BST film.
  • the second electrode 15 is formed of a Pt film.
  • the capacitor element 20 includes a capacitor portion 20a, a first pad electrode 20b, and a second pad electrode 20c. Further, the capacitor element 20 has a first wiring portion between the capacitor portion 20a and the first pad electrode 20b, and a second wiring portion between the capacitor portion 20a and the second pad electrode 20c.
  • the capacitor portion 20 a corresponds to a portion above the central portion of the support layer 12 in the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15.
  • the exposed portion of the first electrode 14 corresponds to the first pad electrode 20b.
  • the exposed portion of the second electrode 15 corresponds to the second pad electrode 20c.
  • the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 also extends to the portion that becomes the first wiring portion between the capacitor portion 20a and the first pad electrode 20b.
  • the first wiring portion may not have the dielectric layer 16 and the second electrode 15.
  • the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 extends to the portion that becomes the second wiring portion between the capacitor portion 20 a and the second pad electrode 20 c.
  • the first electrode 14 and the dielectric layer 16 may not be provided in the second wiring portion.
  • the gap 30 is located below the first electrode 14 of the capacitor element 20 (the direction opposite to the arrow on the Z axis). From the viewpoint of thermally insulating the capacitor unit 20 a and the substrate 11, the capacitor unit 20 a and the air gap 30 in the capacitor element 20 overlap when the variable capacitor 10 is viewed in the direction from the surface protective layer 19 to the substrate 11. In addition, it is preferable that the capacitor portion 20a is defined.
  • the second adhesion layer 17 is made of a Ti film and is laminated on the second electrode 15.
  • the second adhesion layer 17 enhances the adhesion between the interlayer insulating film 18 and the second electrode 15.
  • the second adhesion layer 17 is not limited to the Ti film, and may be formed of, for example, a BST film.
  • the interlayer insulating film 18 is made of a SiO 2 film (silicon oxide film) and is provided so as to cover the capacitor element 20.
  • the interlayer insulating film 18 electrically insulates between the capacitor element 20 and the thin film heater 21.
  • the thin film heater 21 is a resistance heating element.
  • the thin film heater 21 is laminated on the interlayer insulating film 18.
  • the thin film heater 21 includes a first pad electrode 211, a second pad electrode 212, wiring portions 213 and 214, and a heater portion 215.
  • the heater unit 215 heats the capacitor unit 20a described above.
  • the heater portion 215 is formed in a meandering shape.
  • the heater part 215 is provided in the upper part of the capacitor
  • the wiring part 213 is provided to connect the heater part 215 and the first pad electrode 211.
  • the wiring part 214 is provided to connect the heater part 215 and the second pad electrode 212.
  • the heater part 215 is heated by electrically connecting the first pad electrode 211 and the second pad electrode 212 to a power source. Heat generated from the heater portion 215 of the thin film heater 21 is transmitted to the dielectric layer
  • the surface protective layer 19 is made of a SiO 2 film (silicon oxide film), and is laminated on the interlayer insulating film 18 so as to cover the thin film heater 21.
  • the variable capacitor 10 further includes a first opening 31 extending from the surface protective layer 19 to the first pad electrode 20b, and a second opening 32 extending from the surface protective layer 19 to the second pad electrode 20c. .
  • a first opening 31 extending from the surface protective layer 19 to the first pad electrode 20b
  • a second opening 32 extending from the surface protective layer 19 to the second pad electrode 20c.
  • variable capacitor 10 includes a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 of the thin film heater 21, and a fourth opening extending from the surface protective layer 19 to the second pad electrode 212 of the thin film heater 21. And a portion 34.
  • the thin film heater 21 When a voltage is applied between the first pad electrode 211 and the second pad electrode 212 of the thin film heater 21, the thin film heater 21 generates heat. The heat generated from the thin film heater 21 is transmitted to the dielectric layer 16 of the capacitor unit 20a.
  • the heater portion 215 of the thin film heater 21 is provided above the capacitor portion 20a via the interlayer insulating film 18, heat is transmitted to the entire dielectric layer 16 in the capacitor portion 20a.
  • the relative permittivity of the dielectric layer 16 changes as the temperature changes.
  • the capacitance of the capacitor element 20 is changed by the temperature of the dielectric layer 16 being changed by the heat transmitted from the thin film heater 21. In other words, the capacitance of the capacitor element 20 changes according to the temperature of the dielectric layer 16.
  • the capacitance applied to the capacitor element 20 is adjusted by adjusting the voltage applied to the thin film heater 21. In order to adjust the capacitance of the capacitor element 20, it is only necessary that the heater unit 215 can generate Joule heat. Therefore, the amount of current flowing through the thin film heater 21 may be adjusted.
  • the heater portion 215 of the thin film heater 21 is controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor portion 20a to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material. Thus, it is preferable to change the capacitance of the capacitor portion 20a.
  • variable capacitor 10 of this embodiment Next, a method for manufacturing the variable capacitor 10 of this embodiment will be described with reference to FIGS. 2A to 2I.
  • a SiO 2 film is formed on the main surface 111 of the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD (low pressure chemical vapor deposition), whereby the SiO 2 film and the Si 3 N film are formed.
  • a support layer 12 made of a laminated film with four films is formed (see FIG. 2A).
  • the first adhesion layer 13 is formed on the support layer 12 by sputtering, for example.
  • the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees.
  • the first conductive layer 14a that is the basis of the first electrode 14 is formed on the first adhesion layer 13 by, for example, sputtering.
  • the insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 14a by spin coating and baking at 600 to 700 degrees.
  • the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering.
  • the adhesion layer 17a is formed on the second conductive layer 15a by, for example, sputtering (see FIG. 2B).
  • the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by a spin coating method and baking at 600 to 700 degrees.
  • the first electrode 14, the dielectric layer 16, the second electrode 15, and the second adhesion layer are patterned.
  • Layer 17 and the like are formed (see FIG. 2C).
  • an interlayer insulating film 18 is formed by CVD (chemical vapor deposition) or sputtering so as to cover the capacitor element 20 (see FIG. 2D).
  • a platinum film 21a is formed on the interlayer insulating film 18 by sputtering (see FIG. 2E).
  • the thin film heater 21 is formed by patterning the platinum film 21a by a photolithography technique and an etching technique (see FIG. 2F). Next, the surface protective layer 19 is formed by CVD or sputtering so as to cover the thin film heater 21 (see FIG. 2G).
  • a first opening 31 from the surface protective layer 19 to the first electrode 14 and a second opening 32 from the surface protective layer 19 to the second electrode 15 are formed by photolithography technique and reactive ion etching (RIE).
  • RIE reactive ion etching
  • the first electrode 14 and a part of the second electrode 15 are exposed.
  • the exposed portion of the first electrode 14 becomes the first pad electrode 20b
  • the exposed portion of the second electrode 15 becomes the second pad electrode 20c (see FIG. 2H).
  • a third opening 33 and a fourth opening 34 extending from the surface protective layer 19 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed.
  • a portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211
  • a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
  • the space 30 is formed by etching the region where the gap 30 is to be formed from the back surface of the substrate 11 (see FIG. 2I).
  • the substrate 11 it is desirable to use, for example, an inductively coupled plasma (ICP) type dry etching apparatus or a reactive ion etching (RIE) apparatus.
  • ICP inductively coupled plasma
  • RIE reactive ion etching
  • the gap 30 may be formed by etching with an alkaline solution (for example, a TMAH solution, a KOH aqueous solution, or the like) from the back surface of the substrate 11.
  • variable capacitor 10 is manufactured through the above steps.
  • variable capacitor 10 includes the thin film heater 21 as a resistance heating element, but is not limited to the thin film heater 21 and may be a Peltier element, for example.
  • variable capacitor 10 may include a temperature sensor 60 for detecting the temperature of the capacitor portion 20a in the capacitor element 20 in the thin film layer 50 (see FIG. 3A).
  • the variable capacitor 10 is controlled by a control circuit provided separately, for example.
  • the control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60.
  • the temperature sensor 60 is configured to be provided on the surface protective layer 19 in the upward direction of the air gap 30 (the Z-axis arrow direction).
  • the temperature sensor 60 may be provided in the interlayer insulating film 18 in the vicinity of the thin film heater 21.
  • the temperature sensor 60 is preferably provided above the gap 30. By providing the temperature sensor 60 above the gap 30, the detection sensitivity can be increased.
  • the temperature sensor 60 is not limited to this configuration, and may be in the thin film layer 50.
  • the thin film heater 21 may have the function of the temperature sensor 60.
  • the thin film heater 21 is disposed in a layer opposite to the substrate 11 from the capacitor portion 20a (a layer made of the interlayer insulating film 18 and the surface protective layer 19), but the thin film heater 21 is connected to the capacitor portion 20a. You may arrange
  • the thin film heater 21 may be disposed in the support layer 12 as shown in FIG. 3B, for example. Alternatively, the thin film heater 21 may be provided in the dielectric layer 16 of the capacitor unit 20a. That is, the thin film heater 21 only needs to be provided in the thin film layer 50.
  • variable capacitor 10A according to the present embodiment will be described with reference to FIGS. 4A to 5F with a focus on differences from the first embodiment.
  • the variable capacitor 10A according to the present embodiment is different from the variable capacitor 10 according to the first embodiment in the position where the thin film heater 21 is provided.
  • Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • the variable capacitor 10 ⁇ / b> A of this embodiment includes a substrate 11, a support layer 12, an interlayer, in addition to the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16.
  • An insulating film 18 and a thin film heater 21 are provided.
  • the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
  • the substrate 11 is the lowermost part, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, and the interlayer insulating film 18 are arranged in this order.
  • the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, and the interlayer insulating film 18 form a thin film layer 50.
  • the thickness of the thin film layer 50 is several ⁇ m.
  • the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined.
  • FIGS. 4A and 4B arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10A of the present embodiment.
  • the central part of the substrate 11 of this embodiment has a rectangular gap 30 penetrating in the thickness direction.
  • the cross section of the gap 30 in the Z-axis direction has a trapezoidal shape.
  • the main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane.
  • the thin film heater 21 is provided on the first adhesion layer 13 in the same manner as the first electrode 14 of the capacitor element 20.
  • the heater portion 215 of the thin film heater 21 is formed in a meandering shape.
  • the heater portion 215 of the thin film heater 21 is provided above the gap 30 of the substrate 11 and around the capacitor portion 20a (particularly, the first electrode 14).
  • the thin film heater 21 is heated by electrically connecting the first pad electrode 211 and the second pad electrode 212 to a power source. By heating the periphery of the capacitor portion 20 a by the thin film heater 21, the heat generated by the thin film heater 21 is transmitted to the dielectric layer 16.
  • variable capacitor 10A of the present embodiment when a voltage is applied to the first pad electrode 211 and the second pad electrode 212 of the thin film heater 21, the heater unit 215 of the thin film heater 21 generates heat. Heat generated from the heater unit 215 is transmitted to the dielectric layer 16 of the capacitor unit 20a. Here, since the heater portion 215 is provided around the first electrode 14, heat is transferred from the periphery of the dielectric layer 16 to the dielectric layer 16. In the capacitor unit 20a, the capacitance is changed according to the temperature of the dielectric layer 16. In the variable capacitor 10A, the voltage applied to the thin film heater 21 is adjusted, so that the capacitance of the capacitor unit 20a is adjusted.
  • the heater unit 215 of the thin film heater 21 of the present embodiment changes the capacitance of the capacitor unit 20a by being controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor unit 20a to be equal to or higher than the Curie temperature. It is preferable to make it.
  • variable capacitor 10A Next, a method for manufacturing the variable capacitor 10A according to the present embodiment will be described with reference to FIGS. 5A to 5F.
  • a SiO 2 film is formed on the main surface 111 on the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD, whereby a laminated film of the SiO 2 film and the Si 3 N 4 film is formed.
  • a support layer 12 is formed (see FIG. 5A).
  • the first adhesion layer 13 is formed on the support layer 12 by sputtering, for example.
  • the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees.
  • the first conductive layer 100 that is the basis of the first electrode 14 and the thin film heater 21 is formed on the first adhesion layer 13 by, for example, sputtering.
  • the insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 100 by spin coating and baking at 600 to 700 degrees.
  • the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering.
  • the adhesion layer 17a is formed on the second conductive layer 15a by sputtering, for example (see FIG. 5B).
  • the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by a spin coating method and baking at 600 to 700 degrees.
  • the first electrode 14, the thin film heater 21, the dielectric layer 16, and the second electrode 15 are patterned by patterning the first conductive layer 100, the insulating layer 16 a, the second conductive layer 15 a, and the adhesion layer 17 a using a photolithography technique and an etching technique. Then, the second adhesion layer 17 and the like are formed (see FIG. 5C).
  • an interlayer insulating film 18 is formed by CVD or sputtering so as to cover the capacitor element 20 (see FIG. 5D).
  • a first opening 31 extending from the interlayer insulating film 18 to the first electrode 14 and a second opening 32 extending from the surface protective layer 19 to the second electrode 15 are formed by photolithography and reactive ion etching (RIE).
  • RIE reactive ion etching
  • the first electrode 14 and a part of the second electrode 15 are exposed.
  • the exposed portion of the first electrode 14 becomes the first pad electrode 20b
  • the exposed portion of the second electrode 15 becomes the second pad electrode 20c (see FIG. 5E).
  • a third opening 33 and a fourth opening 34 from the interlayer insulating film 18 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed.
  • a portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211
  • a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
  • the space 30 is formed by etching the region where the space 30 is to be formed from the back surface of the substrate 11 (see FIG. 5F).
  • an inductively coupled plasma (ICP) type dry etching apparatus or RIE apparatus is preferably used.
  • the gap 30 may be formed by etching with an alkaline solution (for example, a TMAH solution, a KOH aqueous solution, or the like) from the back surface of the substrate 11.
  • variable capacitor 10A is manufactured through the above steps.
  • the thin film heater 21 is disposed around the first electrode 14 of the capacitor element 20. However, the thin film heater 21 is disposed around the dielectric layer 16 or the second electrode 15 of the capacitor element 20. May be.
  • variable capacitor 10A similarly to the first embodiment, the variable capacitor 10A includes the thin film heater 21 as a resistance heating element, but is not limited to the thin film heater 21, and a Peltier element, for example, may be used.
  • variable capacitor 10 ⁇ / b> A may include the temperature sensor 60 for detecting the temperature of the capacitor element 20 in the thin film layer 50.
  • the variable capacitor 10A is controlled by, for example, a separately provided control circuit.
  • the control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60.
  • the thin film heater 21 may have the function of the temperature sensor 60.
  • the thin film heater 21 is provided around the capacitor element 20 (particularly, the first electrode 14). Thereby, the temperature in the dielectric layer 16 in the capacitor portion 20a can be made uniform.
  • variable capacitor 10B (Embodiment 3) A variable capacitor 10B according to the present embodiment will be described with reference to FIGS. 6A to 7I, focusing on differences from the first embodiment.
  • the variable capacitor 10B of the present embodiment is different from the variable capacitor 10 of the first embodiment in that the support layer 12 is formed in a beam structure. Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • the variable capacitor 10 ⁇ / b> B of this embodiment includes a substrate 11, a support layer 12, an interlayer, in addition to the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16.
  • An insulating film 18, a surface protective layer 19, and a thin film heater 21 are provided.
  • the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
  • the substrate 11 is the bottom, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the thin film
  • the heater 21 and the surface protective layer 19 are laminated in this order.
  • a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19.
  • the thickness of the thin film layer 50 is several ⁇ m.
  • the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined.
  • FIGS. 6A and 6B arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10B of the present embodiment.
  • the capacitor element 20 includes a capacitor portion 20a, a first pad electrode 20b, a second pad electrode 20c, a first wiring portion 20d, and a second wiring portion 20e (see FIG. 6A).
  • the first electrode 14, the dielectric layer 16, and the second electrode 15 are also formed on the portion that becomes the first wiring portion 20 d between the capacitor portion 20 a and the first pad electrode 20 b. Assume that the laminated structure extends. Similarly, it is assumed that the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 extends to a portion that becomes the second wiring portion 20 e between the capacitor portion 20 a and the second pad electrode 20 c.
  • the first wiring portion 20d may not include the dielectric layer 16 and the second electrode 15. Similarly, the first wiring 14 and the dielectric layer 16 may not be provided in the second wiring portion 20e.
  • the substrate 11 is provided with a quadrangular pyramid-shaped gap 30 from the main surface 111 in the direction opposite to the Z-axis direction.
  • the main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane.
  • a support layer 12 is provided on the main surface 111.
  • the support layer 12 includes a support portion 12a, a holding portion 12b provided on the inside thereof, and four beam portions 12c to 12f that connect the support portion 12a and the holding portion 12b.
  • the outer and inner shapes of the support portion 12a are formed in a square shape.
  • the holding portion 12b and the beam portions 12c to 12f are exposed by the gap 30.
  • the holding unit 12b holds at least the capacitor unit 20a of the capacitor element 20. Specifically, the first adhesion layer 13, the capacitor part 20 a, the second adhesion layer 17, the interlayer insulating film 18, the heater part 215 of the thin film heater 21, and the surface protection layer 19 are laminated on the holding part 12 b. .
  • the first wiring portion 20d is at least stacked on the beam portion 12c (see FIG. 6A).
  • the first contact layer 13, the second contact layer 17, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the beam portion 12 c in addition to the first wiring portion 20 d.
  • the beam portion 12c is provided between a first opening 31 and a holding portion 12b described later.
  • At least the second wiring part 20e is laminated on the beam part 12e (see FIG. 6A).
  • the first adhesive layer 13, the second adhesive layer 17, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the beam portion 12e in addition to the second wiring portion 20e.
  • the beam portion 12e is provided between a holding portion 12b and a second opening portion 32 (described later) in a direction opposite to the first opening portion 31.
  • At least the first pad electrode 20b is laminated on the first corner portion 122 of the support portion 12a (see FIG. 6A).
  • the first adhesion layer 13, the dielectric layer 16, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the first corner portion 122.
  • the second pad electrode 20c is stacked on the second corner 123 of the support 12a (see FIG. 6A).
  • the second corner portion 123 includes, in addition to the second pad electrode 20c, the first adhesion layer 13, the first electrode 14 (first electrode portion), the second adhesion layer 17, the interlayer insulating film 18, and the surface.
  • a protective layer 19 is laminated.
  • first corner portion 122 is provided with a first opening 31 from the surface protective layer 19 to the first pad electrode 20b (see FIG. 6A).
  • second corner 123 a second opening 32 extending from the surface protective layer 19 to the second pad electrode 20c is provided (see FIG. 6A).
  • At least a wiring portion 213 of the thin film heater 21 is laminated on the beam portion 12d (see FIG. 6A).
  • a first adhesion layer 13, an interlayer insulating film 18, and a surface protection layer 19 are stacked on the beam portion 12 d in addition to the wiring portion 213.
  • the beam portion 12d is provided between a third opening 33 and a holding portion 12b, which will be described later.
  • At least a wiring portion 214 of the thin film heater 21 is laminated on the beam portion 12f (see FIG. 6A).
  • the first adhesive layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked in addition to the wiring portion 214 on the beam portion 12 f.
  • the beam portion 12f is provided between a holding portion 12b and a fourth opening portion 34 (described later) opposite to the third opening portion 33.
  • At least the first pad electrode 211 is stacked on the third corner portion 124 of the support portion 12a (see FIG. 6A).
  • the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the third corner portion 124.
  • At least the second pad electrode 212 is laminated on the fourth corner portion 125 of the support portion 12a (see FIG. 6A).
  • the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the fourth corner portion 125.
  • a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 is provided in the third corner portion 124 (see FIG. 6A).
  • a fourth opening 34 extending from the surface protective layer 19 to the second pad electrode 212 is provided in the fourth corner 125 (see FIG. 6A).
  • components other than the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are omitted in the beam portion 12c and the beam portion 12d.
  • variable capacitor 10 has a plurality of through holes 40 extending from the surface protective layer 19 to the air gap 30 of the substrate 11.
  • maintenance part 12b can be thermally insulated from the board
  • maintenance part 12b is several hundred micrometers. Since the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19 is several ⁇ m with respect to a length of several hundred ⁇ m in the X-axis direction, the heat generated from the thin film heater 21 is supported by the support portion 12a. It is easier to be transmitted to the dielectric layer 16 than the layers stacked on each other.
  • the heater unit 215 of the thin film heater 21 of the present embodiment changes the capacitance of the capacitor unit 20a by being controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor unit 20a to be equal to or higher than the Curie temperature. It is preferable to make it.
  • variable capacitor 10 of the present embodiment Next, a method for manufacturing the variable capacitor 10 of the present embodiment will be described with reference to FIGS. 7A to 7I.
  • a SiO 2 film is formed on the main surface 111 of the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD, so that a laminated film of the SiO 2 film and the Si 3 N 4 film is formed.
  • a support layer 12 is formed (see FIG. 7A).
  • the first adhesion layer 13 is formed on the support layer 12 by sputtering, for example.
  • the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees.
  • the first conductive layer 14a that is the basis of the first electrode 14 is formed on the first adhesion layer 13 by, for example, sputtering.
  • the insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 14a by spin coating and baking at 600 to 700 degrees. Thereafter, the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering. Next, the adhesion layer 17a is formed on the second conductive layer 15a by, for example, sputtering (see FIG. 7B). Alternatively, the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by spin coating and baking at 600 to 700 degrees.
  • the first electrode 14, the second electrode 15, the dielectric layer 16, and the second adhesion layer are patterned.
  • Layer 17 and the like are formed (see FIG. 7C).
  • an interlayer insulating film 18 is formed by CVD or sputtering so as to cover the capacitor element 20 (see FIG. 7D).
  • a platinum film 21a serving as a base of the thin film heater 21 is formed on the interlayer insulating film 18 by sputtering (see FIG. 7E).
  • the thin film heater 21 is formed by patterning the platinum film 21a by a photolithography technique and an etching technique (see FIG. 7F). Next, the surface protective layer 19 is formed by CVD or sputtering so as to cover the thin film heater 21 (see FIG. 7G).
  • a plurality of through holes 40 extending from the surface protective layer 19 to the substrate 11 are formed by photolithography technology and reactive ion etching (RIE) (see FIG. 7H).
  • RIE reactive ion etching
  • a first opening 31 extending from the surface protective layer 19 to the first electrode 14 and a second opening 32 extending from the surface protective layer 19 to the second electrode 15 are formed, and the first electrode 14 and the second electrode 15 are formed.
  • a third opening 33 and a fourth opening 34 extending from the surface protective layer 19 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed.
  • a portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211, and a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
  • the space 30 is formed by etching the region where the space 30 is to be formed in the substrate 11 from the main surface 111 of the substrate 11 (see FIG. 7I).
  • Etching of the substrate 11 is performed by, for example, performing crystal anisotropic etching from the main surface 111 of the substrate 11 through the plurality of through holes 40 by wet using an alkaline solution (for example, TMAH solution, KOH aqueous solution, etc.). 30 is desirable.
  • an alkaline solution for example, TMAH solution, KOH aqueous solution, etc.
  • variable capacitor 10B is manufactured through the above steps.
  • variable capacitor 10B includes the thin film heater 21 as a resistance heating element as in the first embodiment.
  • the present invention is not limited to the thin film heater 21, and a Peltier element, for example, may be used.
  • variable capacitor 10B may include the temperature sensor 60 for detecting the temperature of the capacitor unit 20a in the thin film layer 50.
  • the variable capacitor 10B is controlled by, for example, a separately provided control circuit.
  • the control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60.
  • the thin film heater 21 may have the function of the temperature sensor 60.
  • the thin film heater 21 is arranged in a layer opposite to the direction of the substrate 11 from the capacitor unit 20a. However, the thin film heater 21 is disposed in a layer between the capacitor unit 20a and the substrate 11, for example, in the support layer 12. It may be arranged. Or the thin film heater 21 may be arrange
  • variable capacitor 10C A variable capacitor 10C according to the present embodiment will be described with reference to FIGS. 8A to 9D, focusing on differences from the first embodiment.
  • the variable capacitor 10C according to the present embodiment is different from the variable capacitor 10 according to the first embodiment in that a part of the substrate 11 is formed of a porous layer. Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • variable capacitor 10C of the present embodiment uses the capacitance of the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16 as the dielectric layer. It is made to change by adjusting the temperature of 16.
  • the variable capacitor 10 ⁇ / b> C includes a substrate 11, a support layer 12, an interlayer insulating film 18, a surface protective layer 19, and a thin film heater 21 (temperature adjusting element) )have.
  • the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
  • the substrate 11 is the lowermost part, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the thin film
  • the heater 21 and the surface protective layer 19 are laminated in this order.
  • a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19.
  • the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19, that is, the thickness of the thin film layer 50 is several ⁇ m.
  • the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined.
  • Yes. 8A and 8B show arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction, but these arrows are merely shown for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10 of the present embodiment.
  • the substrate 11 is a semiconductor substrate, and has a rectangular parallelepiped porous layer 30a in the thickness direction from the main surface 111 at the central portion thereof.
  • the main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane.
  • the thickness (length in the Z-axis direction) of the porous layer 30a is, for example, 10 ⁇ m.
  • this numerical value is an example and is not the meaning limited to this numerical value.
  • the porous layer 30a is located below the first electrode 14 of the capacitor element 20 (the direction opposite to the Z-axis arrow). From the viewpoint of thermally insulating the capacitor portion 20a and the substrate 11, when the variable capacitor 10 is viewed in the direction from the surface protective layer 19 to the substrate 11, the capacitor portion 20a and the porous layer 30a of the capacitor element 20 are It is preferable that the capacitor portion 20a is defined so as to overlap.
  • the support layer 12 is composed of a laminated film of a SiO 2 film on the substrate 11 and a Si 3 N 4 film on the SiO 2 film.
  • the surface (back surface 121) opposite to the surface on which the capacitor element 20 is provided is in contact with the porous layer 30a (see FIG. 8B).
  • the first adhesive layer 13, the capacitor element 20, the second adhesive layer 17, the interlayer insulating film 18, the surface protective layer 19, and the thin film heater 21 are the same as those in the first embodiment, the description thereof is omitted here.
  • variable capacitor 10C includes a first opening 31 extending from the surface protective layer 19 to the first pad electrode 20b, and a second opening extending from the surface protective layer 19 to the second pad electrode 20c. An opening 32 is further provided. By electrically connecting the first pad electrode 20b and the second pad electrode 20c to a power source, charges are accumulated in the capacitor unit 20a.
  • variable capacitor 10 ⁇ / b> C includes a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 of the thin film heater 21, and a second pad of the thin film heater 21 from the surface protective layer 19.
  • a fourth opening 34 reaching the electrode 212 is further provided.
  • the relative permittivity of the dielectric layer 16 changes as the temperature changes. Therefore, the capacitance of the capacitor element 20 is changed by the temperature of the dielectric layer 16 being changed by the heat transmitted from the thin film heater 21. In other words, the capacitance of the capacitor element 20 changes according to the temperature of the dielectric layer 16.
  • the capacitance applied to the capacitor element 20 is adjusted by adjusting the voltage applied to the thin film heater 21. In order to adjust the capacitance of the capacitor element 20, it is only necessary that the heater unit 215 can generate Joule heat. Therefore, the amount of current flowing through the thin film heater 21 may be adjusted.
  • the heater portion 215 of the thin film heater 21 is controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor portion 20a to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material. Thus, it is preferable to change the capacitance of the capacitor portion 20a.
  • variable capacitor 10C Next, a method for manufacturing the variable capacitor 10C according to the present embodiment will be described with reference to FIGS. 9A to 9D.
  • a current-carrying electrode 300 is attached on the main surface 111 of the substrate 11 (see FIG. 9A).
  • a porous layer 30a is formed by anodizing the substrate 11 to which the energizing electrode 300 is attached (see FIG. 9B).
  • the substrate 11 to which the energizing electrode 300 is attached is immersed in an electric field solution, and a platinum electrode is disposed so as to face the surface 112 opposite to the main surface 111.
  • the positive electrode side of the current source is connected to the energizing electrode 300, and the negative electrode side is connected to the platinum electrode.
  • a current having a predetermined current density is allowed to flow from the current source between the energization electrode and the platinum electrode for a predetermined time. Further, in order to increase the porosity, each of the specific resistance and current density of the substrate 11 may be increased.
  • the porosity of the porous layer 30a can be set to 5% to 80%.
  • the average pore diameter of the porous layer 30a can be set to 0.1 ⁇ m to 3 ⁇ m.
  • the energizing electrode 300 is removed (see FIG. 9C).
  • a SiO 2 film is formed on the main surface 111 on the substrate 11 from which the energizing electrode 300 has been removed by a thermal oxidation method, and then an Si 3 N 4 film is formed by LPCVD, whereby the SiO 2 film and the Si 3 film are formed.
  • a support layer 12 made of a laminated film with an N 4 film is formed (see FIG. 9D).
  • variable capacitor 10C is manufactured through the above steps.
  • variable capacitor 10C includes the thin film heater 21 as a resistance heating element.
  • the variable capacitor 10C is not limited to the thin film heater 21 and may be a Peltier element, for example.
  • variable capacitor 10 ⁇ / b> C may include a temperature sensor 60 for detecting the temperature of the capacitor unit 20 a in the capacitor element 20 in the thin film layer 50, as in the first embodiment.
  • the variable capacitor 10C is controlled by a control circuit provided separately, for example.
  • the control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60.
  • the thin film heater 21 may have the function of the temperature sensor 60.
  • the thin film heater 21 is disposed in a layer opposite to the substrate 11 from the capacitor portion 20a (a layer made of the interlayer insulating film 18 and the surface protective layer 19), but the thin film heater 21 is connected to the capacitor portion 20a. You may arrange
  • the thin film heater 21 may be disposed in the support layer 12.
  • the thin film heater 21 may be provided in the dielectric layer 16 of the capacitor unit 20a. That is, the thin film heater 21 only needs to be provided in the thin film layer 50.
  • the substrate 11 provided in the variable capacitor 10C of the present embodiment is a semiconductor substrate, but is not limited to a semiconductor substrate, and may be a substrate made of ceramic or the like.
  • the present invention is not limited to this, and the entire substrate 11 may be formed as the porous layer 30a.
  • variable capacitor 10C of the present embodiment forms a porous layer 30a instead of the gap 30 of the variable capacitor 10 of the first embodiment.
  • a porous layer 30a may be formed instead of the gap 30 of the variable capacitor 10A of the second embodiment, or a porous layer 30a may be formed instead of the gap 30 of the variable capacitor 10B of the third embodiment. May be.
  • variable capacitor 10 (10A, 10B, 10C) of the first aspect includes the substrate 11, the capacitor unit 20a, the thin film layer 50, and the temperature adjusting element (thin film heater 21).
  • the capacitor unit 20 a includes the first electrode 14, the second electrode 15, and the dielectric layer 16 provided between the first electrode 14 and the second electrode 15, and is provided on the substrate 11.
  • the thin film layer 50 covers the capacitor portion 20a.
  • the temperature adjusting element adjusts the temperature of the dielectric layer 16 to change the capacitance of the capacitor unit 20a.
  • variable capacitor 10 (10A, 10B, 10C) since the relative dielectric constant of the dielectric layer 16 depends on the temperature, the capacitance of the capacitor element is changed by changing the temperature. Can be made.
  • the substrate 11 has a gap 30 in the first aspect.
  • the thin film layer 50 is disposed between the substrate 11 and the capacitor portion 20a, and has a support layer 12 that supports the capacitor portion 20a.
  • the surface opposite to the surface on which the capacitor portion 20 a is laminated is exposed from the gap 30.
  • the capacitor unit 20 a overlaps the air gap 30, so that the heat generated by the thin film heater 21 passes through the substrate 11. It becomes difficult to escape. Further, by providing the support layer 12, the residual stress of the layer (thin film) laminated on the support layer 12 can be adjusted.
  • the substrate 11 has the porous layer 30a.
  • the thin film layer 50 is disposed between the substrate 11 and the capacitor portion 20a, and has a support layer 12 that supports the capacitor portion 20a.
  • the surface opposite to the surface on which the capacitor portion 20a is laminated is in contact with the porous layer 30a.
  • the strength of the substrate 11 is increased as compared with the case where the air gap 30 is provided in the substrate 11. Since the capacitor portion 20a overlaps the porous layer 30a, the heat generated by the thin film heater 21 is difficult to escape via the substrate 11 other than the porous layer 30a. Further, by providing the support layer 12, the residual stress of the layer (thin film) laminated on the support layer 12 can be adjusted.
  • the substrate 11 is a semiconductor substrate.
  • the substrate 11 can be easily processed, and the substrate 11 can be formed at a time, so that the manufacturing cost can be reduced.
  • variable capacitor 10 (10A, 10B, 10C) of the fifth aspect
  • the temperature adjusting element is provided in the thin film layer 50 in any of the first to fourth aspects.
  • the temperature adjustment element is a resistance heating element.
  • the formation by the semiconductor processing technology is facilitated, and the thin film heater 21 can be formed at a time, so that the manufacturing cost can be suppressed.
  • the dielectric layer 16 is a ferroelectric substance.
  • the temperature adjustment element changes the capacitance of the capacitor portion 20a by controlling the temperature of the dielectric layer 16 to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material.
  • variable capacitor 10 (10A, 10B, 10C) of the eighth aspect further includes a temperature sensor 60 for detecting the temperature of the capacitor unit 20a in any one of the first to seventh aspects.
  • the voltage applied to the thin film heater 21 can be adjusted based on the detection result. That is, the temperature of the dielectric layer 16 can be adjusted by adjusting the heat generated by the thin film heater 21 based on the detection result.

Abstract

Provided is a variable capacitor, the capacitance of which can be changed without using a driving mechanism or a switch. A variable capacitor (10) comprises a substrate (11), a capacitor unit (20a), a thin film layer (50), and a thin film heater (21). The capacitor unit (20a) has a first electrode (14), a second electrode (15), and a dielectric layer (16) provided between the first electrode (14) and the second electrode (15), and is provided on the substrate (11). The thin film layer (50) covers the capacitor unit (20a). The thin film heater (21) changes the capacitance of the capacitor unit (20a) by adjusting the temperature of the dielectric layer (16).

Description

可変容量コンデンサVariable capacitor
 本発明は、可変容量コンデンサに関し、より詳細には、静電容量を変更させることができる可変容量コンデンサに関する。 The present invention relates to a variable capacitor, and more particularly to a variable capacitor that can change capacitance.
 従来、コンデンサの静電容量を可変にする可変容量コンデンサシステムがある(例えば、特許文献1)。 Conventionally, there is a variable capacitor system that makes the capacitance of a capacitor variable (for example, Patent Document 1).
 特許文献1に記載された可変容量コンデンサシステムは、静電容量を可変にする駆動機構を有する可変容量コンデンサと、複数の固定容量コンデンサとを電気的に連絡する複数のスイッチを備えている。可変容量コンデンサシステムは、複数のスイッチの開閉を制御することで、可変容量コンデンサと、複数の固定容量コンデンサとの組み合わせを変更して、全体的な静電容量を変更する。 The variable capacitor system described in Patent Document 1 includes a variable capacitor having a drive mechanism that makes the capacitance variable, and a plurality of switches that electrically connect the plurality of fixed capacitors. The variable capacitor system changes the overall capacitance by changing the combination of a variable capacitor and a plurality of fixed capacitors by controlling the opening and closing of the plurality of switches.
 特許文献1の可変容量コンデンサでは、駆動機構により静電容量を変更させたり、固定容量コンデンサとの組み合わせにより全体的な静電容量を変更したりしている。そのため、駆動機構に異物等が混入した場合には所望する静電容量に変更できない可能性がある。また、スイッチを用いた場合であっても接点の動作の信頼性が低い場合には、所望する静電容量に変更できない可能性がある。そこで、従来の可変容量コンデンサとは異なる方法で静電容量を変えることが望まれている。 In the variable capacitor disclosed in Patent Document 1, the capacitance is changed by a driving mechanism, or the overall capacitance is changed by a combination with a fixed capacitor. Therefore, there is a possibility that the capacitance cannot be changed to a desired capacitance when foreign matter or the like is mixed into the drive mechanism. Further, even when a switch is used, if the operation reliability of the contact is low, there is a possibility that it cannot be changed to a desired capacitance. Therefore, it is desired to change the capacitance by a method different from that of the conventional variable capacitor.
特許第4300865号公報Japanese Patent No. 4300805
 本発明は上記事由に鑑みてなされており、駆動機構及びスイッチを用いることなく静電容量を変更することができる可変容量コンデンサを提供することを目的とする。 The present invention has been made in view of the above reasons, and an object thereof is to provide a variable capacitor capable of changing the capacitance without using a drive mechanism and a switch.
 本発明に係る第1の態様の可変容量コンデンサは、基板と、コンデンサ部と、薄膜層と、温度調整素子とを備える。前記コンデンサ部は、第1電極、第2電極及び前記第1電極と前記第2電極との間に設けられた誘電体層とを有し、前記基板に設けられている。前記薄膜層は、前記コンデンサ部を覆う。前記温度調整素子は、前記誘電体層の温度を調整して前記コンデンサ部の静電容量を変更させる。 The variable capacitor according to the first aspect of the present invention includes a substrate, a capacitor portion, a thin film layer, and a temperature adjustment element. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer provided between the first electrode and the second electrode, and is provided on the substrate. The thin film layer covers the capacitor portion. The temperature adjusting element adjusts the temperature of the dielectric layer to change the capacitance of the capacitor unit.
 本発明に係る第2の態様の可変容量コンデンサでは、第1の態様において、前記基板は、空隙を有している。前記薄膜層は、前記基板と前記コンデンサ部との間に配置され、前記コンデンサ部を支持する支持層を有している。前記支持層において、前記コンデンサ部が積層される面とは反対の面が、前記空隙から露出している。 In the variable capacitor of the second aspect according to the present invention, in the first aspect, the substrate has a gap. The thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit. In the support layer, a surface opposite to the surface on which the capacitor portion is laminated is exposed from the gap.
 本発明に係る第3の態様の可変容量コンデンサでは、第1の態様において、前記基板は、多孔質層を有している。前記薄膜層は、前記基板と前記コンデンサ部との間に配置され、前記コンデンサ部を支持する支持層を有している。前記支持層において、前記コンデンサ部が積層される面とは反対の面が、前記多孔質層に接している。 In the variable capacitor according to the third aspect of the present invention, in the first aspect, the substrate has a porous layer. The thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit. In the support layer, the surface opposite to the surface on which the capacitor portion is laminated is in contact with the porous layer.
 本発明に係る第4の態様の可変容量コンデンサでは、第1~第3のいずれかの態様において、前記基板は、半導体基板である。 In the variable capacitor according to the fourth aspect of the present invention, in any one of the first to third aspects, the substrate is a semiconductor substrate.
 本発明に係る第5の態様の可変容量コンデンサでは、第1~第4のいずれかの態様において、前記温度調整素子は、前記薄膜層に設けられている。 In the variable capacitor of the fifth aspect according to the present invention, in any of the first to fourth aspects, the temperature adjusting element is provided in the thin film layer.
 本発明に係る第6の態様の可変容量コンデンサでは、第1~第5のいずれかの態様において、前記温度調整素子は、抵抗加熱素子である。 In the variable capacitor according to the sixth aspect of the present invention, in any one of the first to fifth aspects, the temperature adjustment element is a resistance heating element.
 本発明に係る第7の態様の可変容量コンデンサでは、第1~第6のいずれかの態様において、前記誘電体層は、強誘電体である。前記温度調整素子は、前記誘電体層の温度を前記誘電体層が強誘電体から常誘電体に変化するキュリー温度以上に調整するように制御されることで、前記コンデンサ部の静電容量を変化させる。 In the variable capacitor according to the seventh aspect of the present invention, in any one of the first to sixth aspects, the dielectric layer is a ferroelectric. The temperature adjusting element is controlled so that the temperature of the dielectric layer is adjusted to be equal to or higher than a Curie temperature at which the dielectric layer changes from a ferroelectric material to a paraelectric material. Change.
 本発明に係る第8の態様の可変容量コンデンサは、第1~第7のいずれかの態様において、前記コンデンサ部の温度を検出する温度センサを、更に備える。 The variable capacitor of the eighth aspect according to the present invention further comprises a temperature sensor for detecting the temperature of the capacitor part in any one of the first to seventh aspects.
 この発明によると、誘電体層の温度を変化させることで、誘電体層の比誘電率を変えることができ、その結果、コンデンサ部の静電容量を変更させることができる。 According to the present invention, the dielectric constant of the dielectric layer can be changed by changing the temperature of the dielectric layer, and as a result, the capacitance of the capacitor unit can be changed.
図1Aは、本発明の実施形態1に係る可変容量コンデンサの平面図であり、図1Bは、同上の可変容量コンデンサのA-A線断面図である。FIG. 1A is a plan view of a variable capacitor according to Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of the same variable capacitor. 図2A~図2Iは、同上の可変容量コンデンサの製造工程を説明するための断面図である。2A to 2I are cross-sectional views for explaining a manufacturing process of the variable capacitor described above. 図3A、図3Bは、同上の可変容量コンデンサの変形例を説明するための断面図である。3A and 3B are cross-sectional views for explaining a modification of the variable capacitor described above. 図4Aは、本発明の実施形態2に係る可変容量コンデンサの平面図であり、図4Bは、同上の可変容量コンデンサのB-B線断面図である。FIG. 4A is a plan view of a variable capacitor according to Embodiment 2 of the present invention, and FIG. 4B is a cross-sectional view taken along the line BB of the variable capacitor of the above. 図5A~図5Fは、同上の可変容量コンデンサの製造工程を説明するための断面図である。FIG. 5A to FIG. 5F are cross-sectional views for explaining the manufacturing process of the variable capacitor described above. 図6Aは、本発明の実施形態3に係る可変容量コンデンサの平面図であり、図6Bは、同上の可変容量コンデンサのC-C線断面図である。6A is a plan view of a variable capacitor according to Embodiment 3 of the present invention, and FIG. 6B is a cross-sectional view taken along the line CC of the variable capacitor according to the third embodiment. 図7A~図7Iは、同上の可変容量コンデンサの製造工程を説明するための断面図である。FIG. 7A to FIG. 7I are cross-sectional views for explaining the manufacturing process of the variable capacitor described above. 図8Aは、本発明の実施形態4に係る可変容量コンデンサの平面図であり、図8Bは、同上の可変容量コンデンサのD-D線断面図である。FIG. 8A is a plan view of a variable capacitor according to Embodiment 4 of the present invention, and FIG. 8B is a cross-sectional view of the variable capacitor taken along the line DD of the same. 図9A~図9Dは、同上の可変容量コンデンサの製造工程を説明するための断面図である。9A to 9D are cross-sectional views for explaining a manufacturing process of the variable capacitor described above.
 以下に説明する構成は本発明の一例に過ぎない。本発明は、下記の実施形態1~4に限定されず、本発明に係る技術的思想を逸脱しない範囲であれば、設計等に応じて種々の変更が可能である。また、下記の実施形態1~4において、説明する各図は、模式的な図であり、図中の各構成要素の大きさや厚さそれぞれの比が必ずしも実際の寸法比を反映しているとは限らない。 The configuration described below is merely an example of the present invention. The present invention is not limited to the following first to fourth embodiments, and various modifications can be made according to the design or the like as long as they do not depart from the technical idea of the present invention. In the following first to fourth embodiments, each drawing to be described is a schematic diagram, and the ratio of the size and thickness of each component in the drawing necessarily reflects the actual dimensional ratio. Is not limited.
 (実施形態1)
 以下、実施形態に係る可変容量コンデンサ10について、図1A~図2Iを参照して説明する。
(Embodiment 1)
Hereinafter, a variable capacitor 10 according to an embodiment will be described with reference to FIGS. 1A to 2I.
 本実施形態の可変容量コンデンサ10は、第1電極14、第2電極15及び誘電体層16を有するコンデンサ素子20の静電容量を、誘電体層16の温度を調整することで変更させる。 The variable capacitor 10 of the present embodiment changes the capacitance of the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16 by adjusting the temperature of the dielectric layer 16.
 本実施形態の可変容量コンデンサ10は、例えば、非接触通信装置、ワイヤレス給電システム、共振回路等のインピーダンス調整に用いられる。 The variable capacitor 10 according to the present embodiment is used for impedance adjustment of, for example, a non-contact communication device, a wireless power feeding system, a resonance circuit, and the like.
 可変容量コンデンサ10は、図1A,1Bに示すように、コンデンサ素子20に加えて、基板11、支持層12、層間絶縁膜18、表面保護層19及び薄膜ヒータ21(温度調整素子)を有している。可変容量コンデンサ10は、第1密着層13及び第2密着層17を、各々の上下の層の材料に応じて適宜設けてもよい。 As shown in FIGS. 1A and 1B, the variable capacitor 10 includes a substrate 11, a support layer 12, an interlayer insulating film 18, a surface protective layer 19, and a thin film heater 21 (temperature adjustment element) in addition to the capacitor element 20. ing. In the variable capacitor 10, the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
 本実施形態の可変容量コンデンサ10では、基板11を最下部とし、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18、薄膜ヒータ21、表面保護層19の順に積層されている。ここで、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18及び表面保護層19により薄膜層50が形成されている。このとき、支持層12の裏面121から表面保護層19の表面191までの厚さ、つまり薄膜層50の厚さは、数μmである。 In the variable capacitor 10 of the present embodiment, the substrate 11 is the bottom, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, the thin film heater 21, and the surface protection layer 19. Are stacked in this order. Here, a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19. At this time, the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19, that is, the thickness of the thin film layer 50 is several μm.
 本実施形態では、支持層12の表面の中心点を原点として、支持層12の表面において互いに直交するX軸とY軸とを規定し、支持層12の表面に直交するZ軸を規定している。なお、図1A、図1Bには、X軸方向、Y軸方向、Z軸方向を表す矢印を記載しているが、この矢印は、単に説明を補助する目的で記載しているに過ぎず、実体を伴わない。また、上記の方向の規定は、本実施形態の可変容量コンデンサ10の使用形態を限定する趣旨ではない。 In the present embodiment, with the center point of the surface of the support layer 12 as the origin, the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined. Yes. In FIGS. 1A and 1B, arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10 of the present embodiment.
 基板11は、半導体基板であり、例えば単結晶のSi基板である。基板11の主表面111は、(100)面である。基板11は、矩形板状に形成されている。基板11の厚さは、例えば500~600μmである。基板11の中央部位は、厚さ方向に貫通する矩形状の空隙30を有している。 The substrate 11 is a semiconductor substrate, for example, a single crystal Si substrate. The main surface 111 of the substrate 11 is a (100) plane. The substrate 11 is formed in a rectangular plate shape. The thickness of the substrate 11 is, for example, 500 to 600 μm. The central part of the substrate 11 has a rectangular gap 30 penetrating in the thickness direction.
 支持層12は、基板11上のSiO膜(シリコン酸化膜)とSiO膜上のSi膜(シリコン窒化膜)との積層膜からなり、基板11の一の主表面111上に設けられている。上述の基板11には、支持層12において、コンデンサ素子20が設けられる面とは反対の面(上述した裏面121)が露出するように、空隙30が形成されている。 The support layer 12 is a laminated film of a SiO 2 film (silicon oxide film) on the substrate 11 and a Si 3 N 4 film (silicon nitride film) on the SiO 2 film, and is formed on one main surface 111 of the substrate 11. Is provided. In the substrate 11 described above, the air gap 30 is formed so that the surface (back surface 121 described above) opposite to the surface on which the capacitor element 20 is provided in the support layer 12 is exposed.
 第1密着層13は、Ti膜からなる。第1密着層13は、支持層12に積層されており、支持層12と第1電極14との密着性を高める。第1密着層13は、Ti膜に限らず、例えばBST膜((Ba,Sr)TiO膜:チタン酸バリウムストロンチウム膜)で形成されてもよい。 The first adhesion layer 13 is made of a Ti film. The first adhesion layer 13 is laminated on the support layer 12 and enhances the adhesion between the support layer 12 and the first electrode 14. The first adhesion layer 13 is not limited to the Ti film, and may be formed of, for example, a BST film ((Ba, Sr) TiO 3 film: barium strontium titanate film).
 第1密着層13には、第1電極14が積層されている。第1電極14には、誘電体(ここでは、強誘電体)からなる誘電体層16が積層されている。誘電体層16には第2電極15が積層されている。第1電極14は、Pt膜で形成されている。誘電体層16は、BST膜で形成されている。第2電極15は、Pt膜で形成されている。 The first electrode 14 is laminated on the first adhesion layer 13. A dielectric layer 16 made of a dielectric material (here, a ferroelectric material) is laminated on the first electrode 14. A second electrode 15 is laminated on the dielectric layer 16. The first electrode 14 is formed of a Pt film. The dielectric layer 16 is formed of a BST film. The second electrode 15 is formed of a Pt film.
 コンデンサ素子20は、コンデンサ部20aと、第1パッド電極20bと、第2パッド電極20cとを有する。さらに、コンデンサ素子20は、コンデンサ部20aと第1パッド電極20bとの間に第1配線部を、コンデンサ部20aと第2パッド電極20cとの間に第2配線部を、有している。コンデンサ部20aは、第1電極14、誘電体層16及び第2電極15の積層構造のうち支持層12の中央部の上方の部分に相当する。また、第1電極14の露出部分が第1パッド電極20bに相当する。第2電極15の露出部分が第2パッド電極20cに相当する。 The capacitor element 20 includes a capacitor portion 20a, a first pad electrode 20b, and a second pad electrode 20c. Further, the capacitor element 20 has a first wiring portion between the capacitor portion 20a and the first pad electrode 20b, and a second wiring portion between the capacitor portion 20a and the second pad electrode 20c. The capacitor portion 20 a corresponds to a portion above the central portion of the support layer 12 in the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15. The exposed portion of the first electrode 14 corresponds to the first pad electrode 20b. The exposed portion of the second electrode 15 corresponds to the second pad electrode 20c.
 なお、図1Bでは、コンデンサ部20aと第1パッド電極20bとの間の第1配線部となる部分にも第1電極14、誘電体層16及び第2電極15の積層構造が延びているが、第1配線部には誘電体層16及び第2電極15はなくてもよい。同様に、図1Bでは、コンデンサ部20aと第2パッド電極20cとの間の第2配線部となる部分にも第1電極14、誘電体層16及び第2電極15の積層構造が延びているが、第2配線部には第1電極14及び誘電体層16はなくてもよい。 In FIG. 1B, the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 also extends to the portion that becomes the first wiring portion between the capacitor portion 20a and the first pad electrode 20b. The first wiring portion may not have the dielectric layer 16 and the second electrode 15. Similarly, in FIG. 1B, the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 extends to the portion that becomes the second wiring portion between the capacitor portion 20 a and the second pad electrode 20 c. However, the first electrode 14 and the dielectric layer 16 may not be provided in the second wiring portion.
 コンデンサ素子20の第1電極14の下方向(Z軸の矢印とは反対の方向)に空隙30が位置している。コンデンサ部20aと基板11とを熱絶縁する観点からは、表面保護層19から基板11の方向で可変容量コンデンサ10を見た場合に、コンデンサ素子20のうちコンデンサ部20aと空隙30とが重なるように、コンデンサ部20aが規定されることが好ましい。 The gap 30 is located below the first electrode 14 of the capacitor element 20 (the direction opposite to the arrow on the Z axis). From the viewpoint of thermally insulating the capacitor unit 20 a and the substrate 11, the capacitor unit 20 a and the air gap 30 in the capacitor element 20 overlap when the variable capacitor 10 is viewed in the direction from the surface protective layer 19 to the substrate 11. In addition, it is preferable that the capacitor portion 20a is defined.
 第2密着層17は、Ti膜からなり、第2電極15に積層されている。第2密着層17は、層間絶縁膜18と第2電極15との密着性を高める。第2密着層17は、Ti膜に限らず、例えばBST膜で形成されてもよい。 The second adhesion layer 17 is made of a Ti film and is laminated on the second electrode 15. The second adhesion layer 17 enhances the adhesion between the interlayer insulating film 18 and the second electrode 15. The second adhesion layer 17 is not limited to the Ti film, and may be formed of, for example, a BST film.
 層間絶縁膜18は、SiO膜(シリコン酸化膜)からなり、コンデンサ素子20を覆うように設けられている。層間絶縁膜18は、コンデンサ素子20と薄膜ヒータ21との間を電気的に絶縁する。 The interlayer insulating film 18 is made of a SiO 2 film (silicon oxide film) and is provided so as to cover the capacitor element 20. The interlayer insulating film 18 electrically insulates between the capacitor element 20 and the thin film heater 21.
 薄膜ヒータ21は、抵抗加熱素子である、薄膜ヒータ21は、層間絶縁膜18に積層されている。薄膜ヒータ21は、第1パッド電極211、第2パッド電極212、配線部213,214およびヒータ部215を有している。ヒータ部215は、上述したコンデンサ部20aを加熱する。ヒータ部215は、蛇行した形状で形成されている。ヒータ部215は、コンデンサ部20aの上部に設けられている。言い換えると、ヒータ部215は、基板11から熱断熱された位置に設けられている。配線部213は、ヒータ部215と第1パッド電極211とを接続するために設けられている。配線部214は、ヒータ部215と第2パッド電極212とを接続するために設けられている。第1パッド電極211と第2パッド電極212とを電源に電気的に接続することでヒータ部215が加熱される。薄膜ヒータ21のヒータ部215から発せられた熱がコンデンサ部20aの誘電体層16へ伝達される。 The thin film heater 21 is a resistance heating element. The thin film heater 21 is laminated on the interlayer insulating film 18. The thin film heater 21 includes a first pad electrode 211, a second pad electrode 212, wiring portions 213 and 214, and a heater portion 215. The heater unit 215 heats the capacitor unit 20a described above. The heater portion 215 is formed in a meandering shape. The heater part 215 is provided in the upper part of the capacitor | condenser part 20a. In other words, the heater unit 215 is provided at a position where heat insulation is performed from the substrate 11. The wiring part 213 is provided to connect the heater part 215 and the first pad electrode 211. The wiring part 214 is provided to connect the heater part 215 and the second pad electrode 212. The heater part 215 is heated by electrically connecting the first pad electrode 211 and the second pad electrode 212 to a power source. Heat generated from the heater portion 215 of the thin film heater 21 is transmitted to the dielectric layer 16 of the capacitor portion 20a.
 表面保護層19は、SiO膜(シリコン酸化膜)からなり、薄膜ヒータ21を覆うように層間絶縁膜18に積層されている。 The surface protective layer 19 is made of a SiO 2 film (silicon oxide film), and is laminated on the interlayer insulating film 18 so as to cover the thin film heater 21.
 可変容量コンデンサ10は、表面保護層19から第1パッド電極20bに至る第1開口部31と、表面保護層19から第2パッド電極20cに至る第2開口部32とを、更に有している。第1パッド電極20bと第2パッド電極20cとを電源と電気的に接続することで、コンデンサ部20aに電荷が蓄積される。 The variable capacitor 10 further includes a first opening 31 extending from the surface protective layer 19 to the first pad electrode 20b, and a second opening 32 extending from the surface protective layer 19 to the second pad electrode 20c. . By electrically connecting the first pad electrode 20b and the second pad electrode 20c to a power source, charges are accumulated in the capacitor unit 20a.
 さらに、可変容量コンデンサ10は、表面保護層19から薄膜ヒータ21の第1パッド電極211に至る第3開口部33と、表面保護層19から薄膜ヒータ21の第2パッド電極212に至る第4開口部34とを、更に有している。薄膜ヒータ21の第1パッド電極211と第2パッド電極212との間に電圧を印加すると、薄膜ヒータ21は熱を発する。薄膜ヒータ21より発せられた熱は、コンデンサ部20aの誘電体層16に伝達される。このとき、薄膜ヒータ21のヒータ部215はコンデンサ部20aの上方に層間絶縁膜18を介して設けられているので、コンデンサ部20aにおける誘電体層16の全体に熱が伝達される。誘電体層16は、温度が変化すると比誘電率が変化する。そのため、薄膜ヒータ21から伝達された熱により誘電体層16の温度が変化することで、コンデンサ素子20の静電容量が変更する。つまり、コンデンサ素子20では、誘電体層16の温度に応じて静電容量が変更する。可変容量コンデンサ10は、薄膜ヒータ21に印加される電圧が調整されることで、コンデンサ素子20の静電容量が調整される。なお、コンデンサ素子20の静電容量を調整するためには、ヒータ部215がジュール熱を発生できればよいので、薄膜ヒータ21に流れる電流の量を調整してもよい。 Further, the variable capacitor 10 includes a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 of the thin film heater 21, and a fourth opening extending from the surface protective layer 19 to the second pad electrode 212 of the thin film heater 21. And a portion 34. When a voltage is applied between the first pad electrode 211 and the second pad electrode 212 of the thin film heater 21, the thin film heater 21 generates heat. The heat generated from the thin film heater 21 is transmitted to the dielectric layer 16 of the capacitor unit 20a. At this time, since the heater portion 215 of the thin film heater 21 is provided above the capacitor portion 20a via the interlayer insulating film 18, heat is transmitted to the entire dielectric layer 16 in the capacitor portion 20a. The relative permittivity of the dielectric layer 16 changes as the temperature changes. Therefore, the capacitance of the capacitor element 20 is changed by the temperature of the dielectric layer 16 being changed by the heat transmitted from the thin film heater 21. In other words, the capacitance of the capacitor element 20 changes according to the temperature of the dielectric layer 16. In the variable capacitor 10, the capacitance applied to the capacitor element 20 is adjusted by adjusting the voltage applied to the thin film heater 21. In order to adjust the capacitance of the capacitor element 20, it is only necessary that the heater unit 215 can generate Joule heat. Therefore, the amount of current flowing through the thin film heater 21 may be adjusted.
 ここで、薄膜ヒータ21のヒータ部215は、コンデンサ部20aの誘電体層16の温度を誘電体層16が強誘電体から常誘電体に変化するキュリー温度以上に調整するように制御されることで、コンデンサ部20aの静電容量を変化させることが好ましい。 Here, the heater portion 215 of the thin film heater 21 is controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor portion 20a to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material. Thus, it is preferable to change the capacitance of the capacitor portion 20a.
 次に、本実施形態の可変容量コンデンサ10の製造方法について、図2A~図2Iを用いて説明する。 Next, a method for manufacturing the variable capacitor 10 of this embodiment will be described with reference to FIGS. 2A to 2I.
 基板11の主表面111上に、熱酸化法によりSiO膜を形成し、続いて、LPCVD(low pressure chemical vapor deposition)によりSi膜を形成することにより、SiO膜とSi膜との積層膜からなる支持層12を形成する(図2A参照)。支持層12上に、例えばスパッタで第1密着層13を形成する。または、支持層12上に、第1密着層13の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、第1密着層13を形成してもよい。次に、第1密着層13上に第1電極14の元になる第1導電層14aを、例えばスパッタで形成する。第1導電層14a上に誘電体層16の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、絶縁層16aを生成する。その後、絶縁層16a上に第2電極15の元になる第2導電層15aを、例えばスパッタで形成する。次に、第2導電層15a上に、例えばスパッタで密着層17aを形成する(図2B参照)。または、第2導電層15a上に、第2密着層17の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、密着層17aを形成してもよい。 A SiO 2 film is formed on the main surface 111 of the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD (low pressure chemical vapor deposition), whereby the SiO 2 film and the Si 3 N film are formed. A support layer 12 made of a laminated film with four films is formed (see FIG. 2A). The first adhesion layer 13 is formed on the support layer 12 by sputtering, for example. Alternatively, the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees. Next, the first conductive layer 14a that is the basis of the first electrode 14 is formed on the first adhesion layer 13 by, for example, sputtering. The insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 14a by spin coating and baking at 600 to 700 degrees. Thereafter, the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering. Next, the adhesion layer 17a is formed on the second conductive layer 15a by, for example, sputtering (see FIG. 2B). Alternatively, the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by a spin coating method and baking at 600 to 700 degrees.
 第1導電層14a、絶縁層16a、第2導電層15a及び密着層17aをフォトリソグラフィ技術及びエッチング技術によりパターニングすることにより、第1電極14、誘電体層16、第2電極15及び第2密着層17等を形成する(図2C参照)。 By patterning the first conductive layer 14a, the insulating layer 16a, the second conductive layer 15a, and the adhesion layer 17a by a photolithography technique and an etching technique, the first electrode 14, the dielectric layer 16, the second electrode 15, and the second adhesion layer are patterned. Layer 17 and the like are formed (see FIG. 2C).
 その後、コンデンサ素子20を覆うように、層間絶縁膜18をCVD(chemical vapor deposition)又はスパッタで形成する(図2D参照)。次に、層間絶縁膜18上に白金膜21aをスパッタで形成する(図2E参照)。 Thereafter, an interlayer insulating film 18 is formed by CVD (chemical vapor deposition) or sputtering so as to cover the capacitor element 20 (see FIG. 2D). Next, a platinum film 21a is formed on the interlayer insulating film 18 by sputtering (see FIG. 2E).
 白金膜21aをフォトリソグラフィ技術及びエッチング技術によりパターニングすることにより、薄膜ヒータ21を成形する(図2F参照)。次に、薄膜ヒータ21を覆うように表面保護層19をCVD又はスパッタで形成する(図2G参照)。 The thin film heater 21 is formed by patterning the platinum film 21a by a photolithography technique and an etching technique (see FIG. 2F). Next, the surface protective layer 19 is formed by CVD or sputtering so as to cover the thin film heater 21 (see FIG. 2G).
 フォトリソグラフィ技術及び反応性イオンエッチング(RIE)により、表面保護層19から第1電極14に至る第1開口部31及び表面保護層19から第2電極15に至る第2開口部32を形成して、第1電極14及び第2電極15の一部を露出させる。第1電極14の露出部分が第1パッド電極20bとなり、第2電極15の露出部分が第2パッド電極20cとなる(図2H参照)。同様に、表面保護層19から薄膜ヒータ21に至る第3開口部33及び第4開口部34も形成して、薄膜ヒータ21の一部を露出させる。薄膜ヒータ21のうち第3開口部33から露出する部分が第1パッド電極211となり、薄膜ヒータ21のうち第4開口部34から露出する部分が第2パッド電極212となる。 A first opening 31 from the surface protective layer 19 to the first electrode 14 and a second opening 32 from the surface protective layer 19 to the second electrode 15 are formed by photolithography technique and reactive ion etching (RIE). The first electrode 14 and a part of the second electrode 15 are exposed. The exposed portion of the first electrode 14 becomes the first pad electrode 20b, and the exposed portion of the second electrode 15 becomes the second pad electrode 20c (see FIG. 2H). Similarly, a third opening 33 and a fourth opening 34 extending from the surface protective layer 19 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed. A portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211, and a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
 次に、フォトリソグラフィ技術及びエッチング技術を利用して、基板11における空隙30の形成予定領域を基板11の裏面からエッチングすることにより、空隙30を形成する(図2I参照)。基板11のエッチングは、例えば、誘導結合プラズマ(ICP)型等のドライエッチング装置又は反応性イオンエッチング(RIE)装置を利用するのが望ましい。または、基板11の裏面からアルカリ系溶液(例えば、TMAH溶液、KOH水溶液等)でエッチングすることで、空隙30を形成してもよい。 Next, using the photolithography technique and the etching technique, the space 30 is formed by etching the region where the gap 30 is to be formed from the back surface of the substrate 11 (see FIG. 2I). For etching the substrate 11, it is desirable to use, for example, an inductively coupled plasma (ICP) type dry etching apparatus or a reactive ion etching (RIE) apparatus. Alternatively, the gap 30 may be formed by etching with an alkaline solution (for example, a TMAH solution, a KOH aqueous solution, or the like) from the back surface of the substrate 11.
 以上の工程を経て可変容量コンデンサ10が製造される。 The variable capacitor 10 is manufactured through the above steps.
 なお、本実施形態では、可変容量コンデンサ10は、抵抗加熱素子として薄膜ヒータ21を備えているが、薄膜ヒータ21に限らず、例えばペルチェ素子を用いてもよい。 In this embodiment, the variable capacitor 10 includes the thin film heater 21 as a resistance heating element, but is not limited to the thin film heater 21 and may be a Peltier element, for example.
 また、可変容量コンデンサ10は、コンデンサ素子20におけるコンデンサ部20aの温度を検出する温度センサ60を薄膜層50内に備えてもよい(図3A参照)。可変容量コンデンサ10は、例えば別に設けられた制御回路によって制御される。制御回路は、温度センサ60で検出された温度に応じて、薄膜ヒータ21に印加する電圧を調整する。図3Aでは、温度センサ60は、空隙30の上方向(Z軸の矢印方向)における表面保護層19に設けられる構成としている。温度センサ60は、薄膜ヒータ21の近傍の層間絶縁膜18に設けてもよい。温度センサ60は、空隙30の上方向に設けることが好ましい。温度センサ60が空隙30の上方向に設けられることで、検出感度を高めることができる。なお、温度センサ60は、この構成に限定されず、薄膜層50内であればよい。または、薄膜ヒータ21が、温度センサ60の機能を兼ね備えてもよい。 Further, the variable capacitor 10 may include a temperature sensor 60 for detecting the temperature of the capacitor portion 20a in the capacitor element 20 in the thin film layer 50 (see FIG. 3A). The variable capacitor 10 is controlled by a control circuit provided separately, for example. The control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60. In FIG. 3A, the temperature sensor 60 is configured to be provided on the surface protective layer 19 in the upward direction of the air gap 30 (the Z-axis arrow direction). The temperature sensor 60 may be provided in the interlayer insulating film 18 in the vicinity of the thin film heater 21. The temperature sensor 60 is preferably provided above the gap 30. By providing the temperature sensor 60 above the gap 30, the detection sensitivity can be increased. The temperature sensor 60 is not limited to this configuration, and may be in the thin film layer 50. Alternatively, the thin film heater 21 may have the function of the temperature sensor 60.
 また、薄膜ヒータ21は、コンデンサ部20aから基板11とは反対の層(層間絶縁膜18と表面保護層19とからなる層)内に配置してあるが、薄膜ヒータ21は、コンデンサ部20aと基板11との間の層に配置してもよい。薄膜ヒータ21は、例えば図3Bに示すように、支持層12内に配置されてもよい。または、薄膜ヒータ21は、コンデンサ部20aの誘電体層16内に設けられてもよい。つまり、薄膜ヒータ21は、薄膜層50内に設けられていればよい。 The thin film heater 21 is disposed in a layer opposite to the substrate 11 from the capacitor portion 20a (a layer made of the interlayer insulating film 18 and the surface protective layer 19), but the thin film heater 21 is connected to the capacitor portion 20a. You may arrange | position in the layer between the board | substrates 11. The thin film heater 21 may be disposed in the support layer 12 as shown in FIG. 3B, for example. Alternatively, the thin film heater 21 may be provided in the dielectric layer 16 of the capacitor unit 20a. That is, the thin film heater 21 only needs to be provided in the thin film layer 50.
 (実施形態2)
 本実施形態における可変容量コンデンサ10Aについて、実施形態1とは異なる点を中心に、図4A~図5Fを用いて説明する。本実施形態の可変容量コンデンサ10Aは、実施形態1の可変容量コンデンサ10と比較して、薄膜ヒータ21が設けられた位置が異なっている。実施形態1と同様の構成要素には同一の符号を付して説明を適宜省略する。
(Embodiment 2)
A variable capacitor 10A according to the present embodiment will be described with reference to FIGS. 4A to 5F with a focus on differences from the first embodiment. The variable capacitor 10A according to the present embodiment is different from the variable capacitor 10 according to the first embodiment in the position where the thin film heater 21 is provided. Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
 本実施形態の可変容量コンデンサ10Aは、図4A,4Bに示すように、第1電極14、第2電極15及び誘電体層16を有するコンデンサ素子20に加えて、基板11、支持層12、層間絶縁膜18及び薄膜ヒータ21を備えている。可変容量コンデンサ10Aは、第1密着層13及び第2密着層17を、上下層の材料に応じて適宜設けてもよい。 As shown in FIGS. 4A and 4B, the variable capacitor 10 </ b> A of this embodiment includes a substrate 11, a support layer 12, an interlayer, in addition to the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16. An insulating film 18 and a thin film heater 21 are provided. In the variable capacitor 10A, the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
 本実施形態の可変容量コンデンサ10Aでは、実施形態1と同様に、基板11を最下部とし、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18の順に積層されている。ここで、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18により、薄膜層50が形成されている。薄膜層50の厚さは、数μmである。 In the variable capacitor 10A of the present embodiment, as in the first embodiment, the substrate 11 is the lowermost part, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, and the interlayer insulating film 18 are arranged in this order. Are stacked. Here, the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, and the interlayer insulating film 18 form a thin film layer 50. The thickness of the thin film layer 50 is several μm.
 本実施形態では、支持層12の表面の中心点を原点として、支持層12の表面において互いに直交するX軸とY軸とを規定し、支持層12の表面に直交するZ軸を規定している。なお、図4A、図4Bには、X軸方向、Y軸方向、Z軸方向を表す矢印を記載しているが、この矢印は、単に説明を補助する目的で記載しているに過ぎず、実体を伴わない。また、上記の方向の規定は、本実施形態の可変容量コンデンサ10Aの使用形態を限定する趣旨ではない。 In the present embodiment, with the center point of the surface of the support layer 12 as the origin, the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined. Yes. In FIGS. 4A and 4B, arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10A of the present embodiment.
 本実施形態の基板11の中央部位は、厚さ方向に貫通する矩形状の空隙30を有している。空隙30のZ軸方向における断面は、台形の形状となっている。単結晶のSi基板からなる基板11の主表面111は、(100)面である。 The central part of the substrate 11 of this embodiment has a rectangular gap 30 penetrating in the thickness direction. The cross section of the gap 30 in the Z-axis direction has a trapezoidal shape. The main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane.
 本実施形態では、薄膜ヒータ21は、コンデンサ素子20の第1電極14と同様に、第1密着層13上に設けられている。薄膜ヒータ21のヒータ部215は、蛇行した形状で形成されている。薄膜ヒータ21のヒータ部215は、基板11の空隙30の上部に、コンデンサ部20a(特に、第1電極14)の周囲に設けられている。薄膜ヒータ21は、第1パッド電極211と第2パッド電極212とを電源に電気的に接続することで加熱される。薄膜ヒータ21によりコンデンサ部20aの周囲を温めることで、薄膜ヒータ21で発せられた熱が誘電体層16へ伝達される。 In the present embodiment, the thin film heater 21 is provided on the first adhesion layer 13 in the same manner as the first electrode 14 of the capacitor element 20. The heater portion 215 of the thin film heater 21 is formed in a meandering shape. The heater portion 215 of the thin film heater 21 is provided above the gap 30 of the substrate 11 and around the capacitor portion 20a (particularly, the first electrode 14). The thin film heater 21 is heated by electrically connecting the first pad electrode 211 and the second pad electrode 212 to a power source. By heating the periphery of the capacitor portion 20 a by the thin film heater 21, the heat generated by the thin film heater 21 is transmitted to the dielectric layer 16.
 本実施形態の可変容量コンデンサ10Aにおいて、薄膜ヒータ21の第1パッド電極211及び第2パッド電極212に電圧を印加すると、薄膜ヒータ21のヒータ部215は熱を発する。ヒータ部215より発せられた熱は、コンデンサ部20aの誘電体層16に伝達される。ここにおいて、ヒータ部215は第1電極14の周囲に設けられているので、誘電体層16の周囲から熱が誘電体層16に伝達される。コンデンサ部20aでは、誘電体層16の温度に応じて静電容量が変更される。可変容量コンデンサ10Aでは、薄膜ヒータ21に印加される電圧が調整されることで、コンデンサ部20aの静電容量が調整される。 In the variable capacitor 10A of the present embodiment, when a voltage is applied to the first pad electrode 211 and the second pad electrode 212 of the thin film heater 21, the heater unit 215 of the thin film heater 21 generates heat. Heat generated from the heater unit 215 is transmitted to the dielectric layer 16 of the capacitor unit 20a. Here, since the heater portion 215 is provided around the first electrode 14, heat is transferred from the periphery of the dielectric layer 16 to the dielectric layer 16. In the capacitor unit 20a, the capacitance is changed according to the temperature of the dielectric layer 16. In the variable capacitor 10A, the voltage applied to the thin film heater 21 is adjusted, so that the capacitance of the capacitor unit 20a is adjusted.
 ここで、本実施形態の薄膜ヒータ21のヒータ部215は、コンデンサ部20aの誘電体層16の温度をキュリー温度以上に調整するように制御されることで、コンデンサ部20aの静電容量を変化させることが好ましい。 Here, the heater unit 215 of the thin film heater 21 of the present embodiment changes the capacitance of the capacitor unit 20a by being controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor unit 20a to be equal to or higher than the Curie temperature. It is preferable to make it.
 次に、本実施形態の可変容量コンデンサ10Aの製造方法について、図5A~図5Fを用いて説明する。 Next, a method for manufacturing the variable capacitor 10A according to the present embodiment will be described with reference to FIGS. 5A to 5F.
 基板11に主表面111上に、熱酸化法によりSiO膜を形成し、続いて、LPCVDによりSi膜を形成することにより、SiO膜とSi膜との積層膜からなる支持層12を形成する(図5A参照)。支持層12上に、例えばスパッタにより第1密着層13を形成する。または、支持層12上に、第1密着層13の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、第1密着層13を形成してもよい。次に、第1密着層13上に第1電極14及び薄膜ヒータ21の元になる第1導電層100を、例えばスパッタで形成する。第1導電層100上に誘電体層16の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、絶縁層16aを生成する。その後、絶縁層16a上に第2電極15の元になる第2導電層15aを、例えばスパッタで形成する。次に、第2導電層15a上に、例えばスパッタで密着層17aを形成する(図5B参照)。または、第2導電層15a上に、第2密着層17の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、密着層17aを形成してもよい。 A SiO 2 film is formed on the main surface 111 on the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD, whereby a laminated film of the SiO 2 film and the Si 3 N 4 film is formed. A support layer 12 is formed (see FIG. 5A). The first adhesion layer 13 is formed on the support layer 12 by sputtering, for example. Alternatively, the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees. Next, the first conductive layer 100 that is the basis of the first electrode 14 and the thin film heater 21 is formed on the first adhesion layer 13 by, for example, sputtering. The insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 100 by spin coating and baking at 600 to 700 degrees. Thereafter, the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering. Next, the adhesion layer 17a is formed on the second conductive layer 15a by sputtering, for example (see FIG. 5B). Alternatively, the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by a spin coating method and baking at 600 to 700 degrees.
 第1導電層100、絶縁層16a、第2導電層15a及び密着層17aをフォトリソグラフィ技術及びエッチング技術によりパターニングすることにより、第1電極14、薄膜ヒータ21、誘電体層16、第2電極15及び第2密着層17等を形成する(図5C参照)。 The first electrode 14, the thin film heater 21, the dielectric layer 16, and the second electrode 15 are patterned by patterning the first conductive layer 100, the insulating layer 16 a, the second conductive layer 15 a, and the adhesion layer 17 a using a photolithography technique and an etching technique. Then, the second adhesion layer 17 and the like are formed (see FIG. 5C).
 その後、コンデンサ素子20を覆うように、層間絶縁膜18をCVD又はスパッタで形成する(図5D参照)。 Thereafter, an interlayer insulating film 18 is formed by CVD or sputtering so as to cover the capacitor element 20 (see FIG. 5D).
 フォトリソグラフィ技術及び反応性イオンエッチング(RIE)により、層間絶縁膜18から第1電極14に至る第1開口部31及び表面保護層19から第2電極15に至る第2開口部32を形成して、第1電極14及び第2電極15の一部を露出させる。第1電極14の露出部分が第1パッド電極20bとなり、第2電極15の露出部分が第2パッド電極20cとなる(図5E参照)。同様に、層間絶縁膜18から薄膜ヒータ21に至る第3開口部33及び第4開口部34も形成して、薄膜ヒータ21の一部を露出させる。薄膜ヒータ21のうち第3開口部33から露出する部分が第1パッド電極211となり、薄膜ヒータ21のうち第4開口部34から露出する部分が第2パッド電極212となる。 A first opening 31 extending from the interlayer insulating film 18 to the first electrode 14 and a second opening 32 extending from the surface protective layer 19 to the second electrode 15 are formed by photolithography and reactive ion etching (RIE). The first electrode 14 and a part of the second electrode 15 are exposed. The exposed portion of the first electrode 14 becomes the first pad electrode 20b, and the exposed portion of the second electrode 15 becomes the second pad electrode 20c (see FIG. 5E). Similarly, a third opening 33 and a fourth opening 34 from the interlayer insulating film 18 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed. A portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211, and a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
 フォトリソグラフィ技術及びエッチング技術を利用して、基板11における空隙30の形成予定領域を基板11の裏面からエッチングすることにより、空隙30を形成する(図5F参照)。基板11のエッチングは、例えば、誘導結合プラズマ(ICP)型等のドライエッチング装置又はRIE装置を利用するのが望ましい。または、基板11の裏面からアルカリ系溶液(例えば、TMAH溶液、KOH水溶液等)でエッチングすることで、空隙30を形成してもよい。 Using the photolithography technology and the etching technology, the space 30 is formed by etching the region where the space 30 is to be formed from the back surface of the substrate 11 (see FIG. 5F). For the etching of the substrate 11, for example, an inductively coupled plasma (ICP) type dry etching apparatus or RIE apparatus is preferably used. Alternatively, the gap 30 may be formed by etching with an alkaline solution (for example, a TMAH solution, a KOH aqueous solution, or the like) from the back surface of the substrate 11.
 以上の工程を経て可変容量コンデンサ10Aが製造される。 The variable capacitor 10A is manufactured through the above steps.
 なお、本実施形態において、薄膜ヒータ21は、コンデンサ素子20の第1電極14の周囲に配置するとしたが、薄膜ヒータ21は、コンデンサ素子20の誘電体層16または第2電極15の周囲に配置してもよい。 In the present embodiment, the thin film heater 21 is disposed around the first electrode 14 of the capacitor element 20. However, the thin film heater 21 is disposed around the dielectric layer 16 or the second electrode 15 of the capacitor element 20. May be.
 また、本実施形態においても実施形態1と同様に、可変容量コンデンサ10Aは、抵抗加熱素子として薄膜ヒータ21を備えているが、薄膜ヒータ21に限らず、例えばペルチェ素子を用いてもよい。 Also in the present embodiment, similarly to the first embodiment, the variable capacitor 10A includes the thin film heater 21 as a resistance heating element, but is not limited to the thin film heater 21, and a Peltier element, for example, may be used.
 また、本実施形態においても実施形態1と同様に、可変容量コンデンサ10Aは、コンデンサ素子20の温度を検出する温度センサ60を薄膜層50内に備えてもよい。可変容量コンデンサ10Aは、例えば別に設けられた制御回路によって制御される。制御回路は、温度センサ60で検出された温度に応じて、薄膜ヒータ21に印加する電圧を調整する。または、薄膜ヒータ21が、温度センサ60の機能を兼ね備えてもよい。 Also in the present embodiment, similarly to the first embodiment, the variable capacitor 10 </ b> A may include the temperature sensor 60 for detecting the temperature of the capacitor element 20 in the thin film layer 50. The variable capacitor 10A is controlled by, for example, a separately provided control circuit. The control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60. Alternatively, the thin film heater 21 may have the function of the temperature sensor 60.
 通常、薄膜ヒータで発せられた熱は、基板を介して外部に逃げる。そのため、誘電体層の中央部位から離れるにつれて温まりにくくなる。その結果、誘電体層において、温度差が生じる。そこで、本実施形態では、薄膜ヒータ21をコンデンサ素子20(特に、第1電極14)の周囲に設けられている。これにより、コンデンサ部20aにおける誘電体層16における温度について均一化を図ることができる。 Usually, the heat generated by the thin film heater escapes to the outside through the substrate. For this reason, it becomes difficult to warm as the distance from the central portion of the dielectric layer increases. As a result, a temperature difference occurs in the dielectric layer. Therefore, in the present embodiment, the thin film heater 21 is provided around the capacitor element 20 (particularly, the first electrode 14). Thereby, the temperature in the dielectric layer 16 in the capacitor portion 20a can be made uniform.
 (実施形態3)
 本実施形態における可変容量コンデンサ10Bについて、実施形態1とは異なる点を中心に、図6A~図7Iを用いて説明する。本実施形態の可変容量コンデンサ10Bは、実施形態1の可変容量コンデンサ10と比較して、支持層12が梁構造で形成されている点が異なっている。実施形態1と同様の構成要素には同一の符号を付して説明を適宜省略する。
(Embodiment 3)
A variable capacitor 10B according to the present embodiment will be described with reference to FIGS. 6A to 7I, focusing on differences from the first embodiment. The variable capacitor 10B of the present embodiment is different from the variable capacitor 10 of the first embodiment in that the support layer 12 is formed in a beam structure. Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
 本実施形態の可変容量コンデンサ10Bは、図6A,6Bに示すように、第1電極14、第2電極15及び誘電体層16を有するコンデンサ素子20に加えて、基板11、支持層12、層間絶縁膜18、表面保護層19及び薄膜ヒータ21を備えている。可変容量コンデンサ10Bは、第1密着層13及び第2密着層17を、上下層の材料に応じて適宜設けてもよい。 As shown in FIGS. 6A and 6B, the variable capacitor 10 </ b> B of this embodiment includes a substrate 11, a support layer 12, an interlayer, in addition to the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16. An insulating film 18, a surface protective layer 19, and a thin film heater 21 are provided. In the variable capacitor 10B, the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
 本実施形態の可変容量コンデンサ10Bでは、実施形態1と同様に、基板11を最下部とし、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18、薄膜ヒータ21、表面保護層19の順に積層されている。ここで、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18及び表面保護層19により、薄膜層50が形成されている。薄膜層50の厚さは、数μmである。 In the variable capacitor 10B of the present embodiment, as in the first embodiment, the substrate 11 is the bottom, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the thin film The heater 21 and the surface protective layer 19 are laminated in this order. Here, a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19. The thickness of the thin film layer 50 is several μm.
 本実施形態では、支持層12の表面の中心点を原点として、支持層12の表面において互いに直交するX軸とY軸とを規定し、支持層12の表面に直交するZ軸を規定している。なお、図6A、図6Bには、X軸方向、Y軸方向、Z軸方向を表す矢印を記載しているが、この矢印は、単に説明を補助する目的で記載しているに過ぎず、実体を伴わない。また、上記の方向の規定は、本実施形態の可変容量コンデンサ10Bの使用形態を限定する趣旨ではない。 In the present embodiment, with the center point of the surface of the support layer 12 as the origin, the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined. Yes. In FIGS. 6A and 6B, arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction are described, but these arrows are merely described for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10B of the present embodiment.
 コンデンサ素子20は、実施形態1と同様に、コンデンサ部20a、第1パッド電極20b、第2パッド電極20c、第1配線部20d及び第2配線部20eから構成されている(図6A参照)。本実施形態では、実施形態1と同様に、コンデンサ部20aと第1パッド電極20bとの間の第1配線部20dとなる部分にも第1電極14、誘電体層16及び第2電極15の積層構造が延びているとする。同様に、コンデンサ部20aと第2パッド電極20cとの間の第2配線部20eとなる部分にも第1電極14、誘電体層16及び第2電極15の積層構造が延びているとする。なお、第1配線部20dには誘電体層16及び第2電極15はなくてもよい。同様に、第2配線部20eには第1電極14及び誘電体層16はなくてもよい。 As in the first embodiment, the capacitor element 20 includes a capacitor portion 20a, a first pad electrode 20b, a second pad electrode 20c, a first wiring portion 20d, and a second wiring portion 20e (see FIG. 6A). In the present embodiment, as in the first embodiment, the first electrode 14, the dielectric layer 16, and the second electrode 15 are also formed on the portion that becomes the first wiring portion 20 d between the capacitor portion 20 a and the first pad electrode 20 b. Assume that the laminated structure extends. Similarly, it is assumed that the laminated structure of the first electrode 14, the dielectric layer 16, and the second electrode 15 extends to a portion that becomes the second wiring portion 20 e between the capacitor portion 20 a and the second pad electrode 20 c. The first wiring portion 20d may not include the dielectric layer 16 and the second electrode 15. Similarly, the first wiring 14 and the dielectric layer 16 may not be provided in the second wiring portion 20e.
 基板11には、主表面111からZ軸方向と反対方向に向けて四角錐形状の空隙30が設けられている。単結晶のSi基板からなる基板11の主表面111は、(100)面である。主表面111には、支持層12が設けられている。 The substrate 11 is provided with a quadrangular pyramid-shaped gap 30 from the main surface 111 in the direction opposite to the Z-axis direction. The main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane. A support layer 12 is provided on the main surface 111.
 支持層12は、支持部12a、その内側に設けられた保持部12b及び支持部12aと保持部12bとを連結する4つの梁部12c~12fを有している。 The support layer 12 includes a support portion 12a, a holding portion 12b provided on the inside thereof, and four beam portions 12c to 12f that connect the support portion 12a and the holding portion 12b.
 支持部12aは、外形状及及び内形状が、四角形状に形成されている。 The outer and inner shapes of the support portion 12a are formed in a square shape.
 保持部12bと、梁部12c~12fとは、空隙30により露出されている。 The holding portion 12b and the beam portions 12c to 12f are exposed by the gap 30.
 保持部12bは、コンデンサ素子20のうち少なくともコンデンサ部20aを保持する。具体的には、保持部12b上には、第1密着層13、コンデンサ部20a、第2密着層17、層間絶縁膜18、薄膜ヒータ21のヒータ部215及び表面保護層19が積層されている。 The holding unit 12b holds at least the capacitor unit 20a of the capacitor element 20. Specifically, the first adhesion layer 13, the capacitor part 20 a, the second adhesion layer 17, the interlayer insulating film 18, the heater part 215 of the thin film heater 21, and the surface protection layer 19 are laminated on the holding part 12 b. .
 梁部12cには、第1配線部20dが少なくとも積層されている(図6A参照)。本実施形態では、梁部12cには、第1配線部20dの他、第1密着層13、第2密着層17、層間絶縁膜18及び表面保護層19が積層されている。梁部12cは、後述する第1開口部31と保持部12bとの間に設けられている。 The first wiring portion 20d is at least stacked on the beam portion 12c (see FIG. 6A). In the present embodiment, the first contact layer 13, the second contact layer 17, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the beam portion 12 c in addition to the first wiring portion 20 d. The beam portion 12c is provided between a first opening 31 and a holding portion 12b described later.
 梁部12eには、第2配線部20eが少なくとも積層されている(図6A参照)。本実施形態では、梁部12eには、第2配線部20eの他、第1密着層13、第2密着層17、層間絶縁膜18及び表面保護層19が積層されている。梁部12eは、第1開口部31とは反対方向の第2開口部32(後述)と保持部12bとの間に設けられている。 At least the second wiring part 20e is laminated on the beam part 12e (see FIG. 6A). In the present embodiment, the first adhesive layer 13, the second adhesive layer 17, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the beam portion 12e in addition to the second wiring portion 20e. The beam portion 12e is provided between a holding portion 12b and a second opening portion 32 (described later) in a direction opposite to the first opening portion 31.
 支持部12aの第1角部122には、第1パッド電極20bが少なくとも積層されている(図6A参照)。本実施形態では、第1角部122には、第1パッド電極20bの他、第1密着層13、誘電体層16、層間絶縁膜18及び表面保護層19が積層されている。 At least the first pad electrode 20b is laminated on the first corner portion 122 of the support portion 12a (see FIG. 6A). In the present embodiment, in addition to the first pad electrode 20b, the first adhesion layer 13, the dielectric layer 16, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the first corner portion 122.
 支持部12aの第2角部123には、第2パッド電極20cが少なくとも積層されている(図6A参照)。本実施形態では、第2角部123には、第2パッド電極20cの他、第1密着層13、第1電極14(第1電極部)、第2密着層17、層間絶縁膜18及び表面保護層19が積層されている。 At least the second pad electrode 20c is stacked on the second corner 123 of the support 12a (see FIG. 6A). In the present embodiment, the second corner portion 123 includes, in addition to the second pad electrode 20c, the first adhesion layer 13, the first electrode 14 (first electrode portion), the second adhesion layer 17, the interlayer insulating film 18, and the surface. A protective layer 19 is laminated.
 また、第1角部122において、表面保護層19から第1パッド電極20bに至る第1開口部31が設けられている(図6A参照)。第2角部123において、表面保護層19から第2パッド電極20cに至る第2開口部32が設けられている(図6A参照)。第1パッド電極20bと第2パッド電極20cとを電源と電気的に接続することで、コンデンサ部20aに電荷が蓄積される。 Further, the first corner portion 122 is provided with a first opening 31 from the surface protective layer 19 to the first pad electrode 20b (see FIG. 6A). In the second corner 123, a second opening 32 extending from the surface protective layer 19 to the second pad electrode 20c is provided (see FIG. 6A). By electrically connecting the first pad electrode 20b and the second pad electrode 20c to a power source, charges are accumulated in the capacitor unit 20a.
 梁部12dには、薄膜ヒータ21の配線部213が少なくとも積層されている(図6A参照)。本実施形態では、梁部12dには、配線部213の他、第1密着層13、層間絶縁膜18及び表面保護層19が積層されている。梁部12dは、後述する第3開口部33と保持部12bとの間に設けられている。 At least a wiring portion 213 of the thin film heater 21 is laminated on the beam portion 12d (see FIG. 6A). In the present embodiment, a first adhesion layer 13, an interlayer insulating film 18, and a surface protection layer 19 are stacked on the beam portion 12 d in addition to the wiring portion 213. The beam portion 12d is provided between a third opening 33 and a holding portion 12b, which will be described later.
 梁部12fには、薄膜ヒータ21の配線部214が少なくとも積層されている(図6A参照)。本実施形態では、梁部12fには、配線部214の他、第1密着層13、層間絶縁膜18及び表面保護層19が積層されている。梁部12fは、第3開口部33とは反対方向の第4開口部34(後述)と保持部12bとの間に設けられている。 At least a wiring portion 214 of the thin film heater 21 is laminated on the beam portion 12f (see FIG. 6A). In the present embodiment, the first adhesive layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked in addition to the wiring portion 214 on the beam portion 12 f. The beam portion 12f is provided between a holding portion 12b and a fourth opening portion 34 (described later) opposite to the third opening portion 33.
 支持部12aの第3角部124には、第1パッド電極211が少なくとも積層されている(図6A参照)。本実施形態では、第3角部124には、第1パッド電極211の他、第1密着層13、層間絶縁膜18及び表面保護層19が積層されている。 At least the first pad electrode 211 is stacked on the third corner portion 124 of the support portion 12a (see FIG. 6A). In the present embodiment, in addition to the first pad electrode 211, the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the third corner portion 124.
 支持部12aの第4角部125には、第2パッド電極212が少なくとも積層されている(図6A参照)。本実施形態では、第4角部125には、第2パッド電極212の他、第1密着層13、層間絶縁膜18及び表面保護層19が積層されている。 At least the second pad electrode 212 is laminated on the fourth corner portion 125 of the support portion 12a (see FIG. 6A). In the present embodiment, in addition to the second pad electrode 212, the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are stacked on the fourth corner portion 125.
 また、第3角部124において、表面保護層19から第1パッド電極211に至る第3開口部33が設けられている(図6A参照)。第4角部125において、表面保護層19から第2パッド電極212に至る第4開口部34が設けられている(図6A参照)。第3開口部及び第4開口部34を通して電圧を印加すると、薄膜ヒータ21のヒータ部215は熱を発する。ヒータ部215より発せられた熱は、コンデンサ部20aの誘電体層16に伝達される。 Further, a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 is provided in the third corner portion 124 (see FIG. 6A). A fourth opening 34 extending from the surface protective layer 19 to the second pad electrode 212 is provided in the fourth corner 125 (see FIG. 6A). When a voltage is applied through the third opening and the fourth opening 34, the heater part 215 of the thin film heater 21 generates heat. Heat generated from the heater unit 215 is transmitted to the dielectric layer 16 of the capacitor unit 20a.
 なお、図6Bにおいて、説明の都合上、梁部12c及び梁部12dにおいては第1密着層13、層間絶縁膜18及び表面保護層19以外の構成要素については省略している。 In FIG. 6B, for convenience of explanation, components other than the first adhesion layer 13, the interlayer insulating film 18, and the surface protective layer 19 are omitted in the beam portion 12c and the beam portion 12d.
 また、可変容量コンデンサ10は、表面保護層19から基板11の空隙30へ至る複数の貫通孔40を有している。これにより、保持部12bに積層された薄膜ヒータ21のヒータ部215を基板11から断熱することができる。また、保持部12bに積層された支持層12におけるX軸方向に対する長さは、数百μmである。X軸方向の長さ数百μmに対して、支持層12の裏面121から表面保護層19の表面191までの厚みは数μmであるため、薄膜ヒータ21から発せられた熱は、支持部12aに積層された層よりも誘電体層16へ伝達されやすい。 Further, the variable capacitor 10 has a plurality of through holes 40 extending from the surface protective layer 19 to the air gap 30 of the substrate 11. Thereby, the heater part 215 of the thin film heater 21 laminated | stacked on the holding | maintenance part 12b can be thermally insulated from the board | substrate 11. FIG. Moreover, the length with respect to the X-axis direction in the support layer 12 laminated | stacked on the holding | maintenance part 12b is several hundred micrometers. Since the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19 is several μm with respect to a length of several hundred μm in the X-axis direction, the heat generated from the thin film heater 21 is supported by the support portion 12a. It is easier to be transmitted to the dielectric layer 16 than the layers stacked on each other.
 ここで、本実施形態の薄膜ヒータ21のヒータ部215は、コンデンサ部20aの誘電体層16の温度をキュリー温度以上に調整するように制御されることで、コンデンサ部20aの静電容量を変化させることが好ましい。 Here, the heater unit 215 of the thin film heater 21 of the present embodiment changes the capacitance of the capacitor unit 20a by being controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor unit 20a to be equal to or higher than the Curie temperature. It is preferable to make it.
 次に、本実施形態の可変容量コンデンサ10の製造方法について、図7A~図7Iを用いて説明する。 Next, a method for manufacturing the variable capacitor 10 of the present embodiment will be described with reference to FIGS. 7A to 7I.
 基板11の主表面111上に、熱酸化法によりSiO膜を形成し、続いて、LPCVDによりSi膜を形成することにより、SiO膜とSi膜との積層膜からなる支持層12を形成する(図7A参照)。支持層12上に、例えばスパッタにより第1密着層13を形成する。または、支持層12上に、第1密着層13の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、第1密着層13を形成してもよい。次に、第1密着層13上に第1電極14の元になる第1導電層14aを、例えばスパッタで形成する。第1導電層14a上に誘電体層16の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、絶縁層16aを生成する。その後、絶縁層16a上に第2電極15の元になる第2導電層15aを、例えばスパッタで形成する。次に、第2導電層15a上に、例えばスパッタで密着層17aを形成する(図7B参照)。または、第2導電層15a上に第2密着層17の元になるBSTペーストをスピンコート法により塗布し、600~700度で焼成することにより、密着層17aを形成してもよい。 A SiO 2 film is formed on the main surface 111 of the substrate 11 by a thermal oxidation method, and subsequently, a Si 3 N 4 film is formed by LPCVD, so that a laminated film of the SiO 2 film and the Si 3 N 4 film is formed. A support layer 12 is formed (see FIG. 7A). The first adhesion layer 13 is formed on the support layer 12 by sputtering, for example. Alternatively, the first adhesive layer 13 may be formed by applying a BST paste as a base of the first adhesive layer 13 on the support layer 12 by spin coating and baking at 600 to 700 degrees. Next, the first conductive layer 14a that is the basis of the first electrode 14 is formed on the first adhesion layer 13 by, for example, sputtering. The insulating layer 16a is formed by applying a BST paste as a base of the dielectric layer 16 on the first conductive layer 14a by spin coating and baking at 600 to 700 degrees. Thereafter, the second conductive layer 15a that is the basis of the second electrode 15 is formed on the insulating layer 16a by, for example, sputtering. Next, the adhesion layer 17a is formed on the second conductive layer 15a by, for example, sputtering (see FIG. 7B). Alternatively, the adhesion layer 17a may be formed by applying a BST paste as a base of the second adhesion layer 17 on the second conductive layer 15a by spin coating and baking at 600 to 700 degrees.
 第1導電層14a、絶縁層16a、第2導電層15a及び密着層17aをフォトリソグラフィ技術及びエッチング技術によりパターニングすることにより、第1電極14、第2電極15、誘電体層16及び第2密着層17等を形成する(図7C参照)。 By patterning the first conductive layer 14a, the insulating layer 16a, the second conductive layer 15a, and the adhesion layer 17a by a photolithography technique and an etching technique, the first electrode 14, the second electrode 15, the dielectric layer 16, and the second adhesion layer are patterned. Layer 17 and the like are formed (see FIG. 7C).
 その後、コンデンサ素子20を覆うように、層間絶縁膜18をCVD又はスパッタで形成する(図7D参照)。次に、層間絶縁膜18上に薄膜ヒータ21の元になる白金膜21aをスパッタで形成する(図7E参照)。 Thereafter, an interlayer insulating film 18 is formed by CVD or sputtering so as to cover the capacitor element 20 (see FIG. 7D). Next, a platinum film 21a serving as a base of the thin film heater 21 is formed on the interlayer insulating film 18 by sputtering (see FIG. 7E).
 白金膜21aをフォトリソグラフィ技術及びエッチング技術によりパターニングすることにより、薄膜ヒータ21を成形する(図7F参照)。次に、薄膜ヒータ21を覆うように表面保護層19をCVD又はスパッタで形成する(図7G参照)。 The thin film heater 21 is formed by patterning the platinum film 21a by a photolithography technique and an etching technique (see FIG. 7F). Next, the surface protective layer 19 is formed by CVD or sputtering so as to cover the thin film heater 21 (see FIG. 7G).
 フォトリソグラフィ技術及び反応性イオンエッチング(RIE)により、表面保護層19から基板11に至る複数の貫通孔40を形成する(図7H参照)。同様に、表面保護層19から第1電極14に至る第1開口部31及び表面保護層19から第2電極15に至る第2開口部32を形成して、第1電極14及び第2電極15の一部を露出させる。第1電極14の露出部分が第1パッド電極20bとなり、第2電極15の露出部分が第2パッド電極20cとなる。さらに、表面保護層19から薄膜ヒータ21に至る第3開口部33及び第4開口部34も形成して、薄膜ヒータ21の一部を露出させる。薄膜ヒータ21のうち第3開口部33から露出する部分が第1パッド電極211となり、薄膜ヒータ21のうち第4開口部34から露出する部分が第2パッド電極212となる。 A plurality of through holes 40 extending from the surface protective layer 19 to the substrate 11 are formed by photolithography technology and reactive ion etching (RIE) (see FIG. 7H). Similarly, a first opening 31 extending from the surface protective layer 19 to the first electrode 14 and a second opening 32 extending from the surface protective layer 19 to the second electrode 15 are formed, and the first electrode 14 and the second electrode 15 are formed. To expose a part of The exposed portion of the first electrode 14 becomes the first pad electrode 20b, and the exposed portion of the second electrode 15 becomes the second pad electrode 20c. Further, a third opening 33 and a fourth opening 34 extending from the surface protective layer 19 to the thin film heater 21 are also formed, and a part of the thin film heater 21 is exposed. A portion of the thin film heater 21 exposed from the third opening 33 serves as the first pad electrode 211, and a portion of the thin film heater 21 exposed from the fourth opening 34 serves as the second pad electrode 212.
 フォトリソグラフィ技術及びエッチング技術を利用して、基板11における空隙30の形成予定領域を基板11の主表面111からエッチングすることにより、空隙30を形成する(図7I参照)。基板11のエッチングは、例えば、アルカリ系溶液(例えば、TMAH溶液、KOH水溶液等)を用いたウェットにより複数の貫通孔40を通して基板11の主表面111から結晶異方性エッチングをすることにより、空隙30を形成するのが望ましい。 Using the photolithography technique and the etching technique, the space 30 is formed by etching the region where the space 30 is to be formed in the substrate 11 from the main surface 111 of the substrate 11 (see FIG. 7I). Etching of the substrate 11 is performed by, for example, performing crystal anisotropic etching from the main surface 111 of the substrate 11 through the plurality of through holes 40 by wet using an alkaline solution (for example, TMAH solution, KOH aqueous solution, etc.). 30 is desirable.
 以上の工程を経て可変容量コンデンサ10Bが製造される。 The variable capacitor 10B is manufactured through the above steps.
 なお、本実施形態においても実施形態1と同様に、可変容量コンデンサ10Bは、抵抗加熱素子として薄膜ヒータ21を備えているが、薄膜ヒータ21に限らず、例えばペルチェ素子を用いてもよい。 In the present embodiment, the variable capacitor 10B includes the thin film heater 21 as a resistance heating element as in the first embodiment. However, the present invention is not limited to the thin film heater 21, and a Peltier element, for example, may be used.
 また、本実施形態においても実施形態1と同様に、可変容量コンデンサ10Bは、コンデンサ部20aの温度を検出する温度センサ60を薄膜層50に備えてもよい。可変容量コンデンサ10Bは、例えば別に設けられた制御回路により制御される。制御回路は、温度センサ60で検出された温度に応じて、薄膜ヒータ21に印加する電圧を調整する。または、薄膜ヒータ21が、温度センサ60の機能を兼ね備えてもよい。 Also in the present embodiment, as in the first embodiment, the variable capacitor 10B may include the temperature sensor 60 for detecting the temperature of the capacitor unit 20a in the thin film layer 50. The variable capacitor 10B is controlled by, for example, a separately provided control circuit. The control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60. Alternatively, the thin film heater 21 may have the function of the temperature sensor 60.
 また、薄膜ヒータ21は、コンデンサ部20aから基板11の方向とは反対方向の層に配置するとしたが、薄膜ヒータ21は、コンデンサ部20aと基板11との間の層、例えば支持層12内に配置されてもよい。または、薄膜ヒータ21は、コンデンサ部20aの誘電体層16内に配置されてもよい。 The thin film heater 21 is arranged in a layer opposite to the direction of the substrate 11 from the capacitor unit 20a. However, the thin film heater 21 is disposed in a layer between the capacitor unit 20a and the substrate 11, for example, in the support layer 12. It may be arranged. Or the thin film heater 21 may be arrange | positioned in the dielectric material layer 16 of the capacitor | condenser part 20a.
 (実施形態4)
 本実施形態における可変容量コンデンサ10Cについて、実施形態1とは異なる点を中心に、図8A~図9Dを用いて説明する。本実施形態の可変容量コンデンサ10Cは、実施形態1の可変容量コンデンサ10と比較して、基板11の一部が多孔質層で形成されている点が異なっている。実施形態1と同様の構成要素には同一の符号を付して説明を適宜省略する。
(Embodiment 4)
A variable capacitor 10C according to the present embodiment will be described with reference to FIGS. 8A to 9D, focusing on differences from the first embodiment. The variable capacitor 10C according to the present embodiment is different from the variable capacitor 10 according to the first embodiment in that a part of the substrate 11 is formed of a porous layer. Constituent elements similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
 本実施形態の可変容量コンデンサ10Cは、実施形態1の可変容量コンデンサ10と同様に、第1電極14、第2電極15及び誘電体層16を有するコンデンサ素子20の静電容量を、誘電体層16の温度を調整することで変更させる。 Similar to the variable capacitor 10 of the first embodiment, the variable capacitor 10C of the present embodiment uses the capacitance of the capacitor element 20 having the first electrode 14, the second electrode 15, and the dielectric layer 16 as the dielectric layer. It is made to change by adjusting the temperature of 16.
 本実施形態の可変容量コンデンサ10Cは、図8A,8Bに示すように、コンデンサ素子20に加えて、基板11、支持層12、層間絶縁膜18、表面保護層19及び薄膜ヒータ21(温度調整素子)を有している。可変容量コンデンサ10Cは、第1密着層13及び第2密着層17を、各々の上下の層の材料に応じて適宜設けてもよい。 As shown in FIGS. 8A and 8B, the variable capacitor 10 </ b> C according to the present embodiment includes a substrate 11, a support layer 12, an interlayer insulating film 18, a surface protective layer 19, and a thin film heater 21 (temperature adjusting element) )have. In the variable capacitor 10 </ b> C, the first adhesion layer 13 and the second adhesion layer 17 may be appropriately provided according to the material of the upper and lower layers.
 本実施形態の可変容量コンデンサ10では、実施形態1と同様に、基板11を最下部とし、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18、薄膜ヒータ21、表面保護層19の順に積層されている。ここで、支持層12、第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18及び表面保護層19により薄膜層50が形成されている。このとき、支持層12の裏面121から表面保護層19の表面191までの厚さ、つまり薄膜層50の厚さは、数μmである。 In the variable capacitor 10 of the present embodiment, as in the first embodiment, the substrate 11 is the lowermost part, and the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the thin film The heater 21 and the surface protective layer 19 are laminated in this order. Here, a thin film layer 50 is formed by the support layer 12, the first adhesion layer 13, the capacitor element 20, the second adhesion layer 17, the interlayer insulating film 18, and the surface protective layer 19. At this time, the thickness from the back surface 121 of the support layer 12 to the surface 191 of the surface protective layer 19, that is, the thickness of the thin film layer 50 is several μm.
 本実施形態では、支持層12の表面の中心点を原点として、支持層12の表面において互いに直交するX軸とY軸とを規定し、支持層12の表面に直交するZ軸を規定している。なお、図8A、図8Bには、X軸方向、Y軸方向、Z軸方向を表す矢印を記載しているが、この矢印は、単に説明を補助する目的で記載しているに過ぎず、実体を伴わない。また、上記の方向の規定は、本実施形態の可変容量コンデンサ10の使用形態を限定する趣旨ではない。 In the present embodiment, with the center point of the surface of the support layer 12 as the origin, the X axis and the Y axis that are orthogonal to each other on the surface of the support layer 12 are defined, and the Z axis that is orthogonal to the surface of the support layer 12 is defined. Yes. 8A and 8B show arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction, but these arrows are merely shown for the purpose of assisting the explanation, It is not accompanied by an entity. Further, the definition of the above direction is not intended to limit the usage pattern of the variable capacitor 10 of the present embodiment.
 基板11は、半導体基板であり、その中央部位には、主表面111から厚さ方向において直方体形状の多孔質層30aを有している。単結晶のSi基板からなる基板11の主表面111は、(100)面である。多孔質層30aの厚さ(Z軸方向の長さ)は、例えば10μmである。なお、この数値は一例であり、この数値に限定する趣旨ではない。 The substrate 11 is a semiconductor substrate, and has a rectangular parallelepiped porous layer 30a in the thickness direction from the main surface 111 at the central portion thereof. The main surface 111 of the substrate 11 made of a single crystal Si substrate is a (100) plane. The thickness (length in the Z-axis direction) of the porous layer 30a is, for example, 10 μm. In addition, this numerical value is an example and is not the meaning limited to this numerical value.
 コンデンサ素子20の第1電極14の下方向(Z軸の矢印とは反対の方向)に多孔質層30aが位置している。コンデンサ部20aと基板11とを熱絶縁する観点からは、表面保護層19から基板11の方向で可変容量コンデンサ10を見た場合に、コンデンサ素子20のうちコンデンサ部20aと多孔質層30aとが重なるように、コンデンサ部20aが規定されることが好ましい。 The porous layer 30a is located below the first electrode 14 of the capacitor element 20 (the direction opposite to the Z-axis arrow). From the viewpoint of thermally insulating the capacitor portion 20a and the substrate 11, when the variable capacitor 10 is viewed in the direction from the surface protective layer 19 to the substrate 11, the capacitor portion 20a and the porous layer 30a of the capacitor element 20 are It is preferable that the capacitor portion 20a is defined so as to overlap.
 支持層12は、実施形態1と同様に、基板11上のSiO膜とSiO膜上のSi膜との積層膜からなる。支持層12において、コンデンサ素子20が設けられる面とは反対の面(裏面121)が多孔質層30aに接している(図8B参照)。 As in the first embodiment, the support layer 12 is composed of a laminated film of a SiO 2 film on the substrate 11 and a Si 3 N 4 film on the SiO 2 film. In the support layer 12, the surface (back surface 121) opposite to the surface on which the capacitor element 20 is provided is in contact with the porous layer 30a (see FIG. 8B).
 第1密着層13、コンデンサ素子20、第2密着層17、層間絶縁膜18、表面保護層19及び薄膜ヒータ21については、実施形態1と同様であるので、ここでの説明は省略する。 Since the first adhesive layer 13, the capacitor element 20, the second adhesive layer 17, the interlayer insulating film 18, the surface protective layer 19, and the thin film heater 21 are the same as those in the first embodiment, the description thereof is omitted here.
 本実施形態の可変容量コンデンサ10Cは、実施形態1と同様に、表面保護層19から第1パッド電極20bに至る第1開口部31と、表面保護層19から第2パッド電極20cに至る第2開口部32とを、更に有している。第1パッド電極20bと第2パッド電極20cとを電源と電気的に接続することで、コンデンサ部20aに電荷が蓄積される。 Similarly to the first embodiment, the variable capacitor 10C according to the present embodiment includes a first opening 31 extending from the surface protective layer 19 to the first pad electrode 20b, and a second opening extending from the surface protective layer 19 to the second pad electrode 20c. An opening 32 is further provided. By electrically connecting the first pad electrode 20b and the second pad electrode 20c to a power source, charges are accumulated in the capacitor unit 20a.
 さらに、可変容量コンデンサ10Cは、実施形態1と同様に、表面保護層19から薄膜ヒータ21の第1パッド電極211に至る第3開口部33と、表面保護層19から薄膜ヒータ21の第2パッド電極212に至る第4開口部34とを、更に有している。薄膜ヒータ21の第1パッド電極211と第2パッド電極212との間に電圧を印加すると、薄膜ヒータ21は熱を発する。薄膜ヒータ21より発せられた熱は、コンデンサ部20aの誘電体層16に伝達される。このとき、薄膜ヒータ21のヒータ部215はコンデンサ部20aの上方に層間絶縁膜18を介して設けられているので、コンデンサ部20aにおける誘電体層16の全体に熱が伝達される。誘電体層16は、温度が変化すると比誘電率が変化する。そのため、薄膜ヒータ21から伝達された熱により誘電体層16の温度が変化することで、コンデンサ素子20の静電容量が変更する。つまり、コンデンサ素子20では、誘電体層16の温度に応じて静電容量が変更する。可変容量コンデンサ10は、薄膜ヒータ21に印加される電圧が調整されることで、コンデンサ素子20の静電容量が調整される。なお、コンデンサ素子20の静電容量を調整するためには、ヒータ部215がジュール熱を発生できればよいので、薄膜ヒータ21に流れる電流の量を調整してもよい。 Further, similarly to the first embodiment, the variable capacitor 10 </ b> C includes a third opening 33 extending from the surface protective layer 19 to the first pad electrode 211 of the thin film heater 21, and a second pad of the thin film heater 21 from the surface protective layer 19. A fourth opening 34 reaching the electrode 212 is further provided. When a voltage is applied between the first pad electrode 211 and the second pad electrode 212 of the thin film heater 21, the thin film heater 21 generates heat. The heat generated from the thin film heater 21 is transmitted to the dielectric layer 16 of the capacitor unit 20a. At this time, since the heater portion 215 of the thin film heater 21 is provided above the capacitor portion 20a via the interlayer insulating film 18, heat is transmitted to the entire dielectric layer 16 in the capacitor portion 20a. The relative permittivity of the dielectric layer 16 changes as the temperature changes. Therefore, the capacitance of the capacitor element 20 is changed by the temperature of the dielectric layer 16 being changed by the heat transmitted from the thin film heater 21. In other words, the capacitance of the capacitor element 20 changes according to the temperature of the dielectric layer 16. In the variable capacitor 10, the capacitance applied to the capacitor element 20 is adjusted by adjusting the voltage applied to the thin film heater 21. In order to adjust the capacitance of the capacitor element 20, it is only necessary that the heater unit 215 can generate Joule heat. Therefore, the amount of current flowing through the thin film heater 21 may be adjusted.
 ここで、薄膜ヒータ21のヒータ部215は、コンデンサ部20aの誘電体層16の温度を誘電体層16が強誘電体から常誘電体に変化するキュリー温度以上に調整するように制御されることで、コンデンサ部20aの静電容量を変化させることが好ましい。 Here, the heater portion 215 of the thin film heater 21 is controlled so as to adjust the temperature of the dielectric layer 16 of the capacitor portion 20a to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material. Thus, it is preferable to change the capacitance of the capacitor portion 20a.
 次に、本実施形態の可変容量コンデンサ10Cの製造方法について、図9A~図9Dを用いて説明する。 Next, a method for manufacturing the variable capacitor 10C according to the present embodiment will be described with reference to FIGS. 9A to 9D.
 基板11の主表面111上に、通電用電極300を取り付ける(図9A参照)。通電用電極300が取り付けられた基板11に対して陽極酸化処理を施して多孔質層30aを形成する(図9B参照)。具体的には、通電用電極300が取り付けられた基板11を電界溶液に浸漬して、主表面111と反対の面112に対向するように白金電極を配置する。通電用電極300に電流源の正極側を、白金電極に負極側を、それぞれ接続する。その後、多孔質層30aの厚さ及び多孔度に応じて、電流源から通電用電極と白金電極との間に所定の電流密度の電流を所定の時間だけ流す。また、多孔度をより高くするために、基板11の比抵抗及び電流密度のそれぞれを高くしてもよい。多孔質層30aの多孔度は、5%~80%に設けることができる。また、多孔質層30aの平均細孔径は、0.1μm~3μmに設けることができる。 A current-carrying electrode 300 is attached on the main surface 111 of the substrate 11 (see FIG. 9A). A porous layer 30a is formed by anodizing the substrate 11 to which the energizing electrode 300 is attached (see FIG. 9B). Specifically, the substrate 11 to which the energizing electrode 300 is attached is immersed in an electric field solution, and a platinum electrode is disposed so as to face the surface 112 opposite to the main surface 111. The positive electrode side of the current source is connected to the energizing electrode 300, and the negative electrode side is connected to the platinum electrode. Then, according to the thickness and porosity of the porous layer 30a, a current having a predetermined current density is allowed to flow from the current source between the energization electrode and the platinum electrode for a predetermined time. Further, in order to increase the porosity, each of the specific resistance and current density of the substrate 11 may be increased. The porosity of the porous layer 30a can be set to 5% to 80%. The average pore diameter of the porous layer 30a can be set to 0.1 μm to 3 μm.
 基板11に多孔質層30aを形成した後、通電用電極300を除去する(図9C参照)。通電用電極300が除去された基板11に主表面111上に、熱酸化法によりSiO膜を形成し、続いて、LPCVDによりSi膜を形成することにより、SiO膜とSi膜との積層膜からなる支持層12を形成する(図9D参照)。 After the porous layer 30a is formed on the substrate 11, the energizing electrode 300 is removed (see FIG. 9C). A SiO 2 film is formed on the main surface 111 on the substrate 11 from which the energizing electrode 300 has been removed by a thermal oxidation method, and then an Si 3 N 4 film is formed by LPCVD, whereby the SiO 2 film and the Si 3 film are formed. A support layer 12 made of a laminated film with an N 4 film is formed (see FIG. 9D).
 以降の工程は、実施形態1で説明した図2B~図2Hまでの工程と同様であるので、ここでの説明は省略する。 Since the subsequent steps are the same as the steps from FIG. 2B to FIG. 2H described in the first embodiment, description thereof is omitted here.
 以上の工程を経て可変容量コンデンサ10Cが製造される。 The variable capacitor 10C is manufactured through the above steps.
 なお、本実施形態では、可変容量コンデンサ10Cは、抵抗加熱素子として薄膜ヒータ21を備えているが、薄膜ヒータ21に限らず、例えばペルチェ素子を用いてもよい。 In the present embodiment, the variable capacitor 10C includes the thin film heater 21 as a resistance heating element. However, the variable capacitor 10C is not limited to the thin film heater 21 and may be a Peltier element, for example.
 また、可変容量コンデンサ10Cは、実施形態1と同様に、コンデンサ素子20におけるコンデンサ部20aの温度を検出する温度センサ60を薄膜層50内に備えてもよい。可変容量コンデンサ10Cは、例えば別に設けられた制御回路によって制御される。制御回路は、温度センサ60で検出された温度に応じて、薄膜ヒータ21に印加する電圧を調整する。または、薄膜ヒータ21が、温度センサ60の機能を兼ね備えてもよい。 Further, the variable capacitor 10 </ b> C may include a temperature sensor 60 for detecting the temperature of the capacitor unit 20 a in the capacitor element 20 in the thin film layer 50, as in the first embodiment. The variable capacitor 10C is controlled by a control circuit provided separately, for example. The control circuit adjusts the voltage applied to the thin film heater 21 according to the temperature detected by the temperature sensor 60. Alternatively, the thin film heater 21 may have the function of the temperature sensor 60.
 また、薄膜ヒータ21は、コンデンサ部20aから基板11とは反対の層(層間絶縁膜18と表面保護層19とからなる層)内に配置してあるが、薄膜ヒータ21は、コンデンサ部20aと基板11との間の層に配置してもよい。例えば、薄膜ヒータ21は、支持層12内に配置されてもよい。または、薄膜ヒータ21は、コンデンサ部20aの誘電体層16内に設けられてもよい。つまり、薄膜ヒータ21は、薄膜層50内に設けられていればよい。 The thin film heater 21 is disposed in a layer opposite to the substrate 11 from the capacitor portion 20a (a layer made of the interlayer insulating film 18 and the surface protective layer 19), but the thin film heater 21 is connected to the capacitor portion 20a. You may arrange | position in the layer between the board | substrates 11. For example, the thin film heater 21 may be disposed in the support layer 12. Alternatively, the thin film heater 21 may be provided in the dielectric layer 16 of the capacitor unit 20a. That is, the thin film heater 21 only needs to be provided in the thin film layer 50.
 また、本実施形態の可変容量コンデンサ10Cが備える基板11は、半導体基板としたが、半導体基板に限らず、セラミック等の基板であってもよい。 Further, the substrate 11 provided in the variable capacitor 10C of the present embodiment is a semiconductor substrate, but is not limited to a semiconductor substrate, and may be a substrate made of ceramic or the like.
 また、基板11の一部を多孔質層30aとして形成したが、これに限らず、基板11の全体を多孔質層30aとして形成してもよい。 Moreover, although a part of the substrate 11 is formed as the porous layer 30a, the present invention is not limited to this, and the entire substrate 11 may be formed as the porous layer 30a.
 また、本実施形態の可変容量コンデンサ10Cは、実施形態1の可変容量コンデンサ10の空隙30の代わりに多孔質層30aを形成している。同様に、実施形態2の可変容量コンデンサ10Aの空隙30の代わりに多孔質層30aを形成してもよいし、実施形態3の可変容量コンデンサ10Bの空隙30の代わりに多孔質層30aを形成してもよい。 Further, the variable capacitor 10C of the present embodiment forms a porous layer 30a instead of the gap 30 of the variable capacitor 10 of the first embodiment. Similarly, a porous layer 30a may be formed instead of the gap 30 of the variable capacitor 10A of the second embodiment, or a porous layer 30a may be formed instead of the gap 30 of the variable capacitor 10B of the third embodiment. May be.
 (まとめ)
 以上説明したように、第1の態様の可変容量コンデンサ10(10A,10B,10C)は、基板11と、コンデンサ部20aと、薄膜層50と、温度調整素子(薄膜ヒータ21)とを備える。コンデンサ部20aは、第1電極14、第2電極15及び第1電極14と第2電極15との間に設けられた誘電体層16とを有し、基板11に設けられている。薄膜層50は、コンデンサ部20aを覆う。温度調整素子は、誘電体層16の温度を調整してコンデンサ部20aの静電容量を変更させる。
(Summary)
As described above, the variable capacitor 10 (10A, 10B, 10C) of the first aspect includes the substrate 11, the capacitor unit 20a, the thin film layer 50, and the temperature adjusting element (thin film heater 21). The capacitor unit 20 a includes the first electrode 14, the second electrode 15, and the dielectric layer 16 provided between the first electrode 14 and the second electrode 15, and is provided on the substrate 11. The thin film layer 50 covers the capacitor portion 20a. The temperature adjusting element adjusts the temperature of the dielectric layer 16 to change the capacitance of the capacitor unit 20a.
 この構成によると、可変容量コンデンサ10(10A,10B,10C)は、誘電体層16の比誘電率は温度に依存しているため、温度を変化させることで、コンデンサ素子の静電容量を変更させることができる。 According to this configuration, in the variable capacitor 10 (10A, 10B, 10C), since the relative dielectric constant of the dielectric layer 16 depends on the temperature, the capacitance of the capacitor element is changed by changing the temperature. Can be made.
 第2の態様の可変容量コンデンサ10(10A,10B)では、第1の態様において、基板11は、空隙30を有している。薄膜層50は、基板11とコンデンサ部20aとの間に配置され、コンデンサ部20aを支持する支持層12を有している。支持層12において、コンデンサ部20aが積層される面とは反対の面が、空隙30から露出している。 In the variable capacitor 10 (10A, 10B) of the second aspect, the substrate 11 has a gap 30 in the first aspect. The thin film layer 50 is disposed between the substrate 11 and the capacitor portion 20a, and has a support layer 12 that supports the capacitor portion 20a. In the support layer 12, the surface opposite to the surface on which the capacitor portion 20 a is laminated is exposed from the gap 30.
 この構成によると、コンデンサ部20aから基板11の方向に可変容量コンデンサ10を見た場合、コンデンサ部20aは、空隙30と重なっているので、薄膜ヒータ21で発せられた熱は、基板11を介して逃げにくくなる。また、支持層12が設けられることで、支持層12に積層された層(薄膜)の残留応力の調整を行うことができる。 According to this configuration, when the variable capacitor 10 is viewed in the direction from the capacitor unit 20 a to the substrate 11, the capacitor unit 20 a overlaps the air gap 30, so that the heat generated by the thin film heater 21 passes through the substrate 11. It becomes difficult to escape. Further, by providing the support layer 12, the residual stress of the layer (thin film) laminated on the support layer 12 can be adjusted.
 第3の態様の可変容量コンデンサ10Cでは、第1の態様において、基板11は、多孔質層30aを有している。薄膜層50は、基板11とコンデンサ部20aとの間に配置され、コンデンサ部20aを支持する支持層12を有している。支持層12において、コンデンサ部20aが積層される面とは反対の面が、多孔質層30aに接している。 In the variable capacitor 10C according to the third aspect, in the first aspect, the substrate 11 has the porous layer 30a. The thin film layer 50 is disposed between the substrate 11 and the capacitor portion 20a, and has a support layer 12 that supports the capacitor portion 20a. In the support layer 12, the surface opposite to the surface on which the capacitor portion 20a is laminated is in contact with the porous layer 30a.
 この構成によると、基板11に空隙30を設ける場合と比較して基板11の強度が強くなる。コンデンサ部20aは、多孔質層30aと重なっているので、薄膜ヒータ21で発せられた熱は、多孔質層30a以外の基板11を介して逃げにくくなる。また、支持層12が設けられることで、支持層12に積層された層(薄膜)の残留応力の調整を行うことができる。 According to this configuration, the strength of the substrate 11 is increased as compared with the case where the air gap 30 is provided in the substrate 11. Since the capacitor portion 20a overlaps the porous layer 30a, the heat generated by the thin film heater 21 is difficult to escape via the substrate 11 other than the porous layer 30a. Further, by providing the support layer 12, the residual stress of the layer (thin film) laminated on the support layer 12 can be adjusted.
 第4の態様の可変容量コンデンサ10(10A,10B,10C)では、第1~第3のいずれかの態様において、基板11は、半導体基板である。 In the variable capacitor 10 (10A, 10B, 10C) of the fourth aspect, in any one of the first to third aspects, the substrate 11 is a semiconductor substrate.
 この構成によると、基板11の加工が容易となり、基板11を一括形成できるため製造コストを抑えることができる。 According to this configuration, the substrate 11 can be easily processed, and the substrate 11 can be formed at a time, so that the manufacturing cost can be reduced.
 第5の態様の可変容量コンデンサ10(10A,10B,10C)では、第1~第4のいずれかの態様において、温度調整素子は、薄膜層50に設けられている。 In the variable capacitor 10 (10A, 10B, 10C) of the fifth aspect, the temperature adjusting element is provided in the thin film layer 50 in any of the first to fourth aspects.
 この構成によると、薄膜ヒータ21から誘電体層16までの距離が短いため応答性に優れ、さらに熱のロスが少なく、低消費電力で誘電体層16の温度を変化させることができる。 According to this configuration, since the distance from the thin film heater 21 to the dielectric layer 16 is short, the response is excellent, the heat loss is small, and the temperature of the dielectric layer 16 can be changed with low power consumption.
 第6の態様の可変容量コンデンサ10(10A,10B,10C)では、第1~第5のいずれかの態様において、温度調整素子は、抵抗加熱素子である。 In the variable capacitor 10 (10A, 10B, 10C) of the sixth aspect, in any of the first to fifth aspects, the temperature adjustment element is a resistance heating element.
 この構成によると、半導体加工技術での形成が容易となり、薄膜ヒータ21を一括形成できるため製造コストを抑えることができる。 According to this configuration, the formation by the semiconductor processing technology is facilitated, and the thin film heater 21 can be formed at a time, so that the manufacturing cost can be suppressed.
 第7の態様の可変容量コンデンサ10(10A,10B,10C)では、第1~第6のいずれかの態様において、誘電体層16は、強誘電体である。温度調整素子は、誘電体層16の温度を誘電体層16が強誘電体から常誘電体に変化するキュリー温度以上に調整するように制御されることで、コンデンサ部20aの静電容量を変化させる。 In the variable capacitor 10 (10A, 10B, 10C) of the seventh aspect, in any one of the first to sixth aspects, the dielectric layer 16 is a ferroelectric substance. The temperature adjustment element changes the capacitance of the capacitor portion 20a by controlling the temperature of the dielectric layer 16 to be equal to or higher than the Curie temperature at which the dielectric layer 16 changes from a ferroelectric material to a paraelectric material. Let
 この構成によると、コンデンサ部20aの誘電体層16の温度が調整されるので熱損失を抑えることができる。 According to this configuration, since the temperature of the dielectric layer 16 of the capacitor unit 20a is adjusted, heat loss can be suppressed.
 第8の態様の可変容量コンデンサ10(10A,10B,10C)は、第1~第7のいずれかの態様において、コンデンサ部20aの温度を検出する温度センサ60を、更に備える。 The variable capacitor 10 (10A, 10B, 10C) of the eighth aspect further includes a temperature sensor 60 for detecting the temperature of the capacitor unit 20a in any one of the first to seventh aspects.
 この構成によると、検出結果に基づいて薄膜ヒータ21に印加する電圧を調整することができる。つまり、検出結果に基づいて薄膜ヒータ21が発する熱を調整することで、誘電体層16の温度を調整することができる。 According to this configuration, the voltage applied to the thin film heater 21 can be adjusted based on the detection result. That is, the temperature of the dielectric layer 16 can be adjusted by adjusting the heat generated by the thin film heater 21 based on the detection result.
   10,10A,10B,10C  可変容量コンデンサ
   11  基板
   12  支持層
   14  第1電極
   15  第2電極
   16  誘電体層
   20a  コンデンサ部
   21  薄膜ヒータ(温度調整素子)
   30  空隙
   30a  多孔質層
   50  薄膜層
   60  温度センサ
10, 10A, 10B, 10C Variable capacitor 11 Substrate 12 Support layer 14 First electrode 15 Second electrode 16 Dielectric layer 20a Capacitor part 21 Thin film heater (temperature adjusting element)
30 Void 30a Porous layer 50 Thin film layer 60 Temperature sensor

Claims (8)

  1.  基板と、
     第1電極、第2電極及び前記第1電極と前記第2電極との間に設けられた誘電体層とを有し、前記基板に設けられたコンデンサ部と、
     前記コンデンサ部を覆う薄膜層と、
     前記誘電体層の温度を調整して前記コンデンサ部の静電容量を変更させる温度調整素子とを備える
     ことを特徴とする可変容量コンデンサ。
    A substrate,
    A first electrode, a second electrode, and a dielectric layer provided between the first electrode and the second electrode, and a capacitor unit provided on the substrate;
    A thin film layer covering the capacitor portion;
    A variable capacitance capacitor comprising: a temperature adjustment element that adjusts a temperature of the dielectric layer to change a capacitance of the capacitor unit.
  2.  前記基板は、空隙を有しており、
     前記薄膜層は、前記基板と前記コンデンサ部との間に配置され、前記コンデンサ部を支持する支持層を有しており、
     前記支持層において、前記コンデンサ部が積層される面とは反対の面が、前記空隙から露出している
     ことを特徴とする請求項1に記載の可変容量コンデンサ。
    The substrate has voids;
    The thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit,
    2. The variable capacitor according to claim 1, wherein a surface of the support layer opposite to a surface on which the capacitor portion is laminated is exposed from the gap.
  3.  前記基板は、多孔質層を有しており、
     前記薄膜層は、前記基板と前記コンデンサ部との間に配置され、前記コンデンサ部を支持する支持層を有しており、
     前記支持層において、前記コンデンサ部が積層される面とは反対の面が、前記多孔質層に接している
     ことを特徴とする請求項1に記載の可変容量コンデンサ。
    The substrate has a porous layer;
    The thin film layer is disposed between the substrate and the capacitor unit, and has a support layer that supports the capacitor unit,
    2. The variable capacitor according to claim 1, wherein a surface of the support layer opposite to a surface on which the capacitor portion is laminated is in contact with the porous layer.
  4.  前記基板は、半導体基板である
     ことを特徴とする請求項1~3のいずれか一項に記載の可変容量コンデンサ。
    The variable capacitor according to any one of claims 1 to 3, wherein the substrate is a semiconductor substrate.
  5.  前記温度調整素子は、前記薄膜層に設けられている
     ことを特徴とする請求項1~4のいずれか一項に記載の可変容量コンデンサ。
    The variable capacitor according to any one of claims 1 to 4, wherein the temperature adjustment element is provided in the thin film layer.
  6.  前記温度調整素子は、抵抗加熱素子である
     ことを特徴とする請求項1~5のいずれか一項に記載の可変容量コンデンサ。
    The variable capacitor according to any one of claims 1 to 5, wherein the temperature adjusting element is a resistance heating element.
  7.  前記誘電体層は、強誘電体であり、
     前記温度調整素子は、前記誘電体層の温度を前記誘電体層が強誘電体から常誘電体に変化するキュリー温度以上に調整するように制御されることで、前記コンデンサ部の静電容量を変化させる
     ことを特徴とする請求項1~6のいずれか一項に記載の可変容量コンデンサ。
    The dielectric layer is a ferroelectric;
    The temperature adjusting element is controlled so that the temperature of the dielectric layer is adjusted to be equal to or higher than a Curie temperature at which the dielectric layer changes from a ferroelectric material to a paraelectric material. The variable capacitor according to any one of claims 1 to 6, wherein the capacitor is changed.
  8.  前記コンデンサ部の温度を検出する温度センサを、更に備える
     ことを特徴とする請求項1~7のいずれか一項に記載の可変容量コンデンサ。
    The variable capacitor according to any one of claims 1 to 7, further comprising a temperature sensor that detects a temperature of the capacitor unit.
PCT/JP2017/018127 2016-05-30 2017-05-15 Variable capacitor WO2017208790A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019127256A (en) * 2018-01-23 2019-08-01 株式会社デンソー Seat heater
WO2019146282A1 (en) * 2018-01-23 2019-08-01 株式会社デンソー Seat heater

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JPS60169125A (en) * 1984-02-10 1985-09-02 日新電機株式会社 Condenser unit
JPH03180730A (en) * 1989-12-08 1991-08-06 Omron Corp Temperature measuring instrument
JPH09145479A (en) * 1995-11-29 1997-06-06 New Japan Radio Co Ltd Noncontact type temperature sensor
JP2000039458A (en) * 1998-07-22 2000-02-08 Canon Inc Potential measuring apparatus and image forming apparatus
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60169125A (en) * 1984-02-10 1985-09-02 日新電機株式会社 Condenser unit
JPH03180730A (en) * 1989-12-08 1991-08-06 Omron Corp Temperature measuring instrument
JPH09145479A (en) * 1995-11-29 1997-06-06 New Japan Radio Co Ltd Noncontact type temperature sensor
JP2000039458A (en) * 1998-07-22 2000-02-08 Canon Inc Potential measuring apparatus and image forming apparatus
US20130141834A1 (en) * 2011-12-02 2013-06-06 Stmicroelectronics Pte Ltd. Capacitance trimming with an integrated heater

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019127256A (en) * 2018-01-23 2019-08-01 株式会社デンソー Seat heater
WO2019146282A1 (en) * 2018-01-23 2019-08-01 株式会社デンソー Seat heater

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