WO2017201676A1 - Mécanisme de fenêtre auto-adaptatif - Google Patents

Mécanisme de fenêtre auto-adaptatif Download PDF

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Publication number
WO2017201676A1
WO2017201676A1 PCT/CN2016/083192 CN2016083192W WO2017201676A1 WO 2017201676 A1 WO2017201676 A1 WO 2017201676A1 CN 2016083192 W CN2016083192 W CN 2016083192W WO 2017201676 A1 WO2017201676 A1 WO 2017201676A1
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WIPO (PCT)
Prior art keywords
sabm
logic
window
image
input image
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PCT/CN2016/083192
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English (en)
Inventor
Feng Chen
Yi Yang
Zhenyang CHEN
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Intel Corporation
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Priority to CN201680085150.4A priority Critical patent/CN109643395B/zh
Priority to PCT/CN2016/083192 priority patent/WO2017201676A1/fr
Publication of WO2017201676A1 publication Critical patent/WO2017201676A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks

Definitions

  • the present disclosure generally relates to Convolutional Neural Networks.
  • CNNs are a type of feed-forward artificial neural network in which a connectivity pattern between neurons is inspired by organization of an animal visual cortex (e.g., individual neurons are arranged in a manner such that they respond to overlapping regions tiling a visual field.
  • CNNs are currently implemented in various computing platforms (e.g., data centers, mobile devices, etc. ) to perform a wide range of applications, including image and video recognition, natural language processing, and recommender systems, etc.
  • CNN training typically involves designing and tuning a black box target. Areas in the input image at which the current CNN model learning features perform classification must be detected.
  • Figure 1 is a block diagram of a processing system, according to an embodiment.
  • Figure 2 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.
  • FIG. 3 is a block diagram of a graphics processor, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores.
  • FIG. 4 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments.
  • Figure 5 is a block diagram of another embodiment of a graphics processor.
  • Figure 6 illustrates thread execution logic including an array of processing elements employed in some embodiments of a graphics processing engine.
  • Figure 7 is a block diagram illustrating a graphics processor instruction formats according to some embodiments.
  • Figure 8 is a block diagram of another embodiment of a graphics processor.
  • Figure 9A is a block diagram illustrating a graphics processor command format according to an embodiment
  • Figure 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment.
  • Figure 10 illustrates exemplary graphics software architecture for a data processing system according to some embodiments.
  • FIG 11 is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.
  • Figure 12 is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
  • Figure 13 is a block diagram illustrating an exemplary graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
  • Figure 14 is a block diagram illustrating an additional exemplary graphics processor 1410 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
  • Figure 15 illustrates a computing device employing a training mechanism according to one embodiment.
  • Figure 16A illustrates one embodiment of an input image
  • Figures 16B &16C illustrate embodiments windows for the image.
  • Figures 17A & 17B illustrate embodiments of a normalized sensitivity map.
  • FIGS 18A–18F illustrate other embodiments of windows for the image.
  • FIGS 19A–19C illustrate other embodiments of windows for the image.
  • Figures 20A & 20B illustrate a training method according to one embodiment.
  • Embodiments provide for a Convolutional Neural Network (CNN) training mechanism that implements a self-adaptive bi-direction mask window and a normalized sensitivity map to assist in training a deep learning training system.
  • CNN Convolutional Neural Network
  • the training mechanism handles visualization of multiple irregular zones related to a sub-category feature.
  • the size of the area may range from very large to very small, (e.g., face areas related a specific face attribute, or a disease pattern spread over medical images) .
  • the training mechanism may operate with any type of CNN model without having to modify the CNN structure.
  • an “application” or “agent” may refer to or include a computer program, a software application, a game, a workstation application, etc., offered through an API, such as a free rendering API, such as Open Graphics Library 11, 12, etc., where “dispatch” may be interchangeably referred to as “work unit” or “draw” and similarly, “application” may be interchangeably referred to as “workflow” or simply “agent” .
  • a workload such as that of a 3D game, may include and issue any number and type of “frames” where each frame may represent an image (e.g., sailboat, human face) . Further, each frame may include and offer any number and type of work units, where each work unit may represent a part (e.g., mast of sailboat, forehead of human face) of the image (e.g., sailboat, human face) represented by its corresponding frame.
  • each item may be referenced by a single term (e.g., “dispatch” , “agent” , etc. ) throughout this document.
  • ⁇ may be used interchangeably referring to the visible portion of a display device while the rest of the display device may be embedded into a computing device, such as a smartphone, a wearable device, etc. It is contemplated and to be noted that embodiments are not limited to any particular computing device, software application, hardware component, display device, display screen or surface, protocol, standard, etc. For example, embodiments may be applied to and used with any number and type of real-time applications on any number and type of computers, such as desktops, laptops, tablet computers, smartphones, head-mounted displays and other wearable devices, and/or the like. Further, for example, rendering scenarios for efficient performance using this novel technique may range from simple scenarios, such as desktop compositing, to complex scenarios, such as 3D games, augmented reality applications, etc.
  • Figure 1 is a block diagram of a processing system 100, according to an embodiment.
  • the system 100 includes one or more processors 102 and one or more graphics processors 108, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 102 or processor cores 107.
  • the system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.
  • SoC system-on-a-chip
  • An embodiment of system 100 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console.
  • system 100 is a mobile phone, smart phone, tablet computing device or mobile Internet device.
  • Data processing system 100 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device.
  • data processing system 100 is a television or set top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.
  • the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system and user software.
  • each of the one or more processor cores 107 is configured to process a specific instruction set 109.
  • instruction set 109 may facilitate Complex Instruction Set Computing (CISC) , Reduced Instruction Set Computing (RISC) , or computing via a Very Long Instruction Word (VLIW) .
  • Multiple processor cores 107 may each process a different instruction set 109, which may include instructions to facilitate the emulation of other instruction sets.
  • Processor core 107 may also include other processing devices, such a Digital Signal Processor (DSP) .
  • DSP Digital Signal Processor
  • the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC) ) (not shown) , which may be shared among processor cores 107 using known cache coherency techniques.
  • L3 cache Level-3
  • LLC Last Level Cache
  • a register file 106 is additionally included in processor 102 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) . Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 102.
  • processor 102 is coupled with a processor bus 110 to transmit communication signals such as address, data, or control signals between processor 102 and other components in system 100.
  • the system 100 uses an exemplary ‘hub’ s ystem architecture, including a memory controller hub 116 and an Input Output (I/O) controller hub 130.
  • a memory controller hub 116 facilitates communication between a memory device and other components of system 100, while an I/O Controller Hub (ICH) 130 provides connections to I/O devices via a local I/O bus.
  • the logic of the memory controller hub 116 is integrated within the processor.
  • Memory device 120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory.
  • the memory device 120 can operate as system memory for the system 100, to store data 122 and instructions 121 for use when the one or more processors 102 executes an application or process.
  • Memory controller hub 116 also couples with an optional external graphics processor 112, which may communicate with the one or more graphics processors 108 in processors 102 to perform graphics and media operations.
  • ICH 130 enables peripherals to connect to memory device 120 and processor 102 via a high-speed I/O bus.
  • the I/O peripherals include, but are not limited to, an audio controller 146, a firmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi, Bluetooth) , a data storage device 124 (e.g., hard disk drive, flash memory, etc. ) , and a legacy I/O controller 140 for coupling legacy (e.g., Personal System 2 (PS/2) ) devices to the system.
  • legacy I/O controller 140 for coupling legacy (e.g., Personal System 2 (PS/2) ) devices to the system.
  • PS/2 Personal System 2
  • USB Universal Serial Bus
  • a network controller 134 may also couple with ICH 130.
  • a high-performance network controller (not shown) couples with processor bus 110.
  • the system 100 shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used.
  • the I/O controller hub 130 may be integrated within the one or more processor 102, or the memory controller hub 116 and I/O controller hub 130 may be integrated into a discreet external graphics processor, such as the external graphics processor 112.
  • FIG. 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208.
  • processor 200 can include additional cores up to and including additional core 202N represented by the dashed lined boxes.
  • processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments each processor core also has access to one or more shared cached units 206.
  • the internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200.
  • the cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2) , Level 3 (L3) , Level 4 (L4) , or other levels of cache, where the highest level of cache before external memory is classified as the LLC.
  • cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.
  • processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210.
  • the one or more bus controller units 216 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express) .
  • System agent core 210 provides management functionality for the various processor components.
  • system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown) .
  • one or more of the processor cores 202A-202N include support for simultaneous multi-threading.
  • the system agent core 210 includes components for coordinating and operating cores 202A-202N during multi-threaded processing.
  • System agent core 210 may additionally include a power control unit (PCU) , which includes logic and components to regulate the power state of processor cores 202A-202N and graphics processor 208.
  • PCU power control unit
  • processor 200 additionally includes graphics processor 208 to execute graphics processing operations.
  • the graphics processor 208 couples with the set of shared cache units 206, and the system agent core 210, including the one or more integrated memory controllers 214.
  • a display controller 211 is coupled with the graphics processor 208 to drive graphics processor output to one or more coupled displays.
  • display controller 211 may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208 or system agent core 210.
  • a ring based interconnect unit 212 is used to couple the internal components of the processor 200.
  • an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art.
  • graphics processor 208 couples with the ring interconnect 212 via an I/O link 213.
  • the exemplary I/O link 213 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module.
  • a high-performance embedded memory module 218, such as an eDRAM module such as an eDRAM module.
  • each of the processor cores 202A-202N and graphics processor 208 use embedded memory modules 218 as a shared Last Level Cache.
  • processor cores 202A-202N are homogenous cores executing the same instruction set architecture.
  • processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA) , where one or more of processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set.
  • processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption.
  • processor 200 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.
  • FIG. 3 is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores.
  • the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory.
  • graphics processor 300 includes a memory interface 314 to access memory.
  • Memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.
  • graphics processor 300 also includes a display controller 302 to drive display output data to a display device 320.
  • Display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements.
  • graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.
  • MPEG Moving Picture Experts Group
  • AVC Advanced Video Coding
  • JPEG Joint Photographic Experts Group
  • graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers.
  • 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 310.
  • GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.
  • GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc. ) .
  • the 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 315. While 3D pipeline 312 can be used to perform media operations, an embodiment of GPE 310 also includes a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.
  • media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 306.
  • media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 315. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system 315.
  • 3D/Media subsystem 315 includes logic for executing threads spawned by 3D pipeline 312 and media pipeline 316.
  • the pipelines send thread execution requests to 3D/Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources.
  • the execution resources include an array of graphics execution units to process the 3D and media threads.
  • 3D/Media subsystem 315 includes one or more internal caches for thread instructions and data.
  • the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.
  • FIG 4 is a block diagram of a graphics processing engine 410 of a graphics processor in accordance with some embodiments.
  • the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in Figure 3.
  • Elements of Figure 4 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.
  • the 3D pipeline 312 and media pipeline 316 of Figure 3 are illustrated.
  • the media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410.
  • a separate media and/or image processor is coupled to the GPE 410.
  • GPE 410 couples with or includes a command streamer 403, which provides a command stream to the 3D pipeline 312 and/or media pipelines 316.
  • command streamer 403 is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory.
  • command streamer 403 receives commands from the memory and sends the commands to 3D pipeline 312 and/or media pipeline 316.
  • the commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline 312 and media pipeline 316.
  • the ring buffer can additionally include batch command buffers storing batches of multiple commands.
  • the commands for the 3D pipeline 312 can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline 312 and/or image data and memory objects for the media pipeline 316.
  • the 3D pipeline 312 and media pipeline 316 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array 414.
  • the 3D pipeline 312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array 414.
  • the graphics core array 414 provides a unified block of execution resources.
  • Multi-purpose execution logic e.g., execution units
  • within the graphic core array 414 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.
  • the graphics core array 414 also includes execution logic to perform media functions, such as video and/or image processing.
  • the execution units additionally include general-purpose logic that is programmable to perform parallel general purpose computational operations, in addition to graphics processing operations.
  • the general purpose logic can perform processing operations in parallel or in conjunction with general purpose logic within the processor core (s) 107 of Figure 1 or core 202A-202N as in Figure 2.
  • Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418.
  • the URB 418 can store data for multiple threads.
  • the URB 418 may be used to send data between different threads executing on the graphics core array 414.
  • the URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.
  • graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410.
  • the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.
  • the graphics core array 414 couples with shared function logic 420 that includes multiple resources that are shared between the graphics cores in the graphics core array.
  • the shared functions within the shared function logic 420 are hardware logic units that provide specialized supplemental functionality to the graphics core array 414.
  • shared function logic 420 includes but is not limited to sampler 421, math 422, and inter-thread communication (ITC) 423 logic.
  • ITC inter-thread communication
  • some embodiments implement one or more cache (s) 425 within the shared function logic 420.
  • a shared function is implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array 414. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic 420 and shared among the execution resources within the graphics core array 414.
  • the precise set of functions that are shared between the graphics core array 414 and included within the graphics core array 414 varies between embodiments.
  • Figure 5 is a block diagram of another embodiment of a graphics processor 500. Elements of Figure 5 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.
  • graphics processor 500 includes a ring interconnect 502, a pipeline front-end 504, a media engine 537, and graphics cores 580A-580N.
  • ring interconnect 502 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores.
  • the graphics processor is one of many processors integrated within a multi-core processing system.
  • graphics processor 500 receives batches of commands via ring interconnect 502. The incoming commands are interpreted by a command streamer 503 in the pipeline front-end 504.
  • graphics processor 500 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics core (s) 580A-580N.
  • command streamer 503 supplies commands to geometry pipeline 536.
  • command streamer 503 supplies the commands to a video front end 534, which couples with a media engine 537.
  • media engine 537 includes a Video Quality Engine (VQE) 530 for video and image post-processing and a multi-format encode/decode (MFX) 533 engine to provide hardware-accelerated media data encode and decode.
  • VQE Video Quality Engine
  • MFX multi-format encode/decode
  • geometry pipeline 536 and media engine 537 each generate execution threads for the thread execution resources provided by at least one graphics core 580A.
  • graphics processor 500 includes scalable thread execution resources featuring modular cores 580A-580N (sometimes referred to as core slices) , each having multiple sub-cores 550A-550N, 560A-560N (sometimes referred to as core sub-slices) .
  • graphics processor 500 can have any number of graphics cores 580A through 580N.
  • graphics processor 500 includes a graphics core 580A having at least a first sub-core 550A and a second core sub-core 560A.
  • the graphics processor is a low power processor with a single sub-core (e.g., 550A) .
  • graphics processor 500 includes multiple graphics cores 580A-580N, each including a set of first sub-cores 550A-550N and a set of second sub-cores 560A-560N.
  • Each sub-core in the set of first sub-cores 550A-550N includes at least a first set of execution units 552A-552N and media/texture samplers 554A-554N.
  • Each sub-core in the set of second sub-cores 560A-560N includes at least a second set of execution units 562A-562N and samplers 564A-564N.
  • each sub-core 550A-550N, 560A-560N shares a set of shared resources 570A-570N.
  • the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in the various embodiments of the graphics processor.
  • Figure 6 illustrates thread execution logic 600 including an array of processing elements employed in some embodiments of a GPE. Elements of Figure 6 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.
  • thread execution logic 600 includes a shader processor 602, a thread dispatcher 604, instruction cache 606, a scalable execution unit array including a plurality of execution units 608A-608N, a sampler 610, a data cache 612, and a data port 614.
  • the included components are interconnected via an interconnect fabric that links to each of the components.
  • thread execution logic 600 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 606, data port 614, sampler 610, and execution units 608A-608N.
  • each execution unit e.g.
  • the array of execution units 608A-608N is scalable to include any number individual execution units.
  • the execution units 608A-608N are primarily used to execute shader programs.
  • a shader processor 602 can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher 604.
  • the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units 608A-608N.
  • the geometry pipeline e.g., 536 of Figure 5
  • thread dispatcher 604 can also process runtime thread spawning requests from the executing shader programs.
  • the execution units 608A-608N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation.
  • the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders) , pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders) .
  • Each of the execution units 608A-608N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses.
  • SIMD single instruction multiple data
  • Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations.
  • dependency logic within the execution units 608A-608N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader.
  • Each execution unit in execution units 608A-608N operates on arrays of data elements.
  • the number of data elements is the “execution size, ” or the number of channels for the instruction.
  • An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions.
  • the number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor.
  • ALUs Arithmetic Logic Units
  • FPUs Floating Point Units
  • execution units 608A-608N support integer and floating-point data types.
  • the execution unit instruction set includes SIMD instructions.
  • the various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements) , eight separate 32-bit packed data elements (Double Word (DW) size data elements) , sixteen separate 16-bit packed data elements (Word (W) size data elements) , or thirty-two separate 8-bit data elements (byte (B) size data elements) .
  • QW Quad-Word
  • DW Double Word
  • W 16-bit packed data elements
  • B thirty-two separate 8-bit data elements
  • One or more internal instruction caches are included in the thread execution logic 600 to cache thread instructions for the execution units.
  • one or more data caches are included to cache thread data during thread execution.
  • a sampler 610 is included to provide texture sampling for 3D operations and media sampling for media operations.
  • sampler 610 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.
  • pixel processor logic within the shader processor 602 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc. ) .
  • output surfaces e.g., color buffers, depth buffers, stencil buffers, etc.
  • a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object.
  • pixel processor logic within the shader processor 602 then executes an application programming interface (API) -supplied pixel or fragment shader program.
  • API application programming interface
  • the shader processor 602 dispatches threads to an execution unit (e.g., 608A) via thread dispatcher 604.
  • pixel shader 602 uses texture sampling logic in the sampler 610 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.
  • the data port 614 provides a memory access mechanism for the thread execution logic 600 output processed data to memory for processing on a graphics processor output pipeline.
  • the data port 614 includes or couples to one or more cache memories (e.g., data cache 612) to cache data for memory access via the data port.
  • Figure 7 is a block diagram illustrating a graphics processor instruction formats 700 according to some embodiments.
  • the graphics processor execution units support an instruction set having instructions in multiple formats.
  • the solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions.
  • instruction format 700 described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.
  • the graphics processor execution units natively support instructions in a 128-bit instruction format 710.
  • a 64-bit compacted instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands.
  • the native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 730.
  • the native instructions available in the 64-bit format 730 vary by embodiment.
  • the instruction is compacted in part using a set of index values in an index field 713.
  • the execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format 710.
  • instruction opcode 712 defines the operation that the execution unit is to perform.
  • the execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands.
  • instruction control field 714 enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle) .
  • channels selection e.g., predication
  • data channel order e.g., swizzle
  • exec-size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field 716 is not available for use in the 64-bit compact instruction format 730.
  • Some execution unit instructions have up to three operands including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied.
  • Data manipulation instructions can have a third source operand (e.g., SRC2 724) , where the instruction opcode 712 determines the number of source operands.
  • An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.
  • the 128-bit instruction format 710 includes an access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.
  • the 128-bit instruction format 710 includes an access/address mode field 726, which specifies an address mode and/or an access mode for the instruction.
  • the access mode is used to define a data access alignment for the instruction.
  • Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.
  • the address mode portion of the access/address mode field 726 determines whether the instruction is to use direct or indirect addressing.
  • direct register addressing mode bits in the instruction directly provide the register address of one or more operands.
  • indirect register addressing mode the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.
  • instructions are grouped based on opcode 712 bit-fields to simplify Opcode decode 740.
  • bits 4, 5, and 6 allow the execution unit to determine the type of opcode.
  • the precise opcode grouping shown is merely an example.
  • a move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov) , compare (cmp) ) .
  • move and logic group 742 shares the five most significant bits (MSB) , where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb.
  • a flow control instruction group 744 (e.g., call, jump (jmp) ) includes instructions in the form of 0010xxxxb (e.g., 0x20) .
  • a miscellaneous instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30) .
  • a parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40) . The parallel math group 748 performs the arithmetic operations in parallel across data channels.
  • the vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50) .
  • the vector math group performs arithmetic such as dot product calculations on vector operands.
  • Fig 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.
  • graphics processor 800 includes a graphics pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870.
  • graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802.
  • ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of graphics pipeline 820 or media pipeline 830.
  • command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803.
  • vertex fetcher 805 provides vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations to each vertex.
  • vertex fetcher 805 and vertex shader 807 execute vertex-processing instructions by dispatching execution threads to execution units 852A, 852B via a thread dispatcher 831.
  • execution units 852A, 852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 852A, 852B have an attached L1 cache 851 that is specific for each array or shared between the arrays.
  • the cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.
  • graphics pipeline 820 includes tessellation components to perform hardware-accelerated tessellation of 3D objects.
  • a programmable hull shader 811 configures the tessellation operations.
  • a programmable domain shader 817 provides back-end evaluation of tessellation output.
  • a tessellator 813 operates at the direction of hull shader 811 and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to graphics pipeline 820.
  • tessellation components e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed.
  • complete geometric objects can be processed by a geometry shader 819 via one or more threads dispatched to execution units 852A, 852B, or can proceed directly to the clipper 829.
  • the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader 819 receives input from the vertex shader 807. In some embodiments, geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.
  • a clipper 829 processes vertex data.
  • the clipper 829 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions.
  • a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into their per pixel representations.
  • pixel shader logic is included in thread execution logic 850.
  • an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via a stream out unit 823.
  • the graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor.
  • execution units 852A, 852B and associated cache (s) 851, texture and media sampler 854, and texture/sampler cache 858 interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor.
  • sampler 854, caches 851, 858 and execution units 852A, 852B each have separate memory access paths.
  • render output pipeline 870 contains a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation.
  • the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization.
  • An associated render cache 878 and depth cache 879 are also available in some embodiments.
  • a pixel operations component 877 performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine 841, or substituted at display time by the display controller 843 using overlay display planes.
  • a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory.
  • graphics processor media pipeline 830 includes a media engine 837 and a video front end 834.
  • video front end 834 receives pipeline commands from the command streamer 803.
  • media pipeline 830 includes a separate command streamer.
  • video front-end 834 processes media commands before sending the command to the media engine 837.
  • media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.
  • graphics processor 800 includes a display engine 840.
  • display engine 840 is external to processor 800 and couples with the graphics processor via the ring interconnect 802, or some other interconnect bus or fabric.
  • display engine 840 includes a 2D engine 841 and a display controller 843.
  • display engine 840 contains special purpose logic capable of operating independently of the 3D pipeline.
  • display controller 843 couples with a display device (not shown) , which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.
  • graphics pipeline 820 and media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API) .
  • driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor.
  • support is provided for the Open Graphics Library (OpenGL) , Open Computing Language (OpenCL) , and/or Vulkan graphics and compute API, all from the Khronos Group.
  • support may also be provided for the Direct3D library from the Microsoft Corporation.
  • a combination of these libraries may be supported.
  • Support may also be provided for the Open Source Computer Vision Library (OpenCV) .
  • OpenCV Open Source Computer Vision Library
  • a future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.
  • Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments.
  • Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment.
  • the solid lined boxes in Figure 9A illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands.
  • the exemplary graphics processor command format 900 of Figure 9A includes data fields to identify a target client 902 of the command, a command operation code (opcode) 904, and the relevant data 906 for the command.
  • opcode command operation code
  • a sub-opcode 905 and a command size 908 are also included in some commands.
  • client 902 specifies the client unit of the graphics device that processes the command data.
  • a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit.
  • the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands.
  • an explicit command size 908 is expected to specify the size of the command.
  • the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word.
  • the flow diagram in Figure 9B shows an exemplary graphics processor command sequence 910.
  • software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations.
  • a sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence.
  • the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.
  • the graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the currently pending commands for the pipeline.
  • the 3D pipeline 922 and the media pipeline 924 do not operate concurrently.
  • the pipeline flush is performed to cause the active graphics pipeline to complete any pending commands.
  • the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated.
  • any data in the render cache that is marked ‘dirty’ can be flushed to memory.
  • pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor into a low power state.
  • a pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 913 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via the pipeline select command 913.
  • a pipeline control command 914 configures a graphics pipeline for operation and is used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control command 914 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.
  • return buffer state commands 916 are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.
  • the remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination 920, the command sequence is tailored to the 3D pipeline 922 beginning with the 3D pipeline state 930, or the media pipeline 924 beginning at the media pipeline state 940.
  • the commands for the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based the particular 3D API in use. In some embodiments, 3D pipeline state 930 commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.
  • 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex fetch function in the graphics pipeline.
  • the vertex fetch function uses the 3D primitive 932 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers.
  • 3D primitive 932 command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 922 dispatches shader execution threads to graphics processor execution units.
  • 3D pipeline 922 is triggered via an execute 934 command or event.
  • a register write triggers command execution.
  • execution is triggered via a ‘go’ or ‘kick’ command in the command sequence.
  • command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline.
  • the 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.
  • the graphics processor command sequence 910 follows the media pipeline 924 path when performing media operations.
  • the specific use and manner of programming for the media pipeline 924 depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode.
  • the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores.
  • the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.
  • GPGPU general-purpose graphics processor unit
  • media pipeline 924 is configured in a similar manner as the 3D pipeline 922.
  • a set of media pipeline state commands 940 are dispatched or placed into a command queue before the media object commands 942.
  • media pipeline state commands 940 include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format.
  • media pipeline state commands 940 also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.
  • media object commands 942 supply pointers to media objects for processing by the media pipeline.
  • the media objects include memory buffers containing video data to be processed.
  • all media pipeline states must be valid before issuing a media object command 942.
  • the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., register write) .
  • Output from media pipeline 924 may then be post processed by operations provided by the 3D pipeline 922 or the media pipeline 924.
  • GPGPU operations are configured and executed in a similar manner as media operations.
  • Figure 10 illustrates exemplary graphics software architecture for a data processing system 1000 according to some embodiments.
  • software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030.
  • processor 1030 includes a graphics processor 1032 and one or more general-purpose processor core (s) 1034.
  • the graphics application 1010 and operating system 1020 each execute in the system memory 1050 of the data processing system.
  • 3D graphics application 1010 contains one or more shader programs including shader instructions 1012.
  • the shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL) .
  • the application also includes executable instructions 1014 in a machine language suitable for execution by the general-purpose processor core 1034.
  • the application also includes graphics objects 1016 defined by vertex data.
  • operating system 1020 is a operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel.
  • the operating system 1020 can support a graphics API 1022 such as the Direct3D API, the OpenGL API, or the Vulkan API.
  • the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language.
  • the compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation.
  • high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010.
  • the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.
  • SPIR Standard Portable Intermediate Representation
  • user mode graphics driver 1026 contains a back-end shader compiler 1027 to convert the shader instructions 1012 into a hardware specific representation.
  • shader instructions 1012 in the GLSL high-level language are passed to a user mode graphics driver 1026 for compilation.
  • user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029.
  • kernel mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.
  • One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor.
  • the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein.
  • Such representations known as “IP cores, ” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit.
  • the hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit.
  • the integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.
  • FIG 11 is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit to perform operations according to an embodiment.
  • the IP core development system 1100 may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit) .
  • a design facility 1130 can generate a software simulation 1110 of an IP core design in a high level programming language (e.g., C/C++) .
  • the software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112.
  • the simulation model 1112 may include functional, behavioral, and/or timing simulations.
  • a register transfer level (RTL) design can then be created or synthesized from the simulation model 1112.
  • the RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals.
  • lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.
  • the RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL) , or some other representation of physical design data.
  • the HDL may be further simulated or tested to verify the IP core design.
  • the IP core design can be stored for delivery to a 3 rd party fabrication facility 1165 using non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium) .
  • the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1150 or wireless connection 1160.
  • the fabrication facility 1165 may then fabricate an integrated circuit that is based at least in part on the IP core design.
  • the fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.
  • Figs 12-14 illustrated exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.
  • FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment.
  • Exemplary integrated circuit 1200 includes one or more application processor (s) 1205 (e.g., CPUs) , at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities.
  • Integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, UART controller 1230, an SPI/SDIO controller 1235, and an I 2 S/I 2 C controller 1240.
  • the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255.
  • HDMI high-definition multimedia interface
  • MIPI mobile industry processor interface
  • Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller.
  • Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices.
  • Some integrated circuits additionally include an embedded security engine 1270.
  • Figure 13 is a block diagram illustrating an exemplary graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
  • Graphics processor 1310 can be a variant of the graphics processor 1210 of Figure 12.
  • Graphics processor 1310 includes a vertex processor 1305 and one or more fragment processor (s) 1315A-1315N.
  • Graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while the one or more fragment processor (s) 1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs.
  • the vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data.
  • the fragment processor (s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to produce a framebuffer that is displayed on a display device.
  • the fragment processor (s) 1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.
  • Graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache (s) 1325A-1325B, and circuit interconnect (s) 1330A-1330B.
  • MMUs memory management units
  • the one or more MMU (s) 1320A-1320B provide for virtual to physical address mapping for integrated circuit 1300, including for the vertex processor 1305 and/or fragment processor (s) 1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache (s) 1325A-1325B.
  • the one or more MMU (s) 1325A-1325B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor (s) 1205, image processor 1215, and/or video processor 1220 of Figure 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system.
  • the one or more circuit interconnect (s) 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.
  • Figure 14 is a block diagram illustrating an additional exemplary graphics processor 1410 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
  • Graphics processor 1410 can be a variant of the graphics processor 1210 of Figure 12.
  • Graphics processor 1410 includes the one or more MMU (s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the integrated circuit 1300 of Figure 13.
  • Graphics processor 1410 includes one or more shader core (s) 1415A-1415N, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including vertex shaders, fragment shaders, and compute shaders.
  • shader cores can vary among embodiments and implementations.
  • graphics processor 1410 includes an inter-core task manager 1405, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1415A-1415N and a tiling unit 1418 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.
  • inter-core task manager 1405 acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1415A-1415N and a tiling unit 1418 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.
  • FIG. 15 illustrates a computing device 1500 employing CNN training logic 1510 and CNN logic 1520 according to one embodiment.
  • CNN logic 1520 includes multiple layers of small neuron collections that process portions of an input image, called receptive fields. The outputs of these collections are tiled so that their input regions overlap, to obtain a better representation of the original image; this is repeated for every such layer. Tiling allows CNNs to tolerate translation of the input image.
  • CNN logic 1520 architecture is formed by a stack of distinct layers that transform an input volume into an output volume (e.g., holding class scores) through a differentiable function.
  • distinct types of layers e.g., convolutional, pooling, Rectified Linear Units, fully connected, loss, etc. ) are commonly used.
  • Computing device 1500 may be the same as data processing system 100 of Figure 1 and accordingly, for brevity, clarity, and ease of understanding, many of the details stated above with reference to Figures 1-14 are not further discussed or repeated hereafter.
  • computing device 1500 is shown as hosting CNN training mechanism ( “training mechanism” ) 1510.
  • training logic 1510 is shown as being hosted by graphics driver 1516; however, it is contemplated that embodiments are not limited as such.
  • training logic 1510 may be part of firmware of GPU 1514 or, in another embodiment, hosted by operating system 1506.
  • training logic 1510 may be a hardware component hosted by GPU 1514.
  • training logic 1510 may be partially and simultaneously hosted by multiple components of computing device 1500, such as one or more of driver 1516, GPU 1514, GPU firmware, operating system 1506, and/or the like.
  • training logic 1510 may be hosted by graphics driver 1516, while a number of hardware components or units may be hosted by or implemented in or part of GPU 1514.
  • the term “user” may be interchangeably referred to as “viewer” , “observer” , “person” , “individual” , “end-user” , and/or the like. It is to be noted that throughout this document, terms like “graphics domain” may be referenced interchangeably with “graphics processing unit” , “graphics processor” , or simply “GPU” and similarly, “CPU domain” or “host domain” may be referenced interchangeably with “computer processing unit” , “application processor” , or simply “CPU” .
  • Computing device 1500 may include any number and type of communication devices, such as large computing systems, such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., Internet-based cable television set-top boxes, etc. ) , global positioning system (GPS) -based devices, etc.
  • Computing device 1500 may include mobile computing devices serving as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs) , tablet computers, laptop computers, e-readers, smart televisions, television platforms, wearable devices (e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc. ) , media players, etc.
  • PDAs personal digital assistants
  • wearable devices e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc.
  • computing device 1500 may include a mobile computing device employing a computer platform hosting an integrated circuit ( “IC” ) , such as system on a chip ( “SoC” or “SOC” ) , integrating various hardware and/or software components of computing device 1500 on a single chip.
  • IC integrated circuit
  • SoC system on a chip
  • SOC system on a chip
  • computing device 1500 may include any number and type of hardware and/or software components, such as (without limitation) graphics processing unit 1514, graphics driver (also referred to as “GPU driver” , “graphics driver logic” , “driver logic” , user-mode driver (UMD) , UMD, user-mode driver framework (UMDF) , UMDF, or simply “driver” ) 1516, central processing unit 1512, memory 1508, network devices, drivers, or the like, as well as input/output (I/O) sources 1504, such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc.
  • graphics driver also referred to as “GPU driver”
  • graphics driver logic also referred to as “GPU driver”
  • driver logic user-mode driver
  • UMD user-mode driver
  • UMD user-mode driver framework
  • UMDF user-mode driver framework
  • I/O input/output
  • Computing device 1500 may include operating system (OS) 1506 serving as an interface between hardware and/or physical resources of the computer device 1500 and a user. It is contemplated that CPU 1512 may include one or processors, such as processor (s) 102 of Figure 1, while GPU 1514 may include one or more graphics processors, such as graphics processor (s) 108 of Figure 1.
  • OS operating system
  • a graphics pipeline may be implemented in a graphics coprocessor design, where CPU 1512 is designed to work with GPU 1514 which may be included in or co-located with CPU 1512.
  • GPU 1514 may employ any number and type of conventional software and hardware logic to perform the conventional functions relating to graphics rendering as well as novel software and hardware logic to execute any number and type of instructions, such as instructions 121 of Figure 1, to perform the various novel functions of training logic 1510 as disclosed throughout this document.
  • memory 1508 may include a random access memory (RAM) comprising application database having object information.
  • RAM may include double data rate RAM (DDR RAM) , extended data output RAM (EDO RAM) , etc.
  • CPU 1512 interacts with a hardware graphics pipeline, as illustrated with reference to Figure 3, to share graphics pipelining functionality. Processed data is stored in a buffer in the hardware graphics pipeline, and state information is stored in memory 1508. The resulting image is then transferred to I/O sources 1504, such as a display component, such as display device 320 of Figure 3, for displaying of the image.
  • the display device may be of various types, such as Cathode Ray Tube (CRT) , Thin Film Transistor (TFT) , Liquid Crystal Display (LCD) , Organic Light Emitting Diode (OLED) array, etc., to display information to a user.
  • CTR Cathode Ray Tube
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • Memory 1508 may comprise a pre-allocated region of a buffer (e.g., frame buffer) ; however, it should be understood by one of ordinary skill in the art that the embodiments are not so limited, and that any memory accessible to the lower graphics pipeline may be used.
  • Computing device 1500 may further include input/output (I/O) control hub (ICH) 130 as referenced in Figure 1, one or more I/O sources 1504, etc.
  • I/O input/output
  • ICH input/output
  • CPU 1512 may include one or more processors to execute instructions in order to perform whatever software routines the computing system implements.
  • the instructions frequently involve some sort of operation performed upon data.
  • Both data and instructions may be stored in system memory 1508 and any associated cache.
  • Cache is typically designed to have shorter latency times than system memory 1508; for example, cache might be integrated onto the same silicon chip (s) as the processor (s) and/or constructed with faster static RAM (SRAM) cells whilst the system memory 1508 might be constructed with slower dynamic RAM (DRAM) cells.
  • SRAM static RAM
  • DRAM dynamic RAM
  • GPU 1514 may exist as part of CPU 1512 (such as part of a physical CPU package) in which case, memory 1508 may be shared by CPU 1512 and GPU 1514 or kept separated.
  • System memory 1508 may be made available to other components within the computing device 1500.
  • any data e.g., input graphics data
  • the computing device 1500 e.g., keyboard and mouse, printer port, Local Area Network (LAN) port, modem port, etc.
  • an internal storage element of the computer device 1500 e.g., hard disk drive
  • data that a software program determines should be sent from the computing device 1500 to an outside entity through one of the computing system interfaces, or stored into an internal storage element is often temporarily queued in system memory 1508 prior to its being transmitted or stored.
  • an ICH such as ICH 130 of Figure 1
  • an MCH such as MCH 116 of Figure 1
  • MCH 116 of Figure 1 may be used for managing the various contending requests for system memory 1508 accesses amongst CPU 1512 and GPU 1514, interfaces and internal storage elements that may proximately arise in time with respect to one another.
  • I/O sources 1504 may include one or more I/O devices that are implemented for transferring data to and/or from computing device 1500 (e.g., a networking adapter) ; or, for a large scale non-volatile storage within computing device 1500 (e.g., hard disk drive) .
  • User input device including alphanumeric and other keys, may be used to communicate information and command selections to GPU 1514.
  • cursor control such as a mouse, a trackball, a touchscreen, a touchpad, or cursor direction keys to communicate direction information and command selections to GPU 1514 and to control cursor movement on the display device.
  • Camera and microphone arrays of computer device 1500 may be employed to observe gestures, record audio and video and to receive and transmit visual and audio commands.
  • Computing device 1500 may further include network interface (s) to provide access to a network, such as a LAN, a wide area network (WAN) , a metropolitan area network (MAN) , a personal area network (PAN) , Bluetooth, a cloud network, a mobile network (e.g., 3 rd Generation (3G) , 4 th Generation (4G) , etc. ) , an intranet, the Internet, etc.
  • Network interface (s) may include, for example, a wireless network interface having antenna, which may represent one or more antenna (e) .
  • Network interface (s) may also include, for example, a wired network interface to communicate with remote devices via network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.
  • Network interface (s) may provide access to a LAN, for example, by conforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols, including previous and subsequent versions of the standards, may also be supported.
  • network interface (s) may provide wireless communication using, for example, Time Division, Multiple Access (TDMA) protocols, Global Systems for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocols.
  • TDMA Time Division, Multiple Access
  • GSM Global Systems for Mobile Communications
  • CDMA Code Division, Multiple Access
  • Network interface may include one or more communication interfaces, such as a modem, a network interface card, or other well-known interface devices, such as those used for coupling to the Ethernet, token ring, or other types of physical wired or wireless attachments for purposes of providing a communication link to support a LAN or a WAN, for example.
  • the computer system may also be coupled to a number of peripheral devices, clients, control surfaces, consoles, or servers via a conventional network infrastructure, including an Intranet or the Internet, for example.
  • computing device 1500 may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances.
  • Examples of the electronic device or computer system 1500 may include (without limitation) a mobile device, a personal digital assistant, a mobile computing device, a smartphone, a cellular telephone, a handset, a one-way pager, a two-way pager, a messaging device, a computer, a personal computer (PC) , a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, consumer electronics, programmable consumer electronics, television, digital television, set top
  • Embodiments may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a parentboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC) , and/or a field programmable gate array (FPGA) .
  • the term "logic” may include, by way of example, software or hardware and/or combinations of software and hardware.
  • Embodiments may be provided, for example, as a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein.
  • a machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories) , and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only Memories) , EEPROMs (Electrically Erasable Programmable Read Only Memories) , magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions.
  • embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of one or more data signals embodied in and/or modulated by a carrier wave or other propagation medium via a communication link (e.g., a modem and/or network connection) .
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem and/or network connection
  • training logic 1510 implements a self-adaptive bi-direction mask (SABM) window structure to provide visualization of multiple irregular zones that are related to a sub-category feature.
  • SABM self-adaptive bi-direction mask
  • training logic 1510 may operate on either aligned or un-aligned input ranging from a very large to very small area size (e.g., a face) .
  • Training logic 1510 may also operate for inner class and intra-class class visualization, as well as a deep learning training system.
  • the SABM window mechanism implements SABM window and normalized sensitivity map structures to perform processing on an input image.
  • Figure 16A illustrates one embodiment of an input image 1600.
  • input image 1600 is W I *H I *Channel in size, with W I being the width and H I being the height of input image 1600. Note that the channel has been omitted for simplification of the description.
  • SABM windows are generated based on image 1600.
  • SABM windows include two 3-band matrices, with sizes being size are W I * (2H I + H V ) (shown in Figure 16B) , and (2W I +W V ) *H I (shown in Figure 16C) .
  • FIG. 17A illustrates one embodiment of a normalized sensitivity map 1700 having a W I *H I matrix.
  • normalized sensitivity map 1700 records a normalized sensitivity result for each pixel of input image 1600.
  • training logic 1510 uses normalized sensitivity map 1700 and the SABM windows to perform a selective scan.
  • a selective scan involves sliding an SABM window along one direction of input image 1600.
  • a vertical scan begins with sliding the SABM window from the upper side of input image, while performing an “AND” operation between the mask (e.g., band filled with 1s) and input image 1600 (See Figure 18A) .
  • the “AND” operation may be replaced by a more complex process, such as performing an “AND “in the middle of the mask area and performing alpha blending on the two edges of the band.
  • a horizontal band of input image 1600 is preserved ( Figure 18B) , resulting in the remaining sections having 0s.
  • the resulting image is input into a CNN logic 1520 forwarding feeding pass (e.g., currently existing in deep learning training systems) to perform a test, and get the possibility of the classification group (the group which we want to evaluate the sensitivity area in input image) (P 0 ) .
  • the SABM window will slide down to cover another portion of input image 1600 ( Figure 18C) . Accordingly, the process is repeated (e.g., sensitivity scan and image feed into CNN logic 1520 forwarding feeding pass) to achieve classification possibility P 1 , P 2 ...P n .
  • Possibility “P” may be treated as the contribution factor of a pixel of remaining section in input image to the target classification group, and temporally stored in the normalized sensitivity map. Due to the sliding of the SABM window a pixel will receive several “P” values during the procedure. Further all of the “P” values are accumulated.
  • training mechanism 1310 normalizes the globally accumulated P values of normalized sensitivity map to a value between 0 and 1.
  • Figure 17B illustrates one embodiment of a normalized sensitivity map 1500 after addition of the classification group P values. Subsequently, the SABM window is enlarged to cover more of input image 1600, and the process is again repeated (See Figures 18D–18F) .
  • the vertical scan is completed once the SABM window has been enlarged to a size that exceeds a predetermined threshold, for example, covering the 80%of input image.
  • the horizontal scan is performed once the vertical scan has been completed. In such an embodiment, the horizontal scan is performed by repeating the process described above with reference to the vertical scan.
  • Figures 19A–19C illustrate an embodiments of the SABM window process implemented for a horizontal pass.
  • the overall sensitivity heat map is ready for visualization once the vertical and horizontal scans are completed.
  • Figures 20A & 20B illustrate a method 2000 for facilitating training according to one embodiment.
  • Method 2000 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc. ) , software (such as instructions run on a processing device) , or a combination thereof.
  • the processes of method 2000 are illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. For brevity, many of the details discussed with reference to the preceding figures may not be discussed or repeated hereafter.
  • Method 2000 begins at decision block 2001 ( Figure 20A) where a determination is made as to whether the SABM window H V is less than the threshold. If not, a determination is made as to whether a current mask window has reached the end of input image 1600, decision block 2002. The mask is moved down a number of pixels upon a determination that the current mask window has not reached the end of input image 1600, processing block 2003. At processing block 2004, a new image is generated and a classification probability is calculated and accumulated into cells corresponding to current pixels of input image. Control is returned to decision block 2002, where it is again determined whether the current mask window has reached the end of input image 1600. If so, the probability is normalized globally, processing block 2005. At processing block 2006, the sensitivity heat map is updated. At processing block 2007, H V is enlarged. Subsequently control is returned to decision block 2001, where a determination is again made as to whether the SABM window H V is less than the threshold.
  • control is forwarded to decision block 2011 ( Figure 20B) .
  • decision block 2011 a determination is made as to whether the SABM window W V is less than the threshold. If not, a determination is made as to whether a current mask window has reached the end of input image 1600, decision block 2012. The mask is moved down a number of pixels upon a determination that the current mask window has not reached the end of input image 1600, processing block 2013.
  • a new image is generated and a classification probability is calculated.
  • Control is returned to decision block 2012, where it is again determined whether the current mask window has reached the end of input image 1600. If so, the probability is normalized, processing block 2015.
  • the sensitivity heat map is updated.
  • H V is enlarged. Subsequently control is returned to decision block 2011, where a determination is again made as to whether the SABMM window H V is less than the threshold. The process is completed upon a determination that W V is less than the threshold.
  • references to “one embodiment” , “an embodiment” , “example embodiment” , “various embodiments” , etc., indicate that the embodiment (s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • Example 1 includes an apparatus comprising Convolutional Neural Network (CNN) logic and training logic to train the CNN using a self-adaptive bi-direction mask (SABM) window structure and a normalized sensitivity map to process an input image, wherein the SABM window structure is based on the input image.
  • CNN Convolutional Neural Network
  • SABM self-adaptive bi-direction mask
  • Example 2 includes the subject matter of Example 1, wherein the training logic performs a sensitivity scan using the SABM window structure and the normalized sensitivity map.
  • Example 3 includes the subject matter of Examples 1 and 2, wherein the training logic performs the sensitivity scan by sliding an SABM window along a direction of the input image.
  • Example 4 includes the subject matter of Examples 1-3, wherein the sensitivity scan is performed along a vertical direction along the input image, and a horizontal direction along the input image.
  • Example 5 includes the subject matter of Examples 1-4, wherein an image resulting from the sensitivity scans is input into the CNN logic to perform a test.
  • Example 6 includes the subject matter of Examples 1-5, wherein a second sensitivity scan is performed by sliding the SABM window to a second position along the direction of the input image and a second image resulting from the second sensitivity scans is input into the CNN logic to perform a second test.
  • Example 7 includes the subject matter of Examples 1-6, wherein the result of the test generates a first classification group and the result of the second test generates a second classification group.
  • Example 8 includes the subject matter of Examples 1-7, wherein the first classification group and the second classification group are normalized.
  • Example 9 includes the subject matter of Examples 1-8, wherein the first normalized classification group and the second normalized classification group are recorded in the sensitivity map.
  • Example 10 includes the subject matter of Examples 1-9, wherein the SABM window structure comprises horizontal matrices and vertical matrices.
  • Example 11 includes the subject matter of Examples 1-10, wherein a middle band of the horizontal matrices and a middle band of the vertical matrices are implemented as a mask for the input image.
  • Example 12 includes the subject matter of Examples 1-11, wherein the SABM window structure provides visualization of multiple irregular zones that are related to a sub-category feature.
  • Example 13 includes a training method comprising performing a sensitivity scan on an input image using a self-adaptive bi-direction mask (SABM) window structure and a normalized sensitivity map, wherein the SABM window structure is based on the input image; and training Convolutional Neural Network (CNN) logic based on the results of the sensitivity scan.
  • SABM self-adaptive bi-direction mask
  • CNN Convolutional Neural Network
  • Example 14 includes the subject matter of Example 13, wherein performing the sensitivity scan comprises applying the SABM window to the input image in a first direction to generate a first image, inputting the first image into the CNN logic and generating a classification probability as a result of inputting the first image into the CNN logic.
  • Example 15 includes the subject matter of Examples 13 and 14, determining whether the SABM window has reached the end of the input image.
  • Example 16 includes the subject matter of Examples 13-15, further comprising sliding the SABM window to a second position along the first direction of the input image upon determining that the SABM window has not reached the end of the input image, applying the SABM window to the input image at the second position to generate a second image, inputting the second image into the CNN logic and generating a second classification probability as a result of inputting the second image into the CNN logic.
  • Example 17 includes the subject matter of Examples 13-16, further comprising normalizing the first classification probability and the second classification probability upon determining that the SABM window has reached the end of the input image and updating the normalized sensitivity map.
  • Example 18 includes the subject matter of Examples 13-17, further comprising determining whether the SABM window is less than a predetermined threshold.
  • Example 19 includes the subject matter of Examples 13-18, further comprising applying the SABM window to the input image in a second direction to generate a third image upon a determination that the SABM window is less than the predetermined threshold, inputting the third image into the CNN logic and generating a classification probability as a result of inputting the third image into the CNN logic.
  • Example 20 that includes at least one machine-readable storage medium comprising a plurality of instructions, executed on a computing device, to facilitate the computing device to perform the methods of claims 13-19.
  • Example 21 includes a training apparatus comprising means for performing a sensitivity scan on an input image using a self-adaptive bi-direction mask (SABM) window structure and a normalized sensitivity map, wherein the SABM window structure is based on the input image and means for training Convolutional Neural Network (CNN) logic based on the results of the sensitivity scan.
  • SABM self-adaptive bi-direction mask
  • CNN Convolutional Neural Network
  • Example 22 includes the subject matter of Example 21, wherein performing the sensitivity scan comprises means for applying the SABM window to the input image in a first direction to generate a first image, means for inputting the first image into the CNN logic; and means for generating a classification probability as a result of inputting the first image into the CNN logic.
  • Example 23 includes the subject matter of Examples 21 and 22, further comprising means for determining whether the SABM window has reached the end of the input image.
  • Example 24 includes the subject matter of Examples 21-23, further comprising means for sliding the SABM window to a second position along the first direction of the input image upon determining that the SABM window has not reached the end of the input image, means for applying the SABM window to the input image at the second position to generate a second image, means for inputting the second image into the CNN logic and means for generating a second classification probability as a result of inputting the second image into the CNN logic.
  • Example 25 includes the subject matter of Examples 21-24, means for normalizing the first classification probability and the second classification probability upon determining that the SABM window has reached the end of the input image and updating the normalized sensitivity map.
  • Example 26 includes at least one machine-readable storage medium comprising a plurality of instructions, executed on a computing device, to facilitate the computing device to perform operations comprising performing a sensitivity scan on an input image using a self-adaptive bi-direction mask (SABM) window structure and a normalized sensitivity map, wherein the SABM window structure is based on the input image and training Convolutional Neural Network (CNN) logic based on the results of the sensitivity scan.
  • SABM self-adaptive bi-direction mask
  • CNN Convolutional Neural Network
  • Example 27 includes the subject matter of Example 26, wherein performing the sensitivity scan comprises applying the SABM window to the input image in a first direction to generate a first image, inputting the first image into the CNN logic and generating a classification probability as a result of inputting the first image into the CNN logic.
  • Example 28 includes the subject matter of Examples 26 and 27, further comprising determining whether the SABM window has reached the end of the input image.
  • Example 29 includes the subject matter of Examples 26-28, sliding the SABM window to a second position along the first direction of the input image upon determining that the SABM window has not reached the end of the input image, applying the SABM window to the input image at the second position to generate a second image, inputting the second image into the CNN logic and generating a second classification probability as a result of inputting the second image into the CNN logic.
  • Example 30 includes the subject matter of Examples 26-29, further comprising normalizing the first classification probability and the second classification probability upon determining that the SABM window has reached the end of the input image and updating the normalized sensitivity map.
  • Example 31 includes the subject matter of Examples 26-30, further comprising determining whether the SABM window is less than a predetermined threshold.

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Abstract

L'invention concerne un mécanisme permettant de faciliter l'apprentissage de logique de réseau neuronal convolutif (CNN). Un procédé de modes de réalisation, décrit par l'invention, consiste à effectuer un balayage de sensibilité sur une image d'entrée grâce à une structure de fenêtre à masque bidirectionnel auto-adaptatif (SABM) et à une carte de sensibilité normalisée, où la structure de fenêtre SABM est basée sur l'image d'entrée et l'apprentissage de la logique de réseau neuronal convolutif (CNN) est basé sur les résultats du balayage de sensibilité.
PCT/CN2016/083192 2016-05-24 2016-05-24 Mécanisme de fenêtre auto-adaptatif WO2017201676A1 (fr)

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