WO2017193287A1 - 多核处理器的调试方法、装置和系统 - Google Patents

多核处理器的调试方法、装置和系统 Download PDF

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Publication number
WO2017193287A1
WO2017193287A1 PCT/CN2016/081585 CN2016081585W WO2017193287A1 WO 2017193287 A1 WO2017193287 A1 WO 2017193287A1 CN 2016081585 W CN2016081585 W CN 2016081585W WO 2017193287 A1 WO2017193287 A1 WO 2017193287A1
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Prior art keywords
debugging
debug
agent
command
debugger
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PCT/CN2016/081585
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English (en)
French (fr)
Inventor
刘帅
吕璐
王名发
赵金亮
刘宇
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华为技术有限公司
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Priority to PCT/CN2016/081585 priority Critical patent/WO2017193287A1/zh
Publication of WO2017193287A1 publication Critical patent/WO2017193287A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Definitions

  • the present invention relates to a multi-core processor, and more particularly to a method, apparatus and system for debugging a multi-core processor.
  • the development process of multi-core processors usually includes three stages: system analysis and processor design, pre-silicon verification and sample verification.
  • the pre-silicon verification of the multi-core processor specifically includes: simulating the complete function of the multi-core processor on the verification platform, and then performing a series of verification activities on the verification platform to ensure the correctness of the functions of the multi-core processor.
  • the pre-silicon verification system of the multi-core processor is shown in FIG. 1.
  • the system shown in FIG. 1 includes a verification platform, a debugging agent and a debugger, and the verification platform simulates the complete function of the multi-core processor.
  • the debugger is configured to receive a debug command input by the user and send the debug command to the debug agent; the debug agent is used to create a debug channel between the debugger and the simulated multi-core processor, and debug the corresponding kernel by using the debug command to verify Some functions corresponding to the kernel.
  • a single user monopolizes the entire set of verification platform resources. In this way, in the process of one user using the verification platform, other users can only wait, which will lead to poor experience of this part of the user.
  • the time interval between one debugger receiving two adjacent debug commands is generally long, for example, one verification process takes one hour, and the debugger receives two adjacent ones.
  • the time interval between debug commands may be 5 minutes. This will result in a shorter effective debugging time, resulting in lower utilization of the verification platform resources.
  • Embodiments of the present invention provide a method, an apparatus, and a system for debugging a multi-core processor, which are used to improve the utilization of the verification platform resources and improve the user experience.
  • an embodiment of the present invention provides a debugging method for a multi-core processor, which is applied to a debugging system including a verification platform, a debugging agent, and at least two debuggers, where the verification platform simulates a multi-core processor to be debugged. Resources, at least two debuggers connect and communicate with the debug agent.
  • the method includes: the debugging agent determines a debugging command to be scheduled from a plurality of debugging commands according to a priority order of the debugging command; wherein the multiple debugging commands are from at least two debuggers, and each debugging command is used for the verification platform
  • the specific resources on the simulation are debugged; then, the debug agent schedules the debug commands to be scheduled, and schedules the specific resources to be debugged by the debug commands to be scheduled.
  • an embodiment of the present invention provides a debugging agent, which is applied to a debugging system including a verification platform and at least two debuggers.
  • the verification platform simulates resources to be debugged on the multi-core processor, and at least two debuggers.
  • the debugging agent includes: a determining unit and a scheduling unit. a determining unit, configured to determine, according to a priority order of the debug command, a debug command to be scheduled from a plurality of debug commands; wherein the multiple debug commands are from at least two debuggers, and each debug command is used on the verification platform Simulate specific resources for debugging.
  • the scheduling unit is configured to schedule a debugging command to be scheduled, and schedule the specific resource to be debugged by the debugging command to be scheduled.
  • the debugging agent determines the debugging command to be scheduled according to the priority order of the debugging command, that is, in the embodiment of the present invention, the debugging command is used as the granularity for scheduling, and therefore, can be made to a certain extent
  • the debugging agent schedules debugging commands sent by other debuggers during the scheduling of all debugging commands sent by a debugger; that is, debugging that can be sent to other users during scheduling of all debugging commands sent by one user. The command is scheduled. Compared with the prior art "the debugging command can be scheduled by the next user after all the debugging commands sent by one user are scheduled," the user experience can be improved.
  • the scheduling command is granular, so that the effective debugging time can be prolonged compared with the technical solution with the debugger as the granularity in the prior art, thereby improving the verification platform. Resource utilization.
  • the priority order of the debug command is determined according to at least the length of the single execution time of the debug command.
  • the debugging agent determines, according to the priority order of the debugging command, the debugging command to be scheduled from the plurality of debugging commands, which may include: the debugging agent treats the debugging command with the highest priority in a set as A scheduled debug command, wherein the set consists of unscheduled debug commands from each of the plurality of debug commands that arrive at the debug agent first.
  • the determining unit is specifically configured to: use a debugging command with the highest priority in a set as a debugging command to be scheduled, where the set is from each of the multiple debugging commands
  • the debugger consists of unscheduled debug commands that first arrive at the debug agent.
  • the optional implementation provides a method for determining a debug command to be scheduled.
  • the specific implementation is not limited thereto.
  • the method may further include the following steps: the debugging agent increases the priority of the debugging command whose scheduling times are less than or equal to the first threshold; and the debugging agent reduces the scheduled number of times to be greater than or equal to the second threshold.
  • the priority of the scheduling command may further include: an adjusting unit, configured to perform at least one of the following steps: increasing a priority of the debugging command whose scheduled number is less than or equal to the first threshold; and reducing the number of times scheduled The priority of the scheduling command that is greater than or equal to the second threshold.
  • the optional implementation provides a method for adaptively adjusting the priority of the debug command to avoid the problem that the lower priority debug command cannot be scheduled for a long period of time due to a long single execution time. This allows for better scheduling of debug commands from individual debuggers.
  • the debugging agent schedules a debugging command to be scheduled,
  • the method includes: if the single execution time of the debug command to be scheduled is greater than or equal to the preset time, the debug agent schedules the debug command to be scheduled according to the time slice polling algorithm.
  • the scheduling unit may be specifically configured to: if the single execution time of the to-be-scheduled debugging command is greater than or equal to the preset time, the debugging agent schedules the waiting according to the time slice polling algorithm Schedule debugging commands.
  • the optional implementation implements a time slice polling algorithm, which can split a scheduling command into multiple parts according to fine granularity, and then the debugging agent can schedule the scheduling command according to the time slice granularity, and in the process, Schedule other debug commands; thereby reducing the wait time for scheduled commands sent by other debuggers to improve the user experience.
  • a time slice polling algorithm which can split a scheduling command into multiple parts according to fine granularity, and then the debugging agent can schedule the scheduling command according to the time slice granularity, and in the process, Schedule other debug commands; thereby reducing the wait time for scheduled commands sent by other debuggers to improve the user experience.
  • the method of the first aspect may further include: the debugging agent receives the request message sent by the debugger, where the request message includes a resource to be applied to request the resource to be applied; if the resource to be applied is not occupied, the debugging is performed.
  • the agent allocates the resource to be applied to the debugger, and records that the resource to be applied has been occupied by the debugger; or, if the resource to be applied is already occupied, the debugging agent returns a resource conflict alarm to the debugger.
  • the debugging agent in the second aspect may further include: a receiving unit, configured to receive a request message sent by the debugger, where the request message includes a resource to be applied for requesting a resource to be applied.
  • the allocation record unit is configured to allocate a resource to be applied to the debugger if the resource to be applied is not occupied, and record that the resource to be applied has been occupied by the debugger.
  • the sending unit is configured to: when the resource to be applied is occupied, the debugging agent returns a resource conflict alarm to the debugger.
  • the optional implementation provides a technical solution for managing resources that multiple debuggers need to schedule, and can implement isolation of resource access during the debugging process.
  • the debug agent utilizes one thread to schedule one or more kernels to be debugged by the debugger.
  • the scheduling unit is specifically configured to: use one thread to schedule one or more kernels to be scheduled by a debugger.
  • This optional implementation supports multi-core centralized debugging techniques, in which the same Multiple debuggers to be debugged Multiple threads can be debugged by one thread. Debug information between different cores in a kernel group can be shared with each other, making synchronization between multiple cores in a kernel group easier. Multicore Collaborative debugging is more convenient.
  • an embodiment of the present invention provides a debugging agent, where the debugging agent is applied to a debugging system including a verification platform and at least two debuggers, and the verification platform simulates resources to be debugged on the multi-core processor, at least two The debugger connects to and communicates with the debug agent.
  • the debugging agent includes: at least one processor, an interface circuit, a memory, and a system bus; the memory is configured to store computer execution instructions, and at least one processor, the interface circuit, and the memory are connected to each other through a system bus, and when the debugging agent is running, at least one processing
  • the computer executes the memory-storing computer execution instructions to cause the debug agent to perform the multi-core processor debug method of any of the first aspect and the various aspects of the first aspect.
  • an embodiment of the present invention provides a computer readable storage medium, where one or more programs are stored, and one or more programs include instructions, when at least one processor of the debugging agent executes the instructions.
  • the debug agent performs the method of debugging the multi-core processor of any of the above-described first aspect and the various alternatives of the first aspect.
  • an embodiment of the present invention provides a debugging system for a multi-core processor, including a verification platform, at least two debuggers, and any one of the debugging agents described above.
  • the resources to be debugged on the multi-core processor are simulated on the verification platform, and the at least two debuggers are connected and communicate with the debugging agent.
  • FIG. 1 is a schematic diagram of a debugging system of a multi-core processor provided by the prior art
  • FIG. 2 is a schematic diagram of a debugging system of a multi-core processor according to an embodiment of the present invention
  • FIG. 3 is an interaction diagram of a multi-core processor debugging method according to an embodiment of the present invention. schematic diagram;
  • FIG. 4 is a schematic diagram of a scheduling process of a debugging agent according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of another debugging system of a multi-core processor according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of another debugging system of a multi-core processor according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a debugging agent according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another debugging agent according to an embodiment of the present invention.
  • the technical solution provided by the embodiments of the present invention is applied to a pre-silicon verification stage of a multi-core processor, wherein the pre-silicon verification includes, but is not limited to, field-programmable gate array (English: field-programmable gate array, abbreviated: FPGA) verification, or electronic Design automation (English: electronic design automation, abbreviation: EDA) verification.
  • FPGA field-programmable gate array
  • EDA electronic design automation
  • the debug system shown in Figure 2 includes a verification platform, a debug agent, and at least two debuggers.
  • the verification platform simulates resources to be debugged on one or more multi-core processors, and the resources to be debugged include but are not limited to kernel resources, memory resources, and protocols for interconnection between networks (English: internet protocol, abbreviation: IP) resources and the like, wherein only the kernel resources are included on the verification platform in FIG. 2.
  • IP internet protocol, abbreviation: IP
  • At least two debuggers connect to and communicate with the debug agent.
  • the debugging process may include: the debugger receives the debug command input by the user, and sends the debug command to the debug agent; the debug agent dispatches the debug command to debug the corresponding resource on the verification platform.
  • Both the debugger and the debug agent are logical function modules, both of which can be software or Hardware implementation. Any one or more debuggers can be integrated on one host.
  • the debug agent can be integrated with any one or more debuggers on a single host or independently on a single host. It should be noted that the host where the verification platform is located is generally referred to as the target machine, and the host where the debug agent or debugger is located is referred to as the host machine.
  • the debugging agent may provide one or more service modes, including but not limited to: socket, tuxedo, cics, webservice, and the like.
  • socket two programs on the network exchange data through a two-way communication connection.
  • One end of the connection is called a socket
  • tuxedo is a client/server middleware product
  • cics is a middleware product of IBM
  • Webservice, or webservice is a programmable web-based application.
  • the debug agent can connect and communicate with the debugger using any of the service methods it provides.
  • Each debugger can support one or more service modes.
  • the service modes supported by different debuggers can be the same or different.
  • a debugger can be provided by the debug agent and is supported by the debugger itself.
  • Any debugger can establish a connection and communicate with the debug agent when it needs to verify the function of the multi-core processor; and disconnect between the debug agent and the debug agent when there is no need to verify the function of the multi-core processor Connection.
  • the implementation manner of establishing a connection between the debugger and the debugging agent is not limited in the embodiment of the present invention.
  • Each debugger is mapped to a subset of the resources on the verification platform.
  • the resources mapped on each debugger are configurable. Taking kernel resources as an example, the types and number of cores mapped on the debugger are configurable. For example, if the user needs to debug the kernels 3 and 4 by using the debugger A, the debugger A can be configured to be mapped with the kernels 3 and 4 on the verification platform; if the user needs to debug the kernel 5 by using the debugger B, Configure debugger B to map to kernel 5 on the authentication platform.
  • the technical solution provided by the embodiment of the present invention is applied to a scenario in which a debugging agent receives multiple debugging commands sent by multiple debuggers, and specifically provides a selection in the scenario.
  • the technical solution of the debugging command to be scheduled so that multiple debuggers can perform serial operation without user perception, so that for the user, it is equivalent to multiple debuggers to work in parallel, thereby improving the user experience.
  • the technical solution provided by the embodiment of the present invention is debugged with the scheduling command as the granularity, the effective debugging time can be prolonged compared with the prior art technical solution that debugs the granularity of the debugger. Improve the utilization of verification platform resources.
  • the debugging agent may sequentially schedule the debugging commands according to the receiving time of each debugging command.
  • any of a number of alternative implementations provided herein may be combined without conflict.
  • plural refers to two or more.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • FIG. 3 is a schematic diagram of interaction of a multi-core processor debugging method according to an embodiment of the present invention.
  • the debugging system to which the method is applied can be as shown in FIG. 2.
  • the method shown in FIG. 3 includes the following steps S101-S104:
  • At least two debuggers send multiple debug commands to the debug agent; wherein each debug command is used to debug a specific resource simulated on the verification platform.
  • each of the at least two debuggers may send one or more debug commands to the debug agent, for example, the debugger 1 sends 5 debug commands to the debug agent, and the debugger 2 sends 1 debug debugger to the debug agent. command.
  • a "debug command” may include, but is not limited to, a load command (ie, a write command), a read command, a sync command, a single step command, and the like.
  • S101 may include: each of the at least two debuggers transmitting all the debugging instructions required in the respective verification activities to the debugging agent, for example, when the debugger 1 sends the debugging kernels 1 and 2 to the debugging agent.
  • the debugger 2 sends all the debugging instructions required to debug the kernels 3 and 4 to the desktop agent.
  • the technical solution provided by the embodiment of the present invention also supports the following scenario: in the process of scheduling the debugging commands sent by one or more debuggers, the debugging agent receives debugging commands sent by other debuggers.
  • Each debugger is used to debug which resources on the verification platform can be configured according to the user's needs. For example, if a user needs to debug some resources of a multi-core processor (such as kernels 1, 2), the user can pass The resource to be debugged is input to a debugger, and then the debugger applies to the verification platform for the resources. For the specific implementation, refer to the following.
  • Each debug command is used to debug which specific resources can be pre-set.
  • Each debugger can correspond to one user, that is, each user can operate a debugger.
  • Different users can debug one or more multi-core processors through different debuggers.
  • user A uses debugger A to debug kernels 1 to 3 of multi-core processor 1
  • user B uses debugger B to process multi-core.
  • the cores 4 to 5 of the device 1 are debugged;
  • the user C uses the debugger C to debug the cores 1 to 4 of the multi-core processor 2, and the like.
  • connection between the at least two debuggers and the debugging agent has been established before the S101.
  • the specific implementation manner of establishing the connection is not limited in the embodiment of the present invention.
  • the debugger can first load the image (English: image) file into the debug agent, that is, the debugger.
  • the debug agent can send the debugger after the image file is loaded by the debugger connected to it Debug commands (such as read commands, sync commands, single-step commands, load commands, etc.) are scheduled. If a connection is established between the debugger and the debug agent Then, if the debugger has loaded the image file to the debug agent, the debug agent can directly dispatch debug commands (such as read commands, sync commands, single-step commands, load commands, etc.) sent by the debugger.
  • Debug commands such as read commands, sync commands, single-step commands, load commands, etc.
  • the debugging agent receives the plurality of debugging commands sent by the at least two debuggers.
  • S103-S104 is executed cyclically until a plurality of debug commands received by the debug agent are sequentially scheduled in S102. And, each time the process of S103-S104 is performed, a debug command to be scheduled is determined.
  • the debugging agent determines the debugging command to be scheduled from the plurality of debugging commands according to the priority order of the debugging commands.
  • each time S103 is executed specifically, the command to be scheduled is determined from among the debug commands that are not scheduled among the plurality of debug commands in S102.
  • the priority order of the debug commands is determined based at least on the length of the single execution time of the debug command.
  • the single execution time of the debug command refers to the time that the debug agent needs to use during the execution of the debug command. For example, the shorter the single execution time of the debug command, the higher the priority of the debug command.
  • the priority of the debug command can also be related to other factors, as described below.
  • the debugging agent schedules the debugging command to be scheduled, and schedules the specific resource to be debugged by the debugging command to be scheduled.
  • the debug command to be scheduled is a read command
  • the read command is used for reading the kernel 1. That is, the resource to be debugged by the read command is the kernel 1, and the debug agent schedules the read command to read the kernel 1.
  • the scheduling command to be scheduled is a load command
  • the load command is used to write to the kernel 3, that is, the resource to be debugged by the load command is the kernel 2, and the debug agent schedules the load command, thereby Perform a write operation.
  • the debugging agent first receives a plurality of debugging commands, and then sequentially schedules the received multiple debugging commands.
  • the embodiment of the present invention further supports the receiving by the debugging agent in the scheduling step S102. Multiple debug commands to In the process, a scenario of a debug command sent by one or more debuggers is received; and, in this scenario, when S103-S104 is continued, all unscheduled debug commands are referred to as "multiple debug commands" in S103. See below for specific examples.
  • the debugging agent determines the debugging command to be scheduled according to the priority order of the debugging command. That is to say, in the embodiment of the present invention, the debug command is scheduled to be granular. Therefore, the technical solution can, to a certain extent, enable the debug agent to schedule all debugging commands sent by one debugger to other The debug command sent by the debugger is scheduled; that is, the debug command sent by other users can be scheduled during the process of scheduling all debug commands sent by one user. Compared with the prior art "the debugging command can be scheduled by the next user after all the debugging commands sent by one user are scheduled," the user experience can be improved.
  • the scheduling command is granular, so that the effective debugging time can be prolonged compared with the technical solution with the debugger as the granularity in the prior art, thereby improving the verification platform. Resource utilization.
  • S103 may include: S103a, the debugging agent uses a debugging command with the highest priority in a set as a debugging command to be scheduled, wherein the set is first from each debugger among the multiple debugging commands. An unscheduled debug command that arrives at the debug agent.
  • the debugging agent can group the debugging commands from the same debugger into one group; then, the debugging commands in each group are sorted according to the order of reaching the debugging agent.
  • the debug agent can also cache the multiple debug commands separately when receiving multiple debug commands, that is, according to the order of whether they are from the same debugger and/or arrive at the debug proxy. For example, assume that multiple debug commands obtained according to this method are shown in Table 1:
  • Debugger Debug command Debugger A A1, A2, A3 Debugger B B1, B2, B3, B4, B5 Debugger C C1, C2
  • each debugger's multiple debug commands are sorted in order of arrival to the debug agent in a first-to-last order.
  • the set is composed of A1, B1, and C1. If the priority of each debug command in the set is from high to low: B1, A1, C1, then The debug command to be scheduled determined by the second time is B1. Thus, when S103a is executed for the second time, the set is composed of A1, B2, and C1. If the priority of each debug command in the set is from high to low: A1, C1, and B2, the current determination is made.
  • the debug command to be scheduled is A1.
  • the set is composed of A2, B2, and C1, and so on, and the debug command to be scheduled each time the debug agent executes S103a can be sequentially obtained.
  • the unscheduled debug commands in Table 1 are debug commands from the same debugger, for example, after 7 S103a is executed, it is not scheduled.
  • the debugging commands are: B3, B4, and B5. Then, the debugging agent may not judge the priority of the scheduling command, but directly use B3, B4, and B5 as the debugging commands to be scheduled.
  • the method may further include at least one of the following steps: the debugging agent increases the priority of the debugging command whose number of times of scheduling is less than or equal to the first threshold; and the debugging agent reduces the priority of the scheduling command that is scheduled to be greater than or equal to the second threshold level.
  • the optional implementation provides a method for adaptively adjusting the priority of the debugging command.
  • the debugging agent can adjust the priority of the debugging command according to any one of the adaptive adjustment algorithms provided in the prior art.
  • This optional implementation can avoid the problem that the lower priority debugging commands cannot be scheduled for a long time due to the long execution time, so that the debugging from each debugger is better.
  • the commands are scheduled to be balanced.
  • the debugging agent may monitor and count the number of times each debugging command is scheduled, and then increase the priority of the debugging command whose scheduled number is less than or equal to the first threshold, and/or decrease the scheduled number of times greater than or equal to the second.
  • the first threshold is less than or equal to the second threshold, and the values of the first threshold and the second threshold are not limited in the embodiment of the present invention.
  • the debugging agent scheduling the debugging command to be scheduled may include: if the single execution time of the to-be-scheduled debugging command is greater than or equal to the preset time, the debugging agent schedules the debugging command to be scheduled according to the time slice polling algorithm.
  • a time slice polling algorithm is introduced in the optional implementation manner, so that a scheduling command can be split into multiple parts according to fine granularity, and then the debugging agent can schedule the scheduling command according to the time slice granularity, and in the process In the process, other debugging commands are scheduled to reduce the waiting time of the scheduling commands sent by other debuggers to improve the user experience.
  • the scheduling order of the debugging commands may be sequentially determined according to the optional implementation manner provided above.
  • the debugging agent performs the scheduling process as shown in Figure 4, specifically:
  • the debugging agent processes the debugging command sent by debugger C from the 0th time slice; the debugging command sent by debugger B is in the 3rd time.
  • the debug agent is reached within the slice; after the debug agent completes the scheduling of the debug command sent by the debugger C in the third time slice, the debug command sent by the debugger B is scheduled to start at the fourth time slice.
  • the debug agent alternately schedules the debug command sent by debugger B and the debug command sent by debugger C with the time slice as the granularity. .
  • This example intelligently schedules debugging commands from multiple debuggers (ie, debug commands from multiple users) by the debug agent, so that the user does not perceive the serial queuing process, thereby improving the user experience.
  • the method may further include: the debugging agent receives the request message sent by the debugger, where the request message includes a resource to be applied to request the resource to be applied; if the resource to be applied is not occupied, the agent is debugged. Allocating the to-be-applied resource to the debugger, and recording that the to-be-applied resource has been occupied by the debugger; or, if the to-be-applied resource is already occupied, the debugging agent returns a resource conflict warning to the debugger.
  • the optional implementation provides a technical solution for managing resources that multiple debuggers need to schedule.
  • the optional implementation supports various resources of the multi-core processor, such as kernel resources, memory resources, and IP. Resources, etc., resource pool management.
  • Each debugger can apply to the debug agent for the resources it needs to schedule. “Resources are not occupied” means that all resources to be applied for are not occupied by other debuggers; "Occupied” means that some or all of the resources to be applied have been occupied by other debuggers.
  • the record of the resource to be applied has been occupied by the debugger.
  • the specific relationship between the resource to be applied and the identifier of the debugger is recorded.
  • the identifier information of the debugger is a character or a string that can uniquely identify the debugger.
  • the debug agent can connect to the debugger through any of the service modes provided by it; optionally, the debug agent can generate unique identification information according to the connection attribute after successfully connecting with a debugger, the unique The identification information can be used as the identification information of the debugger.
  • the debugging agent may send the identifier information generated according to the connection attribute to the debugger; and each of the signalings that the subsequent debug agent communicates with the debugger may carry the identifier information. So that the debug agent can manage the resources that each debugger needs to schedule according to the identification information of each debugger.
  • the debug agent can release the resources occupied by the debug agent, so that the resources can be occupied by other debuggers. The purpose of resource reuse.
  • the debug agent can obtain the resources that the debugger needs to schedule by parsing the image file loaded by the debugger on the debug agent, or obtain a resource that the debugger needs to schedule by importing.
  • the optional implementation may be implemented by: the debugger imports the resources that need to be scheduled into the debugging agent before loading the image file. If the resource to be applied is not occupied, that is, the resource application is successful, the debugging agent refreshes. The internal resource management information starts to load the image file; if the resource to be applied is occupied, that is, the resource application is unsuccessful, the debugging agent returns a resource conflict warning to the debugger, and terminates loading the image file. This scenario can be referred to as resource isolation for image file loading.
  • the debugger can import the resources that need to be scheduled by itself into the debugging proxy in the form of a resource mapping table.
  • the debugger needs to debug the resource is kernel 1, but the user mistakenly inputs the scheduling command for debugging the resources of kernel 3 to the debugger, in which case the debugger access (or scheduling may occur).
  • the problem of kernel 3, that is, the question of cross-border access This will make the debugger that needs access to kernel 3 unable to access kernel 3 normally.
  • the optional implementation increases the management of the resources occupied by the debugger by the debug agent. Therefore, in the above case, the problem that the kernel 3 does not match the resource requested by the debugger can be determined, so that the kernel 3 is not accessed. This can effectively avoid the problem of cross-border access. That is, this optional implementation enables isolation of resource access during the debugging process.
  • the debugging agent determines the identifier information of the debugger included in the read operation command and the read operation command. If the identifier information of the debugger to which the debugged resource belongs does not match, the read operation may be performed, and the prompt information is returned to the debugger; if the debug command is in the write operation command, the debug agent includes the determination in the write operation command.
  • the write operation may not be performed, and an error indication is returned to the debugger.
  • the specific implementation is not limited to this.
  • the debug agent utilizes a thread to schedule one or more kernels to be debugged by the debugger.
  • the kernel to be debugged by one debugger may have one or more.
  • the multiple cores in the optional implementation may be all the cores to be debugged by the debugger, or may be part of the kernel to be debugged by the debugger.
  • the debug agent can schedule a kernel with one thread, as shown in Figure 5.
  • the debug agent can schedule a kernel group with a thread, as shown in Figure 6; where a kernel group is a collection of all the cores that the debugger is to debug.
  • a kernel group is a collection of all the cores that the debugger is to debug.
  • the specific implementation is not limited to this.
  • the optional implementation supports multi-core centralized debugging technology.
  • multiple cores to be debugged by the same debugger can be debugged by one thread, and debugging between different kernels in one kernel group.
  • the information can be shared with each other, so that synchronization between multiple cores in one core group can be made easier, and multi-core cooperative debugging is more convenient than the single core debugging technique shown in FIG.
  • FIG. 7 is a schematic structural diagram of a debugging agent according to an embodiment of the present invention.
  • the debug agent 7 shown in Figure 7 is used to execute the method embodiment provided above, the debug agent 7 being applied to a debug system comprising a verification platform and at least two debuggers on a multi-core processor The at least two debuggers are connected to and communicate with the debug agent 7 for resources to be debugged.
  • the debug agent 7 includes a determining unit 71 and a scheduling unit 72.
  • a determining unit 71 configured to determine, according to a priority order of the debug command, a debug command to be scheduled from the plurality of debug commands; the multiple debug commands are from the at least two debuggers, and each debug command is used for Debug the specific resources simulated on the verification platform.
  • the scheduling unit 72 is configured to schedule the debugging command to be scheduled to schedule a specific resource to be debugged by the debugging command to be scheduled.
  • the priority order of the debug command is determined according to at least a length of a single execution time of the debug command.
  • the determining unit 71 is specifically configured to: use a debugging command with the highest priority in a set as a debugging command to be scheduled, where the set is from each of the multiple debugging commands.
  • the debugging agent 7 may further include: an adjusting unit 73, configured to perform at least one step of: increasing a priority of the debug command whose scheduled number is less than or equal to the first threshold; and reducing the scheduled number of times greater than or equal to the first The priority of the second threshold scheduling command.
  • an adjusting unit 73 configured to perform at least one step of: increasing a priority of the debug command whose scheduled number is less than or equal to the first threshold; and reducing the scheduled number of times greater than or equal to the first The priority of the second threshold scheduling command.
  • the scheduling unit 72 is specifically configured to: if the single execution time of the to-be-scheduled debugging command is greater than or equal to a preset time, the debugging agent 7 schedules the to-be-served according to a time slice polling algorithm. Schedule debugging commands.
  • the debugging agent 7 may further include:
  • the receiving unit 74 is configured to receive a request message sent by the debugger, where The request message includes a resource to be applied for requesting the resource to be applied.
  • the allocation record unit 75 is configured to allocate the to-be-applied resource to the debugger if the to-be-applied resource is not occupied, and record that the to-be-applied resource has been occupied by the debugger.
  • the sending unit 76 is configured to: if the to-be-applied resource is already occupied, the debugging agent 7 returns a resource conflict alarm to the debugger.
  • the scheduling unit 72 is specifically configured to: use one thread to schedule one or more cores to be debugged by the debugger.
  • the embodiment of the present invention provides a schematic structural diagram of a debugging agent 8.
  • the debug agent 8 shown in FIG. 8 is used to execute the method embodiment provided above, the debug agent 8 being applied to a debug system including a verification platform and at least two debuggers on the multi-core processor The at least two debuggers are connected to and communicate with the debug agent 8 for resources to be debugged.
  • the debug agent 8 includes at least one processor 81, an interface circuit 82, a memory 83, and a system bus 84.
  • memory 83 is used to store computer execution instructions, at least one processor 81, interface circuit 82 and memory 83 are interconnected by a system bus 84, when the debug agent 8 is running
  • At least one processor 81 executes the computer-executed instructions stored in the memory 83 to cause the debug agent 8 to perform the actions performed by the debug agent 8 in the above method embodiment.
  • Narration for the specific implementation of the method, reference may be made to the above. Narration.
  • the embodiment further provides a storage medium, which may include the memory 83.
  • the at least one processor 81 may be a central processing unit (English: central processing unit, abbreviation: CPU).
  • the at least one processor 81 can also be other general purpose processors, digital signal processors (English: digital signal processing, DSP), application specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, Discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor 81 may be any conventional processor or the like.
  • the at least one processor 81 may be a dedicated processor, which may include at least one of a baseband processing chip, a radio frequency processing chip, and the like. Further, the dedicated processor may also include a chip with other dedicated processing functions of the debug agent 8.
  • the memory 83 may include a volatile memory 83 (English: volatile memory), such as a random access memory (English: random-access memory, abbreviation: RAM); the memory 83 may also include a non-volatile memory 83.
  • a volatile memory 83 such as a random access memory (English: random-access memory, abbreviation: RAM); the memory 83 may also include a non-volatile memory 83.
  • non-volatile memory such as read-only memory 83 (English: read-only memory, abbreviation: ROM), flash memory 83 (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) Or a solid state drive (English: solid-state drive, abbreviated: SSD); the memory 83 may also include a combination of the above-described types of memory 83.
  • the system bus 84 can include a data bus, a power bus, a control bus, and a signal status bus. For the sake of clarity in the present embodiment, various buses are illustrated as system bus 84 in FIG.
  • the at least one processor 81 communicates with other devices via the interface circuit 82.
  • each step performed by the debug agent 8 in the above method embodiment may be implemented by executing a computer-executed instruction in the form of software stored in the memory 83 by the processor 81 in hardware form. To avoid repetition, we will not repeat them here.
  • the embodiment of the present invention further provides a computer readable storage medium, where one or more programs are stored, and one or more programs include instructions when at least one processor 81 of the debug agent 8 executes the instructions. , the debug agent 8 performs the above The method of debugging the multi-core processor shown in the method embodiment.
  • the embodiment of the invention further provides a debugging system for a multi-core processor, comprising a verification platform, at least two debuggers, and any one of the debugging agents 7 or the debugging agents 8 provided above.
  • a debugging system for a multi-core processor comprising a verification platform, at least two debuggers, and any one of the debugging agents 7 or the debugging agents 8 provided above.
  • the resources to be debugged on the multi-core processor are simulated on the verification platform, and the at least two debuggers are connected and communicate with the debugging agent 8.
  • a schematic of the debug system can include, but is not limited to, any of the figures shown in Figures 2, 5, and 6.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to implement the solution of the embodiment. purpose.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

本发明公开了一种多核处理器的调试方法、装置和系统，用以提高验证平台资源的利用率，并提高用户的体验。该方法应用于包含验证平台、调试代理和至少两个调试器的调试系统中，验证平台上模拟了多核处理器上待调试的资源，至少两个调试器与调试代理连接并通信。方法包括：调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；多个调试命令来自至少两个调试器，每个调试命令用于对验证平台上模拟的特定资源进行调试；调试代理调度待调度的调试命令，以对待调度的调试命令所要调试的特定资源进行调度。

Description

多核处理器的调试方法、装置和系统 技术领域
本发明涉及多核处理器，尤其涉及多核处理器的调试方法、装置和系统。
背景技术
多核处理器的开发过程通常包括：系统分析与处理器设计、硅前验证以及样片验证共三个阶段。多核处理器的硅前验证具体包括：在验证平台上模拟多核处理器的完整的功能，然后在该验证平台上开展一系列的验证活动，以保证多核处理器的各项功能的正确性。
目前，多核处理器的硅前验证系统如图1所示，图1所示的系统包括验证平台、调试代理和调试器，验证平台上模拟了多核处理器的完整的功能。调试器用于接收用户输入的调试命令，并将该调试命令发送给调试代理；调试代理用于创建调试器与模拟的多核处理器之间的调试通道，并利用调试命令调度相应的内核，以验证内核对应的一些功能。
在图1所示的系统中，单个用户独占整套验证平台资源。这样，在一个用户使用验证平台的过程中，其他用户只能等待，这会导致这部分用户的体验差的问题。另外，由于一次验证过程所需要的时间较长，然而一个调试器接收相邻两个调试命令之间的时间间隔一般较长，例如，一次验证过程需要1小时，而调试器接收相邻两个调试命令之间的时间间隔可能是5分钟。这样，会导致有效调试时间较短，从而导致验证平台资源的利用率较低。
发明内容
本发明的实施例提供一种多核处理器的调试方法、装置和系统，用以提高验证平台资源的利用率，并提高用户的体验。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明的实施例提供一种多核处理器的调试方法，应用于包含验证平台、调试代理和至少两个调试器的调试系统中，验证平台上模拟了多核处理器上待调试的资源，至少两个调试器与调试代理连接并通信。该方法包括：调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；其中，该多个调试命令来自至少两个调试器，每个调试命令用于对验证平台上模拟的特定资源进行调试；然后，调试代理调度待调度的调试命令，以对待调度的调试命令所要调试的特定资源进行调度。
第二方面，本发明的实施例提供一种调试代理，应用于包含验证平台和至少两个调试器的调试系统中，验证平台上模拟了多核处理器上待调试的资源，至少两个调试器与调试代理连接并通信。该调试代理包括：确定单元和调度单元。确定单元，用于按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；其中，该多个调试命令来自至少两个调试器，每个调试命令用于对验证平台上模拟的特定资源进行调试。调度单元，用于调度待调度的调试命令，以对待调度的调试命令所要调试的特定资源进行调度。
上述技术方案中，调试代理按照调试命令的优先级顺序，确定待调度的调试命令，也就是说，本发明实施例中是以调试命令为粒度进行调度的，因此，能够在一定程度上，使得调试代理在调度一个调试器发送的所有的调试命令的过程中，对其他的调试器发送的调试命令进行调度；即能够在调度一个用户发送的所有调试命令的过程中，对其他用户发送的调试命令进行调度。与现有技术中的“只有一个用户发送的所有的调试命令均被调度完之后，才可以调度下一个用户发送的调试命令”的技术方案相比，能够提高用户的体验。 另外，由于本发明实施例提供的技术方案中，是以调度命令为粒度的，因此与现有技术中的以调试器为粒度的技术方案相比，能够延长有效调试时间，从而提高验证平台上的资源利用率。
可选的，基于上述第一方面或第二方面，调试命令的优先级顺序至少是根据调试命令的单次执行时间的长短确定的。
可选的，基于第一方面，调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令，可以包括：调试代理将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，该集合由多个调试命令中的来自每个调试器的最先到达调试代理的未被调度的调试命令构成。对应的，可选的，基于第二方面，确定单元具体用于：将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，该集合由多个调试命令中的来自每个调试器的最先到达调试代理的未被调度的调试命令构成。
该可选的实现方式提供了一直用具体的确定待调度的调试命令的方法，具体实现时，不限于此。
可选的，基于第一方面，该方法还可以包括以下至少一个步骤：调试代理提高被调度次数小于或等于第一阈值的调试命令的优先级；调试代理降低被调度次数大于或等于第二阈值的调度命令的优先级。对应的，可选的，基于第二方面，调试代理还可以包括：调整单元，用于执行以下至少一个步骤：提高被调度次数小于或等于第一阈值的调试命令的优先级；降低被调度次数大于或等于第二阈值的调度命令的优先级。
该可选的实现方式提供了一种自适应调整调试命令的优先级的方法能够避免因单次执行时间较长而导致优先级较低的调试命令在很长一段时间内不能被调度的问题，从而更好地对来自各个调试器的调试命令进行均衡地调度。
可选的，基于第一方面，调试代理调度待调度的调试命令，可 以包括：若待调度调试命令的单次执行时间大于或等于预设时间，则调试代理按照时间片轮询算法，调度待调度调试命令。对应的，可选的，基于第二方面，调度单元具体可以用于：若待调度调试命令的单次执行时间大于或等于预设时间，则调试代理按照时间片轮询算法，调度所述待调度调试命令。
该可选的实现方式中引入了时间片轮询算法，能够实现将一个调度命令按照细粒度拆分为多个部分，然后调试代理可以按照时间片粒度调度该调度命令，并在该过程中，调度其他的调试命令；从而减少其他调试器发送的调度命令的等待时间，以提高用户体验。
可选的，第一方面的方法还可以包括：调试代理接收调试器发送的请求消息，其中，请求消息中包含待申请资源，用以请求待申请资源；若待申请资源未被占用，则调试代理为调试器分配待申请资源，并记录待申请资源已被调试器占用；或者，若待申请资源已被占用，则调试代理向调试器返回资源冲突告警。
对应的，可选的，第二方面中的调试代理还可以包括：接收单元，用于接收调试器发送的请求消息，其中，请求消息中包含待申请资源，用以请求待申请资源。分配记录单元，用于若待申请资源未被占用，则为调试器分配待申请资源，并记录待申请资源已被调试器占用。发送单元，用于若待申请资源已被占用，则调试代理向调试器返回资源冲突告警。
该可选的实现方式提供了一种管理多个调试器需要调度的资源的技术方案，能够实现调试过程的资源访问的隔离。
可选的，基于第一方面，调试代理利用一个线程调度一个调试器待调试的一个或多个内核。对应的，可选的，基于第二方面，调度单元具体用于：利用一个线程调度一个调试器待调度的一个或多个内核。
该可选的实现方式支持多核集中调试技术，在该技术中，同一 个调试器待调试的多个内核可以通过一个线程被调试，一个内核组中的不同内核之间的调试信息可以彼此共享，从而使得一个内核组中的多个内核之间的同步更容易，多核协作调试更方便。
第三方面，本发明实施例提供一种调试代理，该调试代理应用于包含验证平台和至少两个调试器的调试系统中，验证平台上模拟了多核处理器上待调试的资源，至少两个调试器与调试代理连接并通信。该调试代理包括：至少一个处理器、接口电路、存储器和系统总线；存储器用于存储计算机执行指令，至少一个处理器、接口电路和存储器通过系统总线相互连接，当调试代理运行时，至少一个处理器执行存储器存储的计算机执行指令，以使调试代理执行上述第一方面及第一方面的各种可选方式中任意一项所述的多核处理器的调试方法。
第四方面，本发明实施例提供一种计算机可读存储介质，计算机可读存储介质中存储有一个或多个程序，一个或多个程序包括指令，当调试代理的至少一个处理器执行该指令时，调试代理执行上述第一方面及第一方面的各种可选方式中任意之一所述的多核处理器的调试方法。
第五方面，本发明实施例提供一种多核处理器的调试系统，包括验证平台、至少两个调试器以及上文所述的任一种调试代理。其中，验证平台上模拟了多核处理器上待调试的资源，所述至少两个调试器与所述调试代理连接并通信。
附图说明
图1为现有技术提供的一种多核处理器的调试系统的示意图；
图2为本发明实施例提供的一种多核处理器的调试系统的示意图；
图3为本发明实施例提供的一种多核处理器的调试方法的交互 示意图；
图4为本发明实施例提供的一种调试代理的调度过程的示意图；
图5为本发明实施例提供的另一种多核处理器的调试系统的示意图；
图6为本发明实施例提供的另一种多核处理器的调试系统的示意图；
图7为本发明实施例提供的一种调试代理的结构示意图；
图8为本发明实施例提供的另一种调试代理的结构示意图。
具体实施方式
本发明实施例提供的技术方案应用于多核处理器的硅前验证阶段，其中，硅前验证包括但不限于现场可编程门阵列(英文：field-programmable gate array，缩写：FPGA)验证，或电子设计自动化(英文：electronic design automation，缩写：EDA)验证等。下文中均以本发明实施例提供的验证平台是FPGA验证平台为例进行说明。
本发明实施例提供的技术方案所适用的调试系统的架构示意图如图2所示。图2所示的调试系统包括验证平台、调试代理和至少两个调试器。其中，验证平台上模拟了一个或多个多核处理器上待调试的资源，待调试的资源包括但不限于内核资源、内存资源，以及网络之间互连的协议(英文：internet protocol，缩写：IP)资源等，其中，图2中仅示出了验证平台上包含内核资源。至少两个调试器与调试代理连接并通信。调试过程可以包括：调试器接收用户输入的调试命令，并发送给调试代理；调试代理调度该调试命令，以对验证平台上的相应的资源进行调试。
调试器和调试代理均是逻辑功能模块，二者均可以通过软件或 硬件的方式实现。任意一个或多个调试器可以集成在一个主机上。调试代理可以与任意的一个或多个调试器集成在一个主机上，也可以独立设置在一个主机上。需要说明的是，一般将验证平台所在的主机称为目标机，调试代理或调试器所在的主机称为宿主机。
可选的，调试代理可以向外提供一种或多种服务方式，该服务方式包括但不限于：socket、tuxedo、cics、webservice等。其中，网络上的两个程序通过一个双向的通信连接实现数据的交换，这个连接的一端称为一个socket；tuxedo是一个客户机/服务器的中间件产品；cics是IBM公司的一个中间件产品；webservice，即webservice，是基于可编程的web的应用程序。调试代理可以利用其所提供的任意一种服务方式与调试器进行连接并通信。
每个调试器可以支持一种或多种服务方式，不同调试器所支持的服务方式可以相同，也可以不同；一个调试器可以通过调试代理所提供的，并且是该调试器自身所支持的任意一种服务方式，与调试代理进行连接并通信。
任意一个调试器均可以在需要对多核处理器的功能进行验证时，与调试代理之间建立连接并进行通信；并在不需要对多核处理器的功能进行验证时，断开与调试代理之间的连接。本发明实施例对调试器与调试代理之间建立连接的实现方式不进行限定。
每个调试器与验证平台上的一部分资源相映射。每个调试器上映射的资源是可配置的，以内核资源为例，调试器上映射的内核的种类和个数均是可配置的。例如，若用户需要利用调试器A对内核3、4进行调试，则可以配置调试器A与验证平台上的内核3、4相映射；若用户需要利用调试器B对内核5进行调试，则可以配置调试器B与验证平台上的内核5相映射。
本发明实施例提供的技术方案应用于调试代理接收了多个调试器发送的多个调试命令的场景中，并具体提供了在该场景下，选择 待调度的调试命令的技术方案，从而使得多个调试器可以进行用户无感知的串行工作，这样，对于用户而言，相当于多个调试器进行并行工作，从而提高用户的体验。另外，由于本发明实施例提供的技术方案中，是以调度命令为粒度进行调试的，因此与现有技术中的以调试器为粒度进行调试的技术方案相比，能够延长有效调试时间，从而提高验证平台资源的利用率。
需要说明的是，在调试代理接收了一个调试器发送多个调试命令的场景中，调试代理可以按照每个调试命令的接收时间的先后顺序依次对这些调试命令进行调度。另外，在不冲突的情况下，本文中提供的任意的多个可选的实现方式之间可以结合。
本文中的术语“多个”是指两个或两个以上。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
如图3所示，是本发明实施例提供的一种多核处理器的调试方法的交互示意图。该方法所适用的调试系统可以如图2所示。图3所示的方法包括以下步骤S101-S104：
S101：至少两个调试器向调试代理发送多个调试命令；其中，每个调试命令用于对验证平台上模拟的特定资源进行调试。
具体的，至少两个调试器中的每个调试器可以向调试代理发送一个或多个调试命令，例如，调试器1向调试代理发送5个调试命令，调试器2向调试代理发送1个调试命令。示例的，“调试命令”可以包括但不限于：加载命令(即写命令)、读命令、同步命令、单步执行命令等。
示例的，在调试代理所在的宿主机的缓存容量足够的情况下， S101可以包括：至少两个调试器中的每个调试器向调试代理发送各自的一次验证活动中所需要的全部的调试指令，例如，调试器1向调试代理发送调试内核1、2时所需要的全部的调试指令，调试器2向台式代理发送调试内核3、4时所需要的全部的调试指令。另外，本发明实施例提供的技术方案也支持以下场景：调试代理在对一个或多个调试器发送的调试命令进行调度的过程中，又接收到其他的调试器发送的调试命令。
每个调试器用于调试验证平台上的哪些资源可以按照用户的需求进行配置，例如，某个用户需要对某个多核处理器的一些资源(例如内核1、2)进行调试，则该用户可以通过向一个调试器输入该待调试的资源，然后由调试器向该验证平台申请这些资源，其具体实现方式可以参考下文。每个调试命令用于对哪些特定资源进行调试可以预先进行设定。
每个调试器可以对应一个用户，即每个用户可以操作一个调试器。不同的用户可以通过不同的调试器对一个或多个多核处理器进行调试，例如，用户A利用调试器A对多核处理器1的内核1～3进行调试，用户B利用调试器B对多核处理器1的内核4～5进行调试；用户C利用调试器C对多核处理器2的内核1～4进行调试等。
在S101之前，至少两个调试器与调试代理之间已经建立了连接，本发明实施例对建立连接的具体实现方式不进行限定。并且，在调试器与调试代理之间建立了连接之后，若该调试器还未向调试代理加载任何数据，则该调试器可以首先向调试代理中加载镜像(英文：image)文件，即调试器向调试代理发送加载命令，其中，镜像文件是指可在多核处理器的内核上运行的二进制可执行文件；然后，调试代理可以在与其连接的调试器加载完镜像文件之后，对该调试器发送的调试命令(例如包括读命令、同步命令、单步执行命令、加载命令等)进行调度。若在调试器与调试代理之间建立了连接之 后，若该调试器已经向调试代理加载了镜像文件，则调试代理可以直接对该调试器发送的调试命令(例如包括读命令、同步命令、单步执行命令、加载命令等)进行调度。
S102：调试代理接收该至少两个调试器发送的多个调试命令。
在执行S101-S102之后，循环执行S103-S104，直到在S102中调试代理所接收到的多个调试命令依次被调度完为止。并且，每次执行S103-S104的过程中，确定一个待调度的调试命令。
S103：调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令。
需要说明的是，每次执行S103时，具体是从S102中的多个调试命令中未被调度的调试命令中确定待调度的命令。
示例的，调试命令的优先级顺序至少是根据调试命令的单次执行时间的长短确定的。其中，调试命令的单次执行时间是指调试代理在一次执行该调试命令的过程中需要使用的时间。示例的，调试命令的单次执行时间越短，该调试命令的优先级越高。另外，调试命令的优先级的高低还可以与其他因素有关，具体可参考下文。
S104：调试代理调度待调度的调试命令，以对待调度的调试命令所要调试的特定资源进行调度。
示例的，假设待调度的调试命令是读命令，该读命令用于对内核1进行读操作，即读命令所要调试的资源是内核1，则调试代理调度该读命令，从而对内核1进行读操作；又如，假设待调度的调度命令是加载命令，该加载命令用于对内核3进行写操作，即加载命令所要调试的资源是内核2，则调试代理调度该加载命令，从而对内核3执行写操作。
需要说明的是，本实施例是以调试代理首先接收多个调试命令，然后依次调度所接收到的多个调试命令，实际实现时，本发明实施例还支持在调度步骤S102中调试代理所接收到的多个调试命令的 过程中，接收一个或多个调试器发送的调试命令的场景；并且，在该场景中，继续执行S103-S104时，将所有未被调度的调试命令作为S103中的“多个调试命令”。具体示例见下文。
本发明实施例提供的多核处理器的调试方法中，调试代理按照调试命令的优先级顺序，确定待调度的调试命令。也就是说，本发明实施例中是以调试命令为粒度进行调度的，因此，该技术方案能够在一定程度上，使得调试代理在调度一个调试器发送的所有的调试命令的过程中，对其他的调试器发送的调试命令进行调度；即能够在调度一个用户发送的所有调试命令的过程中，对其他用户发送的调试命令进行调度。与现有技术中的“只有一个用户发送的所有的调试命令均被调度完之后，才可以调度下一个用户发送的调试命令”的技术方案相比，能够提高用户的体验。另外，由于本发明实施例提供的技术方案中，是以调度命令为粒度的，因此与现有技术中的以调试器为粒度的技术方案相比，能够延长有效调试时间，从而提高验证平台上的资源利用率。
可选的，S103可以包括：S103a、调试代理将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，该集合由该多个调试命令中的来自每个调试器的最先到达调试代理的未被调度的调试命令构成。
具体的，调试代理在接收到多个调试命令之后，可以将来自同一个调试器的调试命令归为一组；接着，对每个组中的调试命令，按照到达调试代理的先后顺序进行排序。另外，调试代理也可以在接收多个调试命令的同时，即按照是否来自同一个调试器和/或到达调试代理的先后顺序，对该多个调试命令分别进行缓存。示例的，假设按照该方法得到的多个调试命令如表1所示：
表1
调试器 调试命令
调试器A A1、A2、A3
调试器B B1、B2、B3、B4、B5
调试器C C1、C2
表1中，每个调试器的多个调试命令均是按照到达调试代理的时间由先至后的顺序进行排序的。基于表1，调试代理第1次执行S103a时，该集合由A1、B1和C1构成，若该集合中的各调试命令的优先级由高至低的顺序为：B1、A1、C1，则本次所确定的待调度的调试命令是B1。这样，第2次执行S103a时，该集合由A1、B2、C1构成，若该集合中的各调试命令的优先级由高至低的顺序为：A1、C1、B2，则本次所确定的待调度的调试命令是A1。这样，第3次执行S103a时，该集合由A2、B2、C1构成，依次类推，可以依次得到调试代理每次执行S103a时的待调度的调试命令。
需要说明的是，假设在调试代理执行了多次S103a之后，表1中未被调度的调试命令均为来自同一个调试器的调试命令，例如，在执行了7次S103a之后，未被调度的调试命令为：B3、B4、B5，那么，接着，调试代理可以不进行调度命令的优先级的判断，而直接将B3、B4、B5依次作为待调度的调试命令。
可选的，该方法还可以包括以下至少一个步骤：调试代理提高被调度次数小于或等于第一阈值的调试命令的优先级；调试代理降低被调度次数大于或等于第二阈值的调度命令的优先级。
该可选的实现方式提供了一种自适应调整调试命令的优先级的方法，具体实现时，调试代理可以根据现有技术中提供的任意一种自适应调整算法，调整调试命令的优先级。该可选的实现方式，能够避免因单次执行时间较长而导致优先级较低的调试命令在很长一段时间内不能被调度的问题，从而更好地对来自各个调试器的调试 命令进行均衡地调度。
具体的，调试代理可以监控并统计每种调试命令被调度的次数，然后，提高被调度次数小于或等于第一阈值的调试命令的优先级，和/或，降低被调度次数大于或等于第二阈值的调度命令的优先级。其中，第一阈值小于或等于第二阈值，并且本发明实施例对第一阈值和第二阈值的取值不进行限定。
可选的，调试代理调度待调度的调试命令，可以包括：若待调度调试命令的单次执行时间大于或等于预设时间，则调试代理按照时间片轮询算法，调度待调度调试命令。
该可选的实现方式中引入了时间片轮询算法，这样，能够实现将一个调度命令按照细粒度拆分为多个部分，然后调试代理可以按照时间片粒度调度该调度命令，并在该过程中，调度其他的调试命令，从而减少其他调试器发送的调度命令的等待时间，以提高用户体验。其中，调度其他的调试命令时，可以按照上文提供的可选的实现方式依次确定调试命令的调度顺序。
下面列举一个具体示例：假设有三个用户(例如，用户A、B、C)使用各自的调试器(例如，调试器A、B、C)进行并行调试，用户A和B的image文件均已加载完成，正在进行调试，用户C的image文件正在加载。时间片轮询算法的粒度为10ms(毫秒)。用户C加载image文件需要占用100个时间片；用户B通过调试器向调试代理发送读取内存数据的调试命令，需要占用4个时间片，在该过程中，用户A通过调试器A向调试代理发送了2个单步执行调试命令；其中，单步执行调试命令的优先级高于读取内存数据的调试命令，每个单步执行调试命令占用1个时间片。
那么，调试代理进行调度的过程如图4所示，具体的：
1)用户C的加载时间较长，调试代理从第0个时间片开始处理调试器C发送的调试命令；调试器B发送的调试命令在第3个时间 片之内到达了调试代理；调试代理在第3个时间片内完成对调试器C发送的调试命令的调度之后，在第4个时间片开始调度调试器B发送的调试命令。
2)调试器A发送的调度命令在第5个时间片之内到达了调试代理，由于调试器A发送的单步执行调试命令的优先级高于调试器B发送的读内存的调试命令的优先级，因此，调试器A发送的单步执行调试命令很快在第6个时间片内得到调度。
3)第7个时间片至第12个时间片之间没有其他调试命令插入，该情况下，调试代理以时间片为粒度，交替调度调试器B发送的调试命令和调试器C发送的调试命令。
4)假设在第12个时间片结束之后，调试器B发送的调试命令被调度完，并且在调试器C发送的调试命令被调度完之前调试代理没有再接收到其他调试器发送的调试命令，那么，调试代理从第13个时间片开始的每个时间片均调度调试器C发送的调试命令。
该示例通过调试代理对来自多个调试器的调试命令(即：来自多个用户的调试命令)的智能化调度，使得用户无感知串行排队的过程，从而提高了用户的体验。
可选的，该方法还可以包括：调试代理接收调试器发送的请求消息，其中，该请求消息中包含待申请资源，用以请求待申请资源；若该待申请资源未被占用，则调试代理为该调试器分配该待申请资源，并记录该待申请资源已被该调试器占用；或者，若该待申请资源已被占用，则调试代理向该调试器返回资源冲突警告。
该可选的实现方式提供了一种管理多个调试器需要调度的资源的技术方案，具体的：该可选的实现方式支持将多核处理器的各种资源，例如内核资源、内存资源和IP资源等，进行资源池化管理。每个调试器均可以向调试代理申请自身所需要调度的资源。“资源未被占用”是指所有的待申请有的资源均未被其他调试器占用；“资源 已被占用”是指部分或所有的待申请资源已被其他调试器占用。
“记录待申请资源已被该调试器占用”具体可以实现为：记录待申请资源与该调试器的标识信息之间的对应关系。其中，调试器的标识信息是能够唯一标识调试器的字符或字符串。如上文所述，调试代理可以通过其提供的任一种服务方式与调试器连接；可选的，调试代理可以在与一个调试器成功连接之后，根据连接属性，生成唯一的标识信息，该唯一的标识信息可以作为该调试器的标识信息。
在该可选的实现方式中，调试代理可以将根据连接属性所生成的标识信息发送给该调试器；在后续调试代理与该调试器进行通信的每条信令中，均可以携带该标识信息，从而使得调试代理可以根据每个调试器的标识信息对每个调试器需要调度的资源进行管理。另外，在该可选的实现方式中，当某个调试器与调试代理断开连接之后，调试代理可以释放该调试代理已占用的资源，从而使得这些资源能够再被其他的调试器占用，实现资源重复利用的目的。
调试代理可以通过解析一个调试器加载在调试代理上的image文件获取到该调试器需要调度的资源，也可以通过导入的方式获取一个调试器需要调度的资源。示例的，该可选的实现方式可以实现为：调试器在加载image文件之前，将自身需要调度的资源导入到调试代理中，若待申请资源未被占用，即资源申请成功，则调试代理刷新内部资源管理信息，启动加载image文件；若该待申请资源已被占用，即资源申请不成功，则调试代理向该调试器返回资源冲突警告，并终止加载image文件。该场景可以称为image文件加载的资源隔离。其中，调试器可以将自身所需要调度的资源以资源映射表的形式导入到调试代理中。
具体实现时，若调试器需要调试的资源是内核1，但是，用户误向该调试器中输入了用于调试内核3的资源的调度命令，该情况下，可能出现该调试器访问(或调度)内核3的问题，即越界访问的问 题，这样会使得需要对内核3进行访问的调试器不能对内核3进行正常的访问。该可选的实现方式增加了调试代理对调试器所占用的资源的管理，因此，能够在上述情况下，确定内核3与该调试器所申请的资源不匹配的问题，从而不对内核3进行访问，这样可以有效避免越界访问的问题。也就是说，该可选的实现方式能够实现调试过程的资源访问的隔离。
另外，在实现调试过程的资源访问的隔离的过程中，可选的，若调试命令是读操作命令，则调试代理在确定该读操作命令中包含的调试器的标识信息与该读操作命令要调试的资源所属的调试器的标识信息不匹配的情况下，可以进行读操作，并向该调试器返回提示信息；若调试命令是写操作命令中，则调试代理在确定该写操作命令中包含的调试器的标识信息与该写操作的命令要调试的资源所属的调试器的标识信息不匹配的情况下，可以不进行写操作，并向该调试器返回错误指示。当然，具体实现时，不限于此。
可选的，调试代理利用一个线程调度一个调试器待调试的一个或多个内核。其中，一个调试器待调试的内核可以有一个或多个，该可选的实现方式中的多个内核可以是一个调试器待调试的所有内核，也可以是一个调试器待调试的部分内核。
示例的，调试代理可以利用一个线程调度一个内核，如图5所示。或者，调试代理可以利用一个线程调度一个内核组，如图6所示；其中，一个内核组是指一个调试器待调试的所有内核构成的集合。当然，具体实现时不限于此。
由于图6可知，该可选的实现方式支持多核集中调试技术，在该技术中，同一个调试器待调试的多个内核可以通过一个线程被调试，一个内核组中的不同内核之间的调试信息可以彼此共享，这样，与图5所示的单核调试技术相比，能够使得一个内核组中的多个内核之间的同步更容易，多核协作调试更方便。
如图7所示，是本发明实施例提供的一种调试代理的结构示意图。图7所示的调试代理7用以执行上文提供的方法实施例，该调试代理7应用于包含验证平台和至少两个调试器的调试系统中，所述验证平台上模拟了多核处理器上待调试的资源，所述至少两个调试器与所述调试代理7连接并通信。该调试代理7包括：确定单元71和调度单元72。
确定单元71，用于按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；所述多个调试命令来自所述至少两个调试器，每个调试命令用于对所述验证平台上模拟的特定资源进行调试。
调度单元72，用于调度所述待调度的调试命令，以对所述待调度的调试命令所要调试的特定资源进行调度。
可选的，所述调试命令的优先级顺序至少是根据调试命令的单次执行时间的长短确定的。
可选的，所述确定单元71具体可以用于：将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，所述集合由所述多个调试命令中的来自每个所述调试器的最先到达所述调试代理的未被调度的调试命令构成。
可选的，所述调试代理7还可以包括：调整单元73，用于执行以下至少一个步骤：提高被调度次数小于或等于第一阈值的调试命令的优先级；降低被调度次数大于或等于第二阈值的调度命令的优先级。
可选的，所述调度单元72具体可以用于：若所述待调度调试命令的单次执行时间大于或等于预设时间，则所述调试代理7按照时间片轮询算法，调度所述待调度调试命令。
可选的，调试代理7还可以包括：
接收单元74，用于接收所述调试器发送的请求消息，其中，所 述请求消息中包含待申请资源，用以请求所述待申请资源。
分配记录单元75，用于若所述待申请资源未被占用，则为所述调试器分配所述待申请资源，并记录所述待申请资源已被所述调试器占用。
发送单元76，用于若所述待申请资源已被占用，则调试代理7向所述调试器返回资源冲突告警。
可选的，所述调度单元72具体可以用于：利用一个线程调度一个所述调试器待调试的一个或多个内核。
本发明实施例提供的调试代理7能够达到的有益效果可以参考上文提供的方法实施例，此处不再赘述。
如图8所示，本发明实施例提供一种调试代理8的结构示意图。图8所示的调试代理8用以执行上文提供的方法实施例，该调试代理8应用于包含验证平台和至少两个调试器的调试系统中，所述验证平台上模拟了多核处理器上待调试的资源，所述至少两个调试器与所述调试代理8连接并通信。该调试代理8包括：至少一个处理器81、接口电路82、存储器83和系统总线84。
至少一个处理器81、接口电路82、存储器83和系统总线84；存储器83用于存储计算机执行指令，至少一个处理器81、接口电路82和存储器83通过系统总线84相互连接，当调试代理8运行时，至少一个处理器81执行存储器83存储的计算机执行指令，以使调试代理8执行上述方法实施例中调试代理8所执行的动作，该方法的具体实现方式可以参考上文，此处不再赘述。
本实施例还提供一种存储介质，该存储介质可以包括所述存储器83。
所述至少一个处理器81可以为中央处理器(英文：central processing unit，缩写：CPU)。所述至少一个处理器81还可以为其他通用处理器、数字信号处理器(英文：digital signal processing， 简称DSP)、专用集成电路(英文：application specific integrated circuit，简称ASIC)、现场可编程门阵列(英文：field-programmable gate array，简称FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器81也可以是任何常规的处理器等。
所述至少一个处理器81可以为专用处理器，该专用处理器可以包括基带处理芯片、射频处理芯片等中的至少一个。进一步地，该专用处理器还可以包括具有调试代理8其他专用处理功能的芯片。
所述存储器83可以包括易失性存储器83(英文：volatile memory)，例如随机存取存储器83(英文：random-access memory，缩写：RAM)；所述存储器83也可以包括非易失性存储器83(英文：non-volatile memory)，例如只读存储器83(英文：read-only memory，缩写：ROM)，快闪存储器83(英文：flash memory)，硬盘(英文：hard disk drive，缩写：HDD)或固态硬盘(英文：solid-state drive，缩写：SSD)；所述存储器83还可以包括上述种类的存储器83的组合。
所述系统总线84可以包括数据总线、电源总线、控制总线和信号状态总线等。本实施例中为了清楚说明，在图8中将各种总线都示意为系统总线84。
所述至少一个处理器81通过所述接口电路82与其他设备进行通信。
在具体实现过程中，上述方法实施例中调试代理8所执行的每个步骤均可以通过通过硬件形式的处理器81执行存储器83存储的软件形式的计算机执行指令实现。为避免重复，此处不再赘述。
本发明实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有一个或多个程序，一个或多个程序包括指令，当调试代理8的至少一个处理器81执行该指令时，调试代理8执行上述 方法实施例中所示的多核处理器的调试方法。
本发明实施例还提供一种多核处理器的调试系统，包括验证平台、至少两个调试器以及上文提供的任一种调试代理7或调试代理8。其中，验证平台上模拟了多核处理器上待调试的资源，所述至少两个调试器与所述调试代理8连接并通信。该调试系统的示意图可以包括但不限于图2、图5和图6所示的任一附图。
本发明实施例提供的调试的爱丽8，以及调试系统所能够达到的有益效果可以参考上文提供的方法实施例，此处不再赘述。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的 目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (15)

  1. 一种多核处理器的调试方法，其特征在于，应用于包含验证平台、调试代理和至少两个调试器的调试系统中，所述验证平台上模拟了所述多核处理器上待调试的资源，所述至少两个调试器与所述调试代理连接并通信；所述方法包括：
    所述调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；所述多个调试命令来自所述至少两个调试器，每个调试命令用于对所述验证平台上模拟的特定资源进行调试；
    所述调试代理调度所述待调度的调试命令，以对所述待调度的调试命令所要调试的特定资源进行调度。
  2. 根据权利要求1所述的方法，其特征在于，所述调试命令的优先级顺序至少是根据调试命令的单次执行时间的长短确定的。
  3. 根据权利要求1或2所述的方法，其特征在于，所述调试代理按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令，包括：
    所述调试代理将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，所述集合由所述多个调试命令中的来自每个所述调试器的最先到达所述调试代理的未被调度的调试命令构成。
  4. 根据权利要求3所述的方法，其特征在于，所述方法还包括以下至少一个步骤：
    所述调试代理提高被调度次数小于或等于第一阈值的调试命令的优先级；
    所述调试代理降低被调度次数大于或等于第二阈值的调度命令的优先级。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述调试代理调度所述待调度的调试命令，包括：
    若所述待调度调试命令的单次执行时间大于或等于预设时间，则 所述调试代理按照时间片轮询算法，调度所述待调度调试命令。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述方法还包括：
    所述调试代理接收所述调试器发送的请求消息，其中，所述请求消息中包含待申请资源，用以请求所述待申请资源；
    若所述待申请资源未被占用，则所述调试代理为所述调试器分配所述待申请资源，并记录所述待申请资源已被所述调试器占用；或者，若所述待申请资源已被占用，则所述调试代理向所述调试器返回资源冲突告警。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述调试代理利用一个线程调度一个所述调试器待调试的一个或多个内核。
  8. 一种调试代理，其特征在于，应用于包含验证平台和至少两个调试器的调试系统中，所述验证平台上模拟了多核处理器上待调试的资源，所述至少两个调试器与所述调试代理连接并通信；所述调试代理包括：
    确定单元，用于按照调试命令的优先级顺序，从多个调试命令中确定待调度的调试命令；所述多个调试命令来自所述至少两个调试器，每个调试命令用于对所述验证平台上模拟的特定资源进行调试；
    调度单元，用于调度所述待调度的调试命令，以对所述待调度的调试命令所要调试的特定资源进行调度。
  9. 根据权利要求8所述的调试代理，其特征在于，所述调试命令的优先级顺序至少是根据调试命令的单次执行时间的长短确定的。
  10. 根据权利要求8或9所述的调试代理，其特征在于，所述确定单元具体用于：将一集合中的优先级最高的调试命令作为待调度的调试命令，其中，所述集合由所述多个调试命令中的来自每个所述调试器的最先到达所述调试代理的未被调度的调试命令构成。
  11. 根据权利要求10所述的调试代理，其特征在于，所述调试 代理还包括：
    调整单元，用于执行以下至少一个步骤：提高被调度次数小于或等于第一阈值的调试命令的优先级；降低被调度次数大于或等于第二阈值的调度命令的优先级。
  12. 根据权利要求8-11任一项所述的调试代理，其特征在于，
    所述调度单元具体用于：若所述待调度调试命令的单次执行时间大于或等于预设时间，则按照时间片轮询算法，调度所述待调度调试命令。
  13. 根据权利要求8-12任一项所述的调试代理，其特征在于，所述调试代理还包括：
    接收单元，用于接收所述调试器发送的请求消息，其中，所述请求消息中包含待申请资源，用以请求所述待申请资源；
    分配记录单元，用于若所述待申请资源未被占用，则为所述调试器分配所述待申请资源，并记录所述待申请资源已被所述调试器占用；
    发送单元，用于若所述待申请资源已被占用，则所述调试代理向所述调试器返回资源冲突告警。
  14. 根据权利要求8-13任一项所述的调试代理，其特征在于，
    所述调度单元具体用于：利用一个线程调度一个所述调试器待调试的一个或多个内核。
  15. 一种多核处理器的调试系统，其特征在于，包括验证平台、至少两个调试器以及权利要求8-14任一项所述的调试代理；其中，所述验证平台上模拟了所述多核处理器上待调试的资源，所述至少两个调试器与所述调试代理连接并通信。
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