WO2017186013A1 - 表项校验 - Google Patents

表项校验 Download PDF

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Publication number
WO2017186013A1
WO2017186013A1 PCT/CN2017/080763 CN2017080763W WO2017186013A1 WO 2017186013 A1 WO2017186013 A1 WO 2017186013A1 CN 2017080763 W CN2017080763 W CN 2017080763W WO 2017186013 A1 WO2017186013 A1 WO 2017186013A1
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Prior art keywords
entry
data
hardware chip
entries
sent
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English (en)
French (fr)
Inventor
葛长忠
任凯
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New H3C Technologies Co Ltd
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New H3C Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Definitions

  • a data entry is usually generated by the control plane, and the entry is sent to the hardware chip. Then, the hardware chip performs data packet processing on the data layer according to the data table item.
  • the items used by the hardware chip can be stored in an on-chip SRAM (Static Random Access Memory) or in an off-chip DDR SDRAM (Double Rate Synchronous Dynamic Random Access Memory). , referred to as: SDRAM). Since SRAM is susceptible to cosmic rays or other high-energy particles, the content stored in the table changes. The SDRAM uses a capacitor storage entry, which requires constant charging of the capacitor to maintain the contents of the entry. If the charging is interrupted during the charging process, the contents of the entry may be incorrect.
  • 1 is an application system architecture of a data communication device according to an example of the present disclosure
  • FIG. 2 is a schematic structural diagram of a physical structure of a data communication device according to another example of the present disclosure
  • FIG. 3 is a flowchart of an entry verification method according to an example of the present disclosure.
  • FIG. 4 is a schematic diagram of a principle of an entry verification method according to an example of the present disclosure.
  • FIG. 5 is a functional block diagram of an item check logic according to an example of the present disclosure.
  • FIG. 6 is a functional block diagram of an entry verification logic provided by another example of the present disclosure.
  • the data communication device can determine whether there is an abnormal entry by techniques such as ECC (Error Correcting Code) and EDAC (Error Detection And Correction).
  • ECC Error Correcting Code
  • EDAC Error Detection And Correction
  • this method of error detection requires additional hardware resources, such as occupying on-chip SRAM resources or SDRAM particles, thereby reducing hardware resource utilization.
  • an entry verification method is provided, which can be applied to a data communication device such as a switch or a router to determine whether an entry is abnormal, so that the abnormality entry can be corrected as soon as possible, and the data communication device is secured. Reliability.
  • FIG. 1 an application system architecture in a data communication device is illustrated.
  • a host processor (HOST CPU) 11 and one or more hardware chips 12 may be included in the data communication device.
  • the hardware chip 12 may be a chip such as an FPGA (Field-Programmable Gate Array) or an NPU (Network Processing Unit).
  • the host processor 11 and the hardware chip 12 can be connected by a PCI-E (Peripheral Component Interface Express) bus.
  • PCI-E Peripheral Component Interface Express
  • the host processor 11 can send the data table item generated by the control layer to the hardware chip 12, and the hardware chip 12 performs data packet processing at the data level according to the data table item, for example, forwarding the data packet.
  • These data entries issued may be stored in an on-chip memory of the hardware chip 12, such as an SRAM, or may be stored in an off-chip memory of the hardware chip 12, such as DDR SDRAM (simply referred to as SDRAM).
  • the hardware chip 12 can utilize these data entries for packet processing.
  • FIG. 1 when the host processor 11 of the example of the present disclosure sends a data entry to the hardware chip 12 , at least two identical data entries can be delivered.
  • the at least two identical data entries may be stored in the same hardware chip 12 or in different hardware chips 12.
  • at least two identical data entries shown in FIG. 1 may be stored in two hardware chips 12, and a plurality of data entries sent to the hardware chip 12 may form a data table.
  • the entry verification method of the example of the present disclosure is mainly used for verifying a data entry (which may be simply referred to as an entry) that is sent by the host processor 11 to the hardware chip 12 to detect whether an entry is abnormal. Moreover, since the check of the entry is implemented in a software detection manner, the method can reduce the consumption of hardware resources compared with technologies such as ECC and EDAC.
  • the hardware resources may be on-chip SRAM resources, SDRAM particles, or space on a board.
  • the software detection mode may be an algorithm flow when the host processor 11 runs the entry detection, and implements verification of the entry.
  • Figure 2 shows a physical structure diagram of a data communication device.
  • the data communication device can include a processor 21, a communication bus 22, and a machine
  • the storage medium 23 and the communication interface 24 are read.
  • the processor 21 in the device may be the host processor 11 shown in FIG. 1 or an SDN (Software Defined Network) controller, and the processor 21 may execute the storage in the machine readable storage medium 23.
  • the item executable instruction corresponding to the entry verification logic implements the entry verification method.
  • the check method of the entry is explained as follows.
  • the method may compare at least two items of the same content of the hardware chip that are sent to the data communication device, and when the contents of the at least two items with the same content are inconsistent, the method may determine the at least two items.
  • An exception entry exists in the entry. If the data consistency is satisfied between the at least two items with the same content, the at least two items with the same content may be determined to be correct; otherwise, the abnormal items may be determined in at least two of the items.
  • the "data consistency judgment” can include various aspects. For example, if an entry is correct, the "data consistency judgment" may be to determine whether the entry to be verified is the same as the content of the correct entry. Alternatively, it may be determined whether the contents of the plurality of check items stored in different locations are the same. The following will be described by a number of examples.
  • each checksum item can be verified using the following method.
  • the HOST CPU 11 can deliver the first entry to a hardware chip 12.
  • the first entry may be stored in the on-chip SRAM of the hardware chip 12 as a to-be-checked entry when comparing data consistency described later.
  • the HOST CPU 11 can also send a second entry having the same content as the first entry to the DDR SDRAM of the HOST CPU 11 (abbreviation: HOST RAM, off-chip memory of the host processor) as the comparative data consistency described later.
  • HOST RAM off-chip memory of the host processor
  • the HOST RAM can be another hardware chip 12 in FIG. It should be noted that the copy of the entry and the entry to be verified actually have the same content, and only distinguish from the name.
  • the item to be checked can be referred to as an application entry, and the copy of the entry is referred to as a reference entry.
  • the hardware chip 12 that receives the reference entry may be referred to as a first hardware chip, and the hardware chip 12 that receives the application entry is referred to as a second hardware chip.
  • FIG. 3 illustrates a flow chart of an entry verification method.
  • the flowchart describes the above-mentioned method of comparing an application entry with a reference entry to determine whether an application entry is abnormal.
  • the application entry may be verified according to the reference entry.
  • the baseline entry can be used as a benchmark for verification, and the application entry is compared with the content of the baseline entry to determine if the application entry is in error. If the two are the same, it may be determined that the two entries satisfy the data consistency, and in step 303, it is determined that the application entry is correct; otherwise, it may be determined that the two entries do not satisfy the data consistency, thereby determining the application table in step 304.
  • the item is an exception table entry.
  • the HOST CPU 11 issues an item to the hardware chip, the storage location of each entry may be determined.
  • the on-chip SRAM of the hardware chip usually has a small capacity and the number of items that can be stored is relatively small.
  • the HOST CPU 11 can keep a copy of the entry of the entry of the SRAM that is sent to the hardware chip in the HOST RAM. If the number of entries of the off-chip SDRAM of the hardware chip can be stored, the HOST CPU 11 can also store the copy of the entry in the HOST. In RAM. In this way, the above-mentioned table entry verification method can also be used to compare the to-be-checked entry in the SDRAM with the copy of the entry.
  • the verification method of comparing the check item to the copy of the table item can also be applied to other examples.
  • the host processor 11 delivers an entry to the on-chip SRAM of multiple hardware chips
  • the entries in the on-chip SRAM of each hardware chip can be compared with the HOST RAM of the host processor 11 during verification. A copy of the table entry is compared.
  • the HOST RAM can use the ECC mechanism to verify the reference entries. In this way, if a single BIT error occurs in the HOST RAM entry, it can be repaired by ECC. If two BIT errors occur, it can be detected by the hardware and repaired by the HOST CPU, so that all entries in the ECC-protected HOST RAM can be guaranteed. correct. Since only one ECC module that requires hardware space can be set, the method can not only ensure the reliability of the entries in the data communication device, but also save hardware space. For another example, two or more entries may be reserved in the HOST RAM, and the entries may be considered reliable when multiple copies of the same entry are consistent.
  • the method for verifying the entry in FIG. 4 is also a method for comparing the reference data entry used in FIG. 3, and the difference is that the application scenario is different.
  • the hardware chip may have a plurality of off-chip memories, such as a plurality of SDRAMs. Due to limitations in capacity, board area, etc., error correction mechanisms (such as ECC protection) may not be configured for each SDRAM, but ECC protection may be performed for one of the SDRAMs.
  • ECC-protected SDRAM can be referred to as a reference off-chip memory, and the entries stored in the reference off-chip memory can be considered to be correct.
  • a data table tbl_d' may be stored in the reference off-chip memory 14, and the data table tbl_d' may store a reference entry (a copy of the entry).
  • the to-be-checked entry (i.e., application entry) stored in the data table tbl_d of the other off-chip memory can be compared with the reference entry in the data table tbl_d'.
  • the data table tbl_d is stored in the SDRAM 15, and the data table tbl_d contains an application table entry.
  • the application table entry in the data table tbl_d can be compared with the reference entry in the data table tbl_d' stored in the reference off-chip memory 14. If the two are consistent, it indicates that the application table entry in the data table tbl_d is correct.
  • the SDRAM 16 stores a data table tbl_e, and the data table tbl_e includes an application entry.
  • the application table entry in the data table tbl_e can be compared with the reference data entry included in the data table tbl_e' stored in the reference off-chip memory 14. If the two are consistent, it indicates that the application table entry in the data table tbl_e is correct.
  • the off-chip memory of the hardware chip such as SDRAM
  • methods for copying entries in a bank can be used to increase access bandwidth.
  • the method of copying an entry in a bank may include storing one entry in each of the plurality of banks. In the case of normal entries, the same The contents of the entries in the respective banks are the same.
  • the method shown in FIG. 4 can be used to store a multi-bank copy entry in the reference off-chip memory 14 as well.
  • the check is stored in the reference off-chip memory 14 as a reference entry, and compared with the application entries corresponding to the reference entry stored in the plurality of banks in the other off-chip memories 15, 16.
  • the application table items stored in the SDRAM 15 form the data table tbl_d, and multi-bank copying is performed in the SDRAM 15.
  • a data table tbl_d' formed by the reference entry is stored in the bank of the reference off-chip memory 14.
  • the reference entry in the data table tbl_d' can be compared with the application entry corresponding to the reference entry in the data table tbl_d of each bank of the SDRAM 15. If the comparison result is the same content, it can be confirmed that the application table item in the data table tbl_d is correct.
  • the reference entry may be an entry protected by a mechanism such as ECC, thereby ensuring the correctness of the reference entry. Moreover, by comparing the reference entry with the application entry, it is possible to determine whether the application entry is correct or not. In this way, one of the entries is protected by technologies such as ECC, and the entries stored in other locations do not need to be protected. Therefore, although the protection of the reference entry occupies part of the hardware resources, the consumption of hardware resources can be significantly reduced compared to the mechanism in which all entry storage is ECC protected. The part of the hardware resources occupied by the protection of the reference entry may be the space occupied by the ECC on the board. The saved hardware resources can be used for more efficient use, for example, it can be used to arrange more hardware chips to store more entries, thereby improving the utilization of hardware resources.
  • a mechanism such as ECC
  • the abnormal application entry may be further repaired. Because the baseline entry is correct, you can use this baseline entry to fix anomalous entries. For example, if the application table entry is abnormal when the reference entry in the HOST RAM is compared with the application entry in the SRAM, the application entry in the SRAM can be updated using the reference entry in the HOST RAM. For another example, in the example of FIG. 4, when the reference entry in the off-chip off-chip memory 14 is compared with the application entry in the other off-chip memories 15, 16, if it is determined that the application entry is abnormal, it can be used. The reference entry in the reference off-chip memory 14 protected by the ECC updates the abnormal application entry.
  • the entry verification method of the example of the present disclosure may also apply another method of checking the entries, that is, comparing multiple copies of the entry to be verified to determine multiple copies of the entry to be verified. Whether the contents of the duplicate entry are the same. If the contents of the multiple replicated entries are the same, you can determine that the entry is correct; otherwise, you can determine that the entry is abnormal.
  • Multiple copies of the entries herein may include a plurality of types. For example, it may be a duplicate entry located on the on-chip memory of at least two hardware chips. Assuming that an entry is stored on the on-chip SRAM of two FPGA chips, two entries in the two FPGA chips can be referred to as two replicate entries of the entry. You can compare the two replicated entries. If the content of the two items is consistent, the entry is normal. If the content is inconsistent, the entry is abnormal.
  • the multiple copy entries may also be duplicate entries in multiple banks located in the off-chip memory.
  • the bank is distributed in at least one hardware chip for using the item to be checked.
  • the bank copy entry is a way to improve the access speed of the SDRAM, that is, the same entry is duplicated in multiple banks.
  • the multiple copy entries described in this example may be multiple copies of an entry that are replicated in multiple banks in one SDRAM of an FPGA, or may be that the entry is under two FPGAs. Multiple copies of duplicate entries in multiple banks in SDRAM, and so on. The duplicate entries in the banks are compared. If the contents of the multiple replicated entries are the same, the entries to be verified corresponding to the multiple replicated entries are considered correct.
  • An example of copying multiple bank entries in an SDRAM is used to compare the multiple replicated entries of the table to be verified.
  • the to-be-checked entry stores one entry in each of the two banks, that is, the to-be-checked entry has two duplicate entries.
  • the duplicate entries stored in the two banks may be compared. If the duplicate entries in the two banks are the same, it can be determined that the checksum entry is correct; otherwise, the checksum entry is abnormal.
  • the HOST CPU can be reported to the HOST CPU for device restart or active/standby switchover, so that the network can be restored as soon as possible.
  • this example also provides a simple verification method for three or more banks, that is, a comparison counter method.
  • the multi-bank comparison algorithm is not limited to the comparison counter method, and other multiple data comparison algorithms can also be applied to the check of the entry.
  • Table 1 duplicate entries and corresponding comparison counters
  • each comparison counter corresponding to these duplicate entries When performing table check, first set the value of each comparison counter corresponding to these duplicate entries to zero, and then Each replicated entry is compared in pairs with other replicated entries. If it is determined that the two data entries are different, the values of the comparison counters corresponding to the two data entries are respectively incremented by one. When the pairwise comparison ends, if the value of each comparison counter has a non-zero value, it may be determined that there are exception entries in the at least three data entries.
  • the comparison can be continued.
  • data1 can be compared with data2 and data3 in sequence, and data2 is compared with data3 (that is, all data are compared in pairs, and four data are compared in six times).
  • the value of all comparison counters may be greater than or equal to 1.
  • the comparison counter method it is possible to detect that several entry exceptions have occurred in multiple replication entries in multiple banks. In this example, you can also repair the abnormal entries. For example, when there are three or more banks, through the above comparison counter method, if it is determined that an entry exception occurs, the copy table with the smallest comparison counter value may be used to copy the table with the largest comparison counter value. Item is fixed. For example, above In the example, the data2 corresponding to counter2 is repaired by the data0 corresponding to counter0. If it is determined that at least two duplicate entries have occurred, it may not be repairable.
  • the location information (for example, the location of data2 corresponding to bank2) and the information about whether the repair is abnormal may be reported to the HOST CPU for processing. Even if an abnormal entry has been fixed, the location information and the repair status of the exception entry can be reported.
  • one or more data consistency judgments may be attached. For example, if the data consistency check is performed for a preset number of times, the data to be checked does not meet the data consistency. This is because if the check item is considered to be abnormal when it is considered that the check item to be checked does not satisfy the data consistency, it may be a false positive. For example, at the moment when the item is published under the control level, the contents of the HOST RAM and the contents of the SRAM, or the contents of multiple banks in the SDRAM may be inconsistent. The misjudgment caused by such inconsistency can be prevented by successive M-checks.
  • the mechanism of continuous M-checking can also be applied to compare the reference entry and the application entry, compare between the two banks, and the like. For example, after comparing the at least two entries, record the number of times the at least two entries are inconsistent. When the number of times is greater than the preset number of times, it may be determined that an abnormal entry occurs in the at least two entries.
  • the entry verification method of the present disclosure may all be implemented as a software detection method performed by the HOST CPU.
  • the detection of the SDRAM (for example, comparison of entries between two or more banks) may be implemented in a hardware chip 12 (eg, a chip such as an FPGA or an NPU).
  • the HOST CPU 11 can be notified of the location information and the repair information about the exception entry only when the table entry abnormality is detected, thereby reducing the load of the HOST CPU 11.
  • the method for verifying the entry of the present disclosure is to perform data consistency check on the entire entry. Through the overall comparison of the entries, for example, comparing the entire contents of the application entry with the entire contents of the reference entry, whether it is single-bit, two-bit, or multiple-bit, the entry exception may be determined as long as the data consistency is not satisfied.
  • the checksum of the entry can be used to find the exception entry as soon as possible when the entry is abnormal. You can also modify the exception entry under certain conditions. For example, it can be fixed with a reference entry.
  • the method for verifying the entry of the present disclosure may be a software detection method, as long as the entry of the corresponding location is read according to the method of the present application for comparison, and whether the entry is abnormal according to the comparison result is determined. Therefore, the check method of the entry does not occupy or seldom occupy hardware resources, and can effectively improve the utilization of hardware resources.
  • the verification of all the entries may be completed in multiple times. For example, partial entries may be periodically compared until all entries in the data communication device to be protected are compared. If the number of entries is small, the check of all the entries can be completed at one time.
  • a periodic timer can be started corresponding to each of the SRAM and the SDRAM, and each of the C1 and C2 entries is detected in each cycle.
  • the detection is to perform data consistency judgment on these entries, and the detection of each entry can be performed according to the above-mentioned table entry verification method. If the C1 and C2 entries are found to meet the data consistency, it can be determined that none of the entries are abnormal. The detection is complete.
  • the entry check logic in the data communication device shown in FIG. 2, as shown in FIG. 5, may include an entry delivery module 51 and an entry comparison module 52.
  • the entry issuance module 51 is configured to send at least two items with the same content to the hardware chip in the data communication device.
  • the entry comparison module 52 is configured to determine an abnormal entry in the at least two entries that are sent to the hardware chip by comparing the at least two entries that are sent to the hardware chip.
  • the at least two identical entries include a reference entry and an application entry.
  • the entry issuance module 51 is configured to send the reference entry to the first hardware chip, and send the application entry to the second hardware chip; the entry comparison module 52 The application entry that is sent to the second hardware chip is verified according to the reference entry that is sent to the first hardware chip, and if the verification result is consecutive N times, the verification result is sent to the The application data entry of the second hardware chip is different from the content of the reference data entry that is sent to the first hardware chip, and the application entry is determined to be an abnormal entry.
  • the entry verification logic in the data communication device shown in FIG. 2 may further include a first entry repair module 53 for determining the second hardware chip.
  • the application entry is an exception entry
  • the application entry of the second hardware chip is repaired by the reference entry of the first hardware chip.
  • the entry issuance module 51 is further configured to deliver at least three entries of the same content to at least three banks in the hardware chip.
  • the entry comparison module 52 is further configured to perform a pairwise comparison between the at least three entries that are delivered to at least three banks. If it is determined that the two entries are inconsistent, the entry comparison module 52 adds 1 to the value of the comparison counter corresponding to the two entries. When the pairwise comparison ends, if the value in each comparison counter has a non-zero value, the entry comparison module 52 determines that there is an exception entry in the at least three entries.
  • the entry verification logic in the data communication device shown in FIG. 2 may further include a second entry repair module 54 for determining that the entry with the largest comparison counter value is an exception entry. And repair the exception entry by comparing the entry with the smallest counter value.
  • the functions, if implemented in the form of software functional units and sold or used as separate products, may be stored in a machine readable storage medium.
  • a machine readable storage medium including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like.
  • the present disclosure item verification logic can be understood as machine executable instructions stored in a first storage medium of the processor.
  • the processor on the data communication device of the present disclosure executes the entry verification logic, the processor performs the following operations by invoking an instruction corresponding to the entry verification logic saved on the first storage medium: sending at least the hardware chip Determining an error in the at least two data items sent to the hardware chip by comparing the two data items that are identical in content to the hardware chip by comparing the at least two data entries that are sent to the hardware chip Exception table entry.
  • the machine executable instructions may cause the processor to: issue a reference to a first hardware chip in the data communication device a data item; the application data entry that is the same as the content of the reference data entry is delivered to the second hardware chip in the data communication device.
  • the machine executable instructions may cause the processor to: be issued to the first hardware chip
  • the reference data entry verifies the application data entry that is sent to the second hardware chip; if the verification result is N consecutive times, the application data entry sent to the second hardware chip is The content of the reference data entry that is sent to the first hardware chip is different, and the application data entry is determined to be an abnormal entry, where N is an integer greater than 1.
  • machine executable instructions may further cause the processor to: when determining that the application data entry that is sent to the second hardware chip is an exception entry, according to being sent to the first hardware chip The reference data entry repairs the application data entry that is delivered to the second hardware chip.
  • the machine executable instructions may also cause the processor to: to the data communication device At least three of the hardware chips At least three data entries with the same content are delivered in the banks.
  • the machine executable instructions may also cause the processor to: deliver to the at least three banks The value of each comparison counter corresponding to the at least three data entry items is set to 0; and the two data entries that are mutually inconsistent among the at least three data entries in the at least three banks are delivered The values of the corresponding comparison counters are incremented by one; when the paired data is counted to the end of the pairwise comparison of the at least three data entries in the at least three banks, if the value in each of the comparison counters has a non-zero value, then it is determined An exception entry exists in the at least three data entry items that are delivered to the at least three banks.
  • the machine executable instructions may further cause the processor to: determine that the data entry that compares the counter value is the largest is an exception table entry; and the exception entry is compared according to the data entry with the smallest comparison counter value Make corrections.
  • the hardware chip in the data communication communication device of the present disclosure may include a second storage medium, and the second storage medium may include partial entry verification logic.
  • the hardware chip can read and execute the machine corresponding to the item check logic in the second storage medium Executing instructions to: set a value of each comparison counter corresponding to the at least three data entry items sent to the at least three banks to 0; to be delivered to the at least three banks
  • Executing instructions to: set a value of each comparison counter corresponding to the at least three data entry items sent to the at least three banks to 0; to be delivered to the at least three banks
  • the values of the comparison counters corresponding to the two data entries that are inconsistent with each other in the at least three data entries are incremented by one; when the data is sent to the at least three data entries in the at least three banks At the end of the comparison, if there is a non-zero value in the value of each of the comparison counters, it is determined that an abnormal entry exists in the at least three data entries that are delivered to the at least three banks.
  • the machine executable instructions may further cause the hardware chip to: determine that the data table item having the largest comparison counter value is an exception table entry; and the abnormal table entry according to the data entry with the smallest comparison counter value Make corrections.
  • the relevant parts can be referred to the description of the method embodiment.
  • the logical embodiments described above are merely illustrative, and the components displayed as units may or may not be physical units, ie may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without any creative effort.

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Abstract

一种表项校验方法，该方法应用于数据通信设备中，包括：向所述数据通信设备中的硬件芯片（12）下发至少两条内容相同的数据表项；通过比较下发至所述硬件芯片（12）的所述至少两条数据表项，可确定下发至所述硬件芯片（12）的所述至少两条数据表项中的异常表项。

Description

表项校验
相关申请的交叉引用
本专利申请要求于2016年4月26日提交的、申请号为201610267964.1、发明名称为“一种表项校验方法和装置”的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
背景技术
在数据通信设备(例如，交换机、路由器等)中，通常是由控制层面生成数据表项，并将表项下发到硬件芯片。然后，由硬件芯片根据该数据表项进行数据层面的数据包处理。硬件芯片使用的表项可以存储在片内SRAM(Static Random Access Memory，静态随机存取存储器)，也可以存储在片外DDR SDRAM(Double Data Rate Synchronous Dynamic Random Access Memory，双倍速率同步动态随机存储器，简称：SDRAM)。由于SRAM容易受到宇宙射线或其他高能粒子的影响，使得存储在表项中的内容发生变化。而SDRAM采用电容存储表项，需要不断对电容充电以维持表项内容不变，如果充电刷新过程中受到干扰，也可能发生表项内容错误。
一般来说，SRAM和SDRAM存储的表项内容出错是小概率事件。可是，一旦SRAM和SDRAM存储的表项内容出错，数据通信设备将按照错误的表项处理数据包。这可能无法满足对数据通信设备的可靠性要求。因此，需要通过表项校验，及时发现SRAM和SDRAM中的表项错误。
附图说明
图1是本公开一示例提供的一种数据通信设备的应用系统架构；
图2是本公开另一示例提供的一种数据通信设备的实体结构示意图；
图3是本公开一示例提供的一种表项校验方法的流程图；
图4是本公开一示例提供的一种表项校验方法的原理示意图；
图5是本公开一示例提供的一种表项校验逻辑的功能模块框图；
图6是本公开另一示例提供的一种表项校验逻辑的功能模块框图。
具体实施方式
下面将结合本公开示例中的附图，对本公开示例中的技术方案进行清楚、完整地描述，显然，所描述的示例仅仅是本公开的一部分示例，而不是全部的示例。基于本公开中的示例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他示例，都属于本公开保护的范围。
数据通信设备可以通过ECC(Error Correcting Code，错误检查和纠正)、EDAC(Error Detection And Correction，错误检测与纠正)等技术来确定是否有异常表项。但是，这种错误发现方式需要占用额外的硬件资源，比如占用片内SRAM资源或者SDRAM颗粒，从而可降低硬件资源利用率。根据本公开一示例提供了一种表项校验方法，该方法可以应用于交换机、路由器等数据通信设备，以判断表项是否异常，从而能够在发现异常表项时尽快修正，保障数据通信设备的可靠性。如图1所示，示例了一种数据通信设备中的应用系统架构。在该数据通信设备中可以包括主机处理器(HOST CPU)11、一个或多个硬件芯片12。例如，硬件芯片12可以是FPGA(Field－Programmable Gate Array，现场可编程门阵列)、NPU(Network Processing Unit，网络处理器)等芯片。主机处理器11与硬件芯片12之间可以通过PCI-E(Peripheral Component Interface Express，总线和接口标准)总线连接。
主机处理器11可以将控制层面生成的数据表项下发至硬件芯片12，由硬件芯片12根据该数据表项在数据层面执行数据包处理，例如，转发数据包。下发的这些数据表项可以存储在硬件芯片12的片内存储器，例如SRAM，也可以存储在硬件芯片12的片外存储器，例如DDR SDRAM(可以简称：SDRAM)。不论存储在片内或片外，硬件芯片12都可以利用这些数据表项进行数据包处理。如图1所示，本公开示例的主机处理器11在向硬件芯片12下发数据表项时，可以下发至少两条相同的数据表项。该至少两条相同的数据表项可以存储于同一硬件芯片12，也可以存储于不同的硬件芯片12。例如，图1中所示的至少两条相同的数据表项可以分别存储于两个硬件芯片12，向硬件芯片12中下发的多条数据表项可以形成数据表。
本公开示例的表项校验方法主要用于对主机处理器11向硬件芯片12下发的数据表项(可以简称为表项)进行校验，以检测表项是否发生异常。并且，由于是以软件检测的方式来实现对表项的校验，该方法与ECC、EDAC等技术相比可降低对硬件资源的消耗。所述硬件资源可以是片内SRAM资源、SDRAM颗粒或者单板上的空间。可以参见图2的示例，该软件检测方式可以是当主机处理器11运行表项检测时的算法流程，实现对表项的校验。图2示出了一种数据通信设备的实体结构图。该数据通信设备可包括处理器21、通信总线22、机器可 读存储介质23及通信接口24。该设备中的处理器21可以是图1所示的主机处理器11，也可以是SDN(Software Defined Network，软件定义网络)控制器，该处理器21可以执行机器可读存储介质23中存储的表项校验逻辑对应的机器可执行指令来实现表项校验方法。
如下对该表项校验方法进行说明。该方法可对下发至数据通信设备的硬件芯片的至少两条内容相同的表项进行比较，当所述至少两条内容相同的表项中的内容不一致时，该方法可以确定该至少两条表项中存在异常表项。如果上述的至少两条内容相同的表项之间满足数据一致性，则可确定至少两条内容相同的表项正确；否则，可确定至少两条表项中存在异常表项。该“数据一致性判断”可以包括多种方面。例如，假设某一表项是正确的，该“数据一致性判断”可以是判断待校验的表项与该正确的表项的内容是否相同。或者，还可以是判断存储在不同位置的多份待校验表项的内容是否相同。后续将通过多个例子来进行描述。
在下面的例子中，如图1所示，以对其中一个表项进行校验为例，来说明多种表项校验方法的应用。应能理解，各个待校验表项都可以使用下面的方法进行校验。
HOST CPU 11可以向一个硬件芯片12下发第一表项。该第一表项可以存储在硬件芯片12的片内SRAM作为后述比较数据一致性时的待校验表项。HOST CPU 11还可以向HOST CPU 11的DDR SDRAM(简称：HOST RAM，主机处理器的片外存储器)中发送一份内容与该第一表项相同的第二表项作为后述比较数据一致性时的表项副本。该HOST RAM可以是图1中的另一个硬件芯片12。需要说明的是，表项副本和待校验表项实际上有相同的内容，仅是从名称上进行区分。在本例子中，可以将待校验表项称为应用表项，将表项副本称为基准表项。并且，可以将接收基准表项的硬件芯片12称为第一硬件芯片，将接收应用表项的硬件芯片12称为第二硬件芯片。
图3示例了一种表项校验方法的流程图。该流程图描述的是上面提到的将应用表项和基准表项进行比较来判断应用表项是否异常的方法。在步骤301中，可以根据基准表项校验应用表项。在步骤302中，可判断基准表项和应用表项的内容是否相同。可将基准表项作为校验的基准，并将应用表项与该基准表项的内容进行比较，以确定应用表项是否出错。如果两者相同，则可确定两个表项满足数据一致性，并在步骤303中确定应用表项正确；否则，可确定两个表项不满足数据一致性，从而在步骤304中确定应用表项是异常表项。此外，需要说明的是，HOST CPU 11在向硬件芯片下发表项时，每个表项的存储位置可以是确定的。
如上的例子中，硬件芯片的片内SRAM通常容量较小，可存储的表项数量相对较少。HOST CPU 11可以在HOST RAM中保留下发至硬件芯片的SRAM的表项的表项副本。如果硬件芯片的片外SDRAM可存储的表项数量较少时，也可以由HOST CPU 11存储表项副本在HOST  RAM中。这样，也可采用上述表项校验方法，将SDRAM中的待校验表项与表项副本进行比较。
此外，这种将待校验表项与表项副本进行比较的校验方式，还可以应用于其他例子。比如，当主机处理器11将某个表项下发至多个硬件芯片的片内SRAM时，每个硬件芯片的片内SRAM中的表项在校验时都可以与主机处理器11的HOST RAM中的表项副本进行比较。
在本例子中，为了进一步保证基准表项的正确性，可以对基准表项采用一些保护机制。例如，HOST RAM可采用ECC机制以校验基准表项。这样，HOST RAM中的表项如果出现单BIT错误可以通过ECC修复，如果出现两BIT错误可以通过硬件检测出来并通过HOST CPU进行修复，从而可以保证经过ECC保护的HOST RAM中的所有表项是正确的。由于可以仅设置一个需要占用硬件空间的ECC模块，该方法不仅可以保证数据通信设备中的表项可靠，还可以节省硬件空间。又例如，还可以在HOST RAM中保留两份或更多份表项，当相同表项的多份拷贝都一致时可认为该表项可靠。
图4示意的表项校验方法，也是应用图3中使用的与基准数据表项进行比较的方式，不同点在于应用场景不同。如图4所示，硬件芯片可能多个片外存储器，比如多个SDRAM。由于容量、单板面积等限制，可以不为每个SDRAM均配置纠错机制(如ECC保护)，但是可以针对其中一个SDRAM进行ECC保护。这样，该被ECC保护的SDRAM可以称为基准片外存储器，基准片外存储器中存储的表项可以认为都是正确的。
在图4中，基准片外存储器14中可以存储数据表tbl_d’，该数据表tbl_d’可存储基准表项(表项副本)。存储在其他片外存储器的数据表tbl_d中的待校验表项(即应用表项)可以与数据表tbl_d’中的基准表项进行比较。
例如，假设SDRAM 15中存储有数据表tbl_d，该数据表tbl_d中包含应用表项。可以将数据表tbl_d中的应用表项与基准片外存储器14存储的数据表tbl_d’中的基准表项进行比较。若两者一致，则表明数据表tbl_d中的应用表项正确。
又例如，SDRAM 16中存储有数据表tbl_e，该数据表tbl_e中包含有应用表项。可以将数据表tbl_e中的应用表项与基准片外存储器14存储的数据表tbl_e’中包含的基准数据表项进行比较。若两者一致，则表明数据表tbl_e中的应用表项正确。
此外，假设硬件芯片的片外存储器例如SDRAM的容量在几十G字节数量级，可存放的表项较多。通常，可采用在bank(数据通道)中复制表项的方法来提高访问带宽。在bank中复制表项的方法可以包括在多个bank中分别存储一份表项。在表项正常的情况下，同一个 表项在各个bank中的内容是相同的。本例子中，可以采用图4所示的方法，将多bank复制的表项在基准片外存储器14中也存储一份。这样，校验时以该基准片外存储器14中存储的表项作为基准表项，与其他片外存储器15、16中的多个bank中存储的与该基准表项对应的应用表项进行比较，以判断各个bank中的应用表项与基准表项是否相同。例如，SDRAM 15中存储的应用表项形成数据表tbl_d，并且在SDRAM 15中进行了多bank复制。基准片外存储器14的bank中存储有一份由基准表项形成的数据表tbl_d’。可以将数据表tbl_d’中的基准表项与SDRAM 15的各个bank的数据表tbl_d中的对应该基准表项的应用表项进行比较。若比较结果为内容相同，则可确认数据表tbl_d中的应用表项正确。
如图4所示，将应用表项与基准表项比较的例子中，基准表项可以是采用ECC等机制进行保护的表项，从而可以确保基准表项的正确性。并且，通过将基准表项与应用表项进行比较，就可以确定应用表项的正确与否。这种方式，相当于将其中一份表项用ECC等技术保护，其他位置存储的表项不需要保护。因此，尽管基准表项的保护占用了部分硬件资源，但与所有表项存储器都进行ECC保护的机制相比，可显著减少硬件资源的消耗。基准表项的保护占用的部分硬件资源可以是在单板上ECC占用的空间。而节省下来的硬件资源可以用于更有效的使用，比如，可以用于布置更多的硬件芯片以存储更多的表项，从而可提高对硬件资源的利用率。
在另一个例子中，将应用表项与基准表项进行比较的校验方式中，如果校验结果确定应用表项异常，还可以进一步对异常的应用表项进行修复。由于基准表项是正确的，可以使用该基准表项修复异常的表项。例如，如果将HOST RAM中的基准表项与SRAM中的应用表项比较时，确定应用表项异常，则可以使用HOST RAM中的基准表项更新SRAM中的应用表项。又例如，在图4的例子中，当将基准片外存储器14中的基准表项与其他片外存储器15、16中的应用表项比较时，如果确定所述应用表项异常，则可以使用被ECC保护的基准片外存储器14中的基准表项更新该异常的应用表项。
本公开示例的表项校验方法还可应用另一种表项校验的方式，即在待校验表项的多份复制表项之间进行比较，以判断待校验表项的多份复制表项的内容是否相同。如果这多份复制表项的内容都相同，则可确定该表项正确；否则，可确定该表项异常。这里的多份复制表项可以包括多种。例如，可以是位于至少两个硬件芯片的片内存储器上的复制表项。假设某个表项在两个FPGA芯片的片内SRAM上都有存储，可以将这两个FPGA芯片中的两个表项称为该表项的两份复制表项。可以将这两份复制表项进行比较。如果两者内容一致可认为该表项正常，如果不一致则可说明该表项异常。
又例如，多份复制表项也可以是位于片外存储器的多个bank中的复制表项。该bank分布于至少一个用于使用待校验表项的硬件芯片中。其中，在bank复制表项是一种用于提高SDRAM访问速度的方式，即将同一个表项在多个bank中分别复制一份。本例子中所述的多份复制表项，可以是某个表项在一个FPGA的一个SDRAM中的多个bank中复制的多份复制表项，还可以是该表项在两个FPGA下的SDRAM中的多个bank中复制的多份复制表项，等。将这些bank中的复制表项进行比较，如果多份复制表项的内容相同，则认为该多份复制表项对应的待校验表项正确。
以一个SDRAM中的多个bank复制的表项为例来介绍在待校验表项的多份复制表项之间进行比较。
在一个例子中，假设该SDRAM中有两个bank，待校验表项在这两个bank中各存储一份表项，即待校验表项具有两个复制表项。在对该待校验表项进行校验时，可以将分别存储于这两个bank中的复制表项进行比较。如果这两个bank中的复制表项相同，则可确定该待校验表项正确；否则，可说明该待校验表项发生了异常。在该例子中，当检测到发生表项异常时，可以上报HOST CPU，以便HOST CPU进行设备重启或者进行主备倒换，从而可使网络尽快恢复正常。
在另一个例子中，假设该SDRAM中有三个或三个以上的bank。这种情况下，也可以使用上述的将各个bank之间的内容进行比较的方法来确定表项是否正确。此外，本例子还提供了对于三个以上bank的简易校验方法，即比较计数器法。但是，多bank比较算法不局限于比较计数器法，其它多份数据比较算法也可以应用于该表项校验中。
以一个例子来说明比较计数器法的应用。以四个bank复制的表项为例。假设data0、data1、data2、data3是同一个表项分别存储在bank0、bank1、bank2、bank3中的数据，那么这四个数据data0、data1、data2、data3可以称为该表项的四个复制表项。为每个复制表项分别设置一个对应的比较计数器counter，如下表1所示，counter n(n＝0、1、2、3)。
表1复制表项与对应的比较计数器
bank0 bank1 bank2 bank3
data0 data1 data2 data3
counter0 counter1 counter2 counter3
在进行表项校验时，先将这些复制表项对应的各个比较计数器的数值设置为零，然后将 每个复制表项与其他复制表项进行成对比较。若确定两个数据表项不相同，则分别对所述两个数据表项对应的比较计数器的数值加一。当成对比较结束时，如果各个比较计数器的数值存在非零值，则可确定该至少三个数据表项中存在异常表项。
例如，以表1中的counter0为例。将data0依次与data1、data2、data3进行比较，并在比较结果指示其中两个数据不一致时使对应的比较计数器加一。假设data0、data1、data3是正确的数据，而data2是异常的数据。那么按照上述的原则，在data0依次与data1、data2、data3比较时，只有data0与data2不一致，则data0对应的counter0加1，并因此等于1；同时，data2对应的counter2也加1，并因此等于1。
如果经过上述的三次比较，即data0依次与data1、data2、data3比较后，四个比较计数器的数值都为0，则可确定这四个bank的表项都正确，本次校验结束。
如果三次比较结果至少出现一次不一致时，比如上面的例子中，假设data2错误时，counter0和counter2的数值为1，counter1和counter3为零，则此时可继续比较。例如，可将data1依次与data2、data3进行比较，data2与data3进行比较(即所有数据进行两两比较，四条数据共进行六次比较)。当两两比较结束时，所有比较计数器的数值可能都大于等于1。仍以上述data2错误的例子，比较结束后，各个比较计数器的数值为：counter0＝1，counter1＝1，counter2＝3，counter3＝1。即这多份复制表项对应的比较计数器的数值不相等，包括大于一和等于一的数值。这种情况下，可认为这四个bank对应的数据表项中至少一个出现异常。
进而可以根据比较计数器所记录的数值确定可能出现异常的表项。因为进行成对比较，每次在将异常表项和其他表项比较时对应该异常表项的计数器都会进行计数，可以理解异常表项是counter的数值最大的表项。比如，在上面的例子中，counter0＝1，counter1＝1，counter2＝3，counter3＝1。从比较计数器的数值来看，counter2的数值为3，而其他counter的数值为1。由于counter2的数值最大，可以理解为counter2对应的复制表项data2就是异常表项。
另外，可以根据比较计数器的数值中的最小值来判断多个bank的复制表项中有几个出现异常。如上述比较计数器的最小值为1，则可说明四个复制表项中有一个出现了异常。如果比较计数器的最小值大于1，则可说明多个复制表项出现异常。
由上述的描述可以看到，利用比较计数器的方法，可以检测到在多个bank中多个复制表项发生了几份表项异常。本例子中，还可以对异常的表项进行修复。例如，当有三个或三个以上的bank时，通过上述的比较计数器的方法，如果确定发生了一份表项异常，则可用出现比较计数器数值最小的复制表项对比较计数器数值最大的复制表项进行修复。比如，在上面 的例子中，用counter0对应的data0修复counter2对应的data2。而如果确定发生了至少两份复制表项异常，则可能是不可以修复的。这时，可以将检测到复制表项异常的位置信息(比如，bank2对应的data2的位置)、以及是否修复的信息上报HOST CPU进行处理。即使已经修复了异常的表项，也可以将关于异常表项的位置信息和修复情况上报。
在确定待校验表项发生异常时，为了使得判断结果更加准确，可以附加一次或者多次数据一致性判断。例如，若经过连续的预设次数的数据一致性判断，待校验表项均不满足数据一致性，则确定待校验表项异常。这是因为，如果在一次校验认为待校验表项不满足数据一致性时就认为待校验表项异常，有可能是误判。比如，控制层面下发表项的瞬间，HOST RAM中的表项内容与SRAM中的内容，或者SDRAM中多个bank间的内容可能是不一致的。通过连续M次校验可以防止这种不一致导致的误判。连续M次校验的机制同样可以适用于基准表项和应用表项进行比较、两个bank之间进行比较等。例如，在比较所述至少两条表项之后，记录所述至少两条表项不一致的次数。当所述次数大于预设次数时，可确定所述至少两条表项中出现了异常表项。
此外，本公开的表项校验方法可以全部实现为由HOST CPU执行的软件检测方式。或者，还可以将SDRAM的检测(比如，两个或更多bank之间的表项比较)在硬件芯片12(如，FPGA或NPU等芯片)中实现。当在硬件芯片12实现时，可以只在检测到表项异常时才将关于异常表项的位置信息和修复信息通知HOST CPU 11，从而减轻HOST CPU 11的负载。
本公开的表项校验方法，是对表项整体进行数据一致性校验。通过表项整体比较，比如，将应用表项的全部内容与基准表项的全部内容进行比较，不论是单bit、两bit或者多bit，只要不满足数据一致性就可以确定表项异常。
该表项校验方法不仅可以在表项出现异常时尽快的发现异常表项，还可以在一定情况下修正异常表项。比如，可用基准表项修复。此外，本公开的表项校验方法可以是一种软件检测方法，只要按照本申请的方法读取相应位置的表项进行比较，根据比较结果判断表项是否出现异常。因此，该表项校验方法不会占用或很少占用硬件资源，可以有效提高硬件资源的利用率。
在一个例子中，如果数据通信设备中要保护的表项数量比较多，可以分多次完成对所有表项的校验。例如，可周期性地比较部分表项，直至比较完成该数据通信设备中要保护的所有表项。如果表项数量较少，也可以一次完成所有表项的校验。
例如，假设SRAM中有三个表T10、T11、T12，分别存储有E10、E11、E12个表项。那 么总的表项个数就是(E10+E11+E12)。假设需要在N1秒钟完成一次SRAM中的所有表项检测，而定时器的时间间隔是S1毫秒，那么每次可检测的表项个数约为C1＝((E10+E11+E12)*S1)/(1000*N1)。
又例如，假设SDRAM中总共有三个表T20、T21、T22，分别存储有E20、E21、E22个表项。那么总的表项个数就是(E20+E21+E22)。假设需要在N2秒钟完成一次SDRAM中的所有表项检测，而定时器的时间间隔是S2毫秒，那么每次可检测的表项个数约为C2＝((E20+E21+E22)*S2)/(1000*N2)。
可以对应SRAM和SDRAM各启动一个周期性的定时器，每个周期分别检测C1和C2个表项。该检测为对这些表项进行数据一致性判断，每个表项的检测都可以按照上述的表项校验方法进行。如果在检测时发现该C1和C2个表项都满足数据一致性，则可以确定这些表项都没有发现异常，是正确的，本次检测结束。
从功能上划分，图2所示的数据通信设备中的表项校验逻辑，如图5所示，可以包括表项下发模块51和表项比较模块52。其中，表项下发模块51，用于向所述数据通信设备中的硬件芯片下发至少两条内容相同的表项。表项比较模块52，用于通过比较下发至所述硬件芯片的所述至少两条表项，来确定下发至所述硬件芯片的所述至少两条表项中的异常表项。
在一个例子中，所述至少两条相同的表项包括基准表项和应用表项。在这种情况下，所述表项下发模块51可用于向第一硬件芯片下发所述基准表项，并向第二硬件芯片下发所述应用表项；所述表项比较模块52可用于根据下发至所述第一硬件芯片的所述基准表项校验下发至所述第二硬件芯片的所述应用表项，若连续N次的校验结果表示下发至所述第二硬件芯片的所述应用数据表项与下发至所述第一硬件芯片的所述基准数据表项内容不相同，则确定所述应用表项为异常表项。
在一个例子中，参见图6，从功能上划分，图2所示的数据通信设备中的表项校验逻辑还可以包括第一表项修复模块53，用于当确定所述第二硬件芯片的所述应用表项为异常表项时，通过所述第一硬件芯片的所述基准表项修复所述第二硬件芯片的所述应用表项。
在一个例子中，所述表项下发模块51还可用于分别向所述硬件芯片中的至少三个bank中下发内容相同的至少三条表项。所述表项比较模块52还可用于在下发至至少三个bank中的所述至少三条表项之间进行成对比较。若确定两个表项不一致，则所述表项比较模块52分别对所述两个表项对应的比较计数器的数值加1。当成对比较结束时，若各比较计数器中的数值存在非零值，则所述表项比较模块52确定所述至少三个表项中存在异常表项。
在一个例子中，从功能上划分，图2所示的数据通信设备中的表项校验逻辑还可包括第二表项修复模块54，用于确定比较计数器数值最大的表项为异常表项，并通过比较计数器数值最小的表项修复所述异常表项。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个机器可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
下面以软件实现为例，进一步描述数据通信设备如何执行该表项校验逻辑。在该例子中，本公开表项校验逻辑可以理解为存储在处理器的第一存储介质中的机器可执行指令。当本公开数据通信设备上的处理器执行该表项校验逻辑时，处理器通过调用第一存储介质上保存的表项校验逻辑对应的指令执行如下操作：向所述硬件芯片下发至少两条内容相同的数据表项；通过比较下发至所述硬件芯片的所述至少两条数据表项，来确定下发至所述硬件芯片的所述至少两条数据表项中出现错误的异常表项。
根据一示例，在向所述硬件芯片下发至少两条相同的数据表项时，所述机器可执行指令可促使所述处理器：向所述数据通信设备中的第一硬件芯片下发基准数据表项；向所述数据通信设备中的第二硬件芯片下发与所述基准数据表项内容相同的应用数据表项。
在此情况下，在比较下发至所述硬件芯片的所述至少两条数据表项时，所述机器可执行指令可促使所述处理器：根据下发至所述第一硬件芯片的所述基准数据表项校验下发至所述第二硬件芯片的所述应用数据表项；若连续N次的校验结果表示下发至所述第二硬件芯片的所述应用数据表项与下发至所述第一硬件芯片的所述基准数据表项内容不相同，确定所述应用数据表项为异常表项，其中N为大于1的整数。
此外，所述机器可执行指令还可促使所述处理器：当确定下发至所述第二硬件芯片的所述应用数据表项为异常表项时，根据下发至所述第一硬件芯片的所述基准数据表项修复下发至所述第二硬件芯片的所述应用数据表项。
根据另一示例，当向所述数据通信设备中的硬件芯片下发至少两条内容相同的数据表项时，所述机器可执行指令还可促使所述处理器：向所述数据通信设备中的硬件芯片的至少三 个bank中下发内容相同的至少三条数据表项。
在这种情况下，当比较下发至所述硬件芯片的所述至少两条数据表项时，所述机器可执行指令还可促使所述处理器：将下发至所述至少三个bank中的所述至少三条数据表项对应的各比较计数器的数值置为0；将下发至所述至少三个bank中的所述至少三条数据表项中相互不一致的两个所述数据表项分别对应的比较计数器的数值加1；当下发至所述至少三个bank中的所述至少三条数据表项成对比较结束时，若各所述比较计数器中的数值存在非零值，则确定下发至所述至少三个bank中的所述至少三条数据表项中存在异常表项。此外，在该示例中，所述机器可执行指令还可促使所述处理器：确定比较计数器数值最大的数据表项为异常表项；根据比较计数器数值最小的数据表项对所述异常表项进行修正。
或者，本公开数据通信通信设备中的硬件芯片可包括第二存储介质，第二存储介质中可以包括部分表项校验逻辑。当处理器向硬件芯片的至少三个bank下发表项内容相同的至少三条数据表项时，所述硬件芯片可通过读取并执行所述第二存储介质中与表项校验逻辑对应的机器可执行指令来执行以下操作：将下发至所述至少三个bank中的所述至少三条数据表项对应的各比较计数器的数值置为0；将下发至所述至少三个bank中的所述至少三条数据表项中相互不一致的两个所述数据表项分别对应的比较计数器的数值加1；当下发至所述至少三个bank中的所述至少三条数据表项之间的成对比较结束时，若各所述比较计数器中的数值存在非零值，则确定下发至所述至少三个bank中的所述至少三条数据表项中存在异常表项。
此外，在该示例中，所述机器可执行指令还可促使所述硬件芯片：确定比较计数器数值最大的数据表项为异常表项；根据比较计数器数值最小的数据表项对所述异常表项进行修正。
对于表项校验逻辑实施例而言，由于其基本对应于方法实施例，所以相关之处参见方法实施例的部分说明即可。以上所描述的逻辑实施例仅仅是示意性的，其中作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、 方法、物品或者设备中还存在另外的相同要素。
以上对本公开实施例所提供的方法进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (15)

  1. 一种表项校验方法，应用于数据通信设备中，所述方法包括：
    向所述数据通信设备中的硬件芯片下发至少两条内容相同的数据表项；
    通过比较下发至所述硬件芯片的所述至少两条数据表项，来确定下发至所述硬件芯片的所述至少两条数据表项中的异常表项。
  2. 根据权利要求1所述的方法，其中，向所述数据通信设备中的硬件芯片下发至少两条相同的数据表项，包括：
    向所述数据通信设备中的第一硬件芯片下发基准数据表项；
    向所述数据通信设备中的第二硬件芯片下发与所述基准数据表项内容相同的应用数据表项。
  3. 根据权利要求2所述的方法，其中，比较下发至所述硬件芯片的所述至少两条数据表项，包括：
    根据下发至所述第一硬件芯片的所述基准数据表项校验下发至所述第二硬件芯片的所述应用数据表项；
    若连续N次的校验结果表示下发至所述第二硬件芯片的所述应用数据表项与下发至所述第一硬件芯片的所述基准数据表项内容不相同，确定所述应用数据表项为异常表项，其中N为大于1的整数。
  4. 根据权利要求3所述的方法，其中，所述方法还包括：
    当确定下发至所述第二硬件芯片的所述应用数据表项为异常表项时，根据下发至所述第一硬件芯片的所述基准数据表项修复下发至所述第二硬件芯片的所述应用数据表项。
  5. 根据权利要求2所述的方法，其中，所述方法还包括：
    对所述第一硬件芯片配置纠错保护机制。
  6. 根据权利要求1所述的方法，其中，向所述数据通信设备中的硬件芯片下发至少两条内容相同的数据表项，包括：
    向所述数据通信设备中的硬件芯片的至少三个bank中下发内容相同的至少三条数据表项。
  7. 根据权利要求6所述的方法，其中，比较下发至所述硬件芯片的所述至少两条数据表项，包括：
    将下发至所述至少三个bank中的所述至少三条数据表项对应的各比较计数器的数值置为0；
    将下发至所述至少三个bank中的所述至少三条数据表项中相互不一致的两个所述数据表项分别对应的比较计数器的数值加1；
    当下发至所述至少三个bank中的所述至少三条数据表项成对比较结束时，若各所述比较计数器中的数值存在非零值，则确定下发至所述至少三个bank中的所述至少三条数据表项中存在异常表项。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    确定比较计数器数值最大的数据表项为异常表项；
    根据比较计数器数值最小的数据表项对所述异常表项进行修正。
  9. 一种数据通信设备，包括：
    处理器，其包括第一存储介质；以及
    硬件芯片，其中，通过读取并执行所述第一存储介质中与表项校验逻辑对应的机器可执行指令，所述处理器被促使：
    向所述硬件芯片下发至少两条内容相同的数据表项；以及
    通过比较下发至所述硬件芯片的所述至少两条数据表项，来确定下发至所述硬件芯片的所述至少两条数据表项中的异常表项。
  10. 根据权利要求9所述的数据通信设备，其中，在向所述硬件芯片下发至少两条相同的数据表项时，所述机器可执行指令促使所述处理器：
    向所述数据通信设备中的第一硬件芯片下发基准数据表项，
    向所述数据通信设备中的第二硬件芯片下发与所述基准数据表项内容相同的应用数据表项。
  11. 根据权利要求10所述的数据通信设备，其中，在比较下发至所述硬件芯片的所述至少两条数据表项时，所述机器可执行指令促使所述处理器：
    根据下发至所述第一硬件芯片的所述基准数据表项校验下发至所述第二硬件芯片的所述应用数据表项；
    若连续N次的校验结果表示下发至所述第二硬件芯片的所述应用数据表项与下发至所述第一硬件芯片的所述基准数据表项内容不相同，确定所述应用数据表项为异常表项，其中N为大于1的整数。
  12. 根据权利要求11所述的数据通信设备，其中，所述机器可执行指令还促使所述处理器：
    当确定下发至所述第二硬件芯片的所述应用数据表项为异常表项时，根据下发至所述第一硬件芯片的所述基准数据表项修复下发至所述第二硬件芯片的所述应用数据表项。
  13. 根据权利要求9所述的数据通信设备，其中，当向所述硬件芯片下发至少两条内容相同的数据表项时，所述机器可执行指令还促使所述处理器：
    向所述硬件芯片的至少三个bank中下发内容相同的至少三条数据表项；
    当比较下发至所述硬件芯片的所述至少两条数据表项时，所述机器可执行指令还促使所述处理器：
    将下发至所述至少三个bank中的所述至少三条数据表项对应的各比较计数器的数值置为0；
    将下发至所述至少三个bank中的所述至少三条数据表项中相互不一致的两个所述数据表项分别对应的比较计数器的数值加1；
    当下发至所述至少三个bank中的所述至少三条数据表项成对比较结束时，若各所述比较计数器中的数值存在非零值，则确定下发至所述至少三个bank中的所述至少三条数据表项中存在异常表项。
  14. 根据权利要求9所述的数据通信设备，其中，
    所述硬件芯片包括第二存储介质，
    通过读取并执行所述第一存储介质中与表项校验逻辑对应的机器可执行指令，所述处理器被促使向所述硬件芯片的至少三个bank下发内容相同的至少三条数据表项，以及
    通过读取并执行所述第二存储介质中与表项校验逻辑对应的机器可执行指令，所述硬件芯片被促使：
    将下发至所述至少三个bank中的所述至少三条数据表项对应的各比较计数器的数 值置为0；
    将下发至所述至少三个bank中的所述至少三条数据表项中相互不一致的两个所述数据表项分别对应的比较计数器的数值加1；
    当下发至所述至少三个bank中的所述至少三条数据表项之间的成对比较结束时，若各所述比较计数器中的数值存在非零值，则确定下发至所述至少三个bank中的所述至少三条数据表项中存在异常表项。
  15. 根据权利要求14所述的数据通信设备，其中，所述机器可执行指令还促使所述硬件芯片：
    确定比较计数器数值最大的数据表项为异常表项；
    根据比较计数器数值最小的数据表项对所述异常表项进行修正。
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CN103814409A (zh) * 2011-07-28 2014-05-21 桑迪士克科技股份有限公司 使用以二进制格式和多状态格式写入的数据的比较的非易失性存储器中的写入后读取
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CN1031148A (zh) * 1987-05-14 1989-02-15 计数设备公司 自动测量存储器系统
CN101459749A (zh) * 2007-12-12 2009-06-17 佳能株式会社 信息处理装置及其控制方法
CN103814409A (zh) * 2011-07-28 2014-05-21 桑迪士克科技股份有限公司 使用以二进制格式和多状态格式写入的数据的比较的非易失性存储器中的写入后读取
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