WO2017184525A1 - Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus - Google Patents
Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus Download PDFInfo
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- WO2017184525A1 WO2017184525A1 PCT/US2017/027995 US2017027995W WO2017184525A1 WO 2017184525 A1 WO2017184525 A1 WO 2017184525A1 US 2017027995 W US2017027995 W US 2017027995W WO 2017184525 A1 WO2017184525 A1 WO 2017184525A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus.
- Flash memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
- NAND may be a basic architecture of integrated flash memory.
- a NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string).
- NAND architecture may be configured to comprise vertically- stacked memory cells. It is desired to develop improved NAND architecture.
- FIG. 1 is a diagrammatic cross-sectional view illustrating regions of an integrated construction at a processing stage of an example embodiment.
- FIG. 2 is a diagrammatic cross-sectional view illustrating the regions of FIG. 1 at an example embodiment processing stage subsequent to that of FIG. 1.
- FIG. 3 is a diagrammatic cross-sectional view illustrating regions similar to those of FIG. 1 at another example embodiment processing stage subsequent to that of FIG. 1.
- Some embodiments include integrated circuit constructions having a material containing silicon, nitrogen and at least one of carbon, oxygen, boron and phosphorus.
- the material may extend across a memory array region.
- the memory array region comprises vertically- stacked wordline levels which extend to a staircase region (also sometimes referred to as a stepped region, shark jaw region, etc.) where conductive contacts are extended to individual wordline levels.
- the material may extend across one or both of the memory array region and the staircase region.
- the material may provide numerous advantages. For instance, the material may provide an insulative barrier to protect underlying conductive levels in the event of mask misalignment during fabrication of conductive contacts to regions over and/or near the conductive levels.
- the material may be fabricated to have compressive/tensile stress properties which compensate for stresses of underlying materials to alleviate bending and/or other undesired contortion of an integrated circuit die. Example embodiments are described with reference to FIGS. 1-3.
- portions of a construction 10 are illustrated, with such portions corresponding to integrated structures.
- One of the portions is a fragment of a memory array region 12 and the other is a fragment of a staircase region 14.
- a stack 15 of alternating levels 18 and 20 extends across the regions 12 and 14.
- the levels 18 may comprise dielectric material, such as, for example, silicon dioxide.
- the levels 20 may comprise sacrificial (i.e., replaceable) material, such as, for example, silicon nitride.
- the levels 18 and 20 may have any suitable thicknesses.
- the levels 18 and 20 may be the same thickness as one another in some embodiments, and may differ in thickness relative to one another in other embodiments.
- An insulative region 22 is over the uppermost level 20.
- Such insulative region may comprise any suitable insulative composition or combination of insulative compositions; including, for example, silicon dioxide.
- the region 22 is shown to comprise a single homogeneous composition, in other embodiments the region 22 may comprise two or more discrete compositions.
- a layer 26 is over the insulative region 22, and such layer is composed of a material 24.
- Material 24 comprises silicon, nitrogen and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus.
- a total concentration of carbon, oxygen, boron and/or phosphorus within material 24 is at least about 2 atomic percent, at least about 4 atomic percent, at least about 10 atomic percent, etc. In some embodiments a total concentration of carbon, oxygen, boron and/or phosphorus within the material 24 is within a range of from about 2 atomic percent to about 20 atomic percent; within a range of from about 6 atomic percent to about 11 atomic percent, etc. In some embodiments, the material 24 may consist of silicon, nitrogen and one or more of carbon, oxygen, boron and phosphorus.
- An advantage of including carbon, oxygen, boron and/or phosphorus within the silicon nitride material 24 is that such can render material 24 resistant to etching subsequently utilized to remove sacrificial silicon nitride within levels 20 (discussed below with reference to FIG. 2). Accordingly, it can be desired that the total
- silicon nitride material 24 concentration of carbon, oxygen, boron and/or phosphorus within silicon nitride material 24 be sufficient to render the material 24 resistant to the etch utilized to remove silicon nitride (or other suitable replaceable material) within levels 20. It can also be desired that material 24 be nonconductive. Accordingly, it can be desired that the concentration of substances included within the silicon nitride of material 24 (for instance, carbon) be kept low enough so that the silicon nitride material 24 remains nonconductive.
- the silicon nitride material 24 may be referred to as an "enhanced silicon nitride material" to indicate that the silicon nitride material comprises a composition tailored for advantages relative to silicon nitride alone.
- Patterned material 28 is provided over the enhanced silicon nitride material 24.
- the patterned material 28 may comprise any suitable composition or combination of compositions, and in some embodiments will comprise dielectric material, such as, for example, silicon dioxide.
- Dots are provided above and below the illustrated portions of construction 10 to indicate that there may be multiple additional levels or other structures above and below the illustrated portions. Also, dots are provided at the lower end of the bracket illustrating stack 15 to indicate that the stack may extend below the illustrated portion. A select gate level, source line, etc., may be below the illustrated portions of construction 10 in some embodiments.
- semiconductor substrate means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
- First and second openings 30 and 32 extend through stack 15 within memory array region 12.
- the first opening 30 represents one of a plurality of slits utilized to subdivide a memory array into programmable blocks.
- the individual blocks may correspond to smallest units within the memory array which may be erased, and each block may contain a number of pages which correspond to the smallest units which may be programmed.
- the second opening 32 represents a region where vertically-stacked memory cells are formed.
- Channel material 34 is within opening 32, and is spaced from materials of stack 15 by dielectric material 36, charge-storage material 38 and charge-blocking material 40.
- the materials 34, 36, 38 and 40 may comprise any suitable compositions or combinations of compositions.
- the illustrated channel material 34 lines sidewalls of opening 32 to leave a central region filled with dielectric material 42. Such corresponds to a so-called hollow channel configuration. In other embodiments the channel material may fill a central region of opening 32 as a solid pillar.
- the dielectric material 42 may comprise any suitable composition, such as, for example, oxide (e.g., silicon dioxide).
- a conductive plug 48 is provided over dielectric material 42.
- the conductive plug 48 may comprise any suitable composition or combination of compositions;
- conductively-doped semiconductor material for instance, conductively-doped silicon, conductively-doped germanium, etc.
- metal for instance, tungsten, titanium, etc.
- metal-containing compositions for instance, metal nitride, metal carbide, etc.
- first and second openings 30 and 32, and the structures within opening 32, are representative of numerous openings and structures that may be formed across a memory array.
- First, second and third openings 44-46 extend through various materials of the staircase region 14. Each opening extends to a different one of the levels 20, and ultimately is utilized to form an electrical contact extending to the exposed level.
- Dielectric material 48 is provided within the staircase region adjacent pedestals comprising the alternating levels 18 and 20.
- the dielectric material 48 may comprise any suitable composition or combination of compositions, including, for example, oxide (such as silicon dioxide).
- All of the openings 30, 32 and 44-46 are shown formed at a common processing stage in FIG. 1 in order to simplify description of advantages of the enhanced silicon nitride material 24. In practice, one or more of the openings 30, 32 and 44-46 may be formed at a different processing stage relative to others of the openings.
- the conductive material of levels 50 may comprise any suitable composition or combination of compositions; and may, for example, comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing
- the conductive material of levels 50 may comprise, consist essentially of, or consist of tantalum or tungsten.
- Conductive levels 50 may be referred to as vertically-stacked conductive levels which alternate with dielectric levels 18. In some embodiments, the conductive levels 50 may be referred to as vertically-stacked NAND wordline levels.
- a NAND memory array may be formed across the memory array region 12.
- Such NAND memory array comprises vertically-stacked memory cells, with some example memory cells 52 being diagrammatically illustrated in FIG. 2.
- the memory cells comprise regions of conductive levels 50 as control gate material, and comprise regions of the channel material 34, dielectric material 36, charge-storage material 38 and charge- blocking material 40.
- Conductive interconnects 54-56 are formed within the openings 44-46 across staircase region 14. The conductive interconnects 54-56 are in one-to-one
- the conductive interconnects 54-56 may comprise any suitable electrically conductive compositions or combinations of compositions; and may, for example, comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing composition(s).
- the enhanced silicon nitride material 24 extends across the memory cells 52 of the NAND memory array, and also extends across the staircase region 14.
- the enhanced silicon nitride material 24 remains after replacement of silicon nitride of levels 20 (FIG. 1) due to the incorporation of one or more of carbon, oxygen, boron and phosphorus within the enhanced silicon nitride material.
- the enhanced silicon nitride material 24 may advantageously provide compressive/tensile stress characteristics which balance the stresses of underlying materials to enhance planarity of an integrated circuit die relative to a conventional die lacking enhanced silicon nitride material 24. Further, relative amounts of carbon, oxygen, boron and/or phosphorus within the enhanced silicon nitride material 24 may be tailored to achieve tensile/compressive stress characteristics suitable for specific applications.
- the enhanced silicon nitride material 24 is spaced from an uppermost conductive level 50 by only the single dielectric region 22. Such may simplify processing as compared to other constructions in which enhanced silicon nitride material 24 is spaced from the uppermost conductive level by additional materials.
- a conductive interconnect 58 is shown provided within opening 32 to electrically connect with channel material 34 and conductive plug 48. Such interconnect may electrically connect the channel material 34 with other circuitry (not shown).
- the interconnect 58 may comprise any suitable electrically conductive composition or combination of compositions; and may, for example, comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing composition(s).
- the interconnect 58 is appropriately aligned with underlying materials.
- FIG. 3 shows a construction 10a analogous to the construction of FIG. 2, but having the interconnect 58 misaligned.
- the enhanced silicon nitride material 24 protects the underlying dielectric region 22 from being compromised during formation of the misaligned opening for interconnect 58, and thus avoids a problematic short that could otherwise occur between the conductive material of interconnect 58 and the uppermost conductive level 50.
- Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application- specific modules, and may include multilayer, multichip modules.
- the electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
- the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.
- ALD atomic layer deposition
- CVD chemical vapor deposition
- PVD physical vapor deposition
- dielectric dielectric
- electrically insulative dielectrically insulative
- Some embodiments include an integrated structure comprising vertically-stacked conductive levels alternating with dielectric levels.
- a layer over the conductive levels comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
- Some embodiments include an integrated structure comprising vertically-stacked NAND wordline levels within a NAND memory array.
- a layer over the wordline levels comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is at least about 2 atomic percent.
- the layer is spaced from an uppermost of the wordline levels by no more than one insulative region.
- Some embodiments include an integrated structure comprising vertically-stacked conductive levels alternating with dielectric levels.
- Vertically- stacked NAND memory cells are along the conductive levels within a memory array region.
- a staircase region is proximate the memory array region. The staircase region comprises electrical contacts in one-to-one correspondence with the conductive levels.
- a layer is over the memory array region and over the staircase region. The layer comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
Abstract
Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically- stacked conductive levels alternating with dielectric levels. Vertically- stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
Description
DESCRIPTION:
INTEGRATED STRUCTURES INCLUDING MATERIAL CONTAINING SILICON, NITROGEN, AND AT LEAST ONE OF CARBON, OXYGEN, BORON
AND PHOSPHORUS
TECHNICAL FIELD
Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus. BACKGROUND
Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured to comprise vertically- stacked memory cells. It is desired to develop improved NAND architecture. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagrammatic cross-sectional view illustrating regions of an integrated construction at a processing stage of an example embodiment.
FIG. 2 is a diagrammatic cross-sectional view illustrating the regions of FIG. 1 at an example embodiment processing stage subsequent to that of FIG. 1.
FIG. 3 is a diagrammatic cross-sectional view illustrating regions similar to those of FIG. 1 at another example embodiment processing stage subsequent to that of FIG. 1.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
Some embodiments include integrated circuit constructions having a material containing silicon, nitrogen and at least one of carbon, oxygen, boron and phosphorus. The material may extend across a memory array region. In some embodiments the memory array region comprises vertically- stacked wordline levels which extend to a staircase region (also sometimes referred to as a stepped region, shark jaw region, etc.) where conductive contacts are extended to individual wordline levels. In some embodiments the material may extend across one or both of the memory array region and the staircase region. The material may provide numerous advantages. For instance, the material may provide an insulative barrier to protect underlying conductive levels in the event of mask misalignment during fabrication of conductive contacts to regions over and/or near the conductive levels. As another example, the material may be fabricated to have compressive/tensile stress properties which compensate for stresses of underlying materials to alleviate bending and/or other undesired contortion of an integrated circuit die. Example embodiments are described with reference to FIGS. 1-3.
Referring to FIG. 1, portions of a construction 10 are illustrated, with such portions corresponding to integrated structures. One of the portions is a fragment of a memory array region 12 and the other is a fragment of a staircase region 14.
A stack 15 of alternating levels 18 and 20 extends across the regions 12 and 14. The levels 18 may comprise dielectric material, such as, for example, silicon dioxide. The levels 20 may comprise sacrificial (i.e., replaceable) material, such as, for example, silicon nitride. The levels 18 and 20 may have any suitable thicknesses. The levels 18 and 20 may be the same thickness as one another in some embodiments, and may differ in thickness relative to one another in other embodiments.
An insulative region 22 is over the uppermost level 20. Such insulative region may comprise any suitable insulative composition or combination of insulative compositions; including, for example, silicon dioxide. Although the region 22 is shown to comprise a single homogeneous composition, in other embodiments the region 22 may comprise two or more discrete compositions.
A layer 26 is over the insulative region 22, and such layer is composed of a material 24. Material 24 comprises silicon, nitrogen and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus. In some
embodiments a total concentration of carbon, oxygen, boron and/or phosphorus within material 24 is at least about 2 atomic percent, at least about 4 atomic percent, at least
about 10 atomic percent, etc. In some embodiments a total concentration of carbon, oxygen, boron and/or phosphorus within the material 24 is within a range of from about 2 atomic percent to about 20 atomic percent; within a range of from about 6 atomic percent to about 11 atomic percent, etc. In some embodiments, the material 24 may consist of silicon, nitrogen and one or more of carbon, oxygen, boron and phosphorus.
An advantage of including carbon, oxygen, boron and/or phosphorus within the silicon nitride material 24 is that such can render material 24 resistant to etching subsequently utilized to remove sacrificial silicon nitride within levels 20 (discussed below with reference to FIG. 2). Accordingly, it can be desired that the total
concentration of carbon, oxygen, boron and/or phosphorus within silicon nitride material 24 be sufficient to render the material 24 resistant to the etch utilized to remove silicon nitride (or other suitable replaceable material) within levels 20. It can also be desired that material 24 be nonconductive. Accordingly, it can be desired that the concentration of substances included within the silicon nitride of material 24 (for instance, carbon) be kept low enough so that the silicon nitride material 24 remains nonconductive. The silicon nitride material 24 may be referred to as an "enhanced silicon nitride material" to indicate that the silicon nitride material comprises a composition tailored for advantages relative to silicon nitride alone.
Patterned material 28 is provided over the enhanced silicon nitride material 24. The patterned material 28 may comprise any suitable composition or combination of compositions, and in some embodiments will comprise dielectric material, such as, for example, silicon dioxide.
Dots are provided above and below the illustrated portions of construction 10 to indicate that there may be multiple additional levels or other structures above and below the illustrated portions. Also, dots are provided at the lower end of the bracket illustrating stack 15 to indicate that the stack may extend below the illustrated portion. A select gate level, source line, etc., may be below the illustrated portions of construction 10 in some embodiments.
In some embodiments the illustrated portions of construction 10 would be supported by a semiconductor substrate; which may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone
or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
First and second openings 30 and 32 extend through stack 15 within memory array region 12.
The first opening 30 represents one of a plurality of slits utilized to subdivide a memory array into programmable blocks. In some embodiments the individual blocks may correspond to smallest units within the memory array which may be erased, and each block may contain a number of pages which correspond to the smallest units which may be programmed.
The second opening 32 represents a region where vertically-stacked memory cells are formed. Channel material 34 is within opening 32, and is spaced from materials of stack 15 by dielectric material 36, charge-storage material 38 and charge-blocking material 40. The materials 34, 36, 38 and 40 may comprise any suitable compositions or combinations of compositions. For instance, channel material 34 may comprise appropriately-doped silicon; dielectric material 36 may comprise one or more of silicon dioxide, hafnium oxide, aluminum oxide, zirconium oxide, etc.; charge- storage material 38 may comprise one or more charge-trapping materials, such as silicon nitride, silicon oxynitride, metal dots, etc.; and charge-blocking material 40 may comprise one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.
The illustrated channel material 34 lines sidewalls of opening 32 to leave a central region filled with dielectric material 42. Such corresponds to a so-called hollow channel configuration. In other embodiments the channel material may fill a central region of opening 32 as a solid pillar. The dielectric material 42 may comprise any suitable composition, such as, for example, oxide (e.g., silicon dioxide).
A conductive plug 48 is provided over dielectric material 42. The conductive plug 48 may comprise any suitable composition or combination of compositions;
including, for example, one or more of conductively-doped semiconductor material (for instance, conductively-doped silicon, conductively-doped germanium, etc.), metal (for instance, tungsten, titanium, etc.), and metal-containing compositions (for instance, metal nitride, metal carbide, etc.).
The first and second openings 30 and 32, and the structures within opening 32, are representative of numerous openings and structures that may be formed across a memory array.
First, second and third openings 44-46 extend through various materials of the staircase region 14. Each opening extends to a different one of the levels 20, and ultimately is utilized to form an electrical contact extending to the exposed level.
Dielectric material 48 is provided within the staircase region adjacent pedestals comprising the alternating levels 18 and 20. The dielectric material 48 may comprise any suitable composition or combination of compositions, including, for example, oxide (such as silicon dioxide).
All of the openings 30, 32 and 44-46 are shown formed at a common processing stage in FIG. 1 in order to simplify description of advantages of the enhanced silicon nitride material 24. In practice, one or more of the openings 30, 32 and 44-46 may be formed at a different processing stage relative to others of the openings.
Referring to FIG. 2, the sacrificial material of levels 20 (FIG. 1) is removed and replaced by conductive material to form conductive levels 50. The conductive material of levels 50 may comprise any suitable composition or combination of compositions; and may, for example, comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing
composition(s). In some embodiments, the conductive material of levels 50 may comprise, consist essentially of, or consist of tantalum or tungsten.
Conductive levels 50 may be referred to as vertically-stacked conductive levels which alternate with dielectric levels 18. In some embodiments, the conductive levels 50 may be referred to as vertically-stacked NAND wordline levels.
A NAND memory array may be formed across the memory array region 12. Such NAND memory array comprises vertically-stacked memory cells, with some example memory cells 52 being diagrammatically illustrated in FIG. 2. The memory cells comprise regions of conductive levels 50 as control gate material, and comprise regions of the channel material 34, dielectric material 36, charge-storage material 38 and charge- blocking material 40.
Conductive interconnects 54-56 are formed within the openings 44-46 across staircase region 14. The conductive interconnects 54-56 are in one-to-one
correspondence with the conductive levels (i.e. wordline levels) 50 and connect specific wordline levels with other circuitry (not shown). Such other circuitry may be utilized to, for example, trigger specific wordline levels during programming, erasing and/or reading operations. The conductive interconnects 54-56 may comprise any suitable electrically conductive compositions or combinations of compositions; and may, for example,
comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing composition(s).
The enhanced silicon nitride material 24 extends across the memory cells 52 of the NAND memory array, and also extends across the staircase region 14. The enhanced silicon nitride material 24 remains after replacement of silicon nitride of levels 20 (FIG. 1) due to the incorporation of one or more of carbon, oxygen, boron and phosphorus within the enhanced silicon nitride material. The enhanced silicon nitride material 24 may advantageously provide compressive/tensile stress characteristics which balance the stresses of underlying materials to enhance planarity of an integrated circuit die relative to a conventional die lacking enhanced silicon nitride material 24. Further, relative amounts of carbon, oxygen, boron and/or phosphorus within the enhanced silicon nitride material 24 may be tailored to achieve tensile/compressive stress characteristics suitable for specific applications.
In the illustrated embodiment, the enhanced silicon nitride material 24 is spaced from an uppermost conductive level 50 by only the single dielectric region 22. Such may simplify processing as compared to other constructions in which enhanced silicon nitride material 24 is spaced from the uppermost conductive level by additional materials.
A conductive interconnect 58 is shown provided within opening 32 to electrically connect with channel material 34 and conductive plug 48. Such interconnect may electrically connect the channel material 34 with other circuitry (not shown). The interconnect 58 may comprise any suitable electrically conductive composition or combination of compositions; and may, for example, comprise, consist essentially of, or consist of one or more of conductively-doped semiconductor material(s), metal(s), or metal-containing composition(s).
In the illustrated embodiment of FIG. 2, the interconnect 58 is appropriately aligned with underlying materials. However, in some applications there may be misalignment of the interconnect 58 due to, for example, misalignment of a mask utilized to pattern an opening for interconnect 58. FIG. 3 shows a construction 10a analogous to the construction of FIG. 2, but having the interconnect 58 misaligned. Advantageously, the enhanced silicon nitride material 24 protects the underlying dielectric region 22 from being compromised during formation of the misaligned opening for interconnect 58, and thus avoids a problematic short that could otherwise occur between the conductive material of interconnect 58 and the uppermost conductive level 50.
Although various embodiments are described above with reference to NAND architectures, it is to be understood that aspects of the invention(s) described herein may extend to architectures other than NAND. Such other architectures may include memory architectures, logic architectures, etc.
The constructions discussed above may be incorporated into electronic systems.
Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application- specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.
Both of the terms "dielectric" and "electrically insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "electrically insulative" in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.
The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.
The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.
When a structure is referred to above as being "on" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present. When a structure is referred
to as being "connected" or "coupled" to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being "directly connected" or "directly coupled" to another structure, there are no intervening structures present.
Some embodiments include an integrated structure comprising vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
Some embodiments include an integrated structure comprising vertically-stacked NAND wordline levels within a NAND memory array. A layer over the wordline levels comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is at least about 2 atomic percent. The layer is spaced from an uppermost of the wordline levels by no more than one insulative region.
Some embodiments include an integrated structure comprising vertically-stacked conductive levels alternating with dielectric levels. Vertically- stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region comprises electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer comprises silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
Claims
1. An integrated structure, comprising:
vertically- stacked conductive levels alternating with dielectric levels; and a layer over the conductive levels and comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
2. The integrated structure of claim 1 wherein said one or more substances include carbon.
3. The integrated structure of claim 1 wherein said one or more substances include oxygen.
4. The integrated structure of claim 1 wherein said one or more substances include boron.
5. The integrated structure of claim 1 wherein said one or more substances include phosphorus.
6. The integrated structure of claim 1 wherein said vertically- stacked conductive levels are part of a NAND memory array.
7. The integrated structure of claim 6 wherein said layer extends across memory cells of the NAND memory array.
8. The integrated structure of claim 7 wherein the vertically- stacked conductive levels are wordline levels of the NAND memory array, and wherein said layer extends across a staircase region where electrical contact is made to the wordline levels of the NAND memory array.
9. The integrated structure of claim 1 wherein the conductive levels comprise metal.
10. The integrated structure of claim 1 wherein the conductive levels comprise tantalum or tungsten.
11. An integrated structure, comprising:
vertically- stacked NAND wordline levels within a NAND memory array; a layer over the wordline levels and comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is at least about 2 atomic percent; and
wherein said layer is spaced from an uppermost of the wordline levels by no more than one insulative region.
12. The integrated structure of claim 11 wherein said total concentration of the one or more substances is at least about 4 atomic percent.
13. The integrated structure of claim 11 wherein said total concentration of the one or more substances is at least about 10 atomic percent.
14. The integrated structure of claim 11 wherein said total concentration of the one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
15. The integrated structure of claim 11 wherein said total concentration of the one or more substances is within a range of from about 6 atomic percent to about 11 atomic percent.
16. The integrated structure of claim 11 wherein said one or more substances include carbon.
17. The integrated structure of claim 11 wherein said one or more substances include oxygen.
18. The integrated structure of claim 11 wherein said one or more substances include boron.
19. The integrated structure of claim 11 wherein said one or more substances include phosphorus.
20. An integrated structure, comprising:
vertically- stacked conductive levels alternating with dielectric levels; vertically- stacked NAND memory cells along the conductive levels within a memory array region;
a staircase region proximate the memory array region, the staircase region comprising electrical contacts in one-to-one correspondence with the conductive levels; and
a layer over the memory array region and over the staircase region; the layer comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus; wherein a total concentration of said one or more substances is within a range of from about 2 atomic percent to about 20 atomic percent.
21. The integrated structure of claim 20 wherein said total concentration of the one or more substances is within a range of from about 6 atomic percent to about 11 atomic percent.
22. The integrated structure of claim 20 wherein said one or more substances include carbon.
23. The integrated structure of claim 22 wherein the layer consists of silicon, nitrogen and carbon.
24. The integrated structure of claim 20 wherein said one or more substances include oxygen.
25. The integrated structure of claim 24 wherein the layer consists of silicon, nitrogen and oxygen.
26. The integrated structure of claim 20 wherein said one or more substances include boron.
27. The integrated structure of claim 26 wherein the layer consists of silicon, nitrogen and boron.
28. The integrated structure of claim 20 wherein said one or more substances include phosphorus.
29. The integrated structure of claim 28 wherein the layer consists of silicon, nitrogen and phosphorus.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10157933B2 (en) | 2016-04-19 | 2018-12-18 | Micron Technology, Inc. | Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10707121B2 (en) * | 2016-12-31 | 2020-07-07 | Intel Corporatino | Solid state memory device, and manufacturing method thereof |
JP7089967B2 (en) * | 2018-07-17 | 2022-06-23 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
JP2020017572A (en) * | 2018-07-23 | 2020-01-30 | キオクシア株式会社 | Semiconductor memory and method of manufacturing the same |
US11329062B2 (en) | 2018-10-17 | 2022-05-10 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array |
US11121143B2 (en) * | 2019-05-24 | 2021-09-14 | Micron Technology, Inc. | Integrated assemblies having conductive posts extending through stacks of alternating materials |
US11088088B2 (en) | 2019-11-05 | 2021-08-10 | Micron Technology, Inc. | Microelectronic devices with polysilicon fill material between opposing staircase structures, and related devices, systems, and methods |
US11177278B2 (en) * | 2019-11-06 | 2021-11-16 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11177159B2 (en) | 2019-11-13 | 2021-11-16 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11121144B2 (en) | 2019-11-13 | 2021-09-14 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array comprising strings of memory cells |
US11569390B2 (en) * | 2019-12-23 | 2023-01-31 | Micron Technology, Inc. | Memory cells and integrated assemblies having charge-trapping-material with trap-enhancing-additive |
US11101280B2 (en) | 2019-12-27 | 2021-08-24 | Micron Technology, Inc. | Memory arrays and methods used in forming a memory array |
US11411013B2 (en) * | 2020-01-08 | 2022-08-09 | Micron Technology, Inc. | Microelectronic devices including stair step structures, and related electronic devices and methods |
US11081443B1 (en) | 2020-03-24 | 2021-08-03 | Sandisk Technologies Llc | Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same |
US11706918B2 (en) | 2020-07-01 | 2023-07-18 | Micron Technology, Inc. | Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells |
US11889683B2 (en) | 2020-07-01 | 2024-01-30 | Micron Technology, Inc. | Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells |
US11744069B2 (en) * | 2020-08-27 | 2023-08-29 | Micron Technology, Inc. | Integrated circuitry and method used in forming a memory array comprising strings of memory cells |
US11437383B1 (en) * | 2021-06-02 | 2022-09-06 | Nanya Technology Corporation | Method for fabricating dynamic random access memory devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130164922A1 (en) * | 2011-12-27 | 2013-06-27 | Samsung Electronics Co., Ltd. | Methods of manufacturing a semiconductor device |
US20130161731A1 (en) * | 2011-12-22 | 2013-06-27 | Jin Ho Bin | Semiconductor device and method of manufacturing the same |
US20150194441A1 (en) * | 2014-01-09 | 2015-07-09 | Tokyo Electron Limited | Method for manufacturing semiconductor device |
US20150236038A1 (en) * | 2014-02-20 | 2015-08-20 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
US20150372005A1 (en) * | 2014-06-23 | 2015-12-24 | Gukhyon Yon | Three-dimensional semiconductor memory device and method of fabricating the same |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04142079A (en) * | 1990-10-02 | 1992-05-15 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
US5189504A (en) | 1989-12-11 | 1993-02-23 | Nippon Telegraph And Telephone Corporation | Semiconductor device of MOS structure having p-type gate electrode |
US6949829B2 (en) * | 2000-09-11 | 2005-09-27 | Tokyo Electron Limited | Semiconductor device and fabrication method therefor |
US7226845B2 (en) * | 2005-08-30 | 2007-06-05 | Micron Technology, Inc. | Semiconductor constructions, and methods of forming capacitor devices |
US8026169B2 (en) * | 2006-11-06 | 2011-09-27 | Advanced Micro Devices, Inc. | Cu annealing for improved data retention in flash memory devices |
JP5356005B2 (en) * | 2008-12-10 | 2013-12-04 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
JP2011049206A (en) * | 2009-08-25 | 2011-03-10 | Toshiba Corp | Manufacturing method of semiconductor device, and semiconductor device |
US8383512B2 (en) * | 2011-01-19 | 2013-02-26 | Macronix International Co., Ltd. | Method for making multilayer connection structure |
US8158967B2 (en) * | 2009-11-23 | 2012-04-17 | Micron Technology, Inc. | Integrated memory arrays |
US8945996B2 (en) * | 2011-04-12 | 2015-02-03 | Micron Technology, Inc. | Methods of forming circuitry components and methods of forming an array of memory cells |
KR101916223B1 (en) * | 2012-04-13 | 2018-11-07 | 삼성전자 주식회사 | Semiconductor device and manufacturing the same |
US8828884B2 (en) | 2012-05-23 | 2014-09-09 | Sandisk Technologies Inc. | Multi-level contact to a 3D memory array and method of making |
US9595533B2 (en) | 2012-08-30 | 2017-03-14 | Micron Technology, Inc. | Memory array having connections going through control gates |
US8946076B2 (en) * | 2013-03-15 | 2015-02-03 | Micron Technology, Inc. | Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells |
JP6013313B2 (en) | 2013-03-21 | 2016-10-25 | 東京エレクトロン株式会社 | Method of manufacturing stacked semiconductor element, stacked semiconductor element, and manufacturing apparatus thereof |
US9136278B2 (en) * | 2013-11-18 | 2015-09-15 | Micron Technology, Inc. | Methods of forming vertically-stacked memory cells |
US9287379B2 (en) * | 2014-05-19 | 2016-03-15 | Micron Technology, Inc. | Memory arrays |
US9559117B2 (en) * | 2014-06-17 | 2017-01-31 | Sandisk Technologies Llc | Three-dimensional non-volatile memory device having a silicide source line and method of making thereof |
US9616313B2 (en) | 2014-07-11 | 2017-04-11 | Canyon Hard Goods LLC | Portable therapeutic stretching and massage storage device |
US9576975B2 (en) * | 2014-08-26 | 2017-02-21 | Sandisk Technologies Llc | Monolithic three-dimensional NAND strings and methods of fabrication thereof |
US9728546B2 (en) * | 2014-09-05 | 2017-08-08 | Sandisk Technologies Llc | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same |
US9773803B2 (en) * | 2014-09-08 | 2017-09-26 | Toshiba Memory Corporation | Non-volatile memory device and method of manufacturing same |
KR20160106972A (en) * | 2015-03-03 | 2016-09-13 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of the same |
US9601508B2 (en) * | 2015-04-27 | 2017-03-21 | Sandisk Technologies Llc | Blocking oxide in memory opening integration scheme for three-dimensional memory structure |
US9613977B2 (en) * | 2015-06-24 | 2017-04-04 | Sandisk Technologies Llc | Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices |
CN105120544A (en) | 2015-08-20 | 2015-12-02 | 阮保清 | Cyclonic IH electromagnetic heating wire tray |
US10157933B2 (en) | 2016-04-19 | 2018-12-18 | Micron Technology, Inc. | Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus |
US10529620B2 (en) * | 2016-07-13 | 2020-01-07 | Sandisk Technologies Llc | Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same |
-
2016
- 2016-04-19 US US15/133,119 patent/US10157933B2/en active Active
-
2017
- 2017-04-17 KR KR1020187032760A patent/KR102180503B1/en active IP Right Grant
- 2017-04-17 WO PCT/US2017/027995 patent/WO2017184525A1/en active Application Filing
- 2017-04-17 CN CN201780024561.7A patent/CN109075166B/en active Active
- 2017-04-18 TW TW106112981A patent/TWI625844B/en active
-
2018
- 2018-10-11 US US16/158,039 patent/US10720446B2/en active Active
-
2020
- 2020-06-22 US US16/907,967 patent/US11239252B2/en active Active
-
2021
- 2021-12-20 US US17/556,704 patent/US11937429B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130161731A1 (en) * | 2011-12-22 | 2013-06-27 | Jin Ho Bin | Semiconductor device and method of manufacturing the same |
US20130164922A1 (en) * | 2011-12-27 | 2013-06-27 | Samsung Electronics Co., Ltd. | Methods of manufacturing a semiconductor device |
US20150194441A1 (en) * | 2014-01-09 | 2015-07-09 | Tokyo Electron Limited | Method for manufacturing semiconductor device |
US20150236038A1 (en) * | 2014-02-20 | 2015-08-20 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
US20150372005A1 (en) * | 2014-06-23 | 2015-12-24 | Gukhyon Yon | Three-dimensional semiconductor memory device and method of fabricating the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10157933B2 (en) | 2016-04-19 | 2018-12-18 | Micron Technology, Inc. | Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus |
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US20190043890A1 (en) | 2019-02-07 |
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