WO2017168690A1

WO2017168690A1 - Storage device, and method

Info

Publication number: WO2017168690A1
Application number: PCT/JP2016/060709
Authority: WO
Inventors: 升平浅川
Original assignee: 株式会社日立製作所
Priority date: 2016-03-31
Filing date: 2016-03-31
Publication date: 2017-10-05

Abstract

According to the present invention, a control device acquires a first command in a first queue, determines whether or not a first logical area designated by the first command is registered in logical-physical translation information, specifies a first device area that corresponds to the first logical area on the basis of the logical-physical translation information when the first logical area is registered in the logical-physical translation information, and indicates to a physical storage device a write to the first device area of first write data that is received by an interface on the basis of the first command. The control device registers the first command in a second queue when the first logical area is not registered in the logical-physical translation information. A processor acquires the first command from the second queue, and acquires the load status of a cache area. The processor determines whether or not the load status is higher than a preset threshold value, selects the first device area from the physical storage device when the load status is higher than the threshold value, registers the first logical area and the first device area in correlation with each other in the logical-physical translation information, and re-registers the first command in the first queue.

Description

Storage apparatus and method

The present invention relates to a storage apparatus.

The storage device includes a plurality of physical storage devices (recording media) and a storage controller connected to the plurality of physical storage devices and receiving I / O (Input or Output) requests from the host computer. As a physical storage device, for example, an HDD (Hard Disk Drive) is known.

In recent years, SSD (Solid State Drive) realized by flash memory has begun to be widely used as a physical storage device of a storage apparatus. SSDs have features such as response performance and low power consumption compared to conventional HDDs. In particular, the I / O performance of SSDs is nearly 1000 times that of HDDs.

On the other hand, there is a problem that the performance of the storage controller does not catch up with the performance of the SSD and becomes a bottleneck. For example, even when at most a dozen or more flash drives (SSDs) are mounted, the performance of the storage controller may become a bottleneck and the performance of the flash drive may not be fully exploited.

For example, the controller disclosed in Patent Document 1 has a CPU, a memory, a storage I / F, and a disk I / F, and processes an I / O request from a host computer with software by the CPU. Further, for example, Patent Document 2 discloses a method for realizing a high-performance storage controller that processes I / O requests by dedicated hardware different from the CPU.

JP 2014-41646 A US Patent Application Publication No. 2013/0145088

The CPU used in the controller as disclosed in Patent Document 1 has improved its performance according to Moore's law. However, in the change of the physical storage device as described above, a large performance gap is generated between the controller and the physical storage device, and the performance of the storage controller may become a bottleneck.

In addition, with the technology according to Patent Document 2, it is possible to achieve high performance of the storage controller. However, since processing is performed with dedicated hardware, there is a problem that a function specific to the storage apparatus cannot be provided. For example, functions specific to storage devices include Thin Provisioning, volume replication, snapshot, deduplication, and data compression. In order to provide these functions, it is necessary to execute a program having these functions on the processor. For this reason, a volume having these functions must be processed by a processor.

The storage apparatus includes a physical storage device and a controller connected to the physical storage device. The controller includes a front-end interface connected to the host computer, a processor connected to the front-end interface and the physical storage device, and providing a logical volume based on the physical storage device to the host computer, and a memory connected to the processor. , A front-end interface, a memory, and a control device connected to the processor. The memory sequentially stores logical conversion information that correlates the logical area in the logical volume and the device area that is provided by the physical storage device, and the write command received from the host computer by the front-end interface. A first queue to be executed, a second queue different from the first queue, and a cache area. The control device acquires the first write command in the first queue and determines whether or not the first logical area designated by the first write command is registered in the logical-physical conversion information. When the first logical area is registered in the logical-physical conversion information, the control device specifies the first device area corresponding to the first logical area based on the logical-physical conversion information. The control device instructs the physical storage device to write the first write data received by the front end interface to the first device area based on the first write command. If the first logical area is not registered in the logical-physical conversion information, the control device registers the first write command in the second queue. The processor acquires the first write command from the second queue and acquires the load status of the cache area. The processor determines whether or not the load status is higher than a preset threshold value. When the load status is higher than the threshold value, the processor selects the first device area from the physical storage device, associates the first logical area with the first device area, registers the first logical area and the logical / physical conversion information, and outputs the first write area. Re-register the command in the first queue.

∙ Regarding the write processing, the performance of the storage controller can be improved.

1 is an example of a configuration diagram of a storage device according to Embodiment 1. FIG. 2 shows a configuration of the memory 12 in the first controller 10. An example of the address conversion table 121 is shown. It is a figure explaining the outline | summary of the write command distribution process by ACC22. 6 is an example of a flowchart of a write command distribution process 500; It is a figure explaining the outline | summary of a re-offload process. It is a figure explaining the structure of the volume of the storage apparatus which has TP function. It is a figure explaining mapping information creation processing. 6 is an example of a flowchart of a write-through determination process 700. It is an example of the flowchart of a 1st write process. It is a figure explaining a 2nd write process. It is an example of the flowchart of a 2nd write process. It is a figure explaining sharing of each process. It is an example of the flowchart of a re-offload process.

In the following description, each piece of information included in the computer system of each embodiment may be described using expressions such as a table or a list. However, the data structure of each information is not limited, and other data structures may be used. Since each information does not depend on the data structure, for example, “kkk table” can be called “kkk information”.

In the following description, the processor executes a program and performs processing while using a storage resource (for example, a memory) and / or a communication interface device (for example, a communication port). In the following description, the main subject of processing may be various programs, but a processor that executes the program may be the main subject. Further, the processing mainly using the processor may be interpreted as being performed by executing one or more programs. The processor is typically a microprocessor such as a CPU (Central Processing Unit), but may include a hardware circuit that executes a part of the processing (for example, encryption / decryption, compression / decompression). .

Further, in the following description, when a description is made without distinguishing the same type of element, a reference symbol is used, and when a description is made with a distinction between the same type of element, the element is replaced with the reference number. An assigned identifier (eg, at least one of a number and a sign) may be used.

Hereinafter, some examples will be described.

FIG. 1 is an example of a configuration diagram of the storage apparatus according to the first embodiment.

The storage apparatus includes a first storage controller (FCTL) 10, a second storage controller (SCTL) 20, and a physical storage device 31. In the following description, the first storage controller 10 and the second storage controller 20 may be referred to as the first controller 10 and the second controller 20, respectively.

In the illustrated example, each of the first controller 10 and the second controller 20 is made redundant in pairs. However, each of the first controller 10 and the second controller 20 may be configured by one, or may be made redundant by three or more configurations. Each of the redundant first controller 10 and second controller 20 has basically the same configuration. Therefore, in the following, each of the first controller 10 and the second controller 20 will be described.

The second controller 20 includes a front-end interface (hereinafter referred to as FE) 24, a switch (PCIe-SW) 21, an accelerator (ACC) 22, and a device controller (SAS-CTL) 23 as a back-end interface. . In addition, the number of each of these each part is not limited to the number shown in the example of illustration.

The switch 21 is connected to the FE 24, the ACC 22, and the device controller 23 through a signal line. This signal line is, for example, a PCI Express used as a data transfer path inside the controller 10, but is not limited thereto. In the case of signal lines other than PCI Express, a switch suitable for the signal line is applied. Further, the second controller 20 is connected to the first controller 10 via the switch 21.

The second controller 20 is connected to a host computer (not shown) via the FE 24 via a network. Note that the network between the host computer and the second controller 20 is a communication path for exchanging commands and data, and includes, for example, a SAN (Storage Area Network). The FE 24 mutually converts a data transfer protocol between the host computer and the second controller 20 and a data transfer protocol in the second controller 20.

The ACC 22 is a control device different from the processor 11 of the first controller 10. Specifically, for example, the ACC 22 is realized by hardware such as an ASIC (application specific integrated circuit) or an FPGA (field-programmable gate array). In the present embodiment, an example will be described in which the ACC 22 and the processor 11 in the first controller 10 share write processing to realize high-performance (high-speed) processing. For example, it is assumed that the ACC 22 does not execute functions or the like specific to the storage apparatus, and executes some functions such as read / write processing to the physical storage device 31 in a limited manner. As in this embodiment, when the physical storage device 31 is a high-speed drive (the physical storage device 31 will be described later), by limiting the functions of the ACC 22, higher-speed read / write processing can be realized.

In this embodiment, the ACC 22 is hardware such as an ASIC or FPGA. However, the ACC 22 is not limited to hardware such as an ASIC or FPGA, and a processor such as a CPU executes software. It may be realized. For example, a memory (not shown) may be connected to the ACC 22. The memory may be built in or connected externally.

The second controller 20 is connected to the non-volatile physical storage device 31 via the device controller 23, for example. The device controller 23 includes a processor and a memory (not shown) therein, and executes data I / O processing and control command processing.

The physical storage device 31 is, for example, a high-speed drive such as an SSD (Solid state drive). In the illustrated example, a SAS (Serial Attached SCSI) protocol is adopted between the device controller 23 and the physical storage device 31. For this reason, the SAS controller 23 is adopted as the device controller, and the SAS-SSD is adopted as the physical storage device 31. However, a protocol other than SAS may be adopted between the device controller 23 and the physical storage device 31, and in this case, the device controller 23 and the SSD according to the protocol are adopted. Furthermore, as long as the physical storage device 31 is nonvolatile, the physical storage device 31 may not be a nonvolatile semiconductor storage device such as an SSD, and may be, for example, an HDD (Hard Disk Drive). Further, one or more RAID groups (Redundant Array of Independent (or Inexpensive) Disks) may be configured by a plurality of physical storage devices 31.

A device controller 23 in each second controller 20 is connected to the physical storage device 31. Thereby, even if a failure occurs between paths using one device controller 23, IO from the host computer can be continued by switching to a path using another device controller 23.

The first controller 10 includes a front end interface (hereinafter referred to as FE) 14, a processor (CPU; Central Processing Unit) 11, a memory (Memory) 12, a back end interface (hereinafter referred to as BE) 13, and an interface between the controllers ( I / F) 15. These units (FE14, CPU11, memory 12, BE13, I / F15) are internally connected to each other by a signal line such as a bus. In addition, the number of each of these each part is not limited to the number shown in the example of illustration.

The memory 12 is a main storage medium of the processor 11, an area for storing various programs executed by the processor 11, various management information referred to by the processor 11, and a cache area (CM for temporarily storing read or write data). 127). The program stores, for example, a program for controlling the storage apparatus. In this embodiment, the memory 12 is connected to the processor, but the memory 12 may be built in the processor 11.

Each part of the first controller 10 is connected to the switch 21 of the second controller 20 via the I / F 15. Thereby, mutual communication between the first controller 10 and the second controller 20 becomes possible.

The processor 11 provides a logical volume (LU) to the host computer. The logical volume may be a real logical volume or a virtual logical volume. A real logical volume is a logical volume based on one or more physical storage devices 31. For example, a volume generated based on a RAID group composed of a plurality of physical storage devices 31 may be used, or a volume generated from one physical storage device 31 may be used.

The virtual logical volume is a logical volume that is virtually provided to the host computer. When the storage apparatus has a TP (Thin Provisioning) function and a snapshot function as specific functions, a virtual logical volume is provided to the host computer.

The first controller 10 may be connected to a physical storage device (not shown) such as an HDD via the BE 13. The first controller 10 may be connected to a host computer (not shown) via the FE 14.

FIG. 2 is a diagram showing a configuration of the memory 12 in the first controller 10.

The memory 12 includes an address conversion table 121, a temporary queue 125, a micro request queue 123, and a cache area 127.

The processor 11 can access information in the memory 12 (the address conversion table 121, the temporary queue 125, and the micro request queue 123). The ACC 22 can also access information in the memory 12 via the Pcle 21.

In the temporary queue 125, commands transmitted from the host computer are registered. The command transmitted from the host computer is transferred to the temporary queue 125 by the FE 24. Further, commands are registered in the temporary queue 125 by the processor 1 also in the redistribution processing described later. The command in the temporary queue 125 is acquired by the ACC 22 and a distribution process described later is executed.

The micro request queue 123 is a queue in which commands are registered by the ACC 22. Commands in the micro request queue 123 are acquired and processed by the processor 11.

In the cache area 127, write data is temporarily stored when the processor 11 executes the write process. When the processor 11 receives write data based on the acquired write command, the processor 11 stores it in the cache area and transmits a write processing completion response to the host computer. Thereafter, an instruction for asynchronously storing the write data in the cache area 127 in the physical volume is transmitted to the physical storage device 31 via the device controller 23. By returning a write completion response to the host computer when the write to the cache area is completed, the response performance to the host computer can be increased.

In the present embodiment, the information in the memory 12 is shared between the processor 11 and the ACC 22. However, some or all of the information in the memory 12 may be held in a built-in memory (not shown). In this case, the information in the built-in memory and the information in the memory 12 are synchronized.

FIG. 3 shows an example of the address conversion table 121.

The address conversion table 121 is a table referred to by the ACC 22 when a write command is received. In the address conversion table 121, the correspondence between the logical address of the logical volume that can be written by the ACC 22 and the address of the physical volume based on the physical storage device 31 managed by the first controller 10 and the second controller 20 is registered. Is done. When the logical address specified by the write command is registered in the address conversion table 121, the ACC 22 performs the write process itself, and the logical address specified by the write command is not registered in the address conversion table. In this case, the write command is registered in the micro request queue 123 to request the processor 11 for the write process.

The address conversion table 121 has an entry for each logical address. Each entry includes a LUN (Logical Unit Number) 301 that is an identifier of the logical volume, an LBA (Logical Block Address) 302 that indicates an area in the logical volume, a physical storage device 31 corresponding to the LUN and LBA, and its And a drive number (#) 303 indicating an area and an in-drive LBA 304.

In the address conversion table 121, in principle, logical addresses of real logical volumes that do not have storage device specific functions such as replication, deduplication, or data compression are registered. For example, these logical addresses are registered in the address conversion table 121 when a logical volume is created. Registration is performed by the processor 11, for example. By limiting the logical addresses registered in the address conversion table 121, the ACC 22 executes a process for a write process for a logical volume that does not require an operation specific to the storage device, and a logical operation that requires an operation specific to the storage device. For the write processing on the volume, the processor 11 can be requested (assigned). As a result, the ACC 22 can undertake a part of the load on the processor 11 for the write processing.

In this embodiment, the address conversion table 121 can be updated by the processor 11. As a result, a part of the write processing for the logical volume that requires operations specific to the storage apparatus can be reassigned to the ACC 22.

FIG. 4 is a diagram for explaining the outline of the write command distribution process by the ACC 22.

The ACC 22 acquires the write command transferred from the FE 24 to the temporary queue 125, analyzes the received write command by its search engine, acquires the logical address of the destination, and stores the logical address of the destination in the address conversion table 121. It is determined whether it is registered.

If the destination logical address is registered in the address translation table 121 (there is a search hit), the ACC 22 performs the write process based on the write command.

On the other hand, if the destination logical address is not registered in the address conversion table 121 (no search hit), the processor 11 performs a write process based on the write command. Specifically, the ACC 22 requests the processor 11 to perform write processing based on the write command by re-registering the write command in the micro request queue 123 in the memory 12.

Here, the write process executed by the ACC 22 will be described. The ACC 22 acquires the address (drive number 303 and in-drive LBA 304) of the physical storage device 31 corresponding to the destination logical address (LUN 301 and LBA 302) based on the address conversion table 121, and designates the address of the physical storage device 31. The generated drive command is generated and transmitted to the physical storage device 31 via the device controller 23.

The physical storage device 31 transmits a drive command response to the ACC 22. In response to the response, the ACC 22 transmits a write data transmission request to the host computer, and transmits the received write data to the physical storage device 31 via the device controller 23.

The physical storage device 31 stores write data in the storage area of the physical storage device 31 based on the drive command. The physical storage device 31 transmits a write completion notification to the ACC 22. The ACC 22 transmits a completion response corresponding to the write completion notification to the host computer, and ends the write process.

FIG. 5 is an example of a flowchart of a write command distribution process 500.

The FE 24 registers the write command transmitted from the host computer in the temporary queue 125. Hereinafter, the distribution process 500 of the target write command (target command) will be described.

The ACC 22 acquires the target command that is the first write command of the temporary queue 125 (S501). Then, the ACC 22 analyzes the target command (S503) and obtains the destination logical address.

Next, the ACC 22 refers to the address conversion table 121 (S505), and determines whether or not the destination logical address is registered in the address conversion table 121 (S507).

As a result of the determination, when the destination logical address is registered in the address conversion table 121 (S507; Yes), the ACC 22 determines the address of the physical storage device 31 corresponding to the destination logical address (drive number and in-drive LBA, below). (Similar) is generated (S511), and the drive command is transmitted to the physical storage device 31 (S513). As described above, the physical storage device 31 acquires write data based on the drive command and stores it in the corresponding storage area of the physical volume.

On the other hand, as a result of the determination, if the destination logical address is not registered in the address conversion table 121 (S507; No), the ACC 22 registers the target command in the micro request queue 123 in the memory 12 (S509).

After that, the processor 11 acquires the target command from the micro request queue 123 (S521), and executes the write-through determination process 700 for the write command. According to the write-through determination processing 700, the write command acquired by the processor 11 is assigned to itself or the ACC 22 again. Details of the write-through determination processing 700 will be described later.

By the distribution process 500, the processor 11 and the ACC 22 can share the write process to the storage device. Specifically, for a logical volume that does not perform storage-specific operations, its logical address is registered in the address conversion table 121 in advance, so that a write command addressed to the logical address registered in the address conversion table 121 can be obtained. The received ACC 22 can execute the write process.

For the target command addressed to the logical address that is not registered in the address conversion table 121, the ACC 22 registers the target command in the micro request queue 123 to request the processor to determine the target command (write-through determination described later). can do. As a result, it is possible to assign the subject that performs the write process depending on whether or not the logical volume is a storage-specific operation.

In particular, when the physical storage device 31 is a high-speed device such as a nonvolatile semiconductor such as SSD, the processing of the processor 11 may become a bottleneck. Accordingly, the load of the

controllers

10 and 20 can be efficiently distributed by sharing a part of such high-speed write processing to the physical storage device 31 by the ACC 22.

Next, the write-through determination process 700 will be described. The write-through determination process 700 is a process performed by the processor 11 for the write command registered in the micro request queue 123. The write-through in this embodiment is to store the received write data in the physical storage device 31 without temporarily storing it in the cache area 127. Write processing by the ACC 22 is write-through. On the other hand, the write processing by the processor 11 is not write-through because the received write data is temporarily stored in the cache area 127. In the write-through determination processing 700, it is determined whether or not the write-through should be performed for the write processing based on the write command acquired from the micro request queue 123.

FIG. 9 shows an example of a flowchart of the write-through determination process 700.

Hereinafter, the write-through determination process for the target command registered in the micro request queue 123 by the distribution process 500 will be described.

The processor 11 acquires the target command from the micro request queue 123 (S701). The processor 11 acquires the load of the cache area 127 (S703).

As the load of the cache area 127, for example, the usage rate of the cache area or IOPS (Input or Output per second) is applied. However, it is not limited to these.

The processor 11 determines whether or not the acquired load is higher than a preset threshold value (S705).

When the acquired load is equal to or less than the threshold (S705; No), the current load status means that there is no need for write-through. In this case, the processor 11 ends the write-through determination process and performs the first write process for the target command (S720). Specifically, the processor 11 acquires write data based on the target command, stores it in the specified cache area, and transmits a notification of completion of the write process to the host computer. Thereafter, the processor 11 transmits the write data in the cache area 127 to the physical storage device 31 via the device controller 23. Details of the first write process will be described later.

On the other hand, when the acquired load is higher than the threshold (S705; Yes), it means that it is more appropriate to execute the write-through in the current load status. In this case, the processor 11 performs re-offload processing on the target command (S730). The re-offload process will be described later.

The write-through determination processing 700 allows the processor 11 to determine whether it is better to execute the write processing of the write command acquired from the micro request queue 123 or to let the ACC 22 perform it.

When the processor 11 performs the write process, the processor 11 needs to temporarily store the write data in the cache area 127 (caching). In the write-through determination process, it is possible to determine whether or not there is a possibility that the target write data is delayed by caching by considering the load on the cache area.

If the load on the cache area 127 is high, the write processing on the processor 11 side may be delayed due to caching. Then, there is a possibility that the advantage of the processor 11 performing the write process (that is, the advantage that the response time to the host can be shortened by asynchronously writing the cached write data to the physical storage device (write after)) may be offset. .

Specifically, if the load on the cache area is high, a waiting time may occur until the cache area becomes free, which may increase the response time to the host for the write command. In particular, when the storage location of the write data is a flash drive, writing can be performed at a higher speed compared to the HDD. For this reason, in consideration of the waiting time for the free space in the cache area, there is a possibility that the response time to the host can be made shorter in the write-through mode than in the write-after mode when the cache load is high.

FIG. 10 shows an example of a flowchart of the first write process.

This process is the process of S720 in FIG. The processor 11 performs the processing of S1001 to S1007 as the front-end job (FE JOB) when the target command is received, and performs the processing of S1010 to S1019 as the back-end job (BE JOB).

Explain front-end jobs. Note that the TP function may be used as a function unique to the storage apparatus. In this case, the logical volume specified by the write command is TP-VOL as an example of the virtual logical volume. The TP-VOL will be described later.

The processor 11 analyzes and determines whether the target command is a write command to the TP-VOL (S1001). If the target command is a command other than a write command for the TP-VOL 81 (S1001; No), the processor 11 advances the process to S1005. On the other hand, if the target command is a write command for TP-VOL 81 (S1001; Yes), the processor 11 has already registered the logical address (target logical address) of the logical volume specified by the target command in the mapping information described later. It is determined whether or not (S1002).

When the target logical address is not yet registered in the mapping information (S1002; No), the processor 11 executes a mapping information creation process (S1004). For example, the processor 11 acquires the volume address of the physical volume 85 corresponding to the logical address of the logical volume specified by the target command, creates mapping information for associating these, and stores it in the memory 12. Next, the processor 11 advances the process to S1005.

On the other hand, when the target logical address is registered in the mapping information (S1002; Yes), the processor 11 searches the mapping information and identifies the cache area corresponding to the logical address specified by the target command (S1003).

The processor 11 secures a cache area corresponding to the target logical address (S1005). Then, the processor 11 transmits a transmission request for the target write data (target data) based on the target command to the host computer.

The processor 11 acquires the target data received by the FE 24 from the host computer and transfers it to the secured cache area (S1006). The processor 11 sets a flag indicating that the target data is data (dirty data) that has not yet been written to the physical storage device 31. Next, the processor 11 transmits a write process completion notification to the host computer (S1007), and ends the write process.

Explain back-end jobs. The back end job is performed asynchronously with the front end job. The processor 11 acquires the target data in the cache area based on the flag (S1010). Then, the processor 11 determines whether the target data is data stored in the TP-VOL 81 or data stored in the real logical volume (S1013).

In the case of a real logical volume (S1013; No), the processor 11 acquires the address of the physical storage device 31 corresponding to the logical address of the logical volume specified by the target command, and advances the processing to S1017. On the other hand, when the target data is TP-VOL 81 (S1013; Yes), the processor 11 retrieves the mapping information in the memory 12 to obtain the address of the physical volume 85, and further stores the physical storage of the destination from the obtained address. The address of the device 31 is acquired (S1015).

The processor 11 generates a drive command based on the acquired address of the physical storage device 31 and transmits it to the destination physical storage device 31 (S1017). Then, the processor 11 changes the flag of the target data to a flag indicating that the data is already written in the physical volume (clean data).

In the above process, the processor 11 creates mapping information when it receives a write command. As a result, even in the case of a write process to a volume with complicated address conversion such as TP-VOL85, the volume address can be acquired from the mapping information by the back-end process performed asynchronously with the write command. As a result, the drive command designating the destination address can be transmitted to the physical storage device 31.

Through the above processing, the target command is registered in the temporary queue 125, and the ACC 22 acquires and analyzes the target command, thereby allocating the processing following the ACC 22 or the processor 11, thereby reducing the load on the first and second controllers. Can be distributed.

FIG. 7 is a diagram for explaining a volume configuration of a storage apparatus having a TP function.

This storage device manages the TP-VOL 81, the pool 83, and the physical volume 85. The physical volume 85 is a logical volume based on one or more physical storage devices 31. A plurality of physical volumes 85 can be registered in the pool 83. The total capacity of the registered physical volumes 85 becomes the total capacity of the pool 83.

By registering the physical volume 85 in the pool 83, write processing can be performed. The registration of the physical volume 85 is performed by allocating the storage area of the physical volume 85 to the unallocated storage area of the pool 83, respectively.

In the case of a real logical volume, the capacity depends on the capacity of the physical volume corresponding to the real logical volume (and hence the capacity of the physical storage device 31 that is the basis), but in the case of the TP-VOL 81, the capacity is the physical volume. There is an advantage that it can be set freely without depending on the capacity of the volume 85.

However, therefore, the storage area of the TP-VOL 81 and the storage area of the physical volume 85 cannot be associated in advance. Accordingly, the correspondence between the address of the physical storage device 31 that is the source of the physical volume 85 and the logical address of the TP-VOL 81 cannot be registered in the address conversion table 121 in advance. For this reason, mapping information creation processing is required for the write processing.

FIG. 8 is a diagram for explaining the mapping information creation process.

The mapping information creation process is a process performed as a pre-process when the processor 11 causes the ACC 22 to execute the write process in the above-described write-through determination (see S707 in FIG. 9). The mapping information creation process and the mapping information search are processes included in the first write process.

The mapping information creation process is described below. The storage area of each volume (TP-VOL 81, pool 83, and physical volume 85) is managed, for example, in units of pages (not shown). For example, storage areas can be easily managed by managing pages of each volume with the same capacity. However, the pages of each volume need not be managed with the same size as long as they can be associated with each other.

The mapping information creation process is a process for creating mapping information in which a write target TP-VOL 81 page and a physical volume 85 page are associated with each other. The processor 11 stores the created mapping information in the memory 12. Specifically, the processor 11 associates the page of the write target TP-VOL 81 with the empty page of the pool 83 (not shown). The empty page here is a page that is already assigned to the page of the physical volume 85 and is not associated with the page of the TP-VOL 81. By associating the write target TP-VOL 81 page with the pool 83 page, the write target TP-VOL 81 page and the physical volume 85 page are associated with each other.

When writing the data “A”, “B”, “C”, and “D” to each page of the TP-VOL 81 to be written, the processor 11 performs mapping information creation processing on each page of the TP-VOL 81. Thus, by assigning each page of the pool, each page of the physical volume 85 corresponding to each page can be associated with each page of the TP-VOL 81. After the mapping information creation processing, data “A”, “B”, “C”, and “D” are stored in the pages of the physical volume 85 that are associated with the pages of the TP-VOL 81, respectively.

FIG. 6 is a diagram for explaining the outline of the re-offload process.

As described above, the re-offload process is performed when the processor 11 determines that the load on the cache area is higher than a preset threshold value in the write determination process.

In the re-offload processing, the processor 11 performs preprocessing for causing the ACC 22 to execute write processing ((1) -1; preprocessing in the figure). When the write target is TP-VOL, this pre-processing is processing for acquiring the volume address of the physical volume corresponding to the logical address specified by the target command. This pre-processing can be realized by the flow shown in FIG. 14 by using the mapping information creation processing and mapping information search processing of FIG. 10, and the processing time is constant regardless of the cache load and can be processed in a very short time. It is.

Next, the processor 11 registers the correspondence between the destination logical address and the acquired address in the address conversion table 121 ((1) -2 in the figure; address conversion table update). Next, the processor 11 registers the target command in the temporary queue 125 ((1) -3 in the figure; target command re-registration).

When the ACC 22 acquires the target command from the temporary queue 125 by the re-offload process described above ((2) in the figure), the distribution process 500 for the target command is executed again. At this time, the destination logical address of the target command is registered in the address conversion table 121. That is, since the correspondence between the logical address of the destination and the address of the physical storage device 31 is registered, the ACC 22 can execute the write process for the target command by the distribution process. Accordingly, the ACC 22 transmits a write data storage instruction corresponding to the target command to the physical storage device 31 ((3) in the figure; write data storage instruction).

Even when the logical address of the destination of the target command is not registered in the address conversion table 121, that is, even for write processing for a volume that requires storage-specific operations such as TP-VOL, write processing is performed by re-offload processing. It is possible to cause the ACC 22 to execute a part of That is, the processor 11 registers the destination logical address in the address conversion table and registers the target command in the temporary queue 125 again, so that the ACC 22 can execute the target command again. The re-offload process is a process that has a constant processing time and a relatively short time regardless of the load on the cache area. With this re-offload process, the write process can be executed by the ACC 22.

The re-offload process can reduce the load on the cache area and prevent the host response time of the target command from increasing due to the high load on the cache area. Further, it is possible to dynamically determine whether or not re-offload is necessary based on the current state of the system such as the load on the cache area, and write processing can be performed with the optimum route at that time.

FIG. 14 is an example of a flowchart of the re-offload process.

The processor 11 analyzes and determines whether or not the target command is a write command to the TP-VOL (S1401).

When the target command is a command other than the write command for the TP-VOL 81 (S1401; No), the processor 11 advances the process to S1409. On the other hand, when the target command is a write command for the TP-VOL 81 (S1401; Yes), the processor 11 determines whether or not the logical address (target logical address) of the logical volume specified by the target command has already been registered in the mapping information. Is determined (S1403).

When the target logical address is not yet registered in the mapping information (S1403; No), the processor 11 executes a mapping information creation process (S1405). For example, the processor 11 acquires the volume address of the physical volume 85 corresponding to the logical address of the logical volume specified by the target command, and acquires the address of the physical storage device 31 from the acquired volume address. Then, the processor 11 creates mapping information for associating these, and stores them in the memory 12. Next, the processor 11 advances the process to S1409.

On the other hand, when the target logical address is registered in the mapping information (S1403; Yes), the processor 11 searches the mapping information and specifies the cache area corresponding to the logical address specified by the target command (S1407). Next, the processor 11 advances the process to S1409.

The processor 11 updates the address conversion table 121 by registering the correspondence between the logical address of the logical volume and the address of the physical storage device 31 in the address conversion table 121 (S1409). Next, the processor 11 re-registers the target command in the temporary queue 125 (S1411), and ends the process.

By the re-offload process, the volume address of the physical volume 85 corresponding to the logical address of the logical volume (TP-VOL 81) specified by the target command can be acquired in the write process. That is, the processor 11 acquires the address of the physical storage device 31 from the acquired volume address, and registers the correspondence between the logical address of the TP-VOL 81 and the address of the physical storage device 31 in the address conversion table, so that the target command However, even if it is a write command for the TP-VOL 81, the ACC 22 can execute the write process for the logical address of the designated logical volume.

Further, when the processor 11 re-registers the target command in the temporary queue 125, the distribution processing is performed again by the ACC 22. Thereby, regarding the write process of the target command, the processor 11 can cause the ACC 22 to execute the process, and can reduce the load on the cache area. *

The sharing of each process is shown in FIG. When the logical address specified by the write command is registered in the address conversion table 121, the write processing is performed by the ACC 22. The logical address registered in the address conversion table 121 is usually a logical address of a logical volume that does not require a specific operation of the storage apparatus. In such a case, the ACC 22 itself can perform the process. Specifically, the ACC 22 generates a drive command and transmits it to the SAS controller 23. When the destination physical storage device 31 is a component of a RAID group, it is necessary to update the parity data of the parity group including the write data by writing the write data to the physical storage device 31. This generation of parity data is performed by the ACC 22.

If the logical address specified by the write command is not registered in the address conversion table 121, the processor 11 performs the write process in principle. A logical address that is not registered in the address conversion table 121 is usually a logical address of a logical volume that requires a specific operation of the storage apparatus. As described above, when a complicated operation is required for the write process, the ACC 22 can request the processor 11 to perform the process by registering the write command in the micro request queue 123 different from the temporary queue 125. . Specifically, the processor 11 generates a drive command and transmits it to the destination physical storage device 31. The parity data is generated by the processor 11.

The processor 11 can perform a write-through determination process on the write command acquired from the micro request queue 123. If the load on the cache area corresponding to the logical address specified by the write command is higher than the threshold, the processor 11 acquires the address of the physical volume corresponding to the logical address, registers it in the address conversion table 121, and writes the write address. The command is registered in the temporary queue 125 again. As a result, the processor 11 can request the ACC 22 to perform a write process for the write command again. Specifically, the ACC 22 generates a drive command and transmits it to the physical storage device 31. The generation of parity data is performed by the ACC 22, but may be performed by the physical storage device 31.

In this way, even for a logical volume that requires operations specific to the storage apparatus, the address of the physical storage device 31 corresponding to the logical address is acquired, and the association is registered in the address conversion table. Since the processor 11 takes charge of the processing of the copy section, the write processing can be requested to the ACC 22. In particular, when the load of the cache area is high, such as the cache area usage rate or IOPS, the ACC 22 performs the write process, thereby reducing the host response time in the write process.

In particular, in the case of a virtual logical volume such as TP-VOL as described above, the processor 11 associates the logical address with the physical volume address by creating mapping information when a write command is transmitted. As a result, as in the case of the real logical volume, the address of the physical storage device 31 can be acquired from the volume address, and the ACC 22 can perform the write process on the TP-VOL 81 as well.

In the write-through determination process, when the load on the cache area corresponding to the logical address specified by the write command is equal to or less than the threshold, the processor 11 performs the write process (first write process). As described above, when storing the write data in the cache area does not affect the processing time of the write process, the processor 11 that has acquired the write command performs the write process, thereby performing a smooth process. It is carried out.

Further, by using information such as a cache area usage rate and IOPS measured by the processor 11 as the load of the cache area, the load on the processor 11 can be reduced by this measurement.

A write process (hereinafter referred to as a second write process) according to the second embodiment will be described. The second write process is a process performed by the processor 11 instead of the first write process (see S720 in FIG. 9 and FIG. 10). In the second write process, sequential determination is performed on the write command.

In the sequential determination, it is determined whether or not the write command acquired by the processor 11 is a command for data to be sequentially accessed. Sequentially accessed data is data that is continuously transmitted from the host computer and stored in a continuous area of the physical volume. For example, this determination is based on a known method such as determination based on past statistical information. When the processor 11 determines that the write command is for sequentially accessed data, the processor 11 can predict the total data size of write data that is continuously transmitted.

FIG. 11 is a diagram illustrating the second write process. In the front-end job, the processor 11 generates a metadata that is management information of the target write data (target data) and assigns the data set assigned to the target data to the logical address (target logical address) of the target data. Is stored in the cache area (upper side in FIG. 11). Then, the processor 11 performs sequential determination. If the target data is data that is sequentially accessed, the processor 11 estimates the logical address specified by the write command following the target command. Then, the processor 11 generates metadata (additional metadata) to be added to the write data following the target data based on the estimated logical address, and stores the additional metadata in the cache area corresponding to the estimated logical address. (Bottom of FIG. 11). Thereafter, in the back-end job, the processor 11 generates a drive command designating the target logical address and the address of the physical storage device 31 corresponding to the estimated logical address, and transmits the drive command to the destination physical storage device 31.

By the second write process for the target command, the physical storage device 31 can store the target data and the metadata data set in addition to the additional metadata in a storage area continuous thereto. . In the second write process, the processor 11 bears additional functions such as generation of metadata and additional metadata. In this way, by limiting the function of the ACC 22 and sharing roles with the processor 11, the write process can be made faster. Hereinafter, the second write process for the target command will be specifically described.

FIG. 12 shows an example of a flowchart of the second write process.

The processor 11 executes a front-end job (S1201). The front-end job of the present embodiment generates target data metadata (target metadata) in addition to the steps S1001 to S1007 in FIG. In the front-end job, the processor 11 stores a data set obtained by adding the target metadata to the target data in a cache area corresponding to the logical address (target logical address) specified by the target command.

The processor 11 determines whether or not the target data is data that is sequentially accessed (S1205).

When the target data is data to be sequentially accessed (S1205; Yes), the processor 11 thereafter generates additional metadata of one or more write data (hereinafter, additional data) transmitted following the target data. (S1207). Specifically, the processor 11 estimates the logical address range of the logical volume specified by the subsequent write command from the data size of one or more additional data, and based on the estimated logical address range, one or more additional meta data. Create data. Then, the processor 11 stores these additional metadata in a cache area corresponding to the estimated logical address range. The processor 11 acquires the address range of the physical storage device 31 corresponding to the estimated logical address range. Then, the association of these address ranges is registered in the address conversion table 121 (S1209). In this case, the processor 11 may associate the physical volume address with each logical address specified by each write command.

Thereafter, the processor 11 performs a back-end job (S1211). The back-end job in this case is approximately as described in S1010 to S1019 of FIG. At this time, the processor 11 transmits to the destination physical storage device 31 a drive command instructing to write the target data with metadata and the additional metadata to the physical storage device 31. As a result, the physical storage device 31 stores the data set to which one or more additional metadata is added in the designated address range of the physical volume.

On the other hand, when the target data is not sequential data (S1205; No), the processor 11 performs a back-end job (S1211). The back-end job in this case is as described in S1010 to S1019 of FIG.

By performing the sequential determination by the second write process, it is possible to cause the ACC 22 to execute a part of the write process for the sequentially transmitted data that is transmitted continuously.

Specifically, when the target data is sequential data, the additional metadata to be added to the additional data is generated by the processor 11 in the second write process of the target data, and is added to the data set including the target data and the metadata. And stored in the cache area. Thereby, the additional metadata is transmitted to the physical storage device 31 together with the data set, and stored in the physical storage device 31. Then, the processor can register the correspondence between the estimated logical address range and the physical volume address range in the address conversion table 121. Thereby, the processor 11 performs the write processing of the target data, and the ACC 22 can execute the write processing for the write data following the target data.

For the write command transmitted following the target command, the specified logical address is registered in the address conversion table 121, so that the ACC 22 can execute the process. When the ACC 22 transmits the additional data to the physical storage device 31, the physical storage device 31 can store the additional data in the storage area specified by the command. At this time, since additional metadata is already stored in the storage area specified by the command, the data set of the additional data is stored in the corresponding storage area of the physical storage device. The generation of parity data is performed by the processor 11 for the target data, and the ACC 22 for the subsequent write data (see FIG. 13).

In this embodiment, the processor 11 performs the second write process after the write-through determination process 700, but the order of these may be any. That is, the processor 11 may perform the second write process without executing the write-through determination process 700. Further, the processor 11 may perform a write-through determination process on a command determined as a data write command that is not sequential access in the second write process.

Although several embodiments have been described above, this is an example for explaining the present invention, and is not intended to limit the scope of the present invention only to these embodiments. The present invention can be implemented in various other forms.

DESCRIPTION OF SYMBOLS 10 ... 1st storage controller 11 ... Processor 12 ... Memory 20 ... 2nd storage controller 21 ... Switch 22 ... Accelerator 23 ... Control controller 24 ... Front end interface 31 ... Control device

Claims

A physical storage device;
A controller connected to the physical storage device;
With
The controller is
A front-end interface connected to the host computer;
A processor connected to the front-end interface and the physical storage device and providing a logical volume based on the physical storage device to the host computer;
A memory connected to the processor;
A control device connected to the front-end interface, the memory, and the processor;
Have
The memory includes logical / physical conversion information that associates a logical area in the logical volume and a device area that is a storage area provided by the physical storage device, and a write received from the host computer by the front-end interface. A first queue for sequentially storing commands, a second queue different from the first queue, and a cache area,
The control device acquires a first write command in the first queue, determines whether or not the first logical area specified by the first write command is registered in the logical-physical conversion information,
When the first logical area is registered in the logical-physical conversion information, the control device specifies a first device area corresponding to the first logical area based on the logical-physical conversion information,
The control device instructs the physical storage device to write the first write data received by the front-end interface based on the first write command to the first device area.
When the first logical area is not registered in the logical-physical conversion information, the control device registers the first write command in the second queue,
The processor acquires the first write command from the second queue, acquires a load status of the cache area,
The processor determines whether the load status is higher than a preset threshold;
When the load status is higher than the threshold, the processor selects the first device area from the physical storage device, associates the first logical area with the first device area, and converts the logical-physical conversion information. And re-register the first write command in the first queue,
Storage device.
When the load status is below the threshold,
The processor stores the first write data received by the front end interface based on the first write command in a first cache area corresponding to the first logical area;
The processor selects the first device region from the physical storage device;
The processor instructs the physical storage device to write the first write data in the first cache area to the first device area;
The storage apparatus according to claim 1.
The logical volume is a virtual logical volume,
The processor associates the device area with the pool area in the pool by registering a volume based on the physical storage device in the pool,
The processor selects a first pool area corresponding to the first device area from the pool, and assigns the first pool area to the first logical area, thereby causing the first device to move from the physical storage device. Select an area,
The storage apparatus according to claim 2.
The physical storage device is a nonvolatile semiconductor storage device,
The storage device according to claim 3.
The processor acquires the usage rate of the cache area as the load status.
The storage apparatus according to claim 4.
When the load status is less than or equal to the threshold, the processor generates first metadata that is management information of the first write data received by the front end interface based on the first write command,
The processor stores a data set obtained by adding the first metadata to the first write data in a first cache area corresponding to the first logical area,
The processor selects the first device region from the physical storage device;
The processor determines whether the first write command is a sequential access;
When it is determined that the first write command is a sequential access, the processor stores second write data specified by a second write command transmitted from the host computer following the first write command. Estimate the second logical area,
The processor generates second metadata that is management information of the second write data based on the estimation, stores the second metadata in a second cache area corresponding to the second logical area,
The processor selects a second device area, which is an area continuous with the first device area, from the physical storage device, and associates the second logical area with the second device area in the logical-physical conversion information. Register,
The processor writes the data set stored in the first cache area and the second metadata stored in the second cache area to the first device area and the second device area; Instruct the physical storage device,
The storage apparatus according to claim 1.
The control device obtains the second write command from the first queue, determines whether or not the second logical area specified by the second write command is registered in the logical-physical conversion information,
When the second logical area is registered in the logical-physical conversion information, the control device specifies the second device area corresponding to the second logical area based on the logical-physical conversion information,
The control device instructs the physical storage device to write the second write data received by the front-end interface to the second device area based on the second write command;
The storage apparatus according to claim 6.
A physical storage device;
A controller connected to the physical storage device;
With
The controller is
A front-end interface connected to the host computer;
A processor connected to the front-end interface and the physical storage device and providing a logical volume based on the physical storage device to the host computer;
A memory connected to the processor;
A control device connected to the front-end interface, the memory, and the processor;
Have
The memory includes logical / physical conversion information that associates a logical area in the logical volume and a device area that is a storage area provided by the physical storage device, and a write received from the host computer by the front-end interface. A first queue for sequentially storing commands, a second queue different from the first queue, and a cache area,
The control device acquires a first write command in the first queue, determines whether or not the first logical area specified by the first write command is registered in the logical-physical conversion information,
When the first logical area is registered in the logical-physical conversion information, the control device specifies a first device area corresponding to the first logical area based on the logical-physical conversion information,
The control device instructs the physical storage device to write the first write data received by the front-end interface based on the first write command to the first device area.
When the first logical area is not registered in the logical-physical conversion information, the control device registers the first write command in the second queue,
The processor acquires the first write command from the second queue, and receives first metadata that is management information of the first write data received by the front end interface specified by the first write command. Generate and
The processor stores a data set obtained by adding the first metadata to the first write data in a first cache area corresponding to the first logical area,
The processor selects the first device region from the physical storage device;
The processor determines whether the first write command is a sequential access;
When it is determined that the first write command is a sequential access, the processor stores second write data specified by a second write command transmitted from the host computer following the first write command. Estimate the second logical area,
The processor generates second metadata that is management information of the second write data based on the estimation, stores the second metadata in a second cache area corresponding to the second logical area,
The processor selects a second device area, which is an area continuous with the first device area, from the physical storage device, and associates the second logical area with the second device area in the logical-physical conversion information. Register,
The processor writes the data set stored in the first cache area and the second metadata stored in the second cache area to the first device area and the second device area; Instruct the physical storage device,
Storage device.
The control device obtains the second write command from the first queue, determines whether or not the second logical area specified by the second write command is registered in the logical-physical conversion information,
When the second logical area is registered in the logical-physical conversion information, the control device specifies the second device area corresponding to the second logical area based on the logical-physical conversion information,
The control device instructs the physical storage device to write the second write data received by the front-end interface to the second device area based on the second write command;
The storage device according to claim 8.
A write control method for a controller connected to a physical storage device and a host computer,
Providing a logical volume based on the physical storage device to the host computer using a processor in the controller;
Logical-physical conversion information that associates a logical area in the logical volume and a device area that is a storage area provided by the physical storage device, and a write command received from the host computer by the front-end interface in the controller And a second queue different from the first queue, and stores in a memory in the controller,
Using a control device in the controller,
Obtaining a first write command in the first queue, determining whether or not the first logical area designated by the first write command is registered in the logical-physical conversion information;
When the first logical area is registered in the logical-physical conversion information, a first device area corresponding to the first logical area is specified based on the logical-physical conversion information,
Instructing the physical storage device to write the first write data received by the front-end interface to the first device area based on the first write command,
If the first logical area is not registered in the logical-physical conversion information, register the first write command in the second queue,
Using the processor,
Obtaining the first write command from the second queue, obtaining a load status of the cache area;
Determining whether the load status is higher than a preset threshold;
When the load status is higher than the threshold, select the first device area from the physical storage device,
Registering the first logical area and the first device area in association with the logical-physical conversion information;
Re-registering the first write command with the first queue;
A method comprising that.