WO2017166284A1 - Composé de moulage avec perles enrobées - Google Patents

Composé de moulage avec perles enrobées Download PDF

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Publication number
WO2017166284A1
WO2017166284A1 PCT/CN2016/078304 CN2016078304W WO2017166284A1 WO 2017166284 A1 WO2017166284 A1 WO 2017166284A1 CN 2016078304 W CN2016078304 W CN 2016078304W WO 2017166284 A1 WO2017166284 A1 WO 2017166284A1
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WO
WIPO (PCT)
Prior art keywords
coated beads
mold compound
chip
disposed
substrate
Prior art date
Application number
PCT/CN2016/078304
Other languages
English (en)
Inventor
Mao GUO
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/CN2016/078304 priority Critical patent/WO2017166284A1/fr
Publication of WO2017166284A1 publication Critical patent/WO2017166284A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Embodiments of the invention relate generally to a packaged integrated circuit devicesuch as a system-in-package and more particularly, but not exclusively, to a mold compound that protects integrated circuit structures.
  • SSDs Solid State Drives
  • NAND flash memory are just one type of integrated circuit (IC) technology that has proliferated in recent years, both in high performance enterprise storage applications and in consumer devices. To satisfy customer demand, much effort has been taken to decrease the form factor of IC devices while maintaining or improving their capabilities.
  • IC integrated circuit
  • FIG. 1 is a cross-sectional diagram illustrating elements of a system including a packaged integrated circuit device according to an embodiment.
  • FIG. 2 is a flow diagram illustrating elements of a method of manufacturing a packaged device according to an embodiment.
  • FIG. 3 shows cross-sectional views of processing to manufacture a packaged integrated circuit device according to an embodiment.
  • FIGs. 4A, 4B show cross-sectional views of respective packaged integrated devices each according to a corresponding embodiment.
  • FIG. 5 is a high-level functional block diagram illustrating features of a computing device in accordance with one embodiment.
  • FIG. 6 is an interposer implementing one or more embodiments.
  • FIG. 7 is a high-level functional block diagram illustrating features of a computing device built in accordance with an embodiment.
  • Embodiments discussed herein variously include techniques or mechanisms to protect integrated circuitry that is disposed in a mold compound (MC) of a packaged device.
  • a MC includes coated beads that mitigate exposure of an IC chip to electromagnetic radiation. Alternatively or in addition, such beads may mitigate exposure of such integrated circuitry to mechanical damage during mold processing. For example, a coating of the beads may help avoid scratching of passivation (and/or other) structures that might otherwise be caused by conventional mold compound materials.
  • packaged IC device refers to any of a variety of devices that comprise integrated circuitry that has been packaged.
  • a packaged IC device may include mold compound, one or more IC chips and, in some embodiments, a substrate to couple the one or more IC chips to each other and/or to a hardware interface.
  • a substrate e.g., comprising any of a variety of thin core or coreless structures
  • Such a substrate may include one or more layers of an insulator material and interconnect structures disposed therein.
  • the interconnect structures may provide for coupling of the IC chip to conductive contacts (such as pads, bumps or other such structures) that are disposed on an opposite side of the substrate.
  • Coated beads of an MC may serve as a substitute, at least in part, for any of a variety of one or more conventional shielding structures.
  • One technique for attaining smaller form factor devices is to package integrated circuitry in a relatively thin (lower z-height) amount of a mold compound.
  • thinner packaging tends to result in one or more IC dies of a packaged IC device being exposed to higher levels of electromagnetic radiation from a surrounding environment.
  • One source of such radiation is lasers that are typically used during production to mark an external surface of the packaged IC device.
  • Another source is X-rays and other highly energized radiation used in manufacturing processes to inspect circuit connectivity. This increased radiation exposure is more likely to damage, or otherwise affect the operation of, flash memory transistors and/or other active circuit elements of an IC die.
  • conventional package processing typically includes applying very high pressures while a mold compound is disposed around one or more IC chips. Mold compounds will often include a silica material that, when under such pressure, tends to scratch or otherwise damage relatively soft passivation regions disposed on or around integrated circuitry. As the demand for small form factor IC devices continues to grow, there is expected to be an increasing premium placed on incremental improvements to the reliability of packaged IC devices.
  • An MC may include one or more other materials in which coated beads of the MC are suspended.
  • a suspension media includes an epoxy resin.
  • a suspension media may have fluid characteristics during a molding process. Subsequently (e.g., after a curing of the MC) , such a suspension media may form a solid with coated beads of the MC.
  • a suspension material may function as a binder to mechanically and/or chemically aid the coated beads in the formation of support structures within a package mold. For example, a suspension material may reinforce an arrangement of coated beads in the MC which aid in electromagnetic shielding of an IC chip.
  • Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc. ) , set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary.
  • mobile device and/or stationary device such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc. ) , set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the
  • the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a package comprising amold compound including coated beads.
  • FIG. 1 shows features of a system 100 including a package material according to an embodiment.
  • System 100 may include, or function as a component of, a computer (e.g., a server, desktop computer, laptop computer, tablet or the like) , smart phone or any of a variety of other hardware platforms including a packaged IC device.
  • a computer e.g., a server, desktop computer, laptop computer, tablet or the like
  • smart phone or any of a variety of other hardware platforms including a packaged IC device.
  • system 100 includes a packaged device 110 comprising one or more IC chips (as represented by the illustrative IC chip 114) , an interface 118 and a substrate 116 coupling the one or more IC chips to interface 118.
  • IC chip 114 may include a system-on-chip (SoC) or any of various other circuitry comprising processor logic, memory logic, controller logic and/or the like.
  • SoC system-on-chip
  • packaged device 110 comprises one or more additional and/or different IC chips.
  • IC chip 114 and interface 118 may be variously coupled, directly or indirectly, on opposite sides of substrate 116.
  • Interface 118 may include input/output (I/O) contacts (e.g., including conductive pads, bumps, pins and/or other such structures) to enable access to IC chip 114 via substrate 116.
  • Substrate 116 may include one or more layers of an insulator material and interconnect structures–e.g., including conductive vias, traces and/or the like–disposed therein. Such interconnect structures may aid in providing access to IC chip 114 via interface 118.
  • substrate 116 may include a laminate core or, alternatively, a monolithic core–e.g., where substrate 116 includes a thin core.
  • substrate 116 includes structures adapted from any of various conventional coreless substrate designs.
  • a package material of device 110 includes a mold compound (MC) 112 disposed on–e.g., around–one or both of IC chip 114 and substrate 116.
  • MC 112 may include coated beads that, during and/or after manufacture of packaged device 110, aid in mitigating damage to IC chip 114.
  • MC 112 may include a media 134 and beads 132 suspended therein (as illustrated in the detail view of a region 130) .
  • beads refers to spheroid–e.g., ellipsoid–structures that each comprise a core and a coating disposed around the core. Such beads may vary from one another with respect to size, shape and/or materials.
  • a core of a bead may include a conductor (e.g., comprising one or more metals) and the coating may comprise a different material that, as compared to the conductor, is more electrically insulating and/or softer.
  • the bead shown in inset 140 includes a core 142 and a coating 144 disposed around core 142.
  • the conductive cores of beads 132 may contribute to an overall electrical shielding characteristic of MC 112. Such shielding may mitigate exposure of IC chip 114 to electromagnetic radiation that might enter MC 112 from an environment near system 100. Moreover, the coatings of beads 132 may, due to their relative softness, mitigate damage to IC chip 114 that might otherwise be caused by the cores during packaging that compresses and/or otherwise disposes MC 112 on and around IC chip 114. Alternatively or in addition, the coatings of MC 112 may prevent conductive cores of beads 132 from shorting out integrated circuitry of IC chip 114.
  • core 142, and/or other cores of beads 132 may include iron, copper, zinc, aluminum and/or any of various other suitable metals.
  • Bead coating 144, and/or other coatings of beads 132 may include any of a variety of materials that are insulative and/or soft–e.g., as compared to the beads’ cores.
  • a coating material may comprise any of various polymers including, but not limited to, polyimide, polyethylene terephthalate (PET) and/or the like.
  • a coating material has a dielectric constant that is equal to or more than 3.0–e.g., wherein the dielectric constant that is equal to or more than 3.2 and, in some embodiments, equal to or more than 3.4.
  • a coating material may be deformable (soft) to mitigate damage that might otherwise result from the MC being disposed on and/or pressured against integrated circuitry.
  • PET has a Rockwell hardness of M94-101
  • polyimide has a Rockwell hardness of E52-99.
  • other insulative coating materials may be softer or harder, in various embodiments, provided any such coating material is softer than the conductive core it surrounds.
  • Formation of beads 132 may include operations adapted, for example, from processing used in the pharmaceutical industry–e.g., where such processing is to coat particles of a fine powder with a sprayed insulator material that is dispensed in a rotating chamber.
  • processing is to coat particles of a fine powder with a sprayed insulator material that is dispensed in a rotating chamber.
  • the particular techniques for coating such particles are not detailed herein to avoid obscuring certain features of some embodiments.
  • system 100 may further include, or couple to, a support structure for packaged device 110, such as the illustrative printed circuit board 120.
  • Printed circuit board 120 may aid in coupling of packaged device 110–e.g., via I/O contacts of an interface 122–to hardware, software, a user interface and/or any of various other such mechanisms (not shown) that are included in, or are to couple to, system 100.
  • FIG. 2 shows features of a method 200 for producing a packaged circuit device according to an embodiment.
  • Method 200 may produce a device having some or all of the features of packaged device 110, for example.
  • method 200 includes, at 210, forming contacts on a first side of a substrate such as substrate 116.
  • interface 118 may include some or all of the contacts formed at 210.
  • the forming at 210 includes semiconductor processing (such as one or more mask, photolithography, etch, metal deposition and/or other fabrication operations) adapted from conventional techniques for building respective conductive contacts on a substrate and on one or more IC chips. Some embodiments are not limited with respect to such techniques, which are not detailed herein to avoid obscuring certain features of various embodiments.
  • Method 200 may further comprise, at 220, coupling an integrated circuit (IC) chip to the contacts via a second side of the substrate–e.g., where the second side is opposite the first side.
  • the coupling at 220 may include, for example, wire bonding the IC chip to the substrate in addition to adhering or otherwise mechanically attaching the IC chip to the substrate.
  • one or more additional IC chips may be variously coupled directly or indirectly to the substrate–e.g., where multiple IC chips are arranged in a side-by-side configuration or a stacked configuration.
  • the one or more additional IC chips may each be mechanically attached, directly of via another IC chip, to the substrate–e.g., in addition to being wire bonded to the substrate and/or another IC chip.
  • the coupling at 220 includes only indirectly coupling the IC chip to the substrate.
  • the IC chip may itself be part of a first package device prior to the coupling at 220–e.g., wherein method 200 is to fabricate a package-in-package IC device which includes the first packaged device.
  • the coupling at 220 may be part of operations that variously surface mount (for example) a packaged NAND memory, a controller and one or more passive circuit components onto the substrate. Any of a variety of conventional chip stacking, wire bonding, surface mounting and/or other techniques may be adapted to perform the coupling at 220.
  • Method 200 may further comprise, at 230, packaging the IC chip with a mold compound which includes a suspension media and coated beads disposed therein.
  • the packaging at 230 may be performed after the coupling at 220, for example.
  • the packaging at 230 includes disposing the mold compound at least partially around the IC chip–e.g., using operations adapted from any of a wide range of conventional encapsulation techniques such as resin transfer molding, sheet molding and/or the like.
  • suspension media may be adapted from any of a wide range of conventional package materials.
  • examples of such materials include, but are not limited to, an epoxy resin, such as biphenyl or modified biphenyl, and/or any of various filler materials such as a silica, thermally conductive aluminum nitride (AlN) and boron nitride (BN) and/or other additives such as mold release agents, surfactants, etc.
  • Some or all coated beads of the mold compound may mitigate damage to integrated circuitry during or after the packaging at 230.
  • coated beads of the mold compound may each include a conductive core and a coating including an insulation material.
  • Beads of the mold compound may have an average cross-sectional width (e.g., a diameter) in a range from 10 micrometers ( ⁇ m) to 100 ⁇ m–e.g., wherein an average volume of beads is within a range from 400 ⁇ m 3 to 2000000 ⁇ m 3 .
  • such beads may have an eccentricity of 0.9 or less.
  • the average thickness of a layer of coating material on the beads is in a range from 2 ⁇ m 3 to 5 ⁇ m 3 .
  • these parameters of coated beads are merely illustrative, and may vary significantly in different embodiments, according to implementation-specific details.
  • a fractional proportion of coated beads in the mold compound may contribute to electrical shielding and/or other mechanical properties that provide for improved protection of integrated circuitry.
  • beads may comprise 35% or more of a mold compound by volume. Such beads may comprise, for example, between 50% and 80% of the mold compound by volume. In some embodiments, a mold compound comprises between 60% and 75% beads by unit volume.
  • the fractional proportional of coated beads in a mold compound may vary significantly in various embodiments.
  • method 200 may include one or more additional operations (not) shown to provide a packaged device and/or connectivity thereof. Such additional operations may include, for example, metallization processes to form a ball grid array or other conductive contacts of a hardware interface. Additionally, method 200 may further include singulation operations to separate two or more packaged devices from one another. In some embodiments, method 200 couple the packaged IC device to a printed circuit board or other external structure.
  • FIG. 3 shows cross-sectional views illustrating respective stages 300, 302 of processing to fabricate a packaged integrated circuit device according to one embodiment.
  • the processing represented in FIG. 3 may include operations of method 200–e.g., where such processing is to fabricate packaged device 100 at least in part.
  • an IC chip 320 may be bonded to an upper surface of a substrate 310–e.g., by a flip chip process.
  • substrate 310 includes a thin core or a coreless substrate, comprising layers of interconnections and vias, with one surface having conductive bumps or other contacts for electrical connection to corresponding contacts of IC chip 320.
  • the lower surface of the substrate 310 may comprise or have disposed thereon an array 340 of electrical connects, such as solder balls, serving as input/output electrical connections for the package.
  • an underfill material 330 may dispensed–e.g., at the edges of IC die 320–and allowed to seep to a space between the IC die 320 and substrate 310 by a capillary action.
  • a mold compound 350 may be disposed at least partially (e.g., in at least two dimensions) around IC chip 320 and/or substrate 310.
  • Deposition of mold compound 350 may include operations adapted from any of various conventional molding techniques such as injection molding, resin transfer molding, sheet molding and/or the like.
  • mold compound 350 includes coated beads that mitigate damage to structures such as those of IC chip 320 and/or substrate 310.
  • coated beads may be suspended in a media of mold compound 350 that, when cured, reinforces such beads. The beads may contribute to electrical shielding of mold compound 350, while at the same time mitigating scratching and/or electrical shorting at IC chip 320 and/or at substrate 310.
  • IC chip 320 is one of multiple IC chips that, for example, are arranged to form an IC stack configuration and/or a side-by-side IC chip configuration. Such IC chips may be variously wire bonded to each other and/or to substrate 310. The arrangement of such IC chips may be adapted, for example, from conventional chip stacking and wire bonding techniques.
  • IC chip 320 is surrounded by mold compound 350, but is not directly in contact with mold compound 350.
  • processing such as that illustrated by stages 300, 302 may manufacture a package-in-package device wherein a first packaged device—e.g., a packaged NAND memory device–is surface mounted or otherwise coupled, directly or indirectly, to substrate 310.
  • a first packaged device e.g., a packaged NAND memory device–is surface mounted or otherwise coupled, directly or indirectly, to substrate 310.
  • one or more other components e.g., another packaged device, any of various passive circuit elements, an application specific IC (ASIC) and/or the like.
  • Mold compound 350 may be subsequently disposed around the first packaged device and the one or more other components to form a package-in-package integrated circuit device.
  • FIGs. 4A, 4B show in cross-sectional view respective packaged IC devices 400, 450 each according to a corresponding embodiment.
  • packaged IC devices 400, 450 may include features of packaged device 110, for example.
  • performance of method 200 results in packaged IC device 400 and/or packaged IC device 450.
  • packaged device 400 includes a mold compound 430 and a stack 420 of IC dies disposed within mold compound 430.
  • a substrate 410 of packaged device 400 may facilitate coupling of stack 420 to other circuitry that is included in, or is to couple to, packaged device 400.
  • stack 420 may be adhered, or otherwise mechanically coupled, to a side 412 of substrate 410–e.g., wherein conductive contacts 416 of a hardware interface are disposed on an opposite side 414 of substrate 410.
  • Individual IC dies of stack 420 may be variously wire bonded or otherwise coupled directly or indirectly to one another. Alternatively or in addition, such IC dies may be coupled to contacts 416 via substrate 410.
  • To protect damage to integrated circuitry of stack 420–and in some embodiments, to further prevent an electrical short at such integrated circuitry–mold compound 430 may include coated beads having features variously described herein.
  • Packaged IC device 450 is one example of an embodiment including a package-in-package device which comprises a mold compound including coated beads.
  • a mold compound 480 of packaged IC device 450 may include coated beads to facilitate electrical shielding and/or other protection of integrated circuitry.
  • Mold compound 480 may be disposed on a substrate 460 and further disposed around components that are variously coupled, directly or indirectly, to a side 462 of substrate 460.
  • such components include a packaged device 470 and various other components 468 such as one or more passive circuit components, IC chips and/or the like.
  • the particular type, arrangement and number of component coupled at side 462 may vary, in different embodiments, according to implementation specific details.
  • a hardware interface 472 e.g., including surface mount contacts–may provide for coupling of packaged device 470 to side 462.
  • Conductive contacts 466 of another hardware interface may be disposed on a side 464 of substrate 410 which is opposite side 462.
  • Substrate 460 may variously provide for interconnection between packaged device 470, components 468 and contacts 466 may be variously coupled each other via interconnect structures (not shown) disposed in substrate 460.
  • FIG. 5 illustrates a computing device500in accordance with one embodiment.
  • the computing device500 houses a board502.
  • the board502 may include a number of components, including but not limited to a processor504 and at least one communication chip506.
  • the processor504 is physically and electrically coupled to the board502.
  • the at least one communication chip506 is also physically and electrically coupled to the board502.
  • the communication chip506 is part of the processor504.
  • computing device500 may include other components that may or may not be physically and electrically coupled to the board502.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM) , non-volatile memory (e.g., ROM) , flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD) , digital versatile disk (DVD) , and so forth) .
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor
  • the communication chip506 enables wireless communications for the transfer of data to and from the computing device500.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family) , WiMAX (IEEE 802.16 family) , IEEE 802.20, long term evolution (LTE) , Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device500 may include a plurality of communication chips506.
  • a first communication chip506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor504 of the computing device500 includes an integrated circuit die packaged within the processor504.
  • the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip506 also includes an integrated circuit die packaged within the communication chip506.
  • the computing device500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA) , an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device500 may be any other electronic device that processes data.
  • Some embodiments may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment.
  • a machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer) .
  • a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ( “ROM” ) , random access memory ( “RAM” ) , magnetic disk storage media, optical storage media, flash memory devices, etc. ) , a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc. ) ) , etc.
  • ROM read only memory
  • RAM random access memory
  • FIG. 6 illustrates an interposer 600 that includes one or more embodiments.
  • the interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604.
  • the first substrate 602 may be, for instance, an integrated circuit die.
  • the second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604.
  • BGA ball grid array
  • the first and second substrates 602, 604 are attached to opposing sides of the interposer 600.
  • the first and second substrates 602, 604 are attached to the same side of the interposer 600.
  • three or more substrates are interconnected by way of the interposer 600.
  • the interposer 600 may be formed of an epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612.
  • the interposer 600 may further include embedded devices 614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
  • FIG. 7 illustrates a computing device 700 in accordance with one embodiment.
  • the computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard.
  • the components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communication chip 708. In some implementations the communication chip 708 is fabricated as part of the integrated circuit die 702.
  • the integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM) .
  • eDRAM embedded DRAM
  • STTM or STTM-RAM spin-transfer torque memory
  • Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within anSoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM) , non-volatile memory 712 (e.g., ROM or flash memory) , a graphics processing unit 714 (GPU) , a digital signal processor 716, a crypto processor 742 (aspecialized processor that executes cryptographic algorithms within hardware) , a chipset 720, an antenna 722, a display or a touchscreen display 724, a touchscreen controller 726, a battery 729 or other power source, a power amplifier (not shown) , a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass) , a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, styl
  • the communications chip 708 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family) , WiMAX (IEEE 802.16 family) , IEEE 802.20, long term evolution (LTE) , Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 708.
  • a first communication chip 708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA) , an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • a packaged device comprises a substrate including a first side and a second side opposite the first side, wherein contacts are disposed on the first side, an integrated circuit (IC) chip disposed on the second side, the IC chip coupled to the contacts via the substrate, and a mold compound disposed at least partially around the IC chip, the mold compound comprising a suspension media and coated beads disposed in the suspension media, wherein the coated beads each include a conductive core and layer of an insulator material disposed around the conductive core.
  • IC integrated circuit
  • the conductive cores of the coated beads includes a metal, and wherein the insulator material is softer than the metal.
  • a dielectric constant of the insulator material is equal to or more than 3.0.
  • the dielectric constant is equal to or more than 3.2.
  • the dielectric constant is equal to or more than 3.4.
  • the coated beads are 35% or more of the mold compound by volume.
  • the coated beads are between 50% and 80% of the mold compound by volume.
  • the coated beads are between 60% and 75% of the mold compound by volume.
  • the conductive cores of the coated beads include iron, copper, zinc or aluminum.
  • the insulator material includes a polymer.
  • a method comprises forming contacts on a first side of a substrate, coupling an integrated circuit (IC) chip to the contacts via a second side of the substrate, the second side opposite to the first side, and while the IC chip is coupled to the contacts, packaging the IC chip, including disposing mold compound at least partially around the IC chip, the mold compound including a suspension media and coated beads disposed in the suspension media, wherein the coated beads each include a conductive core and layer of an insulator material disposed around the conductive core.
  • IC integrated circuit
  • the conductive cores of the coated beads includes a metal, and wherein the insulator material is softer than the metal.
  • a dielectric constant of the insulator material is equal to or more than 3.0.
  • the dielectric constant is equal to or more than 3.2.
  • the dielectric constant is equal to or more than 3.4.
  • the coated beads are 35% or more of the mold compound by volume.
  • the coated beads are between 50% and 80% of the mold compound by volume.
  • the coated beads are between 60% and 75% of the mold compound by volume.
  • the conductive cores of the coated beads include iron, copper, zinc or aluminum.
  • the insulator material includes a polymer.
  • a system comprises a packaged device including a substrate including a first side and a second side opposite the first side, wherein contacts are disposed on the first side, an integrated circuit (IC) chip disposed on the second side, the IC chip coupled to the contacts via the substrate, and a mold compound disposed at least partially around the IC chip, the mold compound comprising a suspension media and coated beads disposed in the suspension media, wherein the coated beads each include a conductive core and layer of an insulator material disposed around the conductive core.
  • the system further comprises a display device coupled to the packaged device, the display device to display an image based on signals exchanged with the IC chip.
  • the conductive cores of the coated beads includes a metal, and wherein the insulator material is softer than the metal.
  • a dielectric constant of the insulator material is equal to or more than 3.0.
  • the dielectric constant is equal to or more than 3.2.
  • the dielectric constant is equal to or more than 3.4.
  • the coated beads are 35% or more of the mold compound by volume.
  • the coated beads are between 50% and 80% of the mold compound by volume.
  • the coated beads are between 60% and 75% of the mold compound by volume.
  • the conductive cores of the coated beads include iron, copper, zinc or aluminum.
  • the insulator material includes a polymer.
  • This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs) , random access memories (RAMs) such as dynamic RAM (DRAM) , EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne des techniques et des mécanismes pour réaliser un dispositif à circuit intégré (CI) en boîtier. Dans un mode de réalisation, un dispositif à CI en boîtier comprend un composé de moulage disposé au moins partiellement autour d'une puce de circuit intégré. Le composé de moulage comprend des perles enrobées en suspension dans un support qui doit contribuer au renforcement mécanique de ces perles enrobées. Une partie ou l'ensemble de ces perles enrobées comprennent chacune un noyau conducteur et un revêtement isolant entourant le noyau. Les noyaux contribuent à une propriété de blindage électrique du composé de moulage dans son ensemble. Les revêtements empêchent les noyaux conducteurs de court-circuiter le dispositif à CI en boîtier. Dans un autre mode de réalisation, une souplesse des revêtements atténue les dommages au circuit intégré pendant le traitement qui façonne et durcit le composé de moulage sur une puce de CI.
PCT/CN2016/078304 2016-04-01 2016-04-01 Composé de moulage avec perles enrobées WO2017166284A1 (fr)

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CN1665025A (zh) * 2004-03-05 2005-09-07 硕达科技股份有限公司 可避免电磁干扰的半导体封装件及其制法
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Publication number Priority date Publication date Assignee Title
US20220336370A1 (en) * 2018-07-30 2022-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding material with insulator-coated ferromagnetic particles
US11990423B2 (en) * 2018-07-30 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding material with insulator-coated ferromagnetic particles

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