WO2017164515A1

WO2017164515A1 - Address translation method for storage system and memory device controller for storage system

Info

Publication number: WO2017164515A1
Application number: PCT/KR2017/001702
Authority: WO
Inventors: 성윤제; 황병권
Original assignee: 주식회사 디에이아이오
Priority date: 2016-03-21
Filing date: 2017-02-16
Publication date: 2017-09-28
Also published as: KR20170109391A; KR101805828B1

Abstract

An address translation method for a storage system comprises: receiving a target logical address of data from an application; mapping the target logical address to a physical address of a physical storage area by using an address mapping table; and updating an address mapping table by dynamically changing a size of at least one of a plurality of mapping units constituting an entry of the address mapping table, on the basis of the continuity of the target logical address, after writing the data on the basis of the mapped physical address.

Description

Address Translation Methods for Storage Systems and Memory Device Controllers for Storage Systems

The present invention relates to a storage system, and more particularly, to a memory device controller included in the storage system and an address translation method of the storage system.

The flash memory device and the storage system including the same must include a mapping table that maps a logical memory address used by an application to a physical memory address used by the flash memory device. The memory device controller controlling the conversion converts between a logical memory address and a physical memory address using the mapping table.

Typical address mapping methods include a page mapping method, a block mapping method, or a hybrid mapping method by appropriately combining the page mapping and the block mapping. However, the page mapping method requires a large memory for storing the address mapping table because the size of the address mapping table increases, and the block mapping method has an efficiency of data writing speed due to a large mapping unit (ie, a mapping unit). Is lowered. In addition, since the hybrid mapping method requires a plurality of address mapping tables in which different mapping units are stored, management complexity is large and data structure (eg, address mapping table) search time is increased.

An object of the present invention is to provide an address translation method of a storage system that dynamically changes the size of a mapping unit based on the continuity of logical addresses to which data is written.

It is another object of the present invention to provide a memory device controller of a storage system that dynamically changes the size of a mapping unit based on the continuity of logical addresses into which data is written.

However, the object of the present invention is not limited to the above-described objects, and may be variously expanded within a range without departing from the spirit and scope of the present invention.

In order to achieve the object of the present invention, an address translation method of a storage system according to embodiments of the present invention receives a target logical address range of data applied from an application, and an address mapping table. The logical address included in the target logical address range is mapped to a physical address of a physical storage area using an address mapping table, and after the data is written based on the mapped physical address, the logical address is included in the target logical address range. Update the address mapping table by dynamically changing the size of at least one of a plurality of mapping units constituting an entry of the address mapping table based on the continuity of the logical addresses. Can be.

According to an embodiment, the size of each of the mapping units supported by the address mapping table may be 2 ^k to the minimum mapping unit size within a preset minimum mapping unit size to a preset maximum mapping unit size range, where k is Multiplied by zero or more).

According to an embodiment, the size of each of the mapping units may dynamically change in ^2k units within the preset range, and the sizes of all the mapping units may not be the same.

In example embodiments, the mapping units may be divided or fused based on a head logical sector address of each of the mapping units.

In example embodiments, the updating of the address mapping table may include fusion of logical addresses included in the target logical address range to change the target logical address range from first to nth, where n is a natural number of two or more. Classify the sub-target logical address ranges, wherein m is a natural number less than or equal to n, and determine the number of current mapping units including the sub-target logical address ranges, and wherein the m-th sub-target logical address range is single When included in a current mapping unit, splits the current mapping unit, and when the m-th sub-target logical address range overlaps a plurality of current mapping units, a position of the m-th sub-target logical address range and And determining a fusion mapping unit corresponding to the size to update the physical address corresponding to the fusion mapping unit.

According to an embodiment, dividing the target logical address range into the first to nth sub-target logical address ranges may determine a first logical sector address of the mth sub-target logical address range, and the first logical sector address. Calculate a second maximum size based on the sub-size, which is a value obtained by subtracting the size of the entire first to m-th sub-target logical address ranges from the size of the target logical address range; The method may further include fusing the logical addresses consecutive from the first logical sector address to a smaller one of the first maximum size and the second maximum size to determine the m th subtarget logical address range.

According to an embodiment, when the first logical sector address is expressed as a sum of powers of two, the first maximum size may correspond to the smallest value of powers of two.

According to an embodiment, when the subsize is expressed as a sum of powers of two, the second maximum size may correspond to the largest value of the powers of two.

According to an embodiment, the first logical sector address of the first target logical address range corresponds to the first logical sector address of the target logical address range, and the mth sub-target logic is excluded from the first target logical address range. The first logical sector address of the address range may correspond to the next logical sector address of the last logical sector address of the m-1 sub target logical address range.

According to an embodiment, the fusion mapping unit may include contiguous logical addresses and writable contiguous physical addresses corresponding to the logical addresses.

According to an embodiment, dividing the current mapping unit divides the current mapping unit including the m-th sub-target logical address range into half to generate divided current mapping units, and among the divided mapping units. And dividing one of the m-th target logical address ranges into half again.

According to an embodiment, repeating the dividing operation may terminate the division if the size of the divided mapping unit is equal to the size of the m-th sub-target logical address range, and perform the fusion mapping on the divided mapping unit. Can be determined in units.

According to an embodiment, the minimum mapping unit size may correspond to one sector, and the maximum mapping unit size may correspond to 2 ⁿ blocks, where n is a natural number.

According to an embodiment, the head logical sector address of each of the mapping units may change dynamically.

In order to achieve the object of the present invention, a memory device controller of a storage system according to an embodiment of the present invention may refer to an address mapping table to target logical address range of data received from an application. Maps a logical address included in the C) to a physical address of a physical storage area, writes the data based on the mapped physical address, and based on the continuity of the logical address included in the target logical address. It may include a Flash Translation Layer (FTL) for updating the address mapping table by dynamically changing the size of at least one of the plurality of mapping units constituting an entry (entry) have.

According to an embodiment, the flash conversion layer may dynamically change the size of each of the mapping units in ^2k units within the range.

The address translation method of a storage system according to embodiments of the present invention may perform address mapping using a single address mapping table (ie, mapping data structure) including mapping units of various sizes. Therefore, the disadvantage that the search time of the mapping data structure of the existing hybrid mapping scheme managing the plurality of address mapping tables is increased.

The memory device controller of the storage system according to embodiments of the present invention may perform address mapping using a single address mapping table (ie, mapping data structure) including mapping units of various sizes. In addition, since physical address information for a wide logical address area of a single block size or more may be included in an entry of one mapping table, a cache effect of contiguous data for address mapping within a limited size of volatile memory is improved. Therefore, data read performance can be improved.

However, the effects of the present invention are not limited to the above-described effects, and may be variously expanded within a range not departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a memory device controller for managing a storage system according to example embodiments of the inventive concepts.

FIG. 2A is a diagram illustrating an example of a structure of a mapping table controlled by the memory device controller of FIG. 1.

FIG. 2B is a diagram illustrating an example of mapping units supported in the mapping table of FIG. 2A.

3 is a flowchart illustrating an address translation method of a memory system according to example embodiments.

4 is a flowchart illustrating an example of an operation of updating a mapping table in the address translation method of FIG. 3.

FIG. 5 is a flowchart illustrating an example of dividing a target logical address range into a plurality of sub-target logical address ranges in the updating method of the mapping table of FIG. 4.

FIG. 6 is a diagram illustrating an example of sub-target logical address ranges of FIG. 5.

FIG. 7 is a diagram illustrating an example of an operation of updating a fusion mapping unit in the updating method of the mapping table of FIG. 4.

8 is a flowchart illustrating an example of dividing a mapping unit in the updating method of the mapping table of FIG. 4.

9 is a diagram illustrating an example of an operation of dividing a mapping unit of FIG. 8.

FIG. 10 is a diagram illustrating an example of an operation of dividing a mapping unit of FIG. 8.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

FIG. 1 is a block diagram illustrating a memory device controller for managing a storage system according to example embodiments. FIG. 2A is an example of a structure of an address mapping table controlled by the memory device controller of FIG. 1. 2B is a diagram illustrating an example of mapping units supported in the address mapping table of FIG. 2A.

1 to 2B, the memory device controller 100 may include a flash translation layer (FTL) 140.

The storage system including the memory device controller 100 may include a memory device controller 100, an application 10 connected to the memory device controller 100, and a flash memory device 20.

In an embodiment, the memory device controller 100 may further include a file system that provides an interface for writing data generated by the application 10 independently of the type of memory device.

The flash conversion layer 140 may provide an interface to the flash memory device 20 to write data to the flash memory device 20. The flash translation layer 140 may be provided with information of a target logical address of data provided from the application 10. The information of the target logical address may include a target logical address range and information of a logical address included therein. Here, the target logical address range means a range including logical addresses selected by a data write command among logical addresses set in an address mapping table. The flash translation layer 140 may map the target logical address to a physical address of a physical storage area by referring to an address mapping table. The flash translation layer 140 may write the data based on the mapped physical address. In addition, the flash translation layer 140 may dynamically adjust the size of the at least one of a plurality of mapping units constituting an entry of the address mapping table based on the continuity of the logical address. The address mapping table can be updated by changing the address mapping table. The physical address may correspond to a physical address used by the flash memory device 20. In an embodiment, the flash translation layer 140 may directly map a logical memory address to a physical memory address by referring to the address mapping table.

In an embodiment, the size of each of the mapping units supported by the address mapping table is 2k to the minimum mapping unit size within a range of a preset minimum mapping unit size to a preset maximum mapping unit size, where k is 0 or more. Multiplied by an integer). For example, according to the setting of the flash memory device 20, the minimum mapping unit size corresponds to 512 bytes equal to one sector size, and the maximum mapping unit size is 2n (where n is Natural number) memory blocks. For example, one page may include eight sectors, and one block may include 128 pages. However, as an example, the minimum mapping unit size and the maximum mapping unit size may be determined to be optimal sizes according to the memory system used.

As shown in FIG. 2A, the address mapping table may include mapping units of various sizes. For example, the address mapping table entry may include one sector mapping unit (1-SECTOR UNIT) consisting of a single sector, two sector mapping unit (2-SECTOR UNIT) in which two sectors are fused, and four sectors in which four sectors are fused. Sector mapping unit (4-SECTOR UNIT) and the like. In addition, the address mapping table may include a 1-page UNIT unit in which eight sectors are fused, and a 2-PAGE UNIT unit in which 16 sectors (ie, two pages) are fused. And 2k (where k is a natural number) page mapping units fused to super-page mapping units. In addition, the address mapping table may include super-block mapping units in which the super-page units are fused and block units (1-BLOCK UNIT) and 2j (where j is a natural number) are fused. It may include. The mapping table may include the logical address and the corresponding physical address for each sector. The address mapping table may have a mapping table for entries of a plurality of sectors constituting the mapping units.

Here, mapping units including two or more sectors (eg, 2-SECTOR UNIT, 4-SECTOR UNIT, 1-PAGE UNIT, etc.) Can guarantee a contiguous logical address and corresponding contiguous physical address. Thus, the mapping units comprising the two or more sectors may be defined by each head logical sector address (i.e. indicated by HEAD in FIG. 2a) and the subsequent logical sector address (i.e. indicated by NON_HEAD in FIG. 2a). Can be. Logical sector addresses NON_HEAD other than the head logical sector address may be referenced to return a physical address in an address query. For example, as shown in FIG. 2A, when data corresponding to a 2-page unit is continuously written, the head logical sector address of the 2-page unit is included. Two pages of data can be written to the storage area consecutively from the corresponding physical address.

The head logical sector address may be dynamically changed according to a mapping unit including a specific logical sector (ie, a logical sector address used for writing data). For example, when the size of the mapping unit including logical sector address 3 (S3) is 1 sector, the logical sector address 3 (S3) becomes the head logical sector address and the mapping includes logical sector 3 (S3). If the size of the unit is two sectors, logical sector address 2 (S2) may be the head logical sector address. Similarly, when the size of the mapping unit including logical sector address 3 (S3) is 4 sectors, logical sector 0 (S0) may be the head logical sector address. For example, when the data to be written indicates logical sector address 3 (S3), the head logical sector address of the mapping unit including sector address 3 (S3) is referred to by sector address 3 (S3), and A physical address corresponding to sector address 3 (S3) may be returned according to the offset of the head logical sector address and sector address 3 (s3).

In one embodiment, the flash translation layer 140 dynamically adjusts the size of at least some of the mapping units in 2k units within the range of the minimum mapping unit size to the maximum mapping unit size based on the continuity of the logical address indicated by the data. Can be changed. For example, as illustrated in FIG. 2B, the flash conversion layer 140 dynamically sizes the mapping units from one sector mapping unit S, which is the minimum mapping unit size, to j block mapping units, which is the maximum mapping unit size. Can change. That is, the mapping unit size is variously changed into a sector unit size (SUB_PAGE), a super page size (SUPER_PAGE), a super block size (SUPER_BLOCK), and the like based on the continuity of data to be written, and the size is not fixed for each logical address.

As described above, the memory device controller 100 may perform address mapping using a single address mapping table (ie, mapping data structure) including mapping units of various sizes. . In addition, physical address information for a wide logical address area of a block size or more may be written by using an entry of one mapping table by the mapping unit fusion, so that contiguous data for address mapping within a limited size of volatile memory may be written. The cache effect can be improved and data read performance can be improved.

Detailed operations of the flash translation layer 140 and methods of updating the address mapping table will be described in detail with reference to FIGS. 3 to 10.

Referring to FIG. 3, the address translation method of the memory system receives a target logical address range of data applied from an application (S100), and uses the address mapping table to convert the target logical address into a physical address of a physical storage area. After mapping to S200 and writing the data based on the mapped physical address S300, a plurality of mapping units constituting an entry of the address mapping table based on the continuity of the target logical address. The address mapping table may be updated (S400) by dynamically changing the size of at least one of them.

The target logical address range of the data may be input (S100). Here, the target logical address range means logical addresses selected by a data write command among logical addresses set in the address mapping table. For example, the logical address included in the target logical address range may correspond to one sector or a plurality of consecutive sectors.

The logical address included in the target logical address range may be mapped to the physical address by the address mapping table (S200). In one embodiment, a flash translation layer may map the logical address directly to the physical address. The size of each of the mapping units supported by the address mapping table is a value obtained by multiplying the minimum mapping unit size by 2k (where k is an integer of 0 or more) within a preset minimum mapping unit size to a preset maximum mapping unit size range. May correspond to For example, the minimum mapping unit size corresponds to one sector (i.e., sub-page size), and the maximum mapping unit size is 2j (where j is a natural number) blocks (i.e., super-block size). May correspond.

The data may be written (S300) based on the mapped physical address.

The size of at least one of the mapping units may be dynamically changed based on the continuity of logical addresses included in the target logical address range, so that the address mapping table may be updated (S400). In an embodiment, the size of each of the mapping units may change dynamically in 2k units within the set range. The size of each of the mapping units may vary based on the continuity of the logical address indicated by the written data (ie, the size of the target logical address range).

The update S400 of the address mapping table may determine at least one new fusion mapping unit by fusing logical addresses included in the target logical address range. The fusion mapping units may be determined based on sub-target logical address ranges in which the target logical addresses are divided. In one embodiment, the fusion mapping unit may be split based on the size of the existing mapping unit and the sub-target logical address ranges. Here, the fusion mapping units refer to mapping units whose current mapping units are updated through a series of fusion and / or partitioning processes based on sub-target logical address ranges constituting a target logical address range. As described above, the address translation method of the storage system according to embodiments of the present invention uses only one mapping data structure (ie, an address mapping table) including mapping units of various sizes, thereby searching for a plurality of data structures. Compared to the hybrid mapping method, the data structure retrieval time can be further reduced.

3 and 4, in a method of updating an address mapping table (S400), the target logical address range is divided into first to nth (where n is a natural number of two or more) subtarget logical address ranges (S410). And m (where m is a natural number less than n) determines the number of current mapping units including the sub-target logical address range (S420), and the m-th sub-target logical address range is within the single current mapping unit. If included, the current mapping unit may be split (S430). In addition, in the method of updating the address mapping table (S400), when the m-th sub-target logical address range overlaps a plurality of the current mapping units, fusion corresponding to the position and size of the m-th sub-target logical address range may be performed. The mapping unit may be determined (S440), and a physical address corresponding to the fusion mapping unit may be updated (S450).

As the logical addresses included in the target logical address range are fused, the target logical address range may be divided into the first to nth sub-target logical address ranges (S410). The 1 th to n th subtarget logical address ranges are the basis of an updated fusion mapping unit. The 1 th to n th subtarget logical address ranges may each have a size corresponding to 2k. A method of distinguishing sub-target logical address ranges by fusing the logical addresses will be described with reference to FIGS. 5 to 7.

In one embodiment, the first logical sector address (or starting logical sector address) of one sub-target logical address may correspond to the head logical sector address of the corresponding fusion mapping unit.

The number of current mapping units including the m-th sub-target logical address range may be determined (S420). The determination process may be sequentially applied to the first to nth sub-target logical address ranges, respectively. That is, the determination process determines whether the current mapping unit including the first to nth sub-target logical address ranges is divided.

When the m-th sub-target logical address range is included in a single current mapping unit, the current mapping unit may be split at least once (S430). In this case, the size of the current mapping unit is larger than the m th subtarget logical address range. The mapping units in which the split is completed may be determined as new fusion mapping units (S440). In this case, the first logical sector address of each of the fusion mapping units may be updated with the head logical sector address. In addition, a physical address corresponding to each of the fusion mapping units may be updated (S450).

When the m th subtarget logical address range overlaps (or is included in a plurality of current mapping units), the m sub target logical address range corresponds to the position and size of the m th subtarget logical address range. The fusion mapping unit may be determined (S440). For example, when the m-th sub-target logical address range includes a logical sector address 8 to a logical sector address 15 and has a size of 8 sectors, the size of the corresponding fusion mapping unit is 8 sectors, and the fusion mapping The head logical sector address of the unit may correspond to logical sector address 8. The first logical sector address of each of the fusion mapping units may be updated with the head logical sector address. In addition, a physical address corresponding to each of the fusion mapping units may be updated (S450).

Accordingly, current mapping units corresponding to the target logical address range may be divided or fused based on the size and position of the sub-target logical address ranges. Thus, the search time of the mapping data structure (eg, address mapping table) can be greatly shortened.

FIG. 5 is a flowchart illustrating an example of dividing a target logical address range into a plurality of sub-target logical address ranges in the updating method of the mapping table of FIG. 4, and FIG. 6 is a diagram of one of the sub-target logical address ranges of FIG. 5. It is a figure which shows an example.

4 to 6, in the method of dividing the target logical address range into a plurality of sub-target logical address ranges (S410), the first logical sector address of the m th sub-target logical address range is determined (S412), and A first maximum size is calculated based on the first logical sector address (S414), and the sub size (sub) is a value obtained by subtracting the size of the entire first to m-th sub-target logical address ranges from the size of the target logical address range. calculate a second maximum size based on the second size, and merge the logical addresses consecutive from the first logical sector address into a smaller one of the first maximum size and the second maximum size. It may include generating a target logical address range (S418). As the steps S412 to S418 are repeated, the first to nth sub-target logical address ranges STLA1, STLA2, STLA3, and STLA4 may be determined.

First, the first logical sector address of the mth sub-target logical address range may be determined (S412). In one embodiment, the first logical sector address FSA1 of the first sub-target logical address range STLA1 may correspond to the first logical sector address FSA of the target logical address range TLA. The first logical address FSA2 of the second subtarget logical address range STLA2 may be determined after the first subtarget logical address range STLA1 is determined. The first logical address FSA2 of the second subtarget logical address range STLA2 may correspond to the next logical sector address FSA2 of the last logical sector address of the first subtarget logical address range STLA1. Also, the first logical address of the mth subtarget logical address range may be determined after the m-1 subtarget logical address range is determined. In one embodiment, the first logical sector address of the mth subtarget logical address range except the first target logical address range STLA1 is the next logical sector of the last logical sector address of the m-1 subtarget logical address range. May correspond to an address.

Hereinafter, a method of determining the first sub-target logical address range STLA1 will be described.

The first maximum size may be calculated (S414) based on the first logical sector address FSA1 of the first sub-target logical address range STLA1. The first logical sector address FSA1 may be expressed as the sum of powers of two. In one embodiment, the first maximum size may correspond to the smallest of the powers of two. For example, when the first logical sector address FSA1 is logical sector 24 (ie, 24 + 23), the first maximum size may be eight sectors. Alternatively, when the first logical sector address FSA1 is 5 (ie, 22 + 20), the first maximum size may be 1 sector (ie, 20).

In the case of the first sub-target logical address range STLA1, the second maximum size may be calculated (S416) based on the size of the target logical address range TLA. The size of the target logical address range TLA and the sub size may be expressed as a sum of powers of two. In this case, the second maximum size may correspond to the largest value among the powers of two.

In the case of the first sub-target logical address range STLA1, the sub-size may correspond to the size of the target logical address range TLA. For example, in the case of FIG. 6, the size of the target logical address range TLA is 60 sectors (ie, 23 + 25 + 24 + 22), and thus the second maximum size of the first sub target logical address range STLA1. May be 32 sectors (ie, 25).

In an embodiment, for the m sub-target logical address range excluding the first sub-target logical address range STLA1, the sub size is the first to m-1 sub in the size of the target logical address range TLA. It may correspond to a value minus the size of the entire target logical address ranges. For example, the sub-size of the second sub-target logical address range STLA2 is 52 sectors (ie, 26 to 23), and the second maximum size of the second sub-target logical address range STLA2 is 32 sectors ( That is, 25). The second maximum size may be calculated in the same manner for the remaining subtarget logical address ranges.

The logical addresses consecutive from the first logical sector address FSA1 may be fused to the smaller of the first maximum size and the second maximum size to determine the m th sub-target logical address range (S418). As shown in FIG. 6, when the first maximum size of the first sub-target logical address range STLA1 is 8 sectors and the second maximum size is 32 sectors, the first sub-target logical address range STLA1 is It can be fused to 8 sectors in size.

Similarly, the second subtarget logical address range STLA2 is fused to 32 sector size (ie, 25), the third subtarget logical address range STLA3 is fused to 16 sector size (ie, 24), and the fourth The sub target logical address range STLA4 may be fused to a 4-sector size (ie, 22). However, this is merely an example, and the size of the subtarget logical address range is not limited thereto.

As illustrated in FIG. 6, the current mapping units MU1 to MU5 of the current mapping table OLD MAP TABLE corresponding to the target logical address range TLA are the first to fourth sub-target logical address ranges STLA1. To STLA4), may be updated to fusion mapping units NMU1 to NMU6. In an embodiment, since the first sub-target logical address range STLA1 is included in the first current mapping unit MU1, the first current mapping unit MU1 may be split. As a result, the first and second fusion mapping units NMU1 and NMU2 having a 23 sector size may be determined. If the size of the divided mapping unit is equal to the size corresponding to the first sub-target logical address range STLA1, the splitting operation may be terminated. Here, the first current mapping unit MU1 may be divided twice. Similarly, the fifth current mapping unit MU5 may be divided based on the size of the fourth sub-target logical address range STLA4.

In addition, as shown in FIG. 6, parts of the first current mapping unit MU1 to fourth current mapping units MU2 and MU3 based on the second and third sub-target logical address ranges STLA2 and STLA3. , MU4) may be fused to determine third and fourth fusion mapping units NMU3 and NMU4, respectively. The third fusion mapping unit NMU3 may have a size of 25 sectors, and the fourth fusion mapping unit NMU4 may have a size of 24 sectors.

The head logical sector address of each of the first to sixth fusion mapping units NMU1 to NMU6 is updated, and the physical addresses corresponding to the logical addresses of each of the first to sixth fusion mapping units NMU1 to NMU6 are updated. As a result, the address mapping table may be updated.

As described above, current mapping units corresponding to the target logical address range may be divided or fused based on the size and position of the sub-target logical address ranges. Thus, the search time of the mapping data structure (eg, address mapping table) can be greatly shortened.

4 to 7, current mapping units MU1, MU2, and MU3 may be fused (or updated) to a fusion mapping unit NMU based on one sub-target logical address range STLA.

In the existing mapping table, data may be written in the physical addresses A1, A2, and A3 corresponding to the first to third mapping units MU1, MU2, and MU3, respectively. An update of the mapping table is required to map a new physical address corresponding to the target logical address range (TLA).

The sub-target logical address range STLA determined by the above-described process may be compared with the corresponding first to third mapping units MU1, MU2, and MU3. As shown in FIG. 7, the sub-target logical address range STLA has a size of 4 sectors 4S, and the first to third mapping units MU1, MU2, and MU3 have a sub-target logical address range STLA. Can be included. Accordingly, the first to third mapping units MU1, MU2, and MU3 may be fused.

The first maximum size may be calculated based on the first logical sector address LA1 of the subtarget logical address range STLA. In addition, the second maximum size may be calculated based on the size of the target logical address range including the sub-target logical address range STLA. First to third mapping units MU1, MU2, and MU3 may be fused to a smaller one of the first maximum size and the second maximum size. As illustrated in FIG. 7, the first to third mapping units MU1, MU2, and MU3 may be fused into four sectors of a new fusion mapping unit NMU. The head address of the fusion mapping unit NMU may correspond to the first logical address LA1. Since the method of determining the fusion mapping unit has been described above with reference to FIGS. 3 to 6, a description thereof will not be repeated.

The fusion mapping unit NMU may include contiguous logical addresses LA1, LA2 and LA3 and contiguous physical addresses B corresponding to the logical addresses. As such, the address mapping table is updated by mapping unit fusion, thereby reducing the number of head logical sector addresses (ie, increasing non-head logical sectors). Thus, the cache effect of contiguous data for address mapping within the limited size of volatile memory can be improved.

8 is a flowchart illustrating an example of dividing a mapping unit in the updating method of the mapping table of FIG. 4, and FIG. 9 is a diagram illustrating an example of an operation of dividing the mapping unit of FIG. 8.

4, 8, and 9, in the method of dividing the current mapping unit (S430), the current divided by dividing the current mapping unit MU including the m-th sub-target logical address range STLA in half is divided. The mapping units NMU1 and NMU2 may be generated (S432), and one of the divided mapping units including the m th target logical address range STLA may be further divided into half (S436).

Data may be written to a physical address A corresponding to a predetermined logical address LA2 in the current mapping unit MU. Accordingly, the address mapping table needs to be updated. As shown in FIG. 9, the m-th sub-target logical address range STLA has a size of one sector, and the current mapping unit MU has a size of four sectors.

If the mth sub-target logical address range STLA is included in a single current mapping unit MU, the current mapping unit MU including the m-th sub-target logical address range STLA is split in half (S432). Can be. Accordingly, two divided mapping units NMU1 and NMU2 having a two sector size may be generated.

In one embodiment, each of the divided mapping units NMU1 and NMU2 and the sub-target logical address range STLA may be compared. Since the first partitioned mapping unit NMU1 does not include the m-th sub-target logical address range STLA, it is no longer partitioned. Therefore, the first divided mapping unit NMU1 may be determined as a new fusion mapping unit.

The size of the second divided mapping unit NMU1 and the size of the mth sub-target logical address range STLA may be compared (S434). For example, the size of the second divided mapping unit NMU2 may be compared with the size of the mth sub-target logical address range STLA.

As illustrated in FIG. 9, when the size of the second partitioned mapping unit NMU2 is larger than the size of the m-th sub-target logical address range STLA, the second partitioned mapping unit NMU2 is divided into third segments. It may be divided into a mapping unit NMU3 and a fourth divided mapping unit NMU4. The third and fourth divided mapping units NMU3 and NMU4 may each have a size of one sector. Since the fourth divided mapping unit NMU4 does not include the m-th sub-target logical address range STLA, the fourth divided mapping unit NMU4 is no longer divided. Therefore, the fourth divided mapping unit NMU4 may be determined as a new fusion mapping unit.

Again, the size of the third divided mapping unit NMU3 and the size of the m th sub-target logical address range STLA may be compared (S434). In one embodiment, if the size of the divided mapping unit is equal to the size corresponding to the m-th sub-target logical address range, the split may be terminated. As shown in FIG. 9, since the size of the third divided mapping unit NMU3 is the same as the size of the mth sub-target logical address range STLA, the splitting operation may be terminated. Finally, the first, third, and fourth divided mapping units NMU1, NMU3, and NMU4 may be determined as fusion mapping units, respectively.

When the partitioning ends, the physical address corresponding to the sub-target logical address range STLA may be updated based on the head logical sector addresses LA1, LA2, and LA3 of each of the divided mapping units. For example, since the physical address A corresponding to the subtarget logical address range LA2 is used, the position of the physical address corresponding to the subtarget logical address range LA2 may be updated to the position of 'B'. . Accordingly, the entry of the address mapping table and the physical address returned corresponding thereto may be updated.

Referring to FIG. 10, a mapping unit included in an address mapping table may be repeatedly divided based on a subtarget logical address range STLA to update an address mapping table.

As shown in FIG. 10, the sub-target logical address range TLA may be included in one mapping unit having 2x sectors. Thus, the division operation of the mapping unit may be started. The mapping unit may be divided into two mapping units having a 2x-1 sector size. The mapping unit including the sub target logical address STLA may be repeatedly divided. In addition, when the sub-target logical address STLA does not overlap the divided mapping unit, the divided mapping unit is no longer divided.

Finally, if the size of the divided mapping unit is equal to the size corresponding to the sub-target logical address range STLA, the split may be terminated. The divided mapping unit may be determined as the fusion mapping unit. For example, the mapping unit corresponding to the subtarget logical address range STLA may have a size (shown as one sector size 1S in FIG. 10) of the subtarget logical address range STLA.

As described above, the address translation method according to the embodiments of the present invention may dynamically divide and fuse mapping units of various sizes included in one address mapping table size. That is, the disadvantage that the search time of the mapping data structure of the existing hybrid mapping scheme that manages the plurality of address mapping tables is increased.

The present invention can be applied to storage systems and computer systems that use address mapping between logical and physical addresses.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated.

10: application 20: flash memory

100: memory device controller 140: flash conversion layer

Claims

Receiving a target logical address range of data applied from an application;

Mapping a logical address included in the target logical address range to a physical address of a physical storage area using an address mapping table;

Writing the data based on the mapped physical address;

Dynamically changing at least one of a plurality of mapping units constituting an entry of the address mapping table based on the continuity of the logical addresses included in the target logical address range; Updating the address mapping table.
The method of claim 1, wherein the size of each of the mapping units supported by the address mapping table is 2 k to the minimum mapping unit size within a preset minimum mapping unit size to a preset maximum mapping unit size range, where k is Address corresponding to a value multiplied by an integer of 0 or more).
The address translation method of claim 2, wherein the size of each of the mapping units is dynamically changed in units of 2 k within the preset range.
The method of claim 2, wherein updating the address mapping table

Fusing the logical addresses included in the target logical address range to convert the target logical address range from first to nth, where n is a natural number of two or more sub-target logical address ranges. Dividing into;

Determining the number of current mapping units including the m th sub-th target logical address range (where m is a natural number less than or equal to n);

Splitting the current mapping unit when the mth sub-target logical address range is included in a single current mapping unit;

Determining a fusion mapping unit corresponding to a position and a size of the m th subtarget logical address range when the m th subtarget logical address range overlaps a plurality of current mapping units; And

Updating a physical address corresponding to the fusion mapping unit.
The method of claim 4, wherein dividing the target logical address range into the first through n-th sub-target logical address ranges comprises:

Determining a first logical sector address of the mth sub-target logical address range;

Calculating a first maximum size based on the first logical sector address;

Calculating a second maximum size based on a sub-size that is a size of the target logical address range minus the size of the entire first to m-th subtarget logical address ranges; And

Fusing the logical addresses consecutive from the first logical sector address to a smaller one of the first maximum size and the second maximum size to determine the mth sub-target logical address range. How the system translates addresses.
6. The method of claim 5, wherein when the first logical sector address is expressed as a sum of powers of two, the first maximum size corresponds to the smallest value of powers of two. How the storage system translates addresses.
7. The storage system of claim 6, wherein when the subsize is expressed as a sum of powers of two, the second maximum size corresponds to a largest value of powers of two. How address is translated.
6. The method of claim 5 wherein the first logical sector address of the first sub-target logical address range corresponds to the first logical sector address of the target logical address range,

Wherein the first logical sector address of the mth subtarget logical address range except the first subtarget logical address range corresponds to the next logical sector address of the last logical sector address of the m-1 subtarget logical address range. How the storage system translates addresses.
5. The method of claim 4, wherein the fusion mapping unit comprises contiguous logical addresses and writable contiguous physical addresses corresponding to the logical addresses.
The method of claim 4, wherein dividing the current mapping unit

Generating divided mapping units by dividing the current mapping unit including the m-th sub-target logical address range in half; And

The operation of dividing one of the partitioned mapping units including the m th target logical address range into half is repeated until the size of the partitioned mapping unit becomes equal to the size of the m th subtarget logical address range. The address translation method of a storage system comprising the step of.
12. The method of claim 10, wherein repeating the dividing operation comprises: terminating the division if the size of the divided mapping unit is equal to the size of the m-th sub-target logical address range, and each of the divisions at which the division is terminated. And determining the mapped mapping units as the fusion mapping units, respectively.
The storage of claim 2, wherein the minimum mapping unit size corresponds to one sector, and the maximum mapping unit size corresponds to 2 j blocks (where j is a natural number). How the system translates addresses.
The method of claim 2, wherein the head logical sector address of each of the mapping units is dynamically changed.
A logical address included in a target logical address range of data received from an application is mapped to a physical address of a physical storage area by referring to an address mapping table, and based on the mapped physical address. Write at least one of the data, and at least one of a plurality of mapping units constituting an entry of the address mapping table based on the continuity of the logical address included in the target logical address. And a Flash Translation Layer (FTL) to dynamically update the address mapping table.
15. The method of claim 14, wherein the size of each of the mapping units supported by the mapping table is 2 k to the minimum mapping unit size within a range of a preset minimum mapping unit size to a preset maximum mapping unit size. Is an integer greater than or equal to 0).
The memory device controller of claim 15, wherein the flash conversion layer dynamically changes the size of each of the mapping units in 2k units within the preset range.