WO2017162123A1 - 消除报文的交换头阻的方法、装置及计算机存储介质 - Google Patents

消除报文的交换头阻的方法、装置及计算机存储介质 Download PDF

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Publication number
WO2017162123A1
WO2017162123A1 PCT/CN2017/077322 CN2017077322W WO2017162123A1 WO 2017162123 A1 WO2017162123 A1 WO 2017162123A1 CN 2017077322 W CN2017077322 W CN 2017077322W WO 2017162123 A1 WO2017162123 A1 WO 2017162123A1
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Prior art keywords
viq
linked list
pointer
head pointer
packet
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PCT/CN2017/077322
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English (en)
French (fr)
Inventor
季娟
徐凤鸣
赵培培
钱情明
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深圳市中兴微电子技术有限公司
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Publication of WO2017162123A1 publication Critical patent/WO2017162123A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/252—Store and forward routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9015—Buffering arrangements for supporting a linked list

Definitions

  • the present invention relates to a large-capacity data exchange technology, and more particularly to a method, apparatus, and computer storage medium for eliminating exchange header resistance of a message.
  • routing switch chip With the rapid development of the data network, the switching capacity of the routing switch chip is also increasing rapidly.
  • the industry generally adopts a queue linked list management to realize the shared storage space to alleviate the pressure of the switching capacity; the routing switch chip will source the packet of the source port. Switching to the destination port according to the route is generally divided into a two-level storage structure and an intermediate-level switching structure.
  • the first-level storage structure adopts the Virtual Input Queue (VIQ) mode, that is, the packet source port (iport) is used as the queue number to organize the linked list storage; when the packet enters the VIQ, the idle access list of the VIQ is taken from the idle list.
  • VIQ Virtual Input Queue
  • the address is stored in the body random access memory (RAM) (data_ram), and the address of the message in the data_ram is used as the node information, and the pointer to the end of the queue to which the message belongs (qlist_tp) is pointed.
  • VIQ Virtual Input Queue
  • the node information is used as the new qlist_tp; when the message is out of the VIQ, the queue head pointer (qlist_hp) is first used as the read address of the data_ram, the message is fetched, and the address is released to the VIQ idle.
  • the linked list with qlist_hp as the read address of qlist_ram, gets the new qlist_hp.
  • the intermediate-level switching structure randomly dispatches a queue according to the order-preserving algorithm between the VIQs of the first-level storage structure, queries the routing table, obtains the destination port information (bitmap), and returns the first-level storage structure to retrieve the first packet text body.
  • bitmap is sent to the second-level storage structure; here is a general introduction to the order-preserving algorithm, the data packet is sent to the switching network according to a specific basis, and the message is combined according to the specific basis at the exchange destination. Restore to a packet, this basis is Order-preserving algorithm.
  • the second-level storage structure adopts the Virtual Output Queue (VOQ) mode, that is, the destination port (oport) is used as the queue number to organize the linked list storage; the packets sent from the first-level storage are input into the corresponding ones according to the bitmap.
  • VOQ Virtual Output Queue
  • the queue is dispatched between the destination queues by the order-preserving algorithm, which realizes the exchange of packets from source to destination.
  • FIG. 1 is a schematic diagram of a message exchange header resistance generated when data is exchanged by using the prior art.
  • a VIQ stored in a first level may have a message destined for multiple different purposes, for example, the first
  • the routing switch chip will inevitably control the flow of the first-level storage.
  • the queue i_que_0 still has a cell to the queue o_que_2, and there is enough space in the queue o_que_2.
  • a new packet can be received, but because the packet header packet is blocked, the head pointer cannot be skipped from the queue list to obtain the storage address of the team leader packet of the second team, but only the scheduling is stopped, that is, the problem of the exchange header is generated. , reducing system efficiency and performance.
  • embodiments of the present invention are directed to a method, apparatus, and computer storage medium for eliminating exchange header resistance of a message to solve the problem of generating exchange head resistance and improve system efficiency and performance.
  • the present invention provides a method for eliminating exchange header resistance of a message, the method comprising:
  • the at least one second VIQ linked list is established according to the node information and the destination port information of the first VIQ linked list, and the node information of the first VIQ linked list is updated, including:
  • the destination port information is sent to the second level storage, including:
  • the method before the establishing at least one second VIQ linked list according to the node information of the first VIQ linked list and the destination port information of the first packet, the method further includes:
  • the query route After determining the queue header message in the first VIQ linked list by using the sequence-preserving algorithm, the query route obtains the destination port information of the first packet of the team.
  • the method further includes:
  • the method further includes:
  • the head pointer of the at least one second VIQ linked list is released to the free linked list of the ontology random access memory.
  • the using the head pointer of the first VIQ linked list as the new tail pointer of the at least one second VIQ linked list includes:
  • the updating the first VIQ linked list to obtain a new header pointer of the first VIQ linked list includes:
  • the head pointer of the first VIQ linked list is used as a read address, and the linked list random access memory of the first VIQ linked list is read to obtain a new head pointer of the first VIQ linked list.
  • the obtaining, by the head pointer of the at least one second VIQ linked list, the head start message of the at least one second VIQ linked list including:
  • the head pointer of the at least one second VIQ linked list is used as a read address, and the body random access memory is read to obtain a leader packet of the at least one second VIQ linked list.
  • the updating the at least one second VIQ linked list to obtain a new header pointer of the at least one second VIQ linked list comprises:
  • Reading the at least one of the head pointer of the at least one second VIQ linked list as a read address A linked list random access memory of the second VIQ linked list obtains a new header pointer of the at least one second VIQ linked list.
  • the present invention also provides an apparatus for eliminating exchange header resistance of a message, the apparatus comprising:
  • the first processing module is configured to establish at least one second VIQ linked list according to node information and destination port information of the first VIQ linked list, and update node information of the first VIQ linked list;
  • the second processing module is configured to: after determining the leader message of the at least one second VIQ linked list, update node information of the at least one second VIQ linked list, and send the first packet of the at least one second VIQ linked list And transmitting the destination port information to the second level storage.
  • the first processing module is configured to establish at least one second VIQ linked list according to node information of the first VIQ linked list and destination port information of the first packet;
  • the second processing module is configured to obtain a head start message of the at least one second VIQ linked list according to a head pointer of the at least one second VIQ linked list;
  • the first processing module is further configured to use the head pointer of the first VIQ linked list as write data, and write the tail pointer of the at least one second VIQ linked list as a write address into the In the linked list random access memory of the at least one second VIQ linked list, the head pointer of the first VIQ linked list is used as a new tail pointer of the at least one second VIQ linked list;
  • the first processing module is further configured to read a header of the first VIQ linked list as a read address, and read a linked list random access memory of the first VIQ linked list to obtain the first VIQ chain.
  • the new head pointer for the table is further configured to read a header of the first VIQ linked list as a read address, and read a linked list random access memory of the first VIQ linked list to obtain the first VIQ chain.
  • the second processing module is further configured to read the head random pointer of the at least one second VIQ linked list as a read address, and obtain the at least one second VIQ linked list.
  • the second processing module is further configured to: read a head pointer of the at least one second VIQ linked list as a read address, and read a linked list random access memory of the at least one second VIQ linked list to obtain the at least one second The new head pointer for the VIQ linked list.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform the exchange header blocking of the message according to the embodiment of the present invention. method.
  • the method and device for eliminating exchange header blocking of a message and the computer storage medium provided by the embodiment of the present invention, after updating the leader packet of the at least one second VIQ linked list, updating the node of the at least one second VIQ linked list And sending, to the second level storage, the team heading message and the destination port information of the at least one second VIQ linked list, and updating the at least one after determining the team heading message of the at least one second VIQ linked list Node information of the second VIQ linked list, sending the first packet of the at least one second VIQ linked list and the destination port information to the second level storage; without moving the text body, only the original VIQ linked list (first VIQ)
  • the node information of the linked list is re-queued to obtain the second VIQ linked list, and the second VIQ linked list is exchanged with the second-level storage, so that the packets of different destination ports are in different second VIQ linked lists, thereby avoiding mutual blocking and solving.
  • the problem of switching head resistance is increased, which improves system efficiency and performance.
  • FIG. 1 is a schematic diagram of a packet exchange header resistance generated when data is exchanged by using the prior art
  • Embodiment 1 is a flowchart of Embodiment 1 of a method for eliminating exchange header blocking of a packet according to the present invention
  • Embodiment 3 is a flowchart of Embodiment 2 of a method for eliminating exchange header blocking of a packet according to the present invention
  • FIG. 4 is a second embodiment of a unicast message in the second embodiment of the method for eliminating the exchange header of a packet according to the present invention. Schematic diagram of the team;
  • FIG. 5 is a schematic diagram of a unicast packet dequeuing according to Embodiment 2 of the method for eliminating exchange header blocking of a packet according to the present invention
  • FIG. 6 is a schematic diagram of the second time entering the multicast message of the second embodiment of the method for eliminating the exchange header of the packet;
  • FIG. 7 is a schematic diagram of the dequeuing of the multicast packet in the second embodiment of the method for eliminating the exchange header of the packet according to the present invention.
  • FIG. 8 is a schematic structural diagram of an apparatus for canceling exchange head blocking of a message according to the present invention.
  • Embodiment 1 is a flowchart of Embodiment 1 of a method for eliminating exchange header blocking of a packet according to the present invention.
  • the method for eliminating exchange header resistance of a packet according to an embodiment of the present invention is mainly improved in a routing switch chip.
  • the primary storage it may include the following steps:
  • Step 201 Establish at least one second VIQ linked list according to node information and destination port information of the first VIQ linked list, and update node information of the first VIQ linked list.
  • the device for eliminating the exchange header resistance of the packet first stores the packet in the original VIQ linked list (that is, the first VIQ linked list is the original VIQ linked list), and obtains the first query route in the intermediate switch fabric. After the destination port information of the first packet of the VIQ linked list, the node information is dequeued from the first VIQ linked list, and at least one new VIQ linked list is established according to the destination port pointed to by the destination port information of the first packet (ie, at least one The two VIQ linked list is at least one new VIQ linked list established according to the destination port pointed to by the destination port information of the first packet, that is, the second queue, because there are multiple types of exchanges in the routing exchange, for example, one-to-one.
  • Unicast message a pair of N (N>1) multicast messages, so that a suitable second VIQ linked list can be established according to actual needs, and is not limited here; then the node information of the first VIQ linked list is updated, wherein, a VIQ
  • the node information of the linked list includes the head pointer and the tail pointer of the first VIQ linked list; the secondary enqueue is the second enqueue of the node information, and the text body does not really dequeue from the ontology RAM, and the address occupied by the text body is not Released to the free list.
  • Step 202 After determining the team header message of the at least one second VIQ linked list, update the node information of the at least one second VIQ linked list, and set the team heading message of the at least one second VIQ linked list and the destination. Port information is sent to the second level of storage.
  • the device for eliminating the exchange header resistance of the packet uses the sequence-preserving algorithm to determine the node header message of the at least one second VIQ linked list, and updates the node information of the at least one second VIQ linked list, wherein the second VIQ linked list
  • the node information includes a head pointer and a tail pointer of the second VIQ linked list; after that, the head start message and the destination port information of the at least one second VIQ linked list are sent to the second level storage, and are transmitted to the second level through a set of buses.
  • the second-level storage can easily generate the flow control information of the single-queue level of the destination port according to the total cache depth and the single queue depth, because the single queue of the second VIQ linked list and the second-level storage structure are arranged according to the destination port.
  • the response can be distinguished, and the second VIQ linked list controlled by the flow does not participate in the scheduling, and a report is dispatched by the order-preserving algorithm in the remaining second VIQ linked list.
  • the text continues to be transmitted backwards, thus solving the problem of generating exchange head resistance.
  • the method for canceling the exchange header resistance of the packet provided by the embodiment of the present invention, after determining the node information of the at least one second VIQ linked list after determining the leader packet of the at least one second VIQ linked list, Sending the first packet of the second VIQ linked list and the destination port information to the second level storage; and determining the node of the at least one second VIQ linked list after determining the leader packet of the at least one second VIQ linked list And sending, to the second level storage, the team heading message and the destination port information of the at least one second VIQ linked list; and not only moving the message body, only performing node information of the original VIQ linked list (the first VIQ linked list) Re-queuing, obtaining the second VIQ linked list, and exchanging the second VIQ linked list with the second-level storage, so that the packets of different destination ports are in different second VIQ linked lists, thereby avoiding mutual blocking and solving the problem of generating exchange header resistance. , Improve system efficiency and performance.
  • FIG. 3 is a flowchart of Embodiment 2 of a method for eliminating exchange header blocking of a packet according to the present invention. As shown in FIG. 3, the method for eliminating exchange header resistance of a packet according to an embodiment of the present invention may include the following steps:
  • Step 301 After determining the first packet in the first VIQ linked list by using the sequence-preserving algorithm, querying the route to obtain the destination port information of the first packet of the team.
  • the device for eliminating the exchange header resistance of the packet uses the sequence-preserving algorithm to determine the first packet in the first VIQ linked list, and then queries the route to return the bitmap, and parses the destination of the first packet from the bitmap. The port number.
  • Step 302 Establish at least one second VIQ linked list according to node information of the first VIQ linked list and destination port information of the first packet.
  • the means for eliminating the exchange header resistance of the message establishes at least one second VIQ linked list according to the head pointer and the tail pointer of the first VIQ linked list and the destination port number of the first packet.
  • Step 303 Use a head pointer of the first VIQ linked list as a new tail pointer of the at least one second VIQ linked list.
  • the device for eliminating the exchange header of the message uses the head pointer of the first VIQ linked list as write data, and writes the tail pointer of the at least one second VIQ linked list as a write address to the at least one second.
  • the head pointer of the first VIQ linked list is used as a new tail pointer of the at least one second VIQ linked list.
  • the device for eliminating the exchange header resistance of the message uses the head pointer of the first VIQ linked list as the write data, and writes the tail pointer of the at least one second VIQ linked list as the write address to the linked list RAM of the at least one second VIQ linked list;
  • the head pointer of the first VIQ linked list m is used as a new tail pointer of at least one second VIQ linked list.
  • Step 304 Update the first VIQ linked list to obtain a new header of the first VIQ linked list. pointer.
  • the device for canceling the exchange header of the message uses the head pointer of the first VIQ linked list as a read address, reads the linked list random access memory of the first VIQ linked list, and obtains the new VIQ linked list. Head pointer.
  • the device for eliminating the exchange header resistance of the message uses the head pointer of the first VIQ linked list as the read address, reads the linked list RAM of the first VIQ linked list, and obtains a new header pointer of the first VIQ linked list.
  • Step 305 Obtain the at least one second VIQ linked list that meets the condition according to the flow control of the second level storage and the use of a sequence-preserving algorithm.
  • the apparatus for eliminating the exchange header resistance of the message obtains at least one second VIQ linked list that meets the condition according to the flow control stored in the second level and the use of the order-preserving algorithm.
  • Step 306 Obtain a queue header message of the at least one second VIQ linked list according to the head pointer of the at least one second VIQ linked list.
  • the device for eliminating the exchange header of the packet uses the header pointer of the at least one second VIQ linked list as the read address, reads the data_ram, and obtains the leader of the at least one second VIQ linked list that meets the condition. Message.
  • the device for eliminating the exchange header resistance of the message uses the header pointer of the at least one second VIQ linked list as the read address, reads the data_ram, and obtains the first packet of the at least one second VIQ linked list that meets the condition.
  • Step 307 Release a head pointer of the at least one second VIQ linked list to an idle linked list of the ontology random access memory.
  • the means for canceling the exchange header of the message releases the head pointer of the at least one second VIQ linked list that is eligible for the idle list of the data_ram, such that the body of the message is actually completed in the first level of storage.
  • Step 308 Update the at least one second VIQ linked list to obtain a new head pointer of the at least one second VIQ linked list.
  • the device for eliminating the exchange header of the message uses the head pointer of the at least one second VIQ linked list as a read address, and reads the linked list RAM of the at least one second VIQ linked list to obtain the at least one second VIQ.
  • the new head pointer of the linked list uses the head pointer of the at least one second VIQ linked list as a read address, and reads the linked list RAM of the at least one second VIQ linked list to obtain the at least one second VIQ.
  • the device for eliminating the exchange header resistance of the message uses the header pointer of the at least one second VIQ linked list as the read address, and reads the linked list RAM of the at least one second VIQ linked list that meets the condition, and obtains at least one second VIQ that meets the condition.
  • the new head pointer of the linked list uses the header pointer of the at least one second VIQ linked list as the read address, and reads the linked list RAM of the at least one second VIQ linked list that meets the condition, and obtains at least one second VIQ that meets the condition.
  • Step 309 Send the first packet of the at least one second VIQ linked list together with the destination port information to the second level storage.
  • the device for eliminating the exchange header resistance of the packet sends the header message and the destination port information of the at least one second VIQ linked list that meet the condition to the second level storage to complete the dequeue of the first level storage.
  • the unicast message is stored in the first level of the second enqueue and dequeue process.
  • the resource only needs to open a cache similar to the linked list RAM of the first VIQ linked list.
  • the linked list RAM of the first VIQ linked list the storage node information is stored. The second entry into the linked list.
  • the multicast message is a pair of N (N>1) exchange process
  • the message can be copied up to N; then in the second When entering the queue, there will be a scenario where a message node information is simultaneously written to the tail pointers of the N second VIQ linked lists. Therefore, the resource needs to open the same cache as the linked list RAM of the first VIQ linked list; another difference is
  • the N second VIQ linked lists may not be controlled by the flow at the same time, and the second VIQ linked list not controlled by the flow may be read from the data_ram to the second-level storage, but as long as there is one copy of the text body. After completion, the address occupied by the data body in the data_ram cannot be released to the free list, and the content of the bitmap at this time is the destination port queue that is not controlled by the flow.
  • FIG. 4 is a schematic diagram of a second unicast packet entlining in the second embodiment of the method for eliminating the exchange header of the packet according to the present invention. As shown in FIG. 4, it is assumed that the first packet of the first queue i_que_1 is selected by the order-preserving algorithm.
  • the RAM is 0-13-2-
  • FIG. 5 is a schematic diagram of the unicast packet dequeuing according to the second embodiment of the method for eliminating the exchange header of the packet. As shown in FIG. 5, it is assumed that the second-level storage queue o_que_n-1 is full, and a single queue level is generated forward.
  • FIG. 6 is a schematic diagram of the secondary enqueue of the multicast message in the second embodiment of the method for eliminating the exchange header of the packet according to the present invention. As shown in FIG. 6, it is assumed that the first packet of the first queue i_que_0 is selected by the order-preserving algorithm.
  • the linked list RAM0 stores the linked list of the second queue vo_que_0, and so on; the new tail pointer of the second queue vo_que_0, the second queue vo_que_1, and the second queue vo_que_2 is used; the first team is read with 15 as the read address.
  • FIG. 7 is a schematic diagram of the dequeuing of the multicast packet in the second embodiment of the method for eliminating the exchange header of the packet according to the present invention. As shown in FIG. 7, it is assumed that the second-level storage queue o_que_0 is full, and a single queue-level flow control is generated forward.
  • the second queue vo_que_0 is removed, and the first packet of the second queue is dispatched by the order-preserving algorithm between the second queues vo_que_1 and vo_que_n-1;
  • the packets of the second queue vo_que_1 and the second queue vo_que_2 should be scheduled at the same time.
  • the at least one second VIQ linked list is established according to the node information of the first VIQ linked list and the destination port information of the first packet; the first VIQ linked list is a header pointer as a new tail pointer of the at least one second VIQ linked list; updating the first VIQ linked list to obtain a new header pointer of the first VIQ linked list; And obtaining, by the head pointer of the at least one second VIQ linked list, a head start message of the at least one second VIQ linked list; updating the at least one second VIQ linked list to obtain a new head pointer of the at least one second VIQ linked list .
  • FIG. 8 is a schematic structural diagram of an apparatus for canceling exchange head blocking of a packet according to the present invention.
  • the apparatus 08 for eliminating exchange header resistance of a packet according to an embodiment of the present invention includes: a first processing module 81 and a second processing module 82; wherein
  • the first processing module 81 is configured to establish at least one second VIQ linked list according to node information and destination port information of the first VIQ linked list, and update node information of the first VIQ linked list;
  • the second processing module 82 is configured to: after determining the leader message of the at least one second VIQ linked list, update the node information of the at least one second VIQ linked list, and the team of the at least one second VIQ linked list The first message and the destination port information are sent to the second level storage.
  • the first processing module 81 is configured to establish at least one second VIQ linked list according to the node information of the first VIQ linked list and the destination port information of the first packet;
  • the second processing module 82 is configured to obtain, according to the head pointer of the at least one second VIQ linked list, a head start message of the at least one second VIQ linked list;
  • the device further includes: an obtaining module 83; wherein
  • the obtaining module 83 is configured to determine, by using a sequence-preserving algorithm, the destination port information in the first VIQ linked list, and query the route to obtain the destination port information of the first packet of the team.
  • the device further includes: a selection module 84; wherein
  • the selecting module 84 is configured to obtain the at least one second VIQ linked list that meets the conditions according to the flow control stored in the second level and the use of the order-preserving algorithm.
  • the device further includes: a release module 85; wherein
  • the release module 85 is configured to release the head pointer of the at least one second VIQ linked list to the free linked list of the ontology random access memory.
  • the first processing module 81 is further configured to use a head pointer of the first VIQ linked list as write data, and write a tail pointer of the at least one second VIQ linked list as a write address.
  • the head pointer of the first VIQ linked list is used as a new tail pointer of the at least one second VIQ linked list.
  • the first processing module 81 is further configured to: read a head pointer of the first VIQ linked list as a read address, and read a linked list random access memory of the first VIQ linked list to obtain the first A new head pointer for a VIQ linked list.
  • the second processing module 82 is further configured to: read a head pointer of the at least one second VIQ linked list as a read address, and read the ontology random access memory to obtain the at least one second VIQ linked list. The first message of the team.
  • the second processing module 82 is further configured to: read a head pointer of the at least one second VIQ linked list as a read address, and read a linked list random access memory of the at least one second VIQ linked list, Obtaining a new head pointer of the at least one second VIQ linked list.
  • the device of this embodiment may be used to implement the technical solution of the method embodiment shown above, The implementation principle and technical effect are similar, and will not be described here.
  • the first processing module 81, the second processing module 82, the obtaining module 83, the selecting module 84, and the releasing module 85 may be a central processing unit (CPU) and a microprocessor (located on the device). MicroProcessor Unit (MPU), digital signal processor (DSP) or Field-Programmable Gate Array (FPGA).
  • CPU central processing unit
  • MPU MicroProcessor Unit
  • DSP digital signal processor
  • FPGA Field-Programmable Gate Array
  • embodiments of the invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • the technical solution of the embodiment of the present invention updates the node information of the at least one second VIQ linked list by determining the node header message of the at least one second VIQ linked list, and displays the at least one second VIQ linked list And the destination port information is sent to the second level storage; after determining the leader packet of the at least one second VIQ linked list, the node information of the at least one second VIQ linked list is updated, and the at least one second The queue message of the VIQ linked list and the destination port information are sent to the second level storage; instead of moving the text body, only the node information of the original VIQ linked list (the first VIQ linked list) is re-queued to obtain the second VIQ linked list.
  • the second VIQ linked list is exchanged with the second-level storage, so that packets of different destination ports are in different second VIQ linked lists, thereby avoiding mutual blocking, solving the problem of generating switching head resistance, and improving system efficiency and performance.

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Abstract

本发明实施例公开了一种消除报文的交换头阻的方法，包括：根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。本发明实施例同时还公开了一种消除报文的交换头阻的装置及计算机存储介质。

Description

消除报文的交换头阻的方法、装置及计算机存储介质 技术领域
本发明涉及大容量数据交换技术，尤其涉及一种消除报文的交换头阻的方法、装置及计算机存储介质。
背景技术
随着数据网络的快速发展，路由交换芯片的交换容量也在急剧增长，业内普遍采用一种队列链表管理实现共享存储空间的方式，来缓解交换容量的压力；路由交换芯片将源端口的报文按照路由交换到目的端口，一般分为两级存储结构和中间级交换结构。
第一级存储结构采用虚拟输入队列(Virtual Input Queue，VIQ)方式，即以报文源端口(iport)为队列号组织链表存储；报文进入VIQ时，先从VIQ的空闲链表中取一个空闲地址，将报文本体存入本体随机存取存储器(Random Access Memory，RAM)(data_ram)中，再将报文在data_ram中的地址作为节点信息，写入报文所属队列尾指针(qlist_tp)指向的队列链表RAM(qlist_ram)地址里，同时将该节点信息作为新的qlist_tp；报文出VIQ时，先以队列头指针(qlist_hp)为data_ram的读地址，取出报文，释放地址到VIQ的空闲链表，同时以qlist_hp为qlist_ram的读地址，得到新的qlist_hp。
中间级交换结构在第一级存储结构的VIQ之间根据保序算法逐一调度出某一队列，去查询路由表，得到目的端口信息(bitmap)，返回第一级存储结构取出队首报文本体，与bitmap一起送到第二级存储结构；这里大致介绍一下保序算法，数据包按照特定的依据切成报文送到交换网，在交换目的端相应地按照此特定的依据将报文组合还原成数据包，这个依据就是 保序算法。
第二级存储结构采用虚拟输出队列(Virtual Output Queue，VOQ)方式，即以目的端口(oport)作为队列号组织链表存储；将第一级存储送来的报文按bitmap输入到相应的一条或几条目的端口链表队列中，在目的队列之间再以保序算法调度出队，这就实现了报文从源到目的的交换。
图1为利用现有技术进行数据交换时产生报文交换头阻的示意图，如图1所示，第一级存储的一个VIQ中可能存在去往多个不同目的的报文，例如，第一级存储的队列i_que_0(iport＝0)的队首报文去往第二级存储的队列o_que_n-1(oport＝n-1)，次队首报文去往第二级存储的队列o_que_2(oport＝2)；如果正在调度队列i_que_0的队首报文，但恰好队列o_que_n-1将满，由于队列链表缓存的只能顺序输出的特性，一旦队首报文发生目的端口阻塞无法输出，余下报文即便是要去往空闲目的端口也无法输出，则必然路由交换芯片会流量控制第一级存储的出口，这时即使队列i_que_0仍有去往队列o_que_2的信元，并且队列o_que_2中有足够空间可以接收新的报文，但因为队首报文的阻塞，无法从队列链表中跳过头指针得到次队的队首报文的存储地址，而只能全部停止调度，即产生交换头阻的问题，降低了系统效率和性能。
发明内容
有鉴于此，本发明实施例期望提供一种消除报文的交换头阻的方法、装置及计算机存储介质，以解决产生交换头阻的问题，提高系统效率和性能。
为达到上述目的，本发明的技术方案是这样实现的：
本发明提供一种消除报文的交换头阻的方法，所述方法包括：
根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；
确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
在一实施例中，所述根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息，包括：
根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；
将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针。
在一实施例中，所述确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储，包括：
根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；
更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针；
将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
在一实施例中，在所述根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表之前，所述方法还包括：
利用保序算法确定所述第一VIQ链表中的队首报文后，查询路由得到所述队首报文的目的端口信息。
在一实施例中，在所述更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针之后，所述方法还包括：
根据所述第二级存储的流量控制和利用保序算法得到符合条件的所述至少一个第二VIQ链表。
在一实施例中，在所述根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文之后，在所述更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针之前，所述方法还包括：
释放所述至少一个第二VIQ链表的头指针给所述本体随机存取存储器的空闲链表。
在一实施例中，所述将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针，包括：
将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表随机存取存储器中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针。
在一实施例中，所述更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针，包括：
将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链表的新的头指针。
在一实施例中，所述根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文，包括：
将所述至少一个第二VIQ链表的头指针作为读地址，读取本体随机存取存储器，得到所述至少一个第二VIQ链表的队首报文。
在一实施例中，所述更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针，包括：
将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一 个第二VIQ链表的链表随机存取存储器，得到所述至少一个第二VIQ链表的新的头指针。
本发明还提供一种消除报文的交换头阻的装置，所述装置包括：
第一处理模块，配置为根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；
第二处理模块，配置为确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
在一实施例中，所述第一处理模块，配置为根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；
将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针。
在一实施例中，所述第二处理模块，配置为根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；
更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针；
将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
在一实施例中，所述第一处理模块，还配置为将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表随机存取存储器中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
所述第一处理模块，还配置为将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链 表的新的头指针。
在一实施例中，所述第二处理模块，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取本体随机存取存储器，得到所述至少一个第二VIQ链表的队首报文；
所述第二处理模块，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一个第二VIQ链表的链表随机存取存储器，得到所述至少一个第二VIQ链表的新的头指针。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的消除报文的交换头阻的方法。
本发明实施例提供的消除报文的交换头阻的方法、装置及计算机存储介质，通过确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；不用移动报文本体，仅对原始VIQ链表(第一VIQ链表)的节点信息进行重新排队，得到第二VIQ链表，通过第二VIQ链表与第二级存储进行交换，使得不同目的端口的报文在不同第二VIQ链表中，从而避免相互阻塞，解决了产生交换头阻的问题，提高了系统效率和性能。
附图说明
图1为利用现有技术进行数据交换时产生报文交换头阻的示意图；
图2为本发明消除报文的交换头阻的方法实施例一的流程图；
图3为本发明消除报文的交换头阻的方法实施例二的流程图；
图4为本发明消除报文的交换头阻的方法实施例二的单播报文二次入 队的示意图；
图5为本发明消除报文的交换头阻的方法实施例二的单播报文出队的示意图；
图6为本发明消除报文的交换头阻的方法实施例二的多播报文二次入队的示意图；
图7为本发明消除报文的交换头阻的方法实施例二的多播报文出队的示意图；
图8为本发明消除报文的交换头阻的装置实施例的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
图2为本发明消除报文的交换头阻的方法实施例一的流程图，如图2所示，本发明实施例提供的消除报文的交换头阻的方法主要改进在路由交换芯片的第一级存储中，其可以包括如下步骤：
步骤201、根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息。
本实施例中，消除报文的交换头阻的装置仍先将报文以原始存在的VIQ链表(即，第一VIQ链表为原始存在的VIQ链表)存储，在中间交换结构查询路由得到第一VIQ链表的队首报文的目的端口信息后，将节点信息从第一VIQ链表出队，根据队首报文的目的端口信息指向的目的端口建立至少一个新的VIQ链表(即，至少一个第二VIQ链表为根据队首报文的目的端口信息指向的目的端口建立的至少一个新的VIQ链表)，即二次入队，因为在路由交换中有多种类型的交换，例如，一对一的单播报文、一对N(N>1)的多播报文，因此可以根据实际需求建立适合的第二VIQ链表，在此不加以限制；之后更新第一VIQ链表的节点信息，其中，第一VIQ 链表的节点信息包括了第一VIQ链表的头指针和尾指针；二次入队是节点信息的二次入队，报文本体并不真正从本体RAM中出队，报文本体占用的地址不释放给空闲链表。
步骤202、确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
本实施例中，消除报文的交换头阻的装置利用保序算法确定出至少一个第二VIQ链表的队首报文后，更新至少一个第二VIQ链表的节点信息，其中，第二VIQ链表的节点信息包括了第二VIQ链表的头指针和尾指针；之后，将至少一个第二VIQ链表的队首报文和目的端口信息发送到第二级存储，通过一组总线传输到第二级存储，第二级存储可以很容易地根据总缓存深度和单队列深度产生目的端口的单队列级的流量控制信息，因为第二VIQ链表与第二级存储结构的单队列都是按目的端口排列的，当收到第二级存储的单队列级流量控制时，可以区别响应，受到流量控制的第二VIQ链表就不参与调度，在剩余的第二VIQ链表中通过保序算法调度出一个报文继续向后传输，于是解决了产生交换头阻的问题。
本发明实施例提供的消除报文的交换头阻的方法，通过确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；不用移动报文本体，仅对原始VIQ链表(第一VIQ链表)的节点信息进行重新排队，得到第二VIQ链表，通过第二VIQ链表与第二级存储进行交换，使得不同目的端口的报文在不同第二VIQ链表中，从而避免相互阻塞，解决了产生交换头阻的问题， 提高了系统效率和性能。
为了更加体现出本发明的目的，在上述实施例的基础上，进一步的举例说明。
图3为本发明消除报文的交换头阻的方法实施例二的流程图，如图3所示，本发明实施例提供的消除报文的交换头阻的方法可以包括如下步骤：
步骤301、利用保序算法确定第一VIQ链表中的队首报文后，查询路由得到所述队首报文的目的端口信息。
本实施例中，消除报文的交换头阻的装置利用保序算法确定出第一VIQ链表中的队首报文后，去查询路由返回bitmap，从bitmap中解析出该队首报文的目的端口号。
步骤302、根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表。
消除报文的交换头阻的装置根据第一VIQ链表的头指针和尾指针以及队首报文的目的端口号建立至少一个第二VIQ链表。
步骤303、将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针。
具体的，消除报文的交换头阻的装置将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表RAM中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针。
消除报文的交换头阻的装置将第一VIQ链表的头指针作为写数据，将至少一个第二VIQ链表的尾指针作为写地址，写入至少一个第二VIQ链表的链表RAM中；之后，将第一VIQ链表m的头指针作为至少一个第二VIQ链表的新的尾指针。
步骤304、更新所述第一VIQ链表，得到所述第一VIQ链表的新的头 指针。
具体的，消除报文的交换头阻的装置将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链表的新的头指针。
消除报文的交换头阻的装置将第一VIQ链表的头指针作为读地址，读取第一VIQ链表的链表RAM，得到第一VIQ链表的新的头指针。
步骤305、根据所述第二级存储的流量控制和利用保序算法得到符合条件的所述至少一个第二VIQ链表。
消除报文的交换头阻的装置根据第二级存储的流量控制和利用保序算法得到符合条件的至少一个第二VIQ链表。
步骤306、根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文。
具体的，消除报文的交换头阻的装置将所述符合条件的至少一个第二VIQ链表的头指针作为读地址，读取data_ram，得到所述符合条件的至少一个第二VIQ链表的队首报文。
消除报文的交换头阻的装置将符合条件的至少一个第二VIQ链表的头指针作为读地址，读取data_ram，得到符合条件的至少一个第二VIQ链表的队首报文。
步骤307、释放所述至少一个第二VIQ链表的头指针给所述本体随机存取存储器的空闲链表。
消除报文的交换头阻的装置释放符合条件的至少一个第二VIQ链表的头指针给所述data_ram的空闲链表，如此该报文本体在第一级存储真正完成出队。
步骤308、更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针。
具体的，消除报文的交换头阻的装置将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一个第二VIQ链表的链表RAM，得到所述至少一个第二VIQ链表的新的头指针。
消除报文的交换头阻的装置将符合条件的至少一个第二VIQ链表的头指针作为读地址，读取符合条件的至少一个第二VIQ链表的链表RAM，得到符合条件的至少一个第二VIQ链表的新的头指针。
步骤309、将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
消除报文的交换头阻的装置将符合条件的至少一个第二VIQ链表的队首报文和目的端口信息一起发送到第二级存储，完成第一级存储的出队。
单播报文在第一级存储的二次入队和出队过程，资源上就只需要另开辟一块和第一VIQ链表的链表RAM一样的缓存，作为第一VIQ链表的链表RAM，存储节点信息的二次入队链表。
不同于一对一的单播报文，交换芯片中另一种典型报文——组播报文是一对N(N>1)的交换过程，报文最多可以复制N份；那么在二次入队的时候会出现将一个报文节点信息同时写入N个第二VIQ链表的尾指针的场景，因此资源上需要开辟N块和第一VIQ链表的链表RAM一样的缓存；另外一个差别是，上述N个第二VIQ链表可能不会同时受到流量控制，未受流量控制的第二VIQ链表可以从data_ram读到报文本体送到第二级存储，但只要报文本体还有一份没有复制完成，data_ram中报文本体所占的地址就不能释放给空闲链表，并且此时的bitmap内容为未受流量控制的目的端口队列。
下面以两种类型报文作进一步的详细描述。
图4为本发明消除报文的交换头阻的方法实施例二的单播报文二次入队的示意图，如图4所示，假设第一队列i_que_1的队首报文被保序算法选 中，去查询路由返回bitmap＝0x4(oport＝2)；根据第一队列i_que_1的节点信息和bitmap建立第二队列vo_que_2；取出第一队列i_que_1的qlist_hp＝0，qlist_hp＝0指示的是该队首报文在data_ram中的地址为0，以0为写数据，以二次入队第二队列vo_que_2的qlist_tp＝12为写地址，写入第二队列vo_que_2的链表RAM；用0作为第二队列vo_que_2的新的尾指针；以0为读地址，读取第一队列i_que_1的链表RAM，得到第一队列i_que_1的新的头指针qlist_hp＝13；即，二次入队前的第一队列i_que_1的链表RAM为0-13-2-6-7，第一队列i_que_1的qlist_hp＝0、qlist_tp＝7，第二队列vo_que_2的链表RAM为10-12，第二队列vo_que_2的qlist_hp＝10、qlist_tp＝12；二次入队后的第一队列i_que_1链表RAM为13-2-6-7，第一队列i_que_1的qlist_hp＝13、qlist_tp＝7，第二队列vo_que_2的链表RAM为10-12-0，第二队列vo_que_2的qlist_hp＝10、qlist_tp＝0；图中eoc表示尾指针的标识。
图5为本发明消除报文的交换头阻的方法实施例二的单播报文出队的示意图，如图5所示，假设第二级存储队列o_que_n-1已满，向前产生单队列级流量控制，那么因为报文在二次队列中已经按目的进行了预排序，即有且仅有第二队列vo_que_n-1的报文是去往第二级存储队列o_que_n-1的，因此剔除第二队列vo_que_n-1，在第二队列vo_que_0～vo_que_n-2之间按保序算法调度某一第二队列的队首报文出队；在本实施例中例如调度第二队列vo_que_2的报文出队，取出第二队列vo_que_2的qlist_hp＝10，以10为读地址，读取data_ram得到第二队列vo_que_2的队首报文；释放地址10给空闲链表，使得该报文本体在第一级存储真正完成出队；以10为读地址，读取第二队列vo_que_2的链表RAM，得到队列vo_que_2的新的头指针qlist_hp＝12，即，出队前的第二队列vo_que_2的链表RAM为10-12-0，第二队列vo_que_2的qlist_hp＝10、qlist_tp＝0；出队后的第二队列vo_que_2的链表RAM为12-0，第二队列vo_que_2的qlist_hp＝12、qlist_tp＝0；最后 把第二队列vo_que_2的队首报文和bitmap＝0x4一起发送到第二级存储，在第二级存储队列o_que_n-1入队，后续处理为现有技术，在此不赘述。
图6为本发明消除报文的交换头阻的方法实施例二的多播报文二次入队的示意图，如图6所示，假设第一队列i_que_0的队首报文被保序算法选中，去查询路由返回bitmap＝0x7(oport＝0、1、2)；根据第一队列i_que_0的节点信息和bitmap建立多个第二队列，分别为第二vo_que_0第二vo_que_1、第二vo_que_2；取出第一队列i_que_0的qlist_hp＝15，qlist_hp＝15指示的是该队首报文在data_ram中的地址为15，以15为写数据，同时以二次入队第二队列vo_que_0的qlist_tp＝1、第二队列vo_que_1的qlist_tp＝2、第二队列vo_que_2的qlist_tp＝7为写地址，写入第二队列vo_que_0的链表RAM0、第二队列vo_que_1的链表RAM1、第二队列vo_que_2链表RAM2(其中，第二队列vo_que_0的链表RAM0存储的是第二队列vo_que_0的链表，其他类推)；用15作为第二队列vo_que_0、第二队列vo_que_1、第二队列vo_que_2的新的尾指针；以15为读地址，读取第一队列i_que_0的链表RAM，得到第一队列i_que_0的新的头指针qlist_hp＝14；即，二次入队前的第一队列i_que_0的链表RAM为15-14-3-4-10-12，第一队列i_que_0的qlist_hp＝15、qlist_tp＝12，第二队列vo_que_0的链表RAM0为1，第二队列vo_que_0的qlist_hp＝1、qlist_tp＝1，第二队列vo_que_1的链表RAM1为0-2，第二队列vo_que_1的qlist_hp＝0、qlist_tp＝2，第二队列vo_que_2的链表RAM2为7，第二队列vo_que_2的qlist_hp＝7、qlist_tp＝7；图中eoc表示尾指针的标识。
图7为本发明消除报文的交换头阻的方法实施例二的多播报文出队的示意图，如图7所示，假设第二级存储队列o_que_0已满，向前产生单队列级流量控制，因此剔除第二队列vo_que_0，在第二队列vo_que_1～vo_que_n-1之间按保序算法调度某一第二队列的队首报文出队；在本实施 例中，因为第二队列vo_que_0、第二队列vo_que_1、第二队列vo_que_2是同一报文复制而来，根据保序算法和流量控制，当前应该同时调度第二队列vo_que_1、第二队列vo_que_2的报文出队，它们共同拥有一份报文本体，因而头指针指向data_ram中同一个地址，取出头指针qlist_hp＝15，以15为读地址，读取data_ram得到第二队列vo_que_1、第二队列vo_que_2的队首报文，该报文本体还要等待单队列流量控制取消后复制一份到第二级存储队列o_que_0才算真正完成出队，因此地址15暂时不能释放给空闲链表；以15为读地址，读取第二队列vo_que_1的链表RAM1，得到第二队列vo_que_1的新的头指针qlist_hp＝7，以15为读地址，读取第二队列vo_que_2的链表RAM2，得到第二队列vo_que_2的新的头指针qlist_hp＝13，即，出队前的第二队列vo_que_0的链表RAM0为15，第二队列vo_que_0的qlist_hp＝15、qlist_tp＝15，出队前的第二队列vo_que_1的链表RAM1为15-7-10-11，第二队列vo_que_1的qlist_hp＝15、qlist_tp＝11，出队前的第二队列vo_que_2的链表RAM2为15-13，第二队列vo_que_2的qlist_hp＝15、qlist_tp＝13；出队后的第二队列vo_que_0的链表RAM0为15，第二队列vo_que_0的qlist_hp＝15、qlist_tp＝15不变，出队后的第二队列vo_que_1的链表RAM1为7-10-11，第二队列vo_que_1的qlist_hp＝7、qlist_tp＝11，出队后的第二队列vo_que_2的链表RAM2为13，第二队列vo_que_2的qlist_hp＝13、qlist_tp＝13；把该报文和bitmap＝0x6一起发送到第二级存储，在第二级队列o_que_1和第二级队列o_que_2分别入队，后续处理为现有技术，在此不赘述。
本发明实施例提供的消除报文的交换头阻的方法，通过根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针；根据 所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针。将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储；通过不用移动报文本体，仅对原始VIQ链表(第一VIQ链表)的节点信息进行重新排队，得到第二VIQ链表，通过第二VIQ链表与第二级存储进行交换，使得不同目的端口的报文在不同第二VIQ链表中，从而避免相互阻塞，解决了产生交换头阻的问题，提高了系统效率和性能。
图8为本发明消除报文的交换头阻的装置实施例的结构示意图，如图8所示，本发明实施例提供的消除报文的交换头阻的装置08包括：第一处理模块81和第二处理模块82；其中，
所述第一处理模块81，配置为根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；
所述第二处理模块82，配置为确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
作为一种实施方式，所述第一处理模块81，配置为根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；
将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针。
作为一种实施方式，所述第二处理模块82，配置为根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；
更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针；
将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
作为一种实施方式，所述装置还包括：获取模块83；其中，
所述获取模块83，配置为利用保序算法确定所述第一VIQ链表中的队首报文后，查询路由得到所述队首报文的目的端口信息。
作为一种实施方式，所述装置还包括：选取模块84；其中，
所述选取模块84，配置为根据所述第二级存储的流量控制和利用保序算法得到符合条件的所述至少一个第二VIQ链表。
作为一种实施方式，所述装置还包括：释放模块85；其中，
所述释放模块85，配置为释放所述至少一个第二VIQ链表的头指针给所述本体随机存取存储器的空闲链表。
作为一种实施方式，所述第一处理模块81，还配置为将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表随机存取存储器中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针。
作为一种实施方式，所述第一处理模块81，还配置为将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链表的新的头指针。
作为一种实施方式，所述第二处理模块82，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取本体随机存取存储器，得到所述至少一个第二VIQ链表的队首报文。
作为一种实施方式，所述第二处理模块82，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一个第二VIQ链表的链表随机存取存储器，得到所述至少一个第二VIQ链表的新的头指针。
本实施例的装置，可以用于执行上述所示方法实施例的技术方案，其 实现原理和技术效果类似，此处不再赘述。
在实际应用中，所述第一处理模块81、第二处理模块82、获取模块83、选取模块84、释放模块85可由位于装置上的中央处理器(Central Processing Unit，CPU)、微处理器(MicroProcessor Unit，MPU)、数字信号处理器(Digital Signal Processor，DSP)或现场可编程门阵列(Field－Programmable Gate Array，FPGA)等器件实现。
本领域内的技术人员应明白，本发明的实施例可提供为方法、装置、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、装置、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机 实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例的技术方案通过确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储；不用移动报文本体，仅对原始VIQ链表(第一VIQ链表)的节点信息进行重新排队，得到第二VIQ链表，通过第二VIQ链表与第二级存储进行交换，使得不同目的端口的报文在不同第二VIQ链表中，从而避免相互阻塞，解决了产生交换头阻的问题，提高了系统效率和性能。

Claims (16)

  1. 一种消除报文的交换头阻的方法，所述方法包括：
    根据第一虚拟输入队列VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；
    确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
  2. 根据权利要求1所述的方法，其中，所述根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息，包括：
    根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；
    将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
    更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针。
  3. 根据权利要求1所述的方法，其中，所述确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储，包括：
    根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；
    更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针；
    将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
  4. 根据权利要求2所述的方法，其中，在所述根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表之前，所述方法还包括：
    利用保序算法确定所述第一VIQ链表中的队首报文后，查询路由得到所述队首报文的目的端口信息。
  5. 根据权利要求2所述的方法，其中，在所述更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针之后，所述方法还包括：
    根据所述第二级存储的流量控制和利用保序算法得到符合条件的所述至少一个第二VIQ链表。
  6. 根据权利要求3所述的方法，其中，在所述根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文之后，在所述更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针之前，所述方法还包括：
    释放所述至少一个第二VIQ链表的头指针给所述本体随机存取存储器的空闲链表。
  7. 根据权利要求2所述的方法，其中，所述将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针，包括：
    将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表随机存取存储器中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针。
  8. 根据权利要求2所述的方法，其中，所述更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针，包括：
    将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链表的新的头指针。
  9. 根据权利要求3所述的方法，其中，所述根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文，包括：
    将所述至少一个第二VIQ链表的头指针作为读地址，读取本体随机存取存储器，得到所述至少一个第二VIQ链表的队首报文。
  10. 根据权利要求3所述的方法，其中，所述更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的新的头指针，包括：
    将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一个第二VIQ链表的链表随机存取存储器，得到所述至少一个第二VIQ链表的新的头指针。
  11. 一种消除报文的交换头阻的装置，所述装置包括：
    第一处理模块，配置为根据第一VIQ链表的节点信息和目的端口信息建立至少一个第二VIQ链表，并更新所述第一VIQ链表的节点信息；
    第二处理模块，配置为确定出所述至少一个第二VIQ链表的队首报文后更新所述至少一个第二VIQ链表的节点信息，将所述至少一个第二VIQ链表的队首报文和所述目的端口信息发送到第二级存储。
  12. 根据权利要求11所述的装置，其中，所述第一处理模块，配置为根据第一VIQ链表的节点信息和队首报文的目的端口信息建立至少一个第二VIQ链表；
    将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
    更新所述第一VIQ链表，得到所述第一VIQ链表的新的头指针。
  13. 根据权利要求11所述的装置，其中，所述第二处理模块，配置为根据所述至少一个第二VIQ链表的头指针得到所述至少一个第二VIQ链表的队首报文；
    更新所述至少一个第二VIQ链表，得到所述至少一个第二VIQ链表的 新的头指针；
    将所述至少一个第二VIQ链表的队首报文和所述目的端口信息一起发送到第二级存储。
  14. 根据权利要求12所述的装置，其中，所述第一处理模块，还配置为将所述第一VIQ链表的头指针作为写数据，将所述至少一个第二VIQ链表的尾指针作为写地址，写入所述至少一个第二VIQ链表的链表随机存取存储器中，将所述第一VIQ链表的头指针作为所述至少一个第二VIQ链表的新的尾指针；
    所述第一处理模块，还配置为将所述第一VIQ链表的头指针作为读地址，读取所述第一VIQ链表的链表随机存取存储器，得到所述第一VIQ链表的新的头指针。
  15. 根据权利要求13所述的装置，其中，所述第二处理模块，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取本体随机存取存储器，得到所述至少一个第二VIQ链表的队首报文；
    所述第二处理模块，还配置为将所述至少一个第二VIQ链表的头指针作为读地址，读取所述至少一个第二VIQ链表的链表随机存取存储器，得到所述至少一个第二VIQ链表的新的头指针。
  16. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至10任一项所述的消除报文的交换头阻的方法。
PCT/CN2017/077322 2016-03-21 2017-03-20 消除报文的交换头阻的方法、装置及计算机存储介质 WO2017162123A1 (zh)

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