WO2017155872A1 - Techniques for manipulating patterned features using ions - Google Patents

Techniques for manipulating patterned features using ions Download PDF

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Publication number
WO2017155872A1
WO2017155872A1 PCT/US2017/020909 US2017020909W WO2017155872A1 WO 2017155872 A1 WO2017155872 A1 WO 2017155872A1 US 2017020909 W US2017020909 W US 2017020909W WO 2017155872 A1 WO2017155872 A1 WO 2017155872A1
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WO
WIPO (PCT)
Prior art keywords
dimension
substrate
layer
cavity
feature
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2017/020909
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French (fr)
Inventor
Simon Ruffell
Huixiong Dai
Jun LANG
John Hautala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Varian Semiconductor Equipment Associates Inc
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Varian Semiconductor Equipment Associates Inc
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Filing date
Publication date
Application filed by Varian Semiconductor Equipment Associates Inc filed Critical Varian Semiconductor Equipment Associates Inc
Priority to KR1020227005074A priority Critical patent/KR102483418B1/en
Priority to JP2018546515A priority patent/JP6983796B2/en
Priority to KR1020187028119A priority patent/KR102365485B1/en
Priority to CN201780016912.XA priority patent/CN108780740B/en
Publication of WO2017155872A1 publication Critical patent/WO2017155872A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2049—Ion beam lithography processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/72—Repair or correction of mask defects
    • G03F1/74—Repair or correction of mask defects by charged particle beam [CPB], e.g. focused ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32366—Localised processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32403—Treating multiple sides of workpieces, e.g. 3D workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32422—Arrangement for selecting ions or species in the plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Definitions

  • the present embodiments relate to transistor processing techniques, and more particularly, to processing for three dimensional device formation.
  • a method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
  • a method of processing a substrate may include providing a cavity in the substrate, the cavity having a first dimension along a first direction within a substrate plane and a second dimension along a second direction within the substrate plane, the second direction being perpendicular to the first direction; depositing a layer comprising a layer material within the cavity; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane; wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the first dimension is selectively altered with respect to the second dimension.
  • a method of processing a substrate may include providing a cavity in the substrate, the cavity disposed at a first cavity location within the substrate; depositing a layer comprising a layer material within the cavity; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane; wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the cavity is disposed at a second cavity location in the substrate after the ion exposure.
  • FIGs. 1A-1D depict one example of processing of a device structure according to various embodiments of the disclosure
  • FIGs. 2A-2D depict another example of processing of a device structure according to embodiments of the disclosure.
  • FIGs. 3A-3G depict processing of a device structure according to further embodiments of the disclosure.
  • FIGs. 4A-4B depict processing of a device structure according to other embodiments of the disclosure.
  • FIGs. 5A-5C show processing of a device structure according to additional embodiments of the disclosure.
  • FIGs. 6A-6F illustrate processing of a device structure according to still other embodiments of the disclosure.
  • FIG. 7A to FIG. 7C illustrate another example of processing a device according to some embodiments of the disclosure
  • FIGs. 8A-8G another example of processing a device according to some additional embodiments of the disclosure.
  • FIG. 9A illustrates an exemplary processing apparatus according to embodiments of the disclosure.
  • FIG. 9B depicts details of an exemplary extraction plate according to embodiments of the disclosure. Detailed Description
  • This present embodiments provide novel techniques to pattern substrates and in particular novel techniques to modify a feature disposed on a substrate surface or extending from a substrate surface into the substrate.
  • substrate may refer to an entity such as a semiconductor wafer, insulating wafer, ceramic, as well as any layers or structures disposed thereon.
  • a surface feature, layer, series of layers, or other entity may be deemed to be disposed on a substrate, where the substrate may represent a combination of structures, such as a silicon wafer, oxide layer, and so forth.
  • the surface feature may be used for patterning a layer disposed underneath the surface feature.
  • a surface feature include a hole formed within a layer, such as a via, or trench.
  • a surface feature may be a pillar, a mesa structure, a line structure (line), or other feature extending above a substrate.
  • the term "hole” may refer to a structure extending through the entirety of a layer, such as a via.
  • the term “hole” may also refer to a structure such as a depression or recess formed within a layer not extending through the entirety of the thickness of a layer.
  • the term "layer” as used herein may refer to a continuous layer, a semicontinuous layer having blanket regions and regions of isolated features, or a group of isolated features generally composed of the same material and disposed on a common layer or substrate.
  • techniques are provided to modify a surface feature or surface features.
  • the techniques may be applied to the surface features after lithography processing is performed to form the surface feature(s).
  • the surface feature may be defined in photoresist, a hard mask material such as oxide, nitride, or carbon containing material, or other material.
  • This post-lithography processing may overcome shortfalls of known lithography, especially at the nanometer scale, such as for features having minimum dimensions in the range of 2 nm to 100 nm. The embodiments are not limited in this context.
  • Various embodiments are related to lithographic patterning and subsequent etching of patterned features used to fabricate features in a substrate, such as a device feature or group of features including an integrated circuit.
  • the techniques disclosed herein in particular address problems associated with fabricating smaller patterned features where the patterned features may be more closely packed than in arrangements achievable through optical lithography alone.
  • Various embodiments also address problems associated with pattern positioning and registration.
  • the present embodiments provide improvements over known techniques such as directional deposition, photoresist trim, focused ion beam modification, shrink etch, and tapered etch during etch of mask.
  • a feature may shrink in all directions. Notably, if a feature is asymmetric, the shrink is greater in the longer dimension.
  • a multiple operation process includes a deposition operation, such as a conformal deposition operation, where the deposition operation is performed on lithographically defined features, referred to herein as a "surface feature.”
  • This deposition operation may be performed on a developed photoresist feature, or alternatively on a feature formed in an etched film making up part or all of a hardmask, where the hardmask will eventually define the feature in the target material.
  • the surface feature may comprise a final material in a substrate, where the final material is not subsequently removed.
  • a directed etch including an ion exposure may be performed to etch at least a portion of the surface feature in a manner achieving one of the following: (a) a feature reduced in dimension along a first direction while not reduced in dimension along a second direction orthogonal to the first direction; (b) a new feature where the new feature is reduced in dimension in a first direction and is longer in dimension than the original surface feature in the second direction orthogonal to the first direction; (c) a feature shifted in position relative to its original position.
  • dimension may refer to a length, width, depth or height of a feature such as a surface feature along a given direction.
  • the surface feature may be reduced in size in addition to being shifted from an original position.
  • the material deposited in the deposition operation may be a first material different to the second material used as the mask material, i.e., the patterned feature material before processing.
  • etch having selectivity to just the deposited material can be taken advantage of, while the original mask material of the surface feature serves as an etch stop.
  • This selectivity can help improve within-wafer uniformity and local critical dimension uniformity (LCDU) of the pattemed features.
  • the material deposited in the deposition operation may be the same as the mask material (substrate feature material before processing). This latter approach avoids complications during the final etch transfer to the target layer when the mask is composed of more than one material.
  • the deposition process may be controllably varied across a wafer (substrate) using techniques available in a deposition chamber used to perform the selective deposition.
  • This variation may achieve controllably variable changes to the dimensions of targeted features. For example, multi-zone heating across different portions of a substrate may achieve this result.
  • local overlay error or variation in critical dimension (CD) may be reduced or eliminated by the intervening selective deposition operation.
  • FIGs. 1A-1D depict one example of processing a substrate such as a device structure according to various embodiments of the disclosure.
  • the cavity 102 may be a lithographically patterned feature formed by a known technique.
  • the substrate 100 includes a substrate base 104, where the substrate base 104 may be composed of a first material.
  • the substrate base 104 may be a hard mask material, a material such as SiC , or anti-reflective coating (ARC). Examples of known ARC materials may include silicon, carbon, or other combination of materials. The embodiments are not limited in this context.
  • the substrate 100 may be patterned by known lithographic techniques to form the cavity 102.
  • the cavity 102 may have a rectangular shape such as appropriate for a contact or via.
  • the illustration in FIG. 1C is for purposes of clarification, and the cavity may assume any shape including curved shapes, or complex shapes in other embodiments.
  • a layer 106 may be deposited on the substrate base 104, where the layer 106 is also deposited within the cavity 102 and coats the cavity 102.
  • the layer 106 may be deposited in a conformal manner so vertical surfaces (parallel to the Z-axis) as well as horizontal surfaces (parallel to the X-Y plane) are coated.
  • the layer thickness of layer 106 may be chosen so the layer thickness is less than approximately half of the smallest dimension (along the X-axis).
  • the embodiments are not limited in this context.
  • the layer 106 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other technique.
  • the embodiments are not limited in this context.
  • the layer 106 may comprise a second material different from the first material of the substrate base 104, or the layer 106 may comprise a same material as the first material of the substrate 104.
  • the layer 106 may be SiN, SiCh, SiARC, TiN.
  • the layer may be SiN while the base is SiCh.
  • the substrate base 104 allows the substrate base 104 to act as an etch stop for etching of layer 106 given the appropriate etch chemistry where SiN is etched selectively with respect to SiCh.
  • the cavity 102 may have dimensions of 10 nm, 20 nm, or 50 nm, while the thickness of the layer 106 is less than 5nm, lOnm, or 25 nm, respectively.
  • directional ions in a subsequent operation, may be directed to the substrate 100 in an ion exposure as shown in FIG. 1A.
  • the ions 110 may be directed at an angle of incidence forming a non-zero angle ( ⁇ ) with respect to a perpendicular 120 to the substrate plane P.
  • the angle ⁇ may vary between 5 degrees and 85 degrees.
  • the embodiments are not limited in this context.
  • the ions 110 may accordingly strike at least one sidewall, in this case shown as sidewall 108.
  • the ions 110 may be provided in an ion exposure including a reactive mixture, where the reactive mixture etches the layer material of layer 106.
  • the reactive mixture may be effective to volatilize layer material of layer 106 so material is evacuated and does not redeposit on other portions of the substrate 100 or cavity 102, as in known reactive ion processes. Etching of the layer material of layer 106 may in particular occur in regions of the substrate 100 impacted by the ions HO
  • RIE reactive ion etching
  • the substrate 100 is simultaneously exposed to reactive species, where the reactive species, together with the incident ions, generate reactive etching of at least the layer 106 of the substrate.
  • One chemical system commonly used in the industry for RIE processing is CEbF mixed with Ch.
  • This chemical system represents a known system for selectively etching SiN with respect to SiC or Si.
  • Another example is the use of CF4 or C4F8 for etching S1O2.
  • a further example is the use of Ch based chemistry for etching TiN.
  • any known RIE etch recipes may be applied for etching the layer 106 according to the composition of layer 106 and the composition of substrate base 104.
  • the use of this chemical system in RIE processing leads to two competing mechanisms taking place on the surfaces of all materials on a substrate subjected to the RIE plasma. The first mechanism is etching of the surfaces of the substrate, while the second mechanism is deposition of a carbon-based polymer on substrate surfaces.
  • polymer deposition may be useful as the dominant mechanism at the substrate surface when not subject to ion bombardment.
  • energetic ion bombardment by species extracted from the RIE plasma can break apart the polymer and produce dangling bonds at the material surface, causing etching of the surface to become the dominant mechanism.
  • Many other chemical systems may be used as needed to provide a reactive ion etching process according to the material to be reactively etched, as will be appreciated by those of skill in the art.
  • the substrate 100 may be exposed to reactive neutral species 124, where the reactive neutral species are derived from precursor gas composition used to generate the RIE plasma.
  • the reactive neutral species 124 may arrive isotropically to the substrate 100, where every portion of the different exposed surfaces of the substrate 100 are impacted by the reactive neutral species 124, as shown in FIG. 1A.
  • the present embodiments harness the principles of known RIE processing where etching of a given surface is enhanced in the presence of ions.
  • etching may take place just in regions of the substrate 100 impacted by the directional ions, i.e., in regions impacted by the ions 110, while leaving other surfaces unetched.
  • the processing apparatus 900 may be a known compact plasma processing system generating an ion beam shown as the ions 110.
  • the ion beam may be extracted from a plasma 904 generated in a plasma chamber 902 by any known technique.
  • the processing apparatus 900 may include an extraction plate 906 having an extraction aperture 908, where the ions 110 are extracted as an ion beam from the plasma 904 and directed to the substrate 100. As shown in FIG.
  • the extraction aperture may be elongated along the Y- axis, providing a ribbon ion beam extending, for example, over an entire substrate along the direction parallel to the Y-axis.
  • the substrate 100 may be disposed on a substrate holder 910 and scanned along the X-axis to provide coverage at different regions of the substrate 100 or over the entirety of the substrate.
  • the extraction aperture 908 may have a different shape such as a square or circular shape.
  • the plasma chamber 902 may also serve as a deposition process chamber to provide material for depositing on the substrate 100 in the deposition operation preceding etching.
  • the substrate holder 910 may further include a heater assembly 91 1 for selectively heating the substrate 100 to different temperatures in different regions within the X-Y plane for selectively changing the amount of depositing material as discussed above.
  • reactive species may be provided or created in the plasma chamber 902 and may also impinge upon the substrate 100. While various non- ionized reactive species may impinge upon all surfaces of substrate 100 including different surfaces in cavity 102, etching may take place in areas impacted by the ions 110, as in known RIE processes, while little or no etching takes place in regions not impacted by ions 110.
  • a first portion 1 12 of a given surface feature such as cavity 102 impacted by the ions 110 may be etched at a first rate, while a second portion 1 14 of cavity 102 not impacted by ions is etched at a second rate less than the first rate. In some examples, the second rate may be zero or may be much less than the first rate.
  • selective etching of the deposited layer, layer 106 may take place along the right sidewall as shown in FIG. IB, shown as sidewall 108.
  • the result of the deposition process for depositing layer 106 and selective directional etching of a portion of layer 106 in cavity 102, is the reduction in width of cavity 102 from width Wl to width W2 along the x-axis, as well as a reduction in length along the X-axis.
  • the ions 110 may be directed along a first direction with respect to the X-Y plane, such as along the X-axis.
  • the first portion 112 may be the region of the cavity 102 lying along the right sidewall parallel to the Y-axis, since this region faces the ions 1 10 and is perpendicular to the direction of ions 110, and accordingly is disposed to intercept the ions 110.
  • the second portion 1 14 may be the region of the cavity 102 lying along sidewalls parallel to the X-axis since these regions may receive little or no impact as ions travel parallel to the surface of these regions.
  • the second portion 114 may also extend to the regions of the cavity 102 along left sidewall as shown in FIG. 1C, since this region is shadowed from the ions 1 10. Because just the layer 106 along the right sidewall is removed due to direction of ions 110 (see also FIG.
  • the reduction in width of cavity 102 from Wl to W2 along the direction parallel to X-axis may correspond to the thickness of layer 106 in this example, while the reduction in length of cavity 102 along the direction parallel to the Y-axis from LI to L2 corresponds to twice the thickness of layer 106.
  • the ions 1 10 may be directed in an exposure where reactive etching of layer 106 is selective with respect to etching of substrate base 104, where the substrate base 104 is a different material than material of layer 106.
  • layer 106 may be a photoresist while substrate base 104 is an oxide material. Accordingly, etching may cease of decrease drastically once layer 106 is removed from sidewall 108.
  • FIGs. 1A-1D affords the ability to selectively change the dimensions of the cavity 102, for example, where a first dimension is selectively altered with respect to a second dimension, e.g., where the dimension along the Y-axis is changed to a different extent as compared to the dimension along the X-axis.
  • FIGs. 2A-2D depict another example of processing of a substrate according to embodiments of the disclosure. In the example shown, the conventions of FIGs. 1A-1D may apply while like reference numbers refer to similar or the same entities. In FIGS.
  • FIG. 2A-2D there is shown a conformal deposition process, where the conformal deposition process may form an initial operation to be followed a directional etch process, such as depicted in FIGs. 3A-3G discussed below.
  • a substrate 200 is provided having a cavity 202, in this case of circular shape, within a base 204.
  • a layer 206 is deposited as generally described above with respect to layer 106. The deposition of the layer 206 may have the effect of reducing the diameter of cavity 202 by from Wl to W2 by an amount equal to twice the thickness of layer 206 as shown.
  • FIGs. 3A-3G depict processing of a device structure according to further embodiments of the disclosure.
  • the reactive neutral species 124 are not shown.
  • FIG. 3A and FIG. 3B there is shown the substrate 200 after deposition of the layer 206.
  • FIG. 3C and FIG. 3D there is shown an example of selective etching of the layer 106, where the ions 210 form trajectories parallel to the Y-axis and are directed to surfaces of the cavity 202 generally oriented along the X-axis, including opposite sidewall portions, while not necessarily parallel to the Y-axis.
  • the ions 210 travel parallel to the Y-axis and accordingly do not impact the layer 206 in regions generally oriented along the Y-axis, while impacting regions of layer 206 more oriented parallel to the X-axis. Accordingly, the resulting structure has no material of layer 206 along the vertical cut (parallel to the Y-axis) shown in FIG. 3C, while the layer 206 is preserved at least in part in portions of the sidewalls of cavity 202 lying along the horizontal cut.
  • the ions 210 may or may not impact the bottom of cavity 202. In the example of FIG.
  • the ions 210 do not impact the bottom of cavity 202, leaving layer 206 intact, while in the example of FIG. 3E and FIG. 3G, ions 210 do impact the bottom surface of cavity, removing the layer 206.
  • the shape and size of cavity 202 is changed from a circular shape to an elongated shape, such as an oval shape or elliptical shape as shown in FIG. 3C.
  • FIGs. 4A to 8C to follow directional ion etching processes are depicted in plan view. Notably in these depictions, the trajectories of ions form a non-zero angle with respect to the perpendicular 120 as illustrate in FIG. 1A.
  • the operations depicted in FIG. 2 and FIG. 3 may be extended wherein etching using directional ions along the directions shown in FIGs. 3D and 3F is continued after layer 206 is removed.
  • the etching species used to etch layer 206 may also be effective to etch the base 204, where the base 204 may be made of a base material, where the base material is the same material or a different material from layer 206.
  • the base 204 may be made of a base material, where the base material is the same material or a different material from layer 206.
  • a more elongated oval shape is formed having greater a dimension than the original dimension of cavity 202 along the Y-axis and shorter dimension along the X-axis as opposed to the original dimension.
  • the greater dimension of an elongated shape may be twice the shorter dimension, or five times the shorter dimension. The embodiments are not limited in this context.
  • FIGs. 5A-5C show processing of a device structure according to additional embodiments of the disclosure.
  • a substrate 500 having a base 504 is provided with a trench 502 elongated along the X-axis and having a racetrack shape.
  • the structure is shown after a deposition process is performed to deposit a layer 506 within the trench 502.
  • the length of the trench 502 has been reduced along the X-axis from an original length LI by an amount equal to 2 times the thickness of the layer 506 as shown by L2.
  • the width along the Y axis of trench 502 has been reduced by a similar amount from an original width Wl to W2. As shown in FIG.
  • the trench 502 may be etched by directing ions 503 toward endwalls 508 and at a non-zero angle of incidence ⁇ with respect to a perpendicular to a substrate plane of base 504 (see FIG. 1A for further definition of ⁇ ).
  • layer 506 may be removed along the endwalls 508.
  • the trench width may be selectively reduced along the Y-axis to W2 while restoring the length of the trench 502 along the X-axis to the original length LI, since the layer 506 remains just along the portions of the trench 502 lying parallel to the ions 503.
  • etch chemistry is used providing a high degree of selectivity of etching material of layer 506 with respect to the material of base 504. In this manner the etching may cease when the base material of base 504 is encountered.
  • the structure of FIG. 5A may be etched using ions 505, where the ions 505 are directed in a similar manner as the process of FIG. 5B to the endwalls 508.
  • the etching process using ions 505 may be continued to etch material within base 504 so the length L3 of the trench 502 is greater than its original length LI before deposition of layer 506.
  • the etch composition of species used during ion etching of base 504 may be changed from the etch composition used to etch the layer 506.
  • the etch composition chosen to etch layer 506 and base 504 may be the same composition and may be relatively non-selective where the etch rate of layer 506 is similar to the etch rate of base 504.
  • FIGs. 6A-6F illustrate processing of a substrate according to still other embodiments of the disclosure.
  • the trench 502 is again shown after formation of the layer 506, reducing the original trench size including the length along the X-axis from LI to L2.
  • ions 603 are directed along trajectories parallel to the X-axis just to the right endwall, shown also as endwall 508, resulting in the trench 502 having reduced dimensions along three sides, while retaining the original position of the right endwall before deposition of layer 506.
  • ions 605 are directed toward the right sidewall to continue etching of the trench 502, as generally described above with respect to FIG.
  • FIG. 6C provides a specific example where a surface feature location, in this case a trench location with respect to a position along the X- axis, is shifted, while the trench is also selectively narrowed along the Y-axis.
  • FIG. 6D there is shown a substrate 610 having a cavity of circular shape after deposition of a layer 616.
  • a resulting shape of the cavity 612 is shown when ions 614 are directed just toward the upper (in FIG. 6E) sidewall 615, resulting in a cavity 612 where the position of the upper sidewall region is the same as before deposition as layer 616, while other regions of cavity 612 are reduced in size, resulting in a more oval shape.
  • further etching by ions 618 may be performed along the same direction as ions 614, where the ions 618 may be similar to or different from the ions 614.
  • FIG. 7A and FIG. 7B there is shown a further example of processing a cavity, where the trench 502 is formed as described above by depositing a layer 506. Subsequently, ions such as the ions 603, or a combination of ions 603 and ions 605, may be directed along the X-axis to etch just the right endwall, shown as endwall 508 in FIG. 7B.
  • the resulting trench shown as trench 502 may have the same length, shown as LI, as before deposition of layer 506, while the center of the trench 502 along the X-axis in FIG. 7B is shifted to the right with respect to trench 502 of FIG. 7A.
  • ions 702 may be directed parallel to the Y- axis to the top edge 704 and bottom edge 706 of the trench 502.
  • the material of layer 506 may differ from the material of base 504 wherein etching by the ions 702 of the layer 506 is highly selective with respect to the etching of base 504.
  • ions 702 may be provided in a reactive ion etch process for etching layer 506 at a rate twice as fast as the etching of base 504, or five times as fast, 10 times as fast, or 20 times as fast.
  • the embodiments are not limited in this context.
  • the layer 506 may be completely removed from the bottom edge 706 and top edge 704, while little or no material from base 504 is removed from these edges.
  • This etching allows the original trench width Wl to be restored, corresponding to the trench width before deposition of layer 506.
  • FIG. 7C A net result of these processes is shown in FIG. 7C, where the trench 502 is shifted to the right from an original trench location before deposition of layer 506, as shown by the dashed curve in FIG.
  • FIGs. 8A-8G another example of processing a substrate according to some additional embodiments of the disclosure.
  • a substrate 800 is provided with a pillar 802 extending above a base 804.
  • the pillar 802 may, but need not be, a different material than the material of base 804.
  • a layer 806 is deposited, as generally described above.
  • FIG. 8B and FIG. 8E a layer 806 is deposited, as generally described above.
  • 8C ions 812 are directed toward the pillar 802 in two opposite directions, where the opposite directions lie parallel to the Y-axis as shown, resulting in removal of layer 806 from regions generally more aligned along the X-axis, as further shown in the cut sections of FIG. 8F and FIG. 8G. Accordingly, the original diameter Dl is increased to a diameter D2 along the X-axis, as shown in FIG. 8D, while the original diameter Dl may be maintained along the X-axis, as shown in FIG. 8B. This directional etching allows the originally circular shape of the pillar 802 to be transformed to an oval shape as illustrate in FIG. 8C.
  • directional etching of ions may be performed by rotating a substrate within the X-Y plane to any desired angle.
  • a trench feature may be oriented with its long axis at a 45-degree angle with respect to the Y-axis while a ribbon beam directed to the trench feature has its axis oriented along the Y-axis as in FIG. 9B.
  • an operation involving deposition of a layer on a surface feature followed by selective directional etching of the surface feature as described above may be repeated in an iterative fashion.
  • a given cycle may be composed of deposition of a layer followed by etching of the surface feature including the deposited layer along a given direction. This given cycle may be repeated a desired number of times to adjust the dimension of a feature selectively along a given direction, to adjust the shape, or adjust the position, for example.
  • an ion beam shown as ions 110 may be present when region 912 is under extraction aperture 908, while the ion beam is extinguished when the region 914 is under extraction aperture 908.
  • the present embodiments provide various advantages over conventional processing to define features in a substrate.
  • Currently there are no known techniques able to achieve what is described in these embodiments, in particular over a full wafer in a manufacturing environment.
  • Several problems may be solved with these embodiments including a first advantage of being able to shift a surface feature within a substrate in a desired direction and in a desired amount.
  • the present embodiments also proved the advantage where a feature may be shifted and the original feature shape or dimensions may be preserved or changed.
  • Another advantage of the present embodiments is the ability to generate otherwise unobtainable feature dimensions and shapes.

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Abstract

A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape, feature location, and dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.

Description

TECHNIQUES FOR MANIPULATING PATTERNED FEATURES USING IONS
Field
[0001] The present embodiments relate to transistor processing techniques, and more particularly, to processing for three dimensional device formation.
Background
[0002] As semiconductor devices continue to scale to smaller dimensions, the ability to pattern features becomes increasingly difficult. These difficulties include in one aspect the ability to obtain features at a target size for a given technology generation. Another difficulty is the ability to obtain the correct shape of a patterned feature, as well as the correct placement of a patterned feature.
[0003] With respect to these and other considerations the present improvements may be useful.
Brief Summary
[0004] In one embodiment, a method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
[0005] In another embodiment, a method of processing a substrate may include providing a cavity in the substrate, the cavity having a first dimension along a first direction within a substrate plane and a second dimension along a second direction within the substrate plane, the second direction being perpendicular to the first direction; depositing a layer comprising a layer material within the cavity; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane; wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the first dimension is selectively altered with respect to the second dimension.
[0006] In a further embodiment, a method of processing a substrate may include providing a cavity in the substrate, the cavity disposed at a first cavity location within the substrate; depositing a layer comprising a layer material within the cavity; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane; wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the cavity is disposed at a second cavity location in the substrate after the ion exposure. Brief Description of the Drawings
[0007] FIGs. 1A-1D depict one example of processing of a device structure according to various embodiments of the disclosure;
[0008] FIGs. 2A-2D depict another example of processing of a device structure according to embodiments of the disclosure;
[0009] FIGs. 3A-3G depict processing of a device structure according to further embodiments of the disclosure;
[0010] FIGs. 4A-4B depict processing of a device structure according to other embodiments of the disclosure;
[0011] FIGs. 5A-5C show processing of a device structure according to additional embodiments of the disclosure;
[0012] FIGs. 6A-6F illustrate processing of a device structure according to still other embodiments of the disclosure;
[0013] FIG. 7A to FIG. 7C illustrate another example of processing a device according to some embodiments of the disclosure;
[0014] FIGs. 8A-8G another example of processing a device according to some additional embodiments of the disclosure;
[0015] FIG. 9A illustrates an exemplary processing apparatus according to embodiments of the disclosure; and
[0016] FIG. 9B depicts details of an exemplary extraction plate according to embodiments of the disclosure. Detailed Description
[0017] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, where some embodiments are shown. The subject matter of the present disclosure may be embodied in many different forms and are not to be construed as limited to the embodiments set forth herein. These embodiments are provided so this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
[0018] This present embodiments provide novel techniques to pattern substrates and in particular novel techniques to modify a feature disposed on a substrate surface or extending from a substrate surface into the substrate. As used herein the term "substrate" may refer to an entity such as a semiconductor wafer, insulating wafer, ceramic, as well as any layers or structures disposed thereon. As such, a surface feature, layer, series of layers, or other entity may be deemed to be disposed on a substrate, where the substrate may represent a combination of structures, such as a silicon wafer, oxide layer, and so forth.
[0019] In various embodiments, the surface feature may be used for patterning a layer disposed underneath the surface feature. Examples of a surface feature include a hole formed within a layer, such as a via, or trench. In other examples a surface feature may be a pillar, a mesa structure, a line structure (line), or other feature extending above a substrate. The term "hole" may refer to a structure extending through the entirety of a layer, such as a via. The term "hole" may also refer to a structure such as a depression or recess formed within a layer not extending through the entirety of the thickness of a layer. Moreover, the term "layer" as used herein may refer to a continuous layer, a semicontinuous layer having blanket regions and regions of isolated features, or a group of isolated features generally composed of the same material and disposed on a common layer or substrate.
[0020] In various embodiments, techniques are provided to modify a surface feature or surface features. The techniques may be applied to the surface features after lithography processing is performed to form the surface feature(s). In various embodiments, the surface feature may be defined in photoresist, a hard mask material such as oxide, nitride, or carbon containing material, or other material. This post-lithography processing may overcome shortfalls of known lithography, especially at the nanometer scale, such as for features having minimum dimensions in the range of 2 nm to 100 nm. The embodiments are not limited in this context.
[0021] Various embodiments are related to lithographic patterning and subsequent etching of patterned features used to fabricate features in a substrate, such as a device feature or group of features including an integrated circuit. The techniques disclosed herein in particular address problems associated with fabricating smaller patterned features where the patterned features may be more closely packed than in arrangements achievable through optical lithography alone. Various embodiments also address problems associated with pattern positioning and registration.
[0022] The present embodiments provide improvements over known techniques such as directional deposition, photoresist trim, focused ion beam modification, shrink etch, and tapered etch during etch of mask. In the latter technique, a feature may shrink in all directions. Notably, if a feature is asymmetric, the shrink is greater in the longer dimension.
[0023] In accordance with various embodiments a multiple operation process includes a deposition operation, such as a conformal deposition operation, where the deposition operation is performed on lithographically defined features, referred to herein as a "surface feature." This deposition operation may be performed on a developed photoresist feature, or alternatively on a feature formed in an etched film making up part or all of a hardmask, where the hardmask will eventually define the feature in the target material. Alternatively, the surface feature may comprise a final material in a substrate, where the final material is not subsequently removed.
[0024] In a subsequent operation, a directed etch including an ion exposure may be performed to etch at least a portion of the surface feature in a manner achieving one of the following: (a) a feature reduced in dimension along a first direction while not reduced in dimension along a second direction orthogonal to the first direction; (b) a new feature where the new feature is reduced in dimension in a first direction and is longer in dimension than the original surface feature in the second direction orthogonal to the first direction; (c) a feature shifted in position relative to its original position. As used herein the term "dimension" may refer to a length, width, depth or height of a feature such as a surface feature along a given direction. In various embodiments, the surface feature may be reduced in size in addition to being shifted from an original position. According to some embodiments, the material deposited in the deposition operation may be a first material different to the second material used as the mask material, i.e., the patterned feature material before processing.
[0025] One advantage to these embodiments is realized where an etch having selectivity to just the deposited material can be taken advantage of, while the original mask material of the surface feature serves as an etch stop. This selectivity can help improve within-wafer uniformity and local critical dimension uniformity (LCDU) of the pattemed features. In other embodiments, the material deposited in the deposition operation may be the same as the mask material (substrate feature material before processing). This latter approach avoids complications during the final etch transfer to the target layer when the mask is composed of more than one material.
[0026] In still additional embodiments, the deposition process may be controllably varied across a wafer (substrate) using techniques available in a deposition chamber used to perform the selective deposition. This variation may achieve controllably variable changes to the dimensions of targeted features. For example, multi-zone heating across different portions of a substrate may achieve this result. In a subsequent operation, if a uniform etch is performed, local overlay error or variation in critical dimension (CD) may be reduced or eliminated by the intervening selective deposition operation.
[0027] FIGs. 1A-1D depict one example of processing a substrate such as a device structure according to various embodiments of the disclosure. In FIG. 1A there is shown a side cross-sectional view of a substrate 100 including a surface feature in the form of a cavity 102. In various embodiments, the cavity 102 may be a lithographically patterned feature formed by a known technique. The substrate 100 includes a substrate base 104, where the substrate base 104 may be composed of a first material. As noted in some examples, the substrate base 104 may be a hard mask material, a material such as SiC , or anti-reflective coating (ARC). Examples of known ARC materials may include silicon, carbon, or other combination of materials. The embodiments are not limited in this context. The substrate 100 may be patterned by known lithographic techniques to form the cavity 102. As shown in FIG. 1C, presenting a plan view, the cavity 102 may have a rectangular shape such as appropriate for a contact or via. The illustration in FIG. 1C is for purposes of clarification, and the cavity may assume any shape including curved shapes, or complex shapes in other embodiments. In accordance with various embodiments, a layer 106 may be deposited on the substrate base 104, where the layer 106 is also deposited within the cavity 102 and coats the cavity 102. In some embodiments the layer 106 may be deposited in a conformal manner so vertical surfaces (parallel to the Z-axis) as well as horizontal surfaces (parallel to the X-Y plane) are coated. In various embodiments, the layer thickness of layer 106 may be chosen so the layer thickness is less than approximately half of the smallest dimension (along the X-axis). The embodiments are not limited in this context. The layer 106 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other technique. The embodiments are not limited in this context. The layer 106 may comprise a second material different from the first material of the substrate base 104, or the layer 106 may comprise a same material as the first material of the substrate 104. For example, the layer 106 may be SiN, SiCh, SiARC, TiN. To name just one example where the material of layer 106 differs from the substrate base 104, the layer may be SiN while the base is SiCh. Such a combination, among others, allows the substrate base 104 to act as an etch stop for etching of layer 106 given the appropriate etch chemistry where SiN is etched selectively with respect to SiCh. As an example, the cavity 102 may have dimensions of 10 nm, 20 nm, or 50 nm, while the thickness of the layer 106 is less than 5nm, lOnm, or 25 nm, respectively.
[0028] According to various embodiments, in a subsequent operation, directional ions, shown as ions 110, may be directed to the substrate 100 in an ion exposure as shown in FIG. 1A. The ions 110 may be directed at an angle of incidence forming a non-zero angle (Θ) with respect to a perpendicular 120 to the substrate plane P. According to various embodiments, the angle Θ, may vary between 5 degrees and 85 degrees. The embodiments are not limited in this context. [0029] The ions 110 may accordingly strike at least one sidewall, in this case shown as sidewall 108. In various embodiments, the ions 110 may be provided in an ion exposure including a reactive mixture, where the reactive mixture etches the layer material of layer 106. The reactive mixture may be effective to volatilize layer material of layer 106 so material is evacuated and does not redeposit on other portions of the substrate 100 or cavity 102, as in known reactive ion processes. Etching of the layer material of layer 106 may in particular occur in regions of the substrate 100 impacted by the ions HOVarious embodiments extend to the use of a broad array of gas mixtures used for conventional reactive ion etching (RIE) processing. Thus, in addition to providing ions to a substrate at a chosen angle(s) of incidence, the substrate 100 is simultaneously exposed to reactive species, where the reactive species, together with the incident ions, generate reactive etching of at least the layer 106 of the substrate. One chemical system commonly used in the industry for RIE processing is CEbF mixed with Ch. This chemical system represents a known system for selectively etching SiN with respect to SiC or Si. Another example is the use of CF4 or C4F8 for etching S1O2. A further example is the use of Ch based chemistry for etching TiN. In other embodiments, any known RIE etch recipes may be applied for etching the layer 106 according to the composition of layer 106 and the composition of substrate base 104. The use of this chemical system in RIE processing leads to two competing mechanisms taking place on the surfaces of all materials on a substrate subjected to the RIE plasma. The first mechanism is etching of the surfaces of the substrate, while the second mechanism is deposition of a carbon-based polymer on substrate surfaces. Under certain process conditions polymer deposition may be useful as the dominant mechanism at the substrate surface when not subject to ion bombardment. Notably, energetic ion bombardment by species extracted from the RIE plasma can break apart the polymer and produce dangling bonds at the material surface, causing etching of the surface to become the dominant mechanism. Many other chemical systems may be used as needed to provide a reactive ion etching process according to the material to be reactively etched, as will be appreciated by those of skill in the art.
[0030] In the operation generally depicted in FIG. 1A, the substrate 100 may be exposed to reactive neutral species 124, where the reactive neutral species are derived from precursor gas composition used to generate the RIE plasma. The reactive neutral species 124 may arrive isotropically to the substrate 100, where every portion of the different exposed surfaces of the substrate 100 are impacted by the reactive neutral species 124, as shown in FIG. 1A. Notably, the present embodiments harness the principles of known RIE processing where etching of a given surface is enhanced in the presence of ions. Notably, in accordance with the present embodiments, etching may take place just in regions of the substrate 100 impacted by the directional ions, i.e., in regions impacted by the ions 110, while leaving other surfaces unetched.
[0031] Turning now to FIG. 9A an exemplary processing apparatus, shown as processing apparatus 900, is illustrated, for providing an ion exposure as also illustrated in FIG. 1A. The processing apparatus 900 may be a known compact plasma processing system generating an ion beam shown as the ions 110. The ion beam may be extracted from a plasma 904 generated in a plasma chamber 902 by any known technique. The processing apparatus 900 may include an extraction plate 906 having an extraction aperture 908, where the ions 110 are extracted as an ion beam from the plasma 904 and directed to the substrate 100. As shown in FIG. 9B, the extraction aperture may be elongated along the Y- axis, providing a ribbon ion beam extending, for example, over an entire substrate along the direction parallel to the Y-axis. In various embodiments, the substrate 100 may be disposed on a substrate holder 910 and scanned along the X-axis to provide coverage at different regions of the substrate 100 or over the entirety of the substrate. In other embodiments, the extraction aperture 908 may have a different shape such as a square or circular shape.
[0032] In some embodiments, the plasma chamber 902 may also serve as a deposition process chamber to provide material for depositing on the substrate 100 in the deposition operation preceding etching. The substrate holder 910 may further include a heater assembly 91 1 for selectively heating the substrate 100 to different temperatures in different regions within the X-Y plane for selectively changing the amount of depositing material as discussed above.
[0033] During an ion exposure, reactive species may be provided or created in the plasma chamber 902 and may also impinge upon the substrate 100. While various non- ionized reactive species may impinge upon all surfaces of substrate 100 including different surfaces in cavity 102, etching may take place in areas impacted by the ions 110, as in known RIE processes, while little or no etching takes place in regions not impacted by ions 110. Thus, referring to FIG. 1C discussed below, a first portion 1 12 of a given surface feature such as cavity 102 impacted by the ions 110 may be etched at a first rate, while a second portion 1 14 of cavity 102 not impacted by ions is etched at a second rate less than the first rate. In some examples, the second rate may be zero or may be much less than the first rate.
[0034] As a result, as shown in FIGs. IB and ID, selective etching of the deposited layer, layer 106, may take place along the right sidewall as shown in FIG. IB, shown as sidewall 108. The result of the deposition process for depositing layer 106 and selective directional etching of a portion of layer 106 in cavity 102, is the reduction in width of cavity 102 from width Wl to width W2 along the x-axis, as well as a reduction in length along the X-axis. As further shown in FIG. 1C, the ions 110 may be directed along a first direction with respect to the X-Y plane, such as along the X-axis. In this manner the first portion 112 may be the region of the cavity 102 lying along the right sidewall parallel to the Y-axis, since this region faces the ions 1 10 and is perpendicular to the direction of ions 110, and accordingly is disposed to intercept the ions 110. The second portion 1 14 may be the region of the cavity 102 lying along sidewalls parallel to the X-axis since these regions may receive little or no impact as ions travel parallel to the surface of these regions. The second portion 114 may also extend to the regions of the cavity 102 along left sidewall as shown in FIG. 1C, since this region is shadowed from the ions 1 10. Because just the layer 106 along the right sidewall is removed due to direction of ions 110 (see also FIG. 1C for the orientation of ions 110 within the X-Y plane), the reduction in width of cavity 102 from Wl to W2 along the direction parallel to X-axis may correspond to the thickness of layer 106 in this example, while the reduction in length of cavity 102 along the direction parallel to the Y-axis from LI to L2 corresponds to twice the thickness of layer 106.
[0035] In various embodiments, the ions 1 10 may be directed in an exposure where reactive etching of layer 106 is selective with respect to etching of substrate base 104, where the substrate base 104 is a different material than material of layer 106. For example, layer 106 may be a photoresist while substrate base 104 is an oxide material. Accordingly, etching may cease of decrease drastically once layer 106 is removed from sidewall 108.
[0036] Accordingly, the multiple operation process outlined in FIGs. 1A-1D affords the ability to selectively change the dimensions of the cavity 102, for example, where a first dimension is selectively altered with respect to a second dimension, e.g., where the dimension along the Y-axis is changed to a different extent as compared to the dimension along the X-axis. [0037] FIGs. 2A-2D depict another example of processing of a substrate according to embodiments of the disclosure. In the example shown, the conventions of FIGs. 1A-1D may apply while like reference numbers refer to similar or the same entities. In FIGS. 2A-2D there is shown a conformal deposition process, where the conformal deposition process may form an initial operation to be followed a directional etch process, such as depicted in FIGs. 3A-3G discussed below. In FIG. 2A and 2B a substrate 200 is provided having a cavity 202, in this case of circular shape, within a base 204. In FIGs. 2C and 2D a layer 206 is deposited as generally described above with respect to layer 106. The deposition of the layer 206 may have the effect of reducing the diameter of cavity 202 by from Wl to W2 by an amount equal to twice the thickness of layer 206 as shown.
[0038] FIGs. 3A-3G depict processing of a device structure according to further embodiments of the disclosure. For clarity, in the figures to follow, the reactive neutral species 124 are not shown. In FIG. 3A and FIG. 3B there is shown the substrate 200 after deposition of the layer 206. Turning now to FIG. 3C and FIG. 3D there is shown an example of selective etching of the layer 106, where the ions 210 form trajectories parallel to the Y-axis and are directed to surfaces of the cavity 202 generally oriented along the X-axis, including opposite sidewall portions, while not necessarily parallel to the Y-axis. In this example, the ions 210 travel parallel to the Y-axis and accordingly do not impact the layer 206 in regions generally oriented along the Y-axis, while impacting regions of layer 206 more oriented parallel to the X-axis. Accordingly, the resulting structure has no material of layer 206 along the vertical cut (parallel to the Y-axis) shown in FIG. 3C, while the layer 206 is preserved at least in part in portions of the sidewalls of cavity 202 lying along the horizontal cut. In different embodiments, depending upon the angle of incidence Θ of ions 210, the width of cavity 202 and height of cavity 202 (along the Z-axis), the ions 210 may or may not impact the bottom of cavity 202. In the example of FIG. 3D and FIG. 3F the ions 210 do not impact the bottom of cavity 202, leaving layer 206 intact, while in the example of FIG. 3E and FIG. 3G, ions 210 do impact the bottom surface of cavity, removing the layer 206. As a result of the operations of FIGs. 2-3 the shape and size of cavity 202 is changed from a circular shape to an elongated shape, such as an oval shape or elliptical shape as shown in FIG. 3C.
[0039] In the FIGs. 4A to 8C to follow directional ion etching processes are depicted in plan view. Notably in these depictions, the trajectories of ions form a non-zero angle with respect to the perpendicular 120 as illustrate in FIG. 1A. In the example of FIG. 4A and FIG. 4B the operations depicted in FIG. 2 and FIG. 3 may be extended wherein etching using directional ions along the directions shown in FIGs. 3D and 3F is continued after layer 206 is removed. In these embodiments, the etching species used to etch layer 206, such as ions 210 in combination with other reactive species, may also be effective to etch the base 204, where the base 204 may be made of a base material, where the base material is the same material or a different material from layer 206. As shown in FIG 4B, a more elongated oval shape is formed having greater a dimension than the original dimension of cavity 202 along the Y-axis and shorter dimension along the X-axis as opposed to the original dimension. In some examples the greater dimension of an elongated shape may be twice the shorter dimension, or five times the shorter dimension. The embodiments are not limited in this context.
[0040] FIGs. 5A-5C show processing of a device structure according to additional embodiments of the disclosure. In this example a substrate 500 having a base 504 is provided with a trench 502 elongated along the X-axis and having a racetrack shape. In FIG. 5A, the structure is shown after a deposition process is performed to deposit a layer 506 within the trench 502. The length of the trench 502 has been reduced along the X-axis from an original length LI by an amount equal to 2 times the thickness of the layer 506 as shown by L2. The width along the Y axis of trench 502 has been reduced by a similar amount from an original width Wl to W2. As shown in FIG. 5B, the trench 502 may be etched by directing ions 503 toward endwalls 508 and at a non-zero angle of incidence Θ with respect to a perpendicular to a substrate plane of base 504 (see FIG. 1A for further definition of Θ). As a result, layer 506 may be removed along the endwalls 508. As a result of the deposition of layer 506 and the direction reactive etching of trench 502 the trench width may be selectively reduced along the Y-axis to W2 while restoring the length of the trench 502 along the X-axis to the original length LI, since the layer 506 remains just along the portions of the trench 502 lying parallel to the ions 503. To facilitate restoration of the length of the trench 502 to its original length LI before deposition of layer 506, etch chemistry is used providing a high degree of selectivity of etching material of layer 506 with respect to the material of base 504. In this manner the etching may cease when the base material of base 504 is encountered.
[0041] In the example of FIG. 5C, the structure of FIG. 5A may be etched using ions 505, where the ions 505 are directed in a similar manner as the process of FIG. 5B to the endwalls 508. In this example, the etching process using ions 505 may be continued to etch material within base 504 so the length L3 of the trench 502 is greater than its original length LI before deposition of layer 506. In some variants, the etch composition of species used during ion etching of base 504 may be changed from the etch composition used to etch the layer 506. Alternatively, the etch composition chosen to etch layer 506 and base 504 may be the same composition and may be relatively non-selective where the etch rate of layer 506 is similar to the etch rate of base 504.
[0042] FIGs. 6A-6F illustrate processing of a substrate according to still other embodiments of the disclosure. In this example, in FIG. 6A the trench 502 is again shown after formation of the layer 506, reducing the original trench size including the length along the X-axis from LI to L2. In FIG. 6B, ions 603 are directed along trajectories parallel to the X-axis just to the right endwall, shown also as endwall 508, resulting in the trench 502 having reduced dimensions along three sides, while retaining the original position of the right endwall before deposition of layer 506. In FIG. 6C ions 605 are directed toward the right sidewall to continue etching of the trench 502, as generally described above with respect to FIG. 5C, except in this case the ions 605 are just directed to the right as shown. This etching process allows for formation of a trench 502 having a narrower width W2 along the Y-axis, and shifted position (location) with respect to the original trench location shown in FIG. 6A. Depending upon the extent of etching performed in the operation of FIG. 6C, the length of the trench along the X-axis may be greater than LI of the original trench, or may be the same as LI , as depicted in FIG. 6C. Accordingly, FIG. 6C provides a specific example where a surface feature location, in this case a trench location with respect to a position along the X- axis, is shifted, while the trench is also selectively narrowed along the Y-axis.
[0043] Turning to FIG. 6D there is shown a substrate 610 having a cavity of circular shape after deposition of a layer 616. In FIG. 6E a resulting shape of the cavity 612 is shown when ions 614 are directed just toward the upper (in FIG. 6E) sidewall 615, resulting in a cavity 612 where the position of the upper sidewall region is the same as before deposition as layer 616, while other regions of cavity 612 are reduced in size, resulting in a more oval shape. As shown in FIG. 6F, further etching by ions 618 may be performed along the same direction as ions 614, where the ions 618 may be similar to or different from the ions 614. This further etching results in etching into base 604 along the same direction as in FIG. 6E, and may result in a more elongated oval shape. [0044] Turning now to FIG. 7A and FIG. 7B there is shown a further example of processing a cavity, where the trench 502 is formed as described above by depositing a layer 506. Subsequently, ions such as the ions 603, or a combination of ions 603 and ions 605, may be directed along the X-axis to etch just the right endwall, shown as endwall 508 in FIG. 7B. By proper selection of etching conditions and etching time, the resulting trench, shown as trench 502, may have the same length, shown as LI, as before deposition of layer 506, while the center of the trench 502 along the X-axis in FIG. 7B is shifted to the right with respect to trench 502 of FIG. 7A. Furthermore, in a second directional etching operation shown in FIG. 7C, ions 702 may be directed parallel to the Y- axis to the top edge 704 and bottom edge 706 of the trench 502. In some embodiments, the material of layer 506 may differ from the material of base 504 wherein etching by the ions 702 of the layer 506 is highly selective with respect to the etching of base 504. For example, ions 702 may be provided in a reactive ion etch process for etching layer 506 at a rate twice as fast as the etching of base 504, or five times as fast, 10 times as fast, or 20 times as fast. The embodiments are not limited in this context. In this manner, the layer 506 may be completely removed from the bottom edge 706 and top edge 704, while little or no material from base 504 is removed from these edges. This etching allows the original trench width Wl to be restored, corresponding to the trench width before deposition of layer 506. A net result of these processes is shown in FIG. 7C, where the trench 502 is shifted to the right from an original trench location before deposition of layer 506, as shown by the dashed curve in FIG. 7 A, while the original dimensions of the trench 502 are preserved. In various embodiments, the cavity location for any cavity shape may be shifted from a first cavity location to a second cavity location in a like manner to the operations of FIGs. 7A-7C while preserving the original cavity dimensions. [0045] FIGs. 8A-8G another example of processing a substrate according to some additional embodiments of the disclosure. In the example of FIG. 8A and FIG. 8D, a substrate 800 is provided with a pillar 802 extending above a base 804. The pillar 802 may, but need not be, a different material than the material of base 804. In FIG. 8B and FIG. 8E a layer 806 is deposited, as generally described above. In FIG. 8C ions 812 are directed toward the pillar 802 in two opposite directions, where the opposite directions lie parallel to the Y-axis as shown, resulting in removal of layer 806 from regions generally more aligned along the X-axis, as further shown in the cut sections of FIG. 8F and FIG. 8G. Accordingly, the original diameter Dl is increased to a diameter D2 along the X-axis, as shown in FIG. 8D, while the original diameter Dl may be maintained along the X-axis, as shown in FIG. 8B. This directional etching allows the originally circular shape of the pillar 802 to be transformed to an oval shape as illustrate in FIG. 8C.
[0046] In further embodiments, directional etching of ions may be performed by rotating a substrate within the X-Y plane to any desired angle. Thus, a trench feature may be oriented with its long axis at a 45-degree angle with respect to the Y-axis while a ribbon beam directed to the trench feature has its axis oriented along the Y-axis as in FIG. 9B.
[0047] In additional embodiments, an operation involving deposition of a layer on a surface feature followed by selective directional etching of the surface feature as described above, may be repeated in an iterative fashion. A given cycle may be composed of deposition of a layer followed by etching of the surface feature including the deposited layer along a given direction. This given cycle may be repeated a desired number of times to adjust the dimension of a feature selectively along a given direction, to adjust the shape, or adjust the position, for example. [0048] In additional embodiments, by scanning a substrate with respect to an ion beam such as along the X-axis as generally shown in FIG. 9B, the possibility is afforded to vary a directed etch across the substrate to achieve location-specific directional selectivity of etching, so features within a certain region, such as region 912 of the substrate may be altered to one extent while features in another region, such as region 914, are not altered or are altered to a different extent or in a different fashion. For example, an ion beam, shown as ions 110 may be present when region 912 is under extraction aperture 908, while the ion beam is extinguished when the region 914 is under extraction aperture 908.
[0049] The present embodiments provide various advantages over conventional processing to define features in a substrate. Currently, there are no known techniques able to achieve what is described in these embodiments, in particular over a full wafer in a manufacturing environment. Several problems may be solved with these embodiments including a first advantage of being able to shift a surface feature within a substrate in a desired direction and in a desired amount. The present embodiments also proved the advantage where a feature may be shifted and the original feature shape or dimensions may be preserved or changed. Another advantage of the present embodiments is the ability to generate otherwise unobtainable feature dimensions and shapes. Further advantages include the ability to provide for overlay correction, providing for overlay margin improvement, providing tip-to-tip separation reduction between adjacent features to dimensions not otherwise obtainable, contact resistance reduction in structures formed according to the present embodiments, increase in pattern density, and elimination of a cut-mask operation.
[0050] The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are in the tended to fall within the scope of the present disclosure. Furthermore, the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, while those of ordinary skill in the art will recognize the usefulness is not limited thereto and the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below are to be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims

What is claimed is;
1. A method, comprising:
providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and
directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane,
wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
2. The method of claim 1, wherein the substrate feature comprises a cavity, the cavity comprising a first dimension along the first direction and a second dimension along a second direction perpendicular to the first direction, and wherein the depositing the layer comprises performing a shrink of the cavity wherein the first dimension and second dimension are reduced.
3. The method of claim 2, wherein the ion exposure comprises etching the layer along the first direction a first amount and etching the layer along the second direction a second amount, the second amount being less than the first amount.
4. The method of claim 3, wherein the cavity comprises a circular shape before the ion exposure and comprises an elongated shape after the ion exposure.
5. The method of claim 3, wherein the layer material is removed from a bottom surface of the cavity after the etching.
6. The method of claim 3, wherein the cavity is formed within a substrate material before the ion exposure, and wherein the ion exposure comprises etching the substrate material along the first direction to form an elongated shape, wherein the elongated shape comprises a third dimension along the first direction, the third dimension being greater than the first dimension.
7. The method of claim 3, wherein the cavity comprises a trench before the depositing the layer, wherein the first dimension is greater than the second dimension, and wherein after the depositing the layer and after the ion exposure, the trench comprises a third dimension along the second direction, the third dimension being less than the first dimension, and further comprises the first dimension along the first direction.
8. The method of claim 3, wherein the cavity comprises a trench before the depositing the layer, wherein the first dimension is greater than the second dimension, and wherein after the depositing the layer and after the ion exposure, the trench comprises a third dimension along the second direction, the third dimension being less than the first dimension, and further comprises a fourth dimension along the first direction, the fourth dimension being greater than the first dimension.
9. The method of claim 3, a location of the cavity is shifted from a first location within the substrate before the depositing the layer to a second location within the substrate after the ion exposure.
10. The method of claim 1, wherein the surface feature extends above the substrate plane, wherein before the depositing the layer the surface feature comprises a first feature dimension along the first direction and a second feature dimension along a second direction perpendicular to the first direction, and wherein the depositing the layer comprises increasing the first feature dimension to a third feature dimension and increasing the second feature dimension to a fourth feature dimension, and wherein the ion exposure comprises decreasing the third feature dimension to a fifth feature dimension less than the fourth feature dimension.
11. The method of claim 1, wherein the ions are directed as a ribbon ion beam and have trajectories parallel to the first direction.
12. The method of claim 1, the depositing the layer comprising selectively depositing the layer on the substrate, wherein the layer comprises a first thickness over a first region of the substrate and comprises a second thickness different from the first thickness over a second region of the substrate, wherein after the depositing the layer, a dimension of the surface feature along the first direction is altered by a first amount in the first region and by a second amount in the second region.
13. A method of processing a substrate, comprising:
providing a cavity in the substrate, the cavity having a first dimension along a first direction within a substrate plane and a second dimension along a second direction within the substrate plane, the second direction being perpendicular to the first direction;
depositing a layer comprising a layer material within the cavity; and
directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane,
wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the first dimension is selectively altered with respect to the second dimension.
14. The method of claim 13, wherein the first dimension is reduced while the second dimension is not reduced.
15. A method of processing a substrate, comprising:
providing a cavity in the substrate, the cavity disposed at a first cavity location within the substrate;
depositing a layer comprising a layer material within the cavity; and
directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the cavity and do not impact a second portion of the cavity, and wherein the cavity is disposed at a second cavity location in the substrate after the ion exposure.
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008384B2 (en) 2015-06-25 2018-06-26 Varian Semiconductor Equipment Associates, Inc. Techniques to engineer nanoscale patterned features using ions
US9984889B2 (en) * 2016-03-08 2018-05-29 Varian Semiconductor Equipment Associates, Inc. Techniques for manipulating patterned features using ions
US9947548B2 (en) * 2016-08-09 2018-04-17 International Business Machines Corporation Self-aligned single dummy fin cut with tight pitch
US10658184B2 (en) * 2016-12-15 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern fidelity enhancement with directional patterning technology
US10504738B2 (en) * 2017-05-31 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Focus ring for plasma etcher
US10529617B2 (en) 2017-09-29 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing with flexible space formed using self-aligned spacer patterning
US10312089B1 (en) * 2017-11-29 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for controlling an end-to-end distance in semiconductor device
US10453684B1 (en) * 2018-05-09 2019-10-22 Applied Materials, Inc. Method for patterning a material layer with desired dimensions
US10629437B2 (en) * 2018-05-09 2020-04-21 Varian Semiconductor Equipment Associates, Inc. Techniques and structure for forming dynamic random-access device using angled ions
US11127593B2 (en) 2018-05-18 2021-09-21 Varian Semiconductor Equipment Associates, Inc. Techniques and apparatus for elongation patterning using angled ion beams
US11640909B2 (en) * 2018-12-14 2023-05-02 Applied Materials, Inc. Techniques and apparatus for unidirectional hole elongation using angled ion beams
US11043381B2 (en) * 2019-01-27 2021-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Directional patterning method
US10777414B1 (en) 2019-03-14 2020-09-15 Applied Materials, Inc. Methods for reducing transfer pattern defects in a semiconductor device
US11043394B1 (en) 2019-12-18 2021-06-22 Applied Materials, Inc. Techniques and apparatus for selective shaping of mask features using angled beams
JP7551542B2 (en) * 2021-03-05 2024-09-17 キオクシア株式会社 Method for manufacturing semiconductor device
US11978640B2 (en) * 2021-04-09 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor devices
CN113391304B (en) * 2021-05-11 2023-09-12 雷远信息技术有限公司 Radar positioning method, positioning radar and positioning system
US12464797B2 (en) * 2021-12-08 2025-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-filling spacer structure
US12255067B2 (en) * 2022-05-23 2025-03-18 Applied Materials, Inc. Method for depositing layers directly adjacent uncovered vias or contact holes
US12463045B2 (en) 2022-10-19 2025-11-04 Applied Materials, Inc. Selective trench modification using directional etch
US12387942B2 (en) 2022-10-19 2025-08-12 Applied Materials, Inc. Modifying patterned features using a directional etch
US20250379063A1 (en) * 2024-06-10 2025-12-11 Applied Materials, Inc. Etch back for enhanced directional deposition

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054317A (en) * 2004-08-11 2006-02-23 Nippon Telegr & Teleph Corp <Ntt> Method for manufacturing semiconductor element and semiconductor element
KR20060078440A (en) * 2004-12-31 2006-07-05 동부일렉트로닉스 주식회사 Preventing Divot Geometry during Shallow Trench Separator Process
US20070051622A1 (en) * 2005-09-02 2007-03-08 Applied Materials, Inc. Simultaneous ion milling and sputter deposition
US20080233691A1 (en) * 2007-03-23 2008-09-25 Kangguo Cheng Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers
US20130328157A1 (en) * 2012-06-06 2013-12-12 International Business Machines Corporation Spacer isolation in deep trench

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484979A (en) 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4680085A (en) 1986-04-14 1987-07-14 Ovonic Imaging Systems, Inc. Method of forming thin film semiconductor devices
US5610441A (en) * 1995-05-19 1997-03-11 International Business Machines Corporation Angle defined trench conductor for a semiconductor device
JP2757838B2 (en) 1995-10-25 1998-05-25 日本電気株式会社 Method for manufacturing semiconductor device
US6414366B1 (en) 1998-07-29 2002-07-02 Tdk Corporation Thin-film magnetic head wafer and manufacturing method of thin-film magnetic head
US6238582B1 (en) 1999-03-30 2001-05-29 Veeco Instruments, Inc. Reactive ion beam etching method and a thin film head fabricated using the method
BR0009489A (en) 1999-03-31 2002-02-19 Cray Valley Sa Heat-curable compositions comprising microparticles with improved mechanical strength
US6787052B1 (en) 2000-06-19 2004-09-07 Vladimir Vaganov Method for fabricating microstructures with deep anisotropic etching of thick silicon wafers
DE10115912A1 (en) * 2001-03-30 2002-10-17 Infineon Technologies Ag Method for producing a semiconductor arrangement and use of an ion beam system for carrying out the method
US20080002749A1 (en) 2004-09-29 2008-01-03 California Institute Of Technology Material processing method for semiconductor lasers
JP4867171B2 (en) 2005-01-21 2012-02-01 富士電機株式会社 Manufacturing method of semiconductor device
US7696102B2 (en) 2005-03-31 2010-04-13 Gang Zhang Methods for fabrication of three-dimensional structures
US7790621B2 (en) 2006-02-23 2010-09-07 Sophia Wen Ion implantation for increasing etch rate differential between adjacent materials
US7542497B2 (en) 2006-07-18 2009-06-02 Binoptics Corporation AlGaInN-based lasers with dovetailed ridge
US8652763B2 (en) 2007-07-16 2014-02-18 The Board Of Trustees Of The University Of Illinois Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same
US20090084757A1 (en) 2007-09-28 2009-04-02 Yuri Erokhin Uniformity control for ion beam assisted etching
US8222154B2 (en) * 2009-02-10 2012-07-17 International Business Machines Corporation Fin and finFET formation by angled ion implantation
US8101510B2 (en) 2009-04-03 2012-01-24 Varian Semiconductor Equipment Associates, Inc. Plasma processing apparatus
US8603591B2 (en) 2009-04-03 2013-12-10 Varian Semiconductor Ewuipment Associates, Inc. Enhanced etch and deposition profile control using plasma sheath engineering
US7767977B1 (en) 2009-04-03 2010-08-03 Varian Semiconductor Equipment Associates, Inc. Ion source
US8192641B2 (en) 2009-07-23 2012-06-05 GlobalFoundries, Inc. Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces
US8912097B2 (en) * 2009-08-20 2014-12-16 Varian Semiconductor Equipment Associates, Inc. Method and system for patterning a substrate
US8089050B2 (en) 2009-11-19 2012-01-03 Twin Creeks Technologies, Inc. Method and apparatus for modifying a ribbon-shaped ion beam
US8421139B2 (en) 2010-04-07 2013-04-16 International Business Machines Corporation Structure and method to integrate embedded DRAM with finfet
CN102915999B (en) * 2011-08-03 2016-08-03 无锡华润上华半导体有限公司 Trench polisilicon excessive erosion step-on testing figure and forming method thereof
US8288741B1 (en) 2011-08-16 2012-10-16 Varian Semiconductor Equipment Associates, Inc. Apparatus and method for three dimensional ion processing
US8339752B1 (en) 2011-09-26 2012-12-25 Hitachi Global Storage Technologies Netherlands B.V. Magnetic head with wide sensor back edge, low resistance, and high signal to-noise ratio and methods of production thereof
US9653309B2 (en) 2012-05-25 2017-05-16 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
US9118001B2 (en) * 2012-07-11 2015-08-25 Varian Semiconductor Equipment Associates, Inc. Techniques for treating sidewalls of patterned structures using angled ion treatment
CN103578921A (en) * 2012-08-10 2014-02-12 南亚科技股份有限公司 patterning process
US9190498B2 (en) 2012-09-14 2015-11-17 Varian Semiconductor Equipment Associates, Inc. Technique for forming a FinFET device using selective ion implantation
US9287178B2 (en) 2012-10-01 2016-03-15 Globalfoundries Inc. Multi-gate field effect transistor (FET) including isolated fin body
CN105008891B (en) 2013-01-11 2018-02-06 Fei公司 For changing the ion implanting of etch-rate
JP6271235B2 (en) * 2013-01-24 2018-01-31 キヤノンアネルバ株式会社 Fin FET manufacturing method and device manufacturing method
US20140357080A1 (en) 2013-06-04 2014-12-04 Tokyo Electron Limited Method for preferential shrink and bias control in contact shrink etch
KR101509529B1 (en) 2013-07-31 2015-04-07 아주대학교산학협력단 Three-dimensional copper nanostructures and fabricating method therefor
US9934981B2 (en) * 2013-09-26 2018-04-03 Varian Semiconductor Equipment Associates, Inc. Techniques for processing substrates using directional reactive ion etching
US9287123B2 (en) 2014-04-28 2016-03-15 Varian Semiconductor Equipment Associates, Inc. Techniques for forming angled structures for reduced defects in heteroepitaxy of semiconductor films
CN105097532A (en) * 2014-05-09 2015-11-25 中芯国际集成电路制造(上海)有限公司 Semiconductor structure forming method
US9336998B2 (en) * 2014-05-09 2016-05-10 Varian Semiconductor Equipment Associates, Inc. Apparatus and method for dynamic control of ion beam energy and angle
US9984889B2 (en) * 2016-03-08 2018-05-29 Varian Semiconductor Equipment Associates, Inc. Techniques for manipulating patterned features using ions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054317A (en) * 2004-08-11 2006-02-23 Nippon Telegr & Teleph Corp <Ntt> Method for manufacturing semiconductor element and semiconductor element
KR20060078440A (en) * 2004-12-31 2006-07-05 동부일렉트로닉스 주식회사 Preventing Divot Geometry during Shallow Trench Separator Process
US20070051622A1 (en) * 2005-09-02 2007-03-08 Applied Materials, Inc. Simultaneous ion milling and sputter deposition
US20080233691A1 (en) * 2007-03-23 2008-09-25 Kangguo Cheng Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers
US20130328157A1 (en) * 2012-06-06 2013-12-12 International Business Machines Corporation Spacer isolation in deep trench

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