WO2017148292A1 - 一种级联板、ssd远程共享访问的系统和方法 - Google Patents

一种级联板、ssd远程共享访问的系统和方法 Download PDF

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Publication number
WO2017148292A1
WO2017148292A1 PCT/CN2017/074148 CN2017074148W WO2017148292A1 WO 2017148292 A1 WO2017148292 A1 WO 2017148292A1 CN 2017074148 W CN2017074148 W CN 2017074148W WO 2017148292 A1 WO2017148292 A1 WO 2017148292A1
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Prior art keywords
access
ssd
processing device
rdma
access processing
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PCT/CN2017/074148
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English (en)
French (fr)
Inventor
许慧锋
郭海涛
张羽
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华为技术有限公司
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Publication of WO2017148292A1 publication Critical patent/WO2017148292A1/zh
Priority to US16/118,850 priority Critical patent/US10901638B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0637—Permissions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0605—Improving or facilitating administration, e.g. storage management by facilitating the interaction with a user or administrator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to the field of communications, and in particular, to a system and method for cascading boards and SSD remote shared access.
  • SSD Solid State Drive
  • a processor In the process of implementing remote shared access to an SSD, access by the remote device to the SSD is processed by a processor (CPU). That is, the processor receives an SSD access command from a remote Direct Internal Memory Access (RDMA) network and forwards the command to the corresponding SSD.
  • RDMA Remote Direct Internal Memory Access
  • this type of access introduces software processing time, resulting in increased access latency.
  • Embodiments of the present invention provide a system and method for remote sharing access of a cascading board and an SSD to reduce the delay of remote shared access to the SSD.
  • a cascading board is provided, the cascading board is connected to the RDMA network at one end, and the SSD is connected to the other end.
  • the cascading board includes an access processing device and a CPU coupled to the access processing device, where:
  • the CPU is configured to complete initialization of the access processing device and the SSD;
  • the access processing device is configured to implement RDMA access to the SSD when receiving an access command from an RDMA network.
  • the access processing device is a device for processing remote shared access, and the CPU no longer processes remote shared access, but is used for initializing the access processing device and the SSD.
  • the software processing time introduced by the CPU to implement remote shared access to the SSD can be avoided, thereby reducing the delay of the remote shared access to the SSD, and realizing the shared access to the SSD remotely without increasing the access time.
  • the access processing apparatus includes: an RDMA interface and a memory, where:
  • the RDMA interface is used to connect to an RDMA network
  • the memory is used to save an access queue.
  • the RDMA of the SSD is completed by the access processing device, and the access processing device may set a memory to save the access queue.
  • An RDMA interface is provided in the access processing device to facilitate connection with the RDMA network.
  • the cascading board further includes a PCIe (Peripheral Component Interface Express) switch chip, the PCIe switch chip and the CPU and the The access processing device is connected and connected to the SSD.
  • PCIe Peripheral Component Interface Express
  • the CPU when there is no PCIe switch chip, the CPU is directly connected to the SSD. With this connection mode, the number of SSDs connected to the CPU is limited, and not many. Thus, when there are many SSDs, the way that the CPU directly SSDs cannot meet the demand.
  • the cascading board can connect more SSDs through the PCIe switch chip 103 on the one hand, and can better function as a connection access processing device 102 and the CPU 101 on the other hand.
  • the processing device 102 and the CPU 101 act as adapters and enable efficient forwarding of data.
  • the access processing device includes: a PCIe interface, an RDMA interface, and a memory;
  • the PCIe interface is configured to connect to the PCIe switch chip
  • the RDMA interface is used to connect to an RDMA network
  • the memory is used to save an access queue.
  • the access processing device may be provided with a PCIe interface for connection with the PCIe switch chip.
  • the access processing device is a Field Programmable Gate Array (FPGA) or an application specific integrated circuit (Application Specific Integrated) Circuit, ASIC).
  • FPGAs and ASICs are particularly well suited as access processing devices due to their faster processing speeds.
  • the CPU, the access processing device, and the PCIe switch chip are integrated.
  • the CPU, the access processing device, and the PCIe interaction chip may be integrated together, for example, integrated on one chip. In this way, the space of the cascading board can be saved.
  • a system for SSD remote shared access comprising at least one SSD, at least one controller, and any of the cascading boards of the above first aspect; wherein:
  • the controller is coupled to the cascading board via an RDMA network and transmits an access command to the access processing device over the RDMA network.
  • the controller can store a controller.
  • the SSD remote shared access system completes the initialization of the access processing device and the SSD by the CPU, and the RDMA of the SSD is completed by the access processing device, thereby dividing the initialization process and the access process into two Independent processes, by introducing access processing devices (such as FPGA or ASIC) hardware to complete RDMA access to the SSD, can avoid software processing time introduced by the CPU to achieve RDMA access to the SSD, and thus can reduce the SSD
  • access processing devices such as FPGA or ASIC
  • the system further includes an RDMA switch, and the RDMA switch is configured to connect the controller and the cascading board.
  • the SSD shared access system provided by the embodiment of the present invention may further include multiple RDMA switches, and the connection of the plurality of cascading boards is implemented by the RDMA switch.
  • the number of cascading boards is small, it is also possible to connect using only one RDMA switch.
  • a method for remote shared access of an SSD comprising:
  • the CPU initializes the access processing device and the SSD;
  • the access processing device implements RDMA access to the SSD upon receiving an access command from the RDMA network.
  • the initialization of the access processing device and the SSD is completed by the CPU, and the RDMA of the SSD is completed by the access processing device, thereby being able to divide the initialization process and the access process into two independent functions.
  • the process of RDMA access to the SSD is implemented by introducing hardware such as an access processing device (such as an FPGA or an ASIC), which can avoid software processing time introduced by the CPU to implement RDMA access to the SSD, thereby reducing the remoteness of the SSD.
  • the delay of shared access enables remote access to the SSD without increasing access time.
  • the initializing, by the CPU, the access processing device includes:
  • the CPU allocates a storage space for storing the access queue on the access processing device according to configuration information of the access queue, and initializes the access queue;
  • the CPU designates an interrupt receiving end as the access processing device.
  • the initialization of the access processing device is completed by the CPU.
  • the interrupt receiving end is designated as the access processing device, so that the subsequent SSD will go to the remote shared access command after executing the remote shared access command.
  • Access to the processing device instead of the CPU feedback interrupt.
  • the access processing device can know that the SSD has executed the command according to the terminal fed back by the SSD.
  • implementing RDMA access to the SSD includes:
  • the access processing device When the access processing device receives the access command, the access processing device prompts the SSD corresponding to the access command to perform an access job;
  • the access processing device returns data or status information through the RDMA network upon receiving an interrupt from the SSD.
  • the subsequent access processing device can process according to the new workflow when receiving the access command to the SSD.
  • the access processing device is an FPGA or an ASIC.
  • FPGAs and ASICs are particularly well suited as access processing devices due to their faster processing speeds.
  • a PCIe interaction chip exists between the CPU and the access processing device, and interaction between the CPU and the access processing device may be transmitted through a PCIe interaction chip.
  • the CPU, the access processing device, and the PCIe interaction chip may be integrated together, for example, integrated on one chip. In this way, the space of the cascading board can be saved.
  • the system and method for cascading board and SSD remote shared access in the embodiment of the present invention complete initialization of the access processing device and the SSD by the CPU, and the RDMA of the SSD is completed by the access processing device, thereby enabling the initialization process
  • the access process is divided into two independent processes, the RDMA access to the SSD is completed by introducing hardware such as an access processing device (such as an FPGA or an ASIC), and the software processing time introduced by the CPU to implement RDMA access to the SSD can be avoided.
  • the delay of the remote shared access to the SSD can be reduced, and the remote shared access to the SSD can be realized without increasing the access time.
  • FIG. 1 is a basic frame diagram of a system for implementing remote shared access to an SSD according to an embodiment of the present invention
  • FIG. 2 is a basic framework diagram of another system for implementing remote shared access to an SSD according to an embodiment of the present invention
  • FIG. 3 is an internal structural diagram of an access processing apparatus according to an embodiment of the present invention.
  • FIG. 4 is a basic framework diagram of another system for implementing remote shared access to an SSD according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for accessing a hard disk according to an embodiment of the present invention.
  • FIG. 1 is a basic framework diagram of a system for implementing remote shared access to an SSD according to an embodiment of the present invention.
  • the system for remotely sharing access to an SSD may include a cascading board 10, a hard disk 104 connected to the cascading board, and a controller 106 connected to the cascading board through the network 110.
  • the controller 106 can be a separately set device or a controller in a network device connected on the network.
  • the controller 106 is configured to receive an RDMA access request and control operation of the cascading board 10; the RDMA access request may be from any network device on the network.
  • the hard disk 104 connected to the cascading board may be a solid state hard disk such as a PCIe (Peripheral Component Interface Express) SSD, and the PCIe SSD may be an NVMe SSD and a non-NVMe SSD, where NVMe (NVM express, NVM high speed) An SSD access protocol defined by Intel Corporation.
  • PCIe SSD Peripheral Component Interface Express
  • NVMe NVM express, NVM high speed
  • Network 110 can be an RDMA network.
  • the storage controller 106 can be in the same local area network as the cascading board 10. Of course, the storage controller 106 can also be in a different local area network from the cascading board 10.
  • the cascading board 10 can include an access processing device 102 and a processor (CPU) 101 coupled to the access processing device 102.
  • the access processing device 102 in the cascading board can be connected to the network 110, and the processor 101 can be connected to the hard disk 104.
  • the access processing device 102 can be an FPGA or an ASIC or the like. among them:
  • the CPU 101 is configured to complete initialization of the access processing device and the SSD at power-on.
  • the access processing device 102 is configured to implement RDMA access to the SSD 104 when an access command from the RDMA network 110 is received.
  • the access command may be sent by the storage controller 106 to the access processing device 102 via the network 110.
  • the initialization of the access processing device and the SSD is completed by the CPU, and the RDMA of the SSD is completed by the access processing device, thereby being able to divide the initialization process and the access process into two independent
  • the process by introducing an access processing device (such as FPGA or ASIC) hardware to complete RDMA access to the SSD, can avoid the software processing time introduced by the CPU to achieve RDMA access to the SSD, thereby reducing the remote sharing of the SSD
  • the delay of access does not increase access time while sharing access to the SSD remotely.
  • FIG. 2 is a basic framework diagram of another system for implementing remote shared access to an SSD according to an embodiment of the present invention.
  • the access processing device 102 in the system shown in FIG. 2 is an FPGA or an ASIC
  • the hard disk 104 is an NVMe SSD
  • the network 110 is an RDMA network as an example.
  • a PCIe switch chip 103 is introduced in the cascading board 10 in the system shown in Fig. 2. That is, the cascading board 10 may include a PCIe switch chip 103 in addition to the CPU 101 and the FPGA or the ASIC 102.
  • the PCIe switch chip 103 is connected to the CPU 101 and the access processing device 102, respectively, and is connected to the SSD 104.
  • An RDMA network connection device 105 may also be included in the system shown in FIG. 2, the RDMA network connection device being located in the RDMA network 110 acting as an interface to the RDMA network to connect the memory controller 106 and the FPGA or ASIC 102.
  • the RDMA network connection device 105 may be an FPGA or an ASIC, or may be a common network chip supporting an RDMA network.
  • the NVMe SSD 104 is a standard PCIe interface SSD.
  • the NVMe SSD 104 and the FPGA/ASIC 102 are connected to the processor 101 through the PCIe switch chip 103.
  • the processor 101 serves as a host for the NVMe SSD 104 and the FPGA/ASIC 102 to complete initial configuration and management of the NVMe SSD 104 and the FPGA/ASIC 102, but processes The device 101 does not participate in a specific hard disk access service.
  • the PCIe switch chip 103 is introduced into the cascode board 10, so that on the one hand, the cascading board can be connected to more SSDs through the PCIe switch chip 103 (since the CPU connected SSD in the manner shown in FIG. 1)
  • the number is often limited, and on the other hand, it can function better to connect the access processing device 102 and the CPU 101, act as an adapter between the access processing device 102 and the CPU 101, and achieve efficient forwarding of data.
  • the FPGA/ASIC 102 may be a customized network chip, and the characteristic is that the network chip integrates a certain storage space (for example, a random access memory (RAM)) and allows creation and Manage NVMe access queues.
  • a certain storage space for example, a random access memory (RAM)
  • FIG. 3 is a diagram showing the internal structure of an access processing apparatus according to an embodiment of the present invention.
  • the access processing device shown in FIG. 3 is an FPGA or an ASIC.
  • the FPGA or ASIC 102 can include a PCIe interface 102-1, an RDMA interface 102-2 port, and a memory 102-3. among them:
  • the PCIe interface 102-1 is used to connect to the PCIe switch chip 103;
  • the RDMA interface 102-2 is configured to connect to an external network 110, such as an RDMA network;
  • the memory 102-3 is used to save an access queue.
  • the memory 102-3 may be a random access memory (RAM), which allows the CPU 101 to create an NVMe access queue in the storage space, and at the storage controller 106 to the completion queue (CQ)/submission queue. After the operation (SQ) is performed, the doorbell of the corresponding NVMe SSD is triggered.
  • RAM random access memory
  • the access processing device 102 may include only the RDMA interface 102-2 and the memory 102-3, and does not include the PCIe interface 102- 1.
  • the system for remotely sharing access to the SSD provided in this embodiment can be applied to the case where the cascading board is connected to multiple SSDs, which can reduce the delay of remote shared access to the SSD, so that the storage controller can achieve high efficiency for multiple SSDs. access.
  • FIG. 4 is a basic framework diagram of another system for implementing remote shared access to an SSD according to an embodiment of the present invention.
  • the system for remote shared access to the SSD in this embodiment includes a plurality of storage controllers 106 connected to one or more NVMe SSD disk frames 100 through a plurality of, for example, two RDMA switches 107.
  • the sash frame 100 is a dual control disk frame and includes two disk frame management units 10, and the disk frame management unit 10 can be a cascading board.
  • Each of the disk management units 10 includes a management processor (CPU) 101, a PCIe switch chip 103, and an FPGA/ASIC 102, and the two disk management units 109 are connected to a number of dual port standard NVMe SSDs 104.
  • the system shown in Figure 4 is only an example.
  • the number of memory controllers, the number of switches, the number of disk management units 10, and the number of NVMe SSDs 104 shown in FIG. 4 are all non-limiting, and various devices may employ any other number within the scope of the present invention.
  • the invention is implemented.
  • the disk frame 100 may also be a single control device, that is, only one disk frame management unit (ie, a cascading board) 10; for example, the NVMe SSD may be a single port standard NVMe SSD.
  • the initialization of the access processing device and the SSD may be completed by the CPU, and when the access processing device receives the access command from the RDMA network, Realizing RDMA access to the SSD, as such, enables remote direct access to the NVMe SSD with minimal latency.
  • the embodiment of the invention further provides a method for hard disk access.
  • the method for accessing the hard disk provided by the embodiment of the present invention is described below with reference to FIG. Referring to FIG. 5, a method for accessing a hard disk according to an embodiment of the present invention may include:
  • the CPU initializes the access processing device and the SSD;
  • the access processing device implements an RDMA access to the SSD when receiving an access command from the RDMA network. ask.
  • the access processing device may be an FPGA or an ASIC.
  • the initializing, by the CPU, the access processing device in step 51 may include:
  • the CPU allocates a storage space for storing the access queue on the access processing device according to configuration information of the access queue, and initializes the access queue;
  • the CPU designates an interrupt receiving end as the access processing device.
  • implementing RDMA access to the SSD may include:
  • the access processing device When the access processing device receives the access command, the access processing device prompts the SSD corresponding to the access command to perform an access job;
  • the access processing device returns data or status information through the RDMA network upon receiving an interrupt from the SSD.
  • the initialization of the access processing device and the SSD is completed by the CPU, and the RDMA of the SSD is completed by the access processing device, thereby being able to divide the initialization process and the access process into two independent functions.
  • the process of RDMA access to the SSD is implemented by introducing hardware such as an access processing device (such as an FPGA or an ASIC), which can avoid software processing time introduced by the CPU to implement RDMA access to the SSD, thereby reducing the remoteness of the SSD.
  • the delay of shared access enables remote access to the SSD without increasing access time.
  • the process of initialization by the CPU 101 can be as follows:
  • the CPU 101 performs PCIe peripheral initialization, for example, completes initialization of some related registers
  • the CPU 101 initializes the access processing device 102 and establishes communication between the access processing device 102 and the memory controller 106;
  • the CPU 101 performs device initialization of the SSD 104;
  • the CPU 101 acquires the queue configuration information locally or obtains the queue configuration information from the storage controller 106 according to a pre-defined policy, allocates a storage space (for example, RAM) on the access processing device 102, and initializes the NVMe access queue, and according to the NVMe protocol requirements.
  • the doorbell address and the interrupt number corresponding to each access queue are obtained, and the doorbell address and the interrupt number corresponding to each access queue are written into the access processing device 102 and the corresponding address space on the SSD 104 according to the rules of the NVMe.
  • the CPU 101 configures the PCIe switch chip 103, and designates the interrupt receiving end as the access processing device 102;
  • the CPU 101 sends a head pointer and a tail pointer of the access queue to the memory controller 106.
  • the head pointer and the tail pointer of the access queue can be obtained. Further, the head pointer and the tail pointer of the access queue may be transmitted to the memory controller 106 in 7).
  • the foregoing initialization process is described by taking the cascading board 10 including a PCIe switch chip as an example.
  • the initialization process is similar to the above, and only the initialization content related to the PCIe switch chip 103 is removed, and details are not described herein.
  • the disk block 108 can send the initialized NVMe queue and its head and tail pointers to all connected storage controllers 106 through the network. Some or all of the resources in the disk frame 108 can be obtained through negotiation between the plurality of storage controllers 106 to avoid the number of access conflicts. According to the risk of consistency.
  • the cascading board 10 in the subsequent disk frame 108 will hand over the hard disk access request to the access processing when receiving the hard disk access request from the network 110 (for example, the RDMA network).
  • the device 102 processes the RDMA access to the SSD 104 by the access processing device 102.
  • the storage controller 106 selects the required access queue and finds the head address and the tail address of the access queue;
  • the storage controller 106 writes a read/write command to the SQ queue on the memory 102-3 in the access processing device 102;
  • the access processing device 102 knocks the hard disk doorbell according to the correspondence between the access queue and the doorbell number;
  • the hard disk (eg, PCIe SSD) 104 acquires and executes a command in an SQ queue stored on the memory 102-3;
  • the hard disk 104 After executing the command, the hard disk 104 writes the executed result into the CQ queue and initiates an interrupt to the access control device 102;
  • the access control device 102 After receiving the interrupt, the access control device 102 returns data or status information to the storage controller 106;
  • the storage controller 106 After receiving the data or status information, the storage controller 106 maintains a tail pointer of the access queue and updates a head pointer of the access queue;
  • the SSD remote shared access method, the cascading board and the SSD remote shared access system provided by the embodiments of the present invention can directly access the NVMe SSD 104 by the access processing device 102 (for example, FPGA/ASIC), and the standard is
  • the NVMe SSD 104 of the PCIe interface is shared by the RDMA network to the plurality of storage controllers 106 to achieve remote shared access to the NVMe SSD 104 without increasing the read and write access time.
  • the apparatus for remotely sharing access (for example, the cascading board 10) provided by the foregoing embodiment is the same concept as the method for remotely sharing access by the SSD. Therefore, corresponding parts between them can be referred to each other for repetition. The content of this, will not repeat them here.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种级联板、SSD远程共享访问的系统和方法，属于通信领域。所述级联板（10）一端连接RDMA网络（110），另一端连接SSD，所述级联板（10）包括访问处理装置（102）和与所述访问处理装置（102）耦接的处理器（101），其中：所述处理器（101），用于完成对所述访问处理装置（102）和所述SSD的初始化；所述访问处理装置（102），用于在接收到来自RDMA网络（110）的访问命令时，实现对所述SSD的RDMA访问。用于对SSD进行远程共享访问。

Description

一种级联板、SSD远程共享访问的系统和方法 技术领域
本发明涉及通信领域，特别涉及一种级联板、SSD远程共享访问的系统和方法。
背景技术
固态硬盘(Solid State Drive，SSD)是用固态电子存储芯片阵列而制成的硬盘。SSD因具有读写速度快、功耗低、轻便等优点，现在已受到越来越多人的欢迎。
当前，随着SSD容量和性能的不断提升，人们越来越关注把单个或一组SSD共享给通过网络相连的其他各种不同设备使用，以充分利用SSD所具有的多种特性。
相关技术在实现对SSD的远端共享访问的过程中，远端设备对SSD的访问会经过处理器(CPU)来处理。即处理器接收来自远程直接内层访问(Remote Direct Memory Access，RDMA)网络的SSD访问命令，并将该命令转发给对应的SSD。但是，这种访问方式会引入软件处理的时间，导致访问时延增加。
发明内容
本发明实施例提供一种级联板、SSD远程共享访问的系统和方法，以减小对SSD的远程共享访问的时延。
第一方面，提供一种级联板，所述级联板一端连接RDMA网络，另一端连接SSD，所述级联板包括访问处理装置和与所述访问处理装置耦接的CPU，其中：
所述CPU，用于完成对所述访问处理装置和所述SSD的初始化；
所述访问处理装置，用于在接收到来自RDMA网络的访问命令时，实现对所述SSD的RDMA访问。
其中，所述访问处理装置为用于处理远程共享访问的装置，而所述CPU不再处理远程共享访问，只是用于对所述访问处理装置和所述SSD的初始化。如此，可以避免因CPU实现对SSD的远程共享访问而引入的软件处理时间，因而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
结合第一方面，在第一种可能的实现方式中，所述访问处理装置包括：RDMA接口以及存储器，其中：
所述RDMA接口用于连接到RDMA网络；
所述存储器用于保存访问队列。
本发明实施例中，由访问处理装置完成对SSD的RDMA，所述访问处理装置中可设置存储器，以保存访问队列。访问处理装置中相应设有RDMA接口以便于与RDMA网络相连。
结合第一方面，在第二种可能的实现方式中，所述级联板还包括PCIe(Peripheral Component Interface Express，周边组件接口高速)交换芯片，所述PCIe交换芯片分别与所述CPU和所述访问处理装置相连，并连接所述SSD。
在本发明实施例中，在不存在PCIe交换芯片时，CPU会与SSD直接连接，采用这种连接方式，CPU所连接的SSD的数目是受限的，不会很多。这样，在存在众多SSD时，CPU直接SSD的方式则无法满足需求。本发明实施例通过引入PCIe交换芯片，一方面可以使级联板通过PCIe交换芯片103连接更多地SSD，另一方面可以更好地起到连接访问处理装置102和CPU 101的作用，在访问处理装置102和CPU 101之间充当转接器，并实现数据的高效转发传输。
结合第一方面的第二种实现方式，在第三种可能的实现方式中，所述访问处理装置包括：PCIe接口、RDMA接口以及存储器；
所述PCIe接口用于连接到所述PCIe交换芯片；
所述RDMA接口用于连接到RDMA网络；
所述存储器用于保存访问队列。
在级联板中存在PCIe交换芯片的情况下，适应性地，访问处理装置中除了可设置RDMA接口和存储器外，还可设有PCIe接口，以与PCIe交换芯片连接。
结合第一方面的上面任一种实现方式，在第四种可能的实现方式中，所述访问处理装置为现场可编程门阵列(Field Programmable Gate Array,FPGA)或特定用途集成电路(Application Specific Integrated Circuit,ASIC)。FPGA和ASIC因其较快的处理速度，特别适合于作为访问处理装置。
结合第一方面的第四种实现方式，在第五种可能的实现方式中，所述CPU、所述访问处理装置和所述PCIe交换芯片集成在一起。在本发明实施例中，CPU、访问处理装置和PCIe交互芯片可集成在一起，例如集成在一个芯片上。如此，可以节省级联板的空间。
第二方面，提供一种SSD远程共享访问的系统，所述系统包括至少一个SSD、至少一个控制器以及上面第一方面所述的任一种级联板；其中：
所述控制器通过RDMA网络与所述级联板相连，并通过所述RDMA网络向所述访问处理装置发送访问命令。
所述控制器可以存储控制器。
本发明实施例提供的SSD远程共享访问的系统，由CPU来完成对访问处理装置和SSD的初始化，并由访问处理装置来完成对SSD的RDMA，由此能够将初始化过程和访问过程分成两个相互独立的过程，通过引入访问处理装置(例如FPGA或ASIC)这一硬件来完成对SSD的RDMA访问，可以避免因CPU实现对SSD的RDMA访问而引入的软件处理时间，进而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
结合第二方面，在一种可能的实现方式中，所述系统还包括RDMA交换机，所述RDMA交换机用于连接所述控制器和所述级联板。
在级联板的数目较多时，本发明实施例提供的SSD共享访问的系统中还可包括多个RDMA交换机，通过所述RDMA交换机来实现对多个级联板的连接。当然，在本发明的范围内，在级联板数目较少时，也可以只用一个RDMA交换机来连接。
第三方面，提供一种SSD远程共享访问的方法，所述方法包括：
CPU对访问处理装置和SSD进行初始化；
访问处理装置在接收到来自RDMA网络的访问命令时，实现对所述SSD的RDMA访问。
本发明实施例中的硬盘访问的方法，由CPU来完成对访问处理装置和SSD的初始化，并由访问处理装置来完成对SSD的RDMA，由此能够将初始化过程和访问过程分成两个相互独立的过程，通过引入访问处理装置(例如FPGA或ASIC)这一硬件来完成对SSD的RDMA访问，可以避免因CPU实现对SSD的RDMA访问而引入的软件处理时间，进而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
结合第三方面，在第一种可能的实现方式中，所述CPU对访问处理装置进行初始化包括：
所述CPU根据访问队列的配置信息，在所述访问处理装置上分配用于存储所述访问队列的存储空间，并初始化所述访问队列；
所述CPU将中断接收端指定为所述访问处理装置。
在本发明实施例中，由CPU来完成对访问处理装置的初始化，在初始化过程中，会将中断接收端指定为访问处理装置，这样一来，后续SSD在执行完远程共享访问命令后会向访问处理装置而非CPU反馈中断。访问处理装置根据SSD反馈的终端即可获知SSD已执行完命令。
结合第三方面或第三方面的第一种实现方式，在第二种可能的实现方式中，所述访问处理装置在接收到访问命令时，实现对所述SSD的RDMA访问包括：
所述访问处理装置在接收到访问命令时，提示所述访问命令对应的SSD进行访问作业；
所述访问处理装置在接收到来自所述SSD的中断后，通过RDMA网络返回数据或状态信息。
在CPU完成对访问处理装置的初始化之后，后续访问处理装置在接收到对SSD的访问命令时，即可按照新的作业流程来处理。
结合第三方面的任一种实现方式，在第三种可能的实现方式中，所述访问处理装置为FPGA或ASIC。FPGA和ASIC因其较快的处理速度，特别适合于作为访问处理装置。
可选地，所述CPU和所述访问处理装置之间存在PCIe交互芯片，所述CPU和所述访问处理装置之间的交互可通过PCIe交互芯片来传递。
在本发明实施例中，CPU、访问处理装置和PCIe交互芯片可集成在一起，例如集成在一个芯片上。如此，可以节省级联板的空间。
本发明实施例中的级联板、SSD远程共享访问的系统和方法，由CPU来完成对访问处理装置和SSD的初始化，并由访问处理装置来完成对SSD的RDMA，由此能够将初始化过程和访问过程分成两个相互独立的过程，通过引入访问处理装置(例如FPGA或ASIC)这一硬件来完成对SSD的RDMA访问，可以避免因CPU实现对SSD的RDMA访问而引入的软件处理时间，进而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种实现对SSD远程共享访问的系统的基本框架图；
图2是本发明实施例提供的另一种实现对SSD远程共享访问的系统的基本框架图；
图3是本发明实施例提供的访问处理装置的内部结构图；
图4是本发明实施例提供的另一种实现对SSD远程共享访问的系统的基本框架图；
图5是本发明实施例提供的硬盘访问的方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图1是本发明实施例提供的一种实现对SSD远程共享访问的系统的基本框架图。
参照图1，本发明实施例提供的对SSD远程共享访问的系统可包括级联板10、与级联板相连的硬盘104、以及通过网络110与级联板相连的控制器106。其中，控制器106可以为一个单独设立的装置，也可以为在网络上连接的网络设备中的控制器。所述控制器106用于接收RDMA访问请求，并控制级联板10的操作；所述RDMA访问请求可以来自于网络上的任一网络设备。与级联板相连的硬盘104可以为诸如PCIe(Peripheral Component Interface Express，周边组件接口高速)SSD的固态硬盘，所述PCIe SSD可以为NVMe SSD和非NVMe SSD，其中NVMe(NVM express，NVM高速)为因特尔(Intel)公司定义的一种SSD访问协议。当所述PCIe SSD为非NVMe的SSD时，所述非NVMe SSD的访问协议是开放的。网络110可以为RDMA网络。在本发明实施例中，存储控制器106可以与级联板10处于同一局域网内，当然存储控制器106也可以和级联板10处于不同的局域网内。
所述级联板10可包括访问处理装置102和与所述访问处理装置102耦接的处理器(CPU)101。所述级联板中的访问处理装置102可连接网络110，所述处理器101可连接硬盘104。所述访问处理装置102可以为FPGA或ASIC等。其中：
所述CPU 101，用于在上电时完成对所述访问处理装置和所述SSD的初始化。
所述访问处理装置102，用于存在接收到来自RDMA网络110的访问命令时，实现对所述SSD104的RDMA访问。
其中，可由所述存储控制器106通过所述网络110向所述访问处理装置102发送访问命令。
本发明实施例中的级联板，由CPU来完成对访问处理装置和SSD的初始化，并由访问处理装置来完成对SSD的RDMA，由此能够将初始化过程和访问过程分成两个相互独立的过程，通过引入访问处理装置(例如FPGA或ASIC)这一硬件来完成对SSD的RDMA访问，可以避免因CPU实现对SSD的RDMA访问而引入的软件处理时间，进而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
图2是本发明实施例提供的另一种实现对SSD远程共享访问的系统的基本框架图。在下文描述中，以图2所示系统中的访问处理装置102为FPGA或ASIC，硬盘104为NVMe SSD，网络110为RDMA网络为例进行说明。
在图1所示实施例的基础上，图2所示系统中的级联板10中引入了PCIe交换芯片103。即，所述级联板10除了包括CPU 101和FPGA或ASIC 102外，还可包括PCIe交换芯片103。所述PCIe交换芯片103分别与所述CPU 101和所述访问处理装置102相连，并连接所述SSD 104。
在图2所示系统中还可包括RDMA网络连接装置105，所述RDMA网络连接装置位于RDMA网络110中，充当RDMA网络的接口，以连接所述存储控制器106和所述FPGA或ASIC 102。
在本发明实施例中，所述RDMA网络连接装置105可以为FPGA或ASIC，也可以为普通的支持RDMA网络的网络芯片。
NVMe SSD 104为标准的PCIe接口的SSD。NVMe SSD 104和FPGA/ASIC 102通过PCIe交换芯片103连接到处理器101，处理器101作为NVMe SSD104和FPGA/ASIC102的主机(host)，完成NVMe SSD104和FPGA/ASIC102的初始化配置和管理，但处理器101不参与具体的硬盘访问业务。
在本实施例中，在级联板10中引入PCIe交换芯片103，这样一来，一方面可以使级联板通过PCIe交换芯片103连接更多地SSD(因为图1所示方式CPU连接的SSD数目往往受限)，另一方面可以更好地起到连接访问处理装置102和CPU 101的作用，在访问处理装置102和CPU 101之间充当转接器，并实现数据的高效转发传输。
在本发明实施例中，FPGA/ASIC 102可以是定制的网络芯片，其特性在于该网络芯片内部集成了一定的存储空间(例如，随机存取存储器(Random Access Memory,RAM))并允许创建和管理NVMe访问队列。
图3是本发明实施例提供的访问处理装置的内部结构图。参见图3，图3所示访问处理装置为FPGA或ASIC。FPGA或ASIC 102可包括：PCIe接口102-1、RDMA接102-2口以及存储器102-3。其中：
所述PCIe接口102-1用于连接到所述PCIe交换芯片103；
所述RDMA接口102-2用于连接到外接网络110，例如RDMA网络；
所述存储器102-3用于保存访问队列。
其中，存储器102-3可以是随机存取存储器(Random Access Memory,RAM)，允许CPU 101在此存储空间创建NVMe访问队列，同时在存储控制器106对完成队列(completion queue，CQ)/提交队列(submission queue，SQ)进行操作后，触发对应的NVMe SSD的门铃控制器(doorbell)。
在此需要说明的是，在图1所示情形下，即不存在PCIe交换芯片103时，访问处理装置102可只包括：RDMA接口102-2和存储器102-3，而不包括PCIe接口102-1。
本实施例提供的对SSD远程共享访问的系统能够适用于级联板连接多个SSD的情形，能够减小对SSD的远程共享访问的时延，使得存储控制器可以实现对多个SSD的高效访问。
图4是本发明实施例提供的另一种实现对SSD远程共享访问的系统的基本框架图。
参见图4，本实施例中的对SSD远程共享访问的系统中包含多个存储控制器106，它们通过多个例如两个RDMA交换机107连接到一台或多台NVMe SSD盘框100上，所示盘框100为一个双控盘框，包含两个盘框管理单元10，所述盘框管理单元10可以为级联板。每个盘框管理单元10包含管理处理器(CPU)101、PCIe交换芯片103以及FPGA/ASIC 102，两个盘框管理单元109连接到一定数量的双端口标准NVMe SSD 104上。
需要指出的是，图4所示的系统仅为示例。图4中所示的存储控制器的数目、交换机的数目、盘框管理单元10的数目、NVMe SSD 104的数目都是非限制性的，在本发明的范围内，各个装置可以采用任何其他数目来实施本发明。例如，在本发明实施例中，盘框100也可以是单控设备，即只包含一个盘框管理单元(即级联板)10；又例如，NVMe SSD可以是单端口标准NVMe SSD。
在上面各个对SSD远程共享访问的系统的实施例中，均可以由CPU来完成对所述访问处理装置和所述SSD的初始化，而由访问处理装置在接收到来自RDMA网络的访问命令时，实现对所述SSD的RDMA访问，如此，能够以极少的时延实现对NVMe SSD的远程直接访问。
本发明实施例还提供一种硬盘访问的方法。下面结合图5对本发明实施例提供的硬盘访问的方法进行阐述。参照图5，本发明实施例提供的硬盘访问的方法可包括：
51、CPU对访问处理装置和SSD进行初始化；
52、访问处理装置在接收到来自RDMA网络的访问命令时，实现对所述SSD的RDMA访 问。
其中，所述访问处理装置可以为FPGA或ASIC。
可选地，在一个实施例中，步骤51中所述CPU对访问处理装置进行初始化可包括：
所述CPU根据访问队列的配置信息，在所述访问处理装置上分配用于存储所述访问队列的存储空间，并初始化所述访问队列；
所述CPU将中断接收端指定为所述访问处理装置。
可选地，在另一个实施例中，步骤52中所述访问处理装置在接收到访问命令时，实现对所述SSD的RDMA访问可包括：
所述访问处理装置在接收到访问命令时，提示所述访问命令对应的SSD进行访问作业；
所述访问处理装置在接收到来自所述SSD的中断后，通过RDMA网络返回数据或状态信息。
本发明实施例中的硬盘访问的方法，由CPU来完成对访问处理装置和SSD的初始化，并由访问处理装置来完成对SSD的RDMA，由此能够将初始化过程和访问过程分成两个相互独立的过程，通过引入访问处理装置(例如FPGA或ASIC)这一硬件来完成对SSD的RDMA访问，可以避免因CPU实现对SSD的RDMA访问而引入的软件处理时间，进而能够减小对SSD的远程共享访问的时延，实现对SSD远端共享访问的同时不增加访问时间。
为了便于进一步理解本发明的具体实现过程。下面对初始化和访问过程进行进一步阐释。
具体地，在级联板10上电后，由CPU 101进行初始化的过程可以如下：
1)级联板10上电启动；
2)CPU 101进行PCIe外设初始化，例如完成对一些相关寄存器的初始化；
3)CPU 101初始化访问处理装置102，并建立访问处理装置102与存储控制器106的通信；
4)CPU 101执行对SSD 104的设备初始化；
5)CPU 101根据预先制定的策略从本地获取队列配置信息或从存储控制器106获得队列配置信息，在访问处理装置102上分配存储空间(例如RAM)并初始化NVMe访问队列，并根据NVMe协议要求获取各个访问队列对应的门铃地址和中断号，并将各个访问队列对应的门铃地址和中断号，按照NVMe的规则写入访问处理装置102以及SSD 104上对应的地址空间。
6)CPU 101配置PCIe交换芯片103，将中断接收端指定为访问处理装置102；
7)所述CPU 101向存储控制器106发送访问队列的头指针和尾指针。
其中，所示CPU 101在5)中初始化NVMe访问队列时，可获得访问队列的头指针和尾指针。进而，在7)中可向存储控制器106发送所述访问队列的头指针和尾指针。
需要说明的是，以上初始化过程是以级联板10包括PCIe交换芯片为例来进行说明的。当级联板10不包括PCIe交换芯片时的初始化过程与上面类似，只需移除与PCIe交换芯片103有关的初始化内容即可，在此不再赘述。
以图4所示系统为例，按照上面所述初始化的流程进行初始化以后，盘框108可通过网络将已经初始化完成的NVMe队列及其头尾指针发给所连接的所有存储控制器106。多个存储控制器106之间可通过协商获得盘框108中部分或全部的资源，避免访问冲突导致数 据一致性的风险。
这样，在CPU 101经过上述过程完成对初始化之后，后续盘框108中的级联板10在接收到来自网络110(例如RDMA网络)的硬盘访问请求时，会将该硬盘访问请求交由访问处理装置102来处理，由访问处理装置102来实现对所述SSD 104的RDMA访问。
下面以典型的读写访问流程为例来进行说明。对SSD进行远程读写访问操作的流程可如下：
存储控制器106选择所需的访问队列，找到访问队列的头地址和尾地址；
存储控制器106向访问处理装置102中存储器102-3上的SQ队列中写入读写命令；
访问处理装置102根据访问队列与门铃号的对应关系敲对应硬盘门铃；
所述硬盘(例如，PCIe SSD)104获取存储器102-3上存储的SQ队列中的命令并执行；
所述硬盘104在执行完命令后，将执行的结果写入CQ队列并向访问控制装置102发起中断；
访问控制装置102接收到所述中断后，向存储控制器106返回数据或状态信息；
存储控制器106接收该数据或状态信息后，维护所述访问队列的尾指针，并更新所述访问队列的头指针；
读写操作结束。
由上可知，本发明实施例提供的SSD远程共享访问的方法、级联板和SSD远程共享访问的系统，可由访问处理装置102(例如，FPGA/ASIC)实现对NVMe SSD104的直接访问，将标准PCIe接口的NVMe SSD 104通过RDMA网络共享给多个存储控制器106，实现对NVMe SSD104远端共享访问的同时不增加读写访问时间。
需要说明的是：上述实施例提供的SSD远程共享访问的装置(例如级联板10)与SSD远程共享访问的方法实施例属于同一构思，因而，它们之间相应的部分可以相互参照，对于重复的内容，这里不再赘述。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置类实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种级联板，其特征在于，所述级联板一端连接远程直接内层访问RDMA网络，另一端连接固态硬盘SSD，所述级联板包括访问处理装置和与所述访问处理装置耦接的CPU，其中：
    所述CPU，用于完成对所述访问处理装置和所述SSD的初始化；
    所述访问处理装置，用于在接收到来自RDMA网络的访问命令时，实现对所述SSD的RDMA访问。
  2. 根据权利要求1所述的级联板，其特征在于，所述访问处理装置包括：RDMA接口以及存储器，其中：
    所述RDMA接口用于连接到RDMA网络；
    所述存储器用于保存访问队列。
  3. 根据权利要求1所述的级联板，其特征在于，所述级联板还包括周边组件接口高速PCIe交换芯片，所述PCIe交换芯片分别与所述CPU和所述访问处理装置相连，并连接所述SSD。
  4. 根据权利要求3所述的级联板，其特征在于，所述访问处理装置包括：PCIe接口、RDMA接口以及存储器；
    所述PCIe接口用于连接到所述PCIe交换芯片；
    所述RDMA接口用于连接到RDMA网络；
    所述存储器用于保存访问队列。
  5. 根据权利要求1-4任一所述的级联板，其特征在于，所述访问处理装置为现场可编程门阵列FPGA或特定用途集成电路ASIC。
  6. 根据权利要求5所述的级联板，其特征在于，所述CPU、所述访问处理装置和所述PCIe交换芯片集成在一起。
  7. 一种固态硬盘SSD远程共享访问的系统，其特征在于，所述系统包括至少一个SSD、至少一个控制器以及根据权利要求1-6任一所述的级联板；其中：
    所述控制器通过RDMA网络与所述级联板相连，并通过所述RDMA网络向所述访问处理装置发送访问命令。
  8. 根据权利要求7所述的系统，其特征在于，所述系统还包括RDMA交换机，所述RDMA交换机用于连接所述控制器和所述级联板。
  9. 一种固态硬盘SSD远程共享访问的方法，其特征在于，所述方法包括：
    CPU对访问处理装置和SSD进行初始化；
    访问处理装置在接收到来自远程直接内层访问RDMA网络的访问命令时，实现对所述SSD的RDMA访问。
  10. 根据权利要求9所述的方法，其特征在于，所述CPU对访问处理装置进行初始化包括：
    所述CPU根据访问队列的配置信息，在所述访问处理装置上分配用于存储所述访问队列的存储空间，并初始化所述访问队列；
    所述CPU将中断接收端指定为所述访问处理装置。
  11. 根据权利要求9或10所述的方法，其特征在于，所述访问处理装置在接收到 访问命令时，实现对所述SSD的RDMA访问包括：
    所述访问处理装置在接收到访问命令时，提示所述访问命令对应的SSD进行访问作业；
    所述访问处理装置在接收到来自所述SSD的中断后，通过RDMA网络返回数据或状态信息。
  12. 根据权利要求6-10任一所述的方法，其特征在于，所述访问处理装置为现场可编程门阵列FPGA或特定用途集成电路ASIC。
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