WO2017147037A1

WO2017147037A1 - Method for improving stability of photovoltaic articles incorporating chalcogenide semiconductors

Info

Publication number: WO2017147037A1
Application number: PCT/US2017/018629
Authority: WO
Inventors: Thomas M. Valeri; Arthur C. Wall; Robert K. Thompson; Szu-Ting Tsai
Original assignee: Dow Global Technologies Llc; NuvoSun, Inc.
Priority date: 2016-02-26
Filing date: 2017-02-21
Publication date: 2017-08-31

Abstract

Methods of making photovoltaic articles that incorporate one or more chalcogenide semiconductors wherein at least one chalcogenide semiconductor comprises copper and at least one chalcogen. More particularly, described herein are methods comprising a post-fabrication, extended heat treatment of such photovoltaic articles that improves stability against light degradation while under electric load.

Description

METHOD FOR IMPROVING STABILITY OF PHOTOVOLTAIC

ARTICLES INCORPORATING CHALCOGENIDE SEMICONDUCTORS

PRIORITY CLAIM

[001] This invention claims priority to U.S. Provisional Patent Application No.

62/300,557, filed February 26, 2016, the entire contents of which is incorporated herein by reference in its entirety for all purposes.

FIELD OF THE INVENTION

[002] The present invention relates to methods of making photovoltaic articles that incorporate one or more chalcogenide semiconductors wherein at least one chalcogenide semiconductor comprises copper and at least one chalcogen. More particularly, the present invention relates to methods comprising a post-fabrication, extended heat treatment of such photovoltaic articles that improves stability against light degradation while under electric load.

BACKGROUND OF THE INVENTION

[003] Both n-type chalcogenide semiconductor compositions and/or p-type chalcogenide semiconductor compositions have been incorporated into photovoltaic articles. The p- type chalcogenide semiconductor compositions have been used as the photovoltaic absorber region in these devices. Illustrative p-type, photovoltaically active chalcogenide compositions often include sulfides, selenides, tellurides and/or oxides of at least one or more of aluminum (Al), copper (Cu), indium (In), and/or gallium (Ga). More typically, at least Cu or even at least two or even all three of Cu, In, and Ga are present. Such materials are referred to as CIS, CIAS, CISS, CIGS, and/or CIGSS compositions, or the like (collectively CIGS-based compositions hereinafter).

[004] Absorbers based upon CIGS-based compositions offer several advantages. As one, these compositions have demonstrated high power conversion efficiencies both at laboratory scale and increasingly at manufacturing scale. Thin film solar cells

incorporating CIGS-based absorber layers can be very thin while still capturing a very high percentage of incident light. Such solar cells, therefore, present a potential low cost alternative to more traditional silicon based technologies. For example, in many devices, CIGS-based absorber layers have a thickness in the range from about 1 μιτι to about 2 μιτι. This is in contrast to much thicker silicon-based absorbers. Silicon-based absorbers have a lower cross-section for light capture and generally must be much thicker to capture the same amount of incident light.

[005] According to one proposed technique for manufacturing chalcogenide

semiconductor films, deposition methods are used in an initial stage to deposit and/or co- deposit all or a portion of the desired chalcogenide semiconductor constituents in one or more layers to form precursor film(s). At least a portion and sometimes all of the chalcogen(s) might not be included in the precursor film(s) at this stage. Instead, all or a portion of the chalcogen content might be incorporated into the precursor via

chalcogenization at a later processing stage. In many instances, chalcogenization involves selenization and/or sulfurization. Chalcogenization often involves a thermal treatment of the precursor film(s) in the presence of chalcogen(s). This kind of thermal treatment not only incorporates chalcogen into the precursor but also converts the crystal structure of the film(s) into a more suitable crystal form for photoactive functionality.

[006] Chalcogenide semiconductors are useful in a wide range of microelectronic devices including photovoltaic articles such as solar cells, strings of solar cells, or other modules incorporating solar cells. Solar cells based on a chalcogenide semiconductor such as Cu(In,Ga)Se₂ achieve higher power conversion efficiency by incorporating alkali metal content, e.g., Na, K, and/or Li incorporation, into the semiconductor as is well known in the literature. This incorporation improves performance at least in part by passivation of defects at grain boundaries, influencing grain growth, and/or improving the p-doping of a thin chalcogenide semiconductor film.

[007] In earlier research, when chalcogenide semiconductor solar cells were deposited on soda lime glass, it was discovered that Na diffused from the substrate and improved the device performance. Such diffusion was a relatively uncontrolled process. Accordingly, processes were developed in which films containing alkali metal content were

purposefully deposited in combination with or prior to chalcogenide precursor films in order to provide a more controllable source of alkali metal to incorporate into the resultant semiconductor film.

[008] The use of techniques to incorporate sodium into chalcogenide semiconductors has been described in Assignee's co-pending PCT Patent Application No.

PCT/US2015/066266 filed December 17, 2015; EP 2410556 A2; WO 2012054467 A2; US 2012/0217157 Al ; WO 2012147985 Al; and US 5,994,163. [009] CIGS -based photovoltaic articles are susceptible to light degradation over time. The degradation accelerates when the articles are under electric load and/or exposed to elevated temperatures. The degradation causes problems, including a loss of power output over time. Strategies to make these articles more robust against light degradation are needed.

SUMMARY OF THE INVENTION

[0010] The present invention provides methods of treating photovoltaic articles of the type that include one or more different kinds of p and/or n-type chalcogenide

semiconductors. In many embodiments, the treatments of the present invention are particularly useful for treating photovoltaic articles that incorporate p-type chalcogenide semiconductors that include Cu and at least one chalcogen and/or n-type chalcogenide semiconductors including Cd and at least one chalcogen. Advantageously, the treatment of the present invention provides photovoltaic devices that are more resistant to light degradation. For example, in accelerated aging tests during which test articles are exposed to high illumination and high electric load, the articles maintained power output even after aging under test conditions for one week. In contrast, comparison articles without the treatment of the present invention experienced significant power losses under the same conditions.

[0011] The present invention is based in part upon treatments in which photovoltaic articles are heat treated for extended periods of time, preferably while limiting exposure of the articles to light during the treatment period. Such extended heat treatments help to stabilize the articles against subsequent light degradation even when the devices are under load or at elevated temperatures. The benefits of using heat to stabilize the articles against light degradation are counterintuitive in view of the conventional understanding that heat accelerates degradation of articles exposed to light.

[0012] Without wishing to be bound by theory, a possible rationale to explain the benefits of the heat treatment can be proposed. Chalcogenide semiconductors, particularly the p- type chalcogenide semiconductors comprising Cu and optionally In, Ga, Al, Na, K, Li, or the like may incorporate species that are relatively mobile. It is believed that the mobility of such one or more of such species may be instigated by light exposure, particularly under electric load and/or when heated. It is believed that the heat treatment of the present invention may help to immobilize such species so that the articles are rendered much more robust against degradation during subsequent photovoltaic use.

[0013] In one aspect, the present invention relates to a method of treating a photovoltaic article, comprising the steps of:

a) providing a photovoltaic article, said photovoltaic article comprising:

1) a support;

2) a first electrical contact region provided on the support;

3) a photovoltaic region, said photovoltaic region comprising (i) a p- type chalcogenide semiconductor layer comprising copper and at least one chalcogen, wherein the p-type chalcogenide semiconductor is in ohmic contact with the first electrical contact region; and (ii) an n-type semiconductor chalcogenide layer comprising cadmium and at least one chalcogen, wherein the n-type semiconductor chalcogenide layer is in rectifying contact with the p-type chalcogenide semiconductor layer; and

4) a light transmissive, top electrical contact region in ohmic contact with the n-type semiconductor layer; and

b) heating at least a portion of the photovoltaic article at a temperature in the range of 100°C to 200°C for a time period of at least 15 hours. Desirably, the heating step occurs under conditions in which light exposure is limited to help protect the article against light degradation during the heat treatment. Desirably, the heating step occurs while the device is not under electric load or is under a reduced electric load.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Fig. 1 schematically shows a photovoltaic article as an example of a

microelectronic device that can be treated using principles of the present invention.

[0015] Fig. 2 schematically shows one exemplary method to make and heat treat the device of Fig. 1 in a roll-to-roll manufacturing scheme.

[0016] Fig. 3 is a graph showing how the heat treatment of the present invention stabilizes the power output of photovoltaic articles against power degradation over time when exposed to light under electric load. [0017] Fig. 4 is a graph showing how comparison samples of photovoltaic articles suffer power degradation when over time when exposed to light under electric load.

[0018] Fig. 5 is a graph showing (1) how comparison samples of photovoltaic articles suffer power degradation when over time when exposed to light under electric load; and (2) how the heat treatment of the present invention stabilizes the power output of photovoltaic articles against power degradation over time when exposed to light under electric load.

DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS

[0019] The embodiments of the present invention described below are not intended to be exhaustive or to limit the invention to the precise forms disclosed in the following detailed description. Rather a purpose of the embodiments chosen and described is so that the appreciation and understanding by others skilled in the art of the principles and practices of the present invention can be facilitated. All patents, patent applications, and publications cited herein are incorporated herein by reference in their respective entireties for all purposes. The foregoing detailed description has been given for clarity of understanding only. No unnecessary limitations are to be understood therefrom. The invention is not limited to the exact details shown and described, for variations obvious to one skilled in the art will be included within the invention defined by the claims.

[0020] The present invention provides treatments that are useful to help stabilize chalcogenide-based photovoltaic articles as well as other chalcogenide-based

microelectronic devices against light degradation. Examples of microelectronic devices include not only photovoltaic articles but also laser diodes, transistors, lasers, quantum heterostructures, liquid crystal displays, substrates for epitaxial growth of other semiconductors, semi-insulating crystals, mobile phones, satellite circuitry, aircraft circuitry, microprocessors, integrated circuits, sensors, detectors, optical windows, integrated circuits, power electronics, and the like.

[0021] As used herein, a photovoltaic article is an article that converts incident light energy, such as solar energy, into electric power using one or more semiconducting materials that exhibit the photovoltaic effect. A photovoltaic article may be initially fabricated as a large web, such as in roll-to-roll processes in which a substrate is conveyed from a supply roll to a take-up roll. As the substrate is conveyed roll-to-roll, the substrate moves through a series of processing stations to fabricate the photovoltaic article. The entire fabricated web may be stored on the take-up roll for further processing (e.g., a post- fabrication heat treatment according to principles of the present invention) or other handling. Alternatively, the fabricated web may be slit into two or more lanes that are each stored on respective take-up rolls prior to further processing or handling. In still further embodiments, the web may be further subdivided into smaller units corresponding to individual solar cells or groups of such cells prior to further processing or handling. Individual solar cells are building blocks of larger units referred to in industry as solar cell strings, solar cell modules, or solar cell panels.

[0022] In an exemplary mode of carrying out a treatment of the present invention, a photovoltaic article is provided. Fig. 1 schematically illustrates an exemplary

photovoltaic article 10 useful in practicing the present invention. Article 10 includes a light incident face 12 that receives light rays 14 and a backside face 16. Article 10 uses photovoltaic principles to absorb light rays 14 and convert the light energy into electric energy.

[0023] Device includes support 17, backside electrical contact region 18 as a first electrical contact region, p-type semiconductor region 20, n-type semiconductor region 22, a light transmissive, top electrical contact (TC) region 24, and optionally electrically conducting grid 30. Each of these features can be a single integral layer as illustrated. Alternatively, any one or more of these regions can be formed from two or more layers. Additionally, one or more barrier layers (not shown) also may be provided over all or portions of article 10 for purposes such as to help isolate article 10 from the ambient and/or to electrically isolate article 10. One or more additional layers (not shown) optionally may be deposited onto the backside face 16 of the support for a variety of reasons, including helping prevent selenization of the substrate during fabrication of the cell. Such one or more layers if present typically include molybdenum.

[0024] The support 17 may be rigid or flexible, but desirably is flexible in those embodiments in which the article 10 may be used in combination with non-flat surfaces, when reduced weight is important, and/or as a way to provide high throughput, low cost, roll-to-roll manufacturing. Support 17 may be formed from a wide range of materials. These include glass, quartz, other ceramic materials, polymers, metals, metal alloys, intermetallic compositions, paper, woven or non-woven fabrics, combinations of these, and the like. Stainless steel is preferred.

[0025] The backside electrical contact region 18 provides a convenient way to electrically couple article 10 to external circuitry. Contact region 18 may be formed from a wide range of electrically conductive materials such as one or more of Cu, Mo, Ag, Al, Cr, Ni, Ti, Ta, Nb, W combinations of these, and the like. Conductive compositions

incorporating Mo may be used in an illustrative embodiment.

[0026] Optional layers (not shown), in addition to the support 17, may be used proximal to backside face 16 in accordance with conventional practices now known or hereafter developed to help enhance adhesion between backside electrical contact region 18 and the support 17 and/or between backside electrical contact region 18 and the region 20.

Collectively, such optional layers (if any), support 17 and region 18 provide a substrate 15 upon which additional components of article 10 are supported.

[0027] A photovoltaic region 21 is provided on the backside electrical contact region 20. Photovoltaic region 21 comprises p-type chalcogenide semiconductor region 20 and n- type chalcogenide semiconductor region 22 in a manner such that the p-type chalcogenide semiconductor region 20 is in ohmic contact with the backside electrical contact region 18 and such that the n-type chalcogenide semiconductor region 22 is in rectifying contact with the p-type chalcogenide semiconductor region 20. The article 10 as illustrated thus is provided with a pn heteroj unction structure. Other photovoltaic junctions may be used in alternative embodiments. For example, other illustrative junctions using such p-type and n-type chalcogenide semiconductor materials may be formed as p-i-n junctions, n-p-n junctions, p-n-p junctions, p-metal contact junctions, n-metal contact junctions, or the like.

[0028] In many embodiments, p-type chalcogenide semiconductor region 20 may be a single integral film as illustrated. In some other embodiments, region 20 may be a film formed from one or more layers (not shown). If region 20 is a film comprising two or more layers, each layer may have the same or differing formulations than other layer(s). For example, a particular layer may have more Ga content than another layer. Each layer may have the same or a different morphology than other layer(s). For example, as taught in Applicant's co-pending US 201 1/0192453-Al , a lower portion of region 20 may have a morphology with relatively fine crystalline domains to promote adhesion to the adjacent backside electrical contact region 18, while an upper portion of region 20 may incorporate relatively larger crystalline domains to promote more desired electronic performance.

[0029] The p-type chalcogenide semiconductor region 20 absorbs light energy embodied in the light rays 14 and then photovoltaically converts this light energy into electric energy. In terminology used by the industry, region 20 may be referred to as an absorber region due to the function of absorbing light energy and converting that energy into electric energy.

[0030] In many embodiments, at least a portion of the p-type chalcogenide

semiconductor(s) of region 20 may be present in poly crystalline form. Advantageously, these materials exhibit excellent cross-sections for light absorption that allow region 20 to be very thin and flexible. In illustrative embodiments, a typical region 20 may have a thickness in the range from about 0.5 μηι to about 5 μιτι, preferably about 0.8 μηι to about 3 μηι, more preferably 1 μιη to about 2 μηι.

[0031] The p-type chalcogenide semiconductor region 20 generally includes at least one p-type, semiconductor chalcogenide comprising Cu and at least one chalcogen. In addition to Cu, many illustrative embodiments of the semiconductor chalcogenides also include at least one of In, Al, and/or Ga. One illustrative semiconductor chalcogenide includes Cu and In. Another illustrative semiconductor chalcogenide includes Cu, In, and Ga. Examples of chalcogens include one or more of S, Se, Te, and/or O. Even though oxygen does not promote photoabsorbing functionality to the same degree and/or in the same manner as Se or S, oxygen may still be incorporated into the resultant semiconductor material to serve one or more other desired objectives. For example, many chalcogenide semiconductor materials could incorporate at least some oxygen as an impurity without significant deleterious effects upon electronic properties. In some other embodiments, O is excluded as much as is reasonable practical.

[0032] Preferred examples of p-type chalcogenide semiconductors are selenides, sulfides, tellurides, selenides-tellurides, sulfides-tellurides, selenides-sulfides, and/or selenides- sulfides-tellurides that include Cu, more preferably Cu and at least one of In, Al, and/or Ga, even more preferably Cu, In, and Ga. Specific examples of selenides and sulfides include but are not limited to copper indium selenides, copper indium gallium selenides, copper gallium selenides, copper indium sulfides, copper indium gallium sulfides, copper gallium sulfides, copper indium sulfide selenides, copper gallium sulfide selenides, copper indium aluminum selenides and copper indium gallium sulfide selenides. The copper indium selenides and copper indium gallium selenides are preferred.

[0033] In the practice of the present invention, at least one p-type chalcogenide semiconductor of the p-type chalcogenide semiconductor region 20 desirably includes at least one alkali metal constituent, preferably at least one of Na, K and Li, more preferably Na and/or K. The alkali metal content of the resultant semiconductor may be present in a variety of forms including but not limited to being present in elemental metal form, metal alloys, intermetallic compositions, compounds, and/or salts. Examples of alkali metal compounds include oxides, fluorides, chlorides, bromides, molybdates, hydroxides, tungstates, sulfates, titanates, metavanadates, sulfides, selenides, carbides, nitrides, and combinations of these. Fluorides, sulfides, and selenides are presently preferred.

[0034] In preferred embodiments, alkali content is present as elemental Na and/or elemental K. The alkali content may be present in the same or different phase(s) than the chalcogenide material(s). Without wishing to be bound by theory, it is believed that the alkali content generally occurs along grain boundaries of the chalcogenide semiconductor. This is supported by microscopic mapping analysis, which shows the alkali content at these boundaries. Without wishing to be bound by theory, it is believed that the alkali content at the grain boundaries is associated with the chalcogenide material by physical or chemical bonds or other association.

[0035] The alkali content of the chalcogenide semiconductor provides many advantages. In particular, the alkali content improves electronic performance compared to otherwise identical materials without alkali content. Examples of electronic properties that are improved by alkali content include efficiency, fill factor, and open circuit voltage.

[0036] The amount of alkali content incorporated into the chalcogenide semiconductor may be selected from a wide range. If too little is present, desired improvements in electronic performance may not result to the degree desired. If too much is present, adhesion between the semiconductor and other layers could be reduced. For example, in one mode of practice, a chalcogenide precursor is formed from a relatively thin layer containing alkali metal content and a relatively thicker layer including additional precursor constituents. During the course of forming the precursor and/or the resultant chalcogenide semiconductor, the alkali content in the relatively thinner layer will tend to diffuse into the chalcogenide material. The chalcogenide material generally has a saturation level for the alkali content. If an excess of alkali material is present relative to this saturation threshold, diffusion of the excess material may not occur. The excess material could reside below and/or above the resultant chalcogenide semiconductor material and unduly reduce adhesion between the chalcogenide semiconductor material and adjacent layers. Accordingly, the alkali content as deposited and as incorporated into the chalcogenide semiconductor is at or below this saturation level. For many

chalcogenide semiconductor materials, the saturation level may tend to occur when the atomic ratio of the alkali metal content to the total amount of metals is about 0.02: 1.

[0037] Desirably, therefore, the atomic ratio of the alkali metal content to the total amount of metals and chalcogen in the chalcogenide semiconductor is up to 0.02: 1 , preferably in the range from 0.001 : 1 to 0.02: 1, more preferably in the range from 0.01 : 1 to 0.02: 1 , even more preferably in the range from 0.01 : 1. The alkali content can be distributed throughout the entirety of the chalcogenide semiconductor or may be incorporated into one or more selected portions of the chalcogenide semiconductor. For example, alkali content may be present in a lower portion of region 18, a middle portion, or a top portion. In other embodiments, the alkali metal content may have a concentration gradient in which the amount of alkali content varies as a function of depth. For example, portions of the chalcogenide semiconductor proximal to the top of the chalcogenide semiconductor may be relatively richer in alkali content than lower regions.

[0038] The practice of the present invention is particularly beneficial when used to treat photovoltaic articles whose p-type chalcogenide materials incorporate alkali metal content. Without wishing to be bound by theory, it is believed that one factor leading to light-induced degradation of p-type chalcogenide semiconductors relates to undue mobility of alkali metal content. It is believed that the extended heating stage (described below) of photovoltaic articles incorporating such alkali metal content may tend to immobilize the alkali metal material, leading to enhanced resistance to light degradation.

[0039] One illustrative class of chalcogenide semiconductors incorporating alkali content may be represented by the formula

Cu_aIn GacSe_wM_z (A)

wherein:

"M" is an alkali metal such as Na, Li, K, or combinations of these;

"a" is < 1 ; "a/(b+c) < 1, preferably 0.8 to 0.95;

"b+c" is approximately 1.0;

"c/(b+c) is about 0.3;

"w" is approximately 2; and

"z" is 0.004 to 0.08 (i.e., up to approximately 2% of all other elements), preferably 0.008 to 0.04.

[0040] In one embodiment, a chalcogenide semiconductor has the composition

Cu(23%)In(19%)Ga(8%)Se(50%)Na(l%), wherein the percentages are atomic percentages.

[0041] The n-type semiconductor region 22 generally comprises at least one n-type chalcogenide semiconductor material with a suitable band gap to help form a p-n heteroj unction proximal to the interface between the p-type region 20 and the n-type region 22. A wide range of n-type chalcogenide semiconductor materials may be incorporated into region 22. Illustrative materials include selenides, sulfides, tellurides, and/or oxides of one or more of cadmium, zinc, lead, indium, tin, combinations of these and the like, optionally doped with materials including one or more of fluorine, sodium, lithium, combinations of these and the like. In some illustrative embodiments, region 22 includes at least one n-type chalcogenide that comprises cadmium and at least one chalcogen. Some illustrative embodiments are a selenide and/or sulfide including cadmium and optionally at least one other metal such as zinc. Other illustrative embodiments may include sulfides and/or selenides of zinc. A typical region 22 may have a thickness in the range from about 20 nm to about 200 nm.

[0042] Article 10 may include an optional intrinsic or resistive window region or layer (not shown) between the n-type semiconductor region 22 and the TC region 24. A window region can help to protect against shunts and also may protect region 22 during subsequent deposition of the TC region 24. The window region may be formed from a wide range of materials and often is formed from a resistive, transparent oxide such as an oxide of Zn, In, Cd, Sn, combinations of these and the like. An exemplary window material is intrinsic ZnO and/or AZO. A typical window region may have a thickness in the range from about 10 nm to about 200 nm.

[0043] The TC region 24 is interposed between the region 22 and light incident surface 12 and is in ohmic contact with the region 22 to provide a top conductive electrode for the article 10. In many embodiments, region 24 comprises one or more transparent conductive oxides (TCO's) and/or very thin, light transmissive, transparent metal film. In many suitable embodiments where the TC region is a transparent conductive oxide (TCO), the TCO layer has a thickness in the range from about 10 nm to about 5000 nm, preferably about 150 nm to about 300 nm. As shown, the TCO region 24 is in direct contact with the region 22. As an example of another option, a window region may be interposed between TCO region 24 and region 22. One or more intervening layers optionally may be interposed for a variety of reasons such as to promote adhesion, enhance electrical performance, or the like.

[0044] A wide variety of transparent conducting oxides (TCO) or combinations of these may be incorporated into the transparent conductive region 24. Examples include fluorine-doped tin oxide, tin oxide, indium oxide, indium tin oxide (ITO), aluminum doped zinc oxide (AZO), zinc oxide, combinations of these, and the like. In one illustrative embodiment, the transparent conductive region 24 is indium tin oxide. TCO layers are conveniently formed via sputtering or other suitable deposition technique.

[0045] The transparent conductive region 24 may have a thickness greater than about 5 nm and more preferably greater than about 30 nm. Additionally, the transparent conductive region is preferably less than about 200 nm thick, more preferably less than about 100 nm thick. These representative embodiments result in films that are sufficiently transparent to allow incident light to reach the absorber region 20. Preferably, the transparent conductive layer is a transparent conductive oxide. As used herein, the term "metal" refers not only to metals, but also to metal admixtures such as alloys, intermetallic compositions, combinations of these, and the like. These metal compositions optionally may be doped. Examples of metals that could be used to form thin, optically transparent layers 30 include the metals suitable for use in the backside electrical contact 28, combinations of these, and the like.

[0046] In many embodiments, an optional electrically conductive collection grid 30 is positioned over TC region 24. Grid 30 can be formed from a wide range of electrically conducting materials, but most desirably is formed from one or more metals, metal alloys, or intermetallic compositions. Exemplary contact materials include one or more of Ag, Al, Cu, Cr, Ni, Ti, combinations of these, and the like. In one illustrative embodiment, the grid has a dual layer construction comprising nickel and silver. Since these materials are not transparent, they are deposited as a grid of spaced apart lines so that the grid occupies a relatively small footprint on the surface (e.g., in some embodiments, the grid occupies about 5% or less, even about 2% or less, or even about 1% or less of the total surface area associated with light capture to allow the photoactive materials to be exposed to incident light). Industry is aware that photovoltaic articles incorporating p-type chalcogenide semiconductors comprising Cu (also known as CIGS-based photovoltaic articles) are vulnerable to light-induced degradation, particularly when exposed to sunlight while connected to an electrical load. The degradation tends to accelerate with increasing temperature. Advantageously, the post-fabrication heat treatment of the present invention makes the device 10 substantially more resistant to light degradation.

[0047] For example, CIGS-based solar cells can be subjected to test conditions under which the cells are under an electric load while illuminated with light. The power output of the cells is monitored as a function of time. One goal is that the solar cells retain at least 92% of their power output after being aged under test conditions for 170 hours. Comparison photovoltaic samples were tested. None of the comparison samples were subjected to a post-fabrication heat treatment in accordance with the present invention. Over half the samples showed substantial power loss and failed the test. Several of the comparison samples even showed power losses down to 70% to 75% of initial power output. Samples of the present invention were prepared in an identical manner but in addition were subjected to the same test conditions. The samples of the present invention received a post-fabrication heat treatment of the present invention. All of the samples receiving the post-fabrication heat treatment passed the test, retaining over 92% of their power output after aging under test conditions for 170 hours.

[0048] Consequently, after device 10 is fabricated to include at least the support 17, backside electrical contact region 18, p-type region 20, n-type region 22, and top electrical contact region 24, the device 10 is subjected to a post-fabrication heat treatment of the present invention. Optionally, all or a portion of grid 30 may be present during such post- fabrication heat treatment. A characteristic of the heat treatment is that it occurs for an extended period of at least 15 hours. In some embodiments, the heat treatment occurs for a time period in the range from 15 to 350 hours, 25 to 200 hours, or even 50 hours to 170 hours. Another characteristic of the heat treatment is that it occurs at a temperature in the range from 100°C to 200°C, preferably 120°C to 200°C, more preferably 150°C to 200°C. The heat treatment desirably occurs in a single stage, but optionally may be heat treated in two or more stages such that the cumulative treatment time at such temperatures is in the time period ranges specified herein.

[0049] The post-fabrication heat treatment may occur in ambient air or in a non-ambient atmosphere. For example, the heat treatment may occur in an inert atmosphere in which oxygen is excluded to levels below ambient levels. In such inert atmospheres, oxygen also may be excluded as much as is practical so that the inert atmosphere includes less than 1 ppm oxygen or even under 100 ppb oxygen on a weight basis. Examples of inert atmospheres include Ar, nitrogen, CO2, and combinations of these. In some

embodiments, the heat treatment may occur in an atmosphere comprising hydrogen.

[0050] The heat treatment may occur at one or more pressures selected from a wide range. Exemplary pressures may be ambient pressure, pressures less than ambient, or pressures greater than ambient. In some embodiments, heat treatment occurs at a pressure of 1 atm to 300 atm as measured by a pressure sensor that monitors pressure in the headspace of the oven above the material being heat treated.

[0051] The heat treatment desirably occurs while the photovoltaic article being treated is not under any electric load or is under a reduced electric load that is sufficiently low to avoid undue degradation during the heat treatment. Desirably, to avoid undue electric load during the heat treatment, the photovoltaic article being treated is not electrically coupled to any other photovoltaic article or other component of an electric circuit during the heat treatment. to avoid undue voltage or current flow during the heat treatment. By avoiding or limiting the electric load during the heat treatment, device 10 is made more robust against light degradation when later placed under electric load while exposed to sunlight.

[0052] The heat treatment may occur under ambient light. More desirably, the heat treatment occurs in an enclosed heating chamber under conditions such that the light incidence face(s) of photovoltaic articles being heat treated is reduced relative to ambient light, particularly portions of the light spectrum that are photovoltaically absorbed by the p-type chalcogenide semiconductor(s) incorporated into the photovoltaic device.

Desirably, the photovoltaic article(s) are heated under a reduced light intensity relative to the ambient, such as a light intensity that is in the range from 0 to 2000 lux, preferably 0 to 40 lux, more preferably 0 to 10 lux, even more preferably 0 to 1 lux, or still even more preferably 0 to 0.25 lux. By way of comparison, bright sunlight is approximately 110,000 lux. Daylight intensity on an overcast day is about 1000 lux to about 2000 lux. Daylight intensity under very heavy storm clouds is under about 200 lux. The full moon on a clear night provides light intensity of about 0.25 lux. Starlight on a clear night without airglow provides a light intensity of about 0.0002 lux.

[0053] When photovoltaic articles are heated in roll form, nearly all of the light incident faces of the articles are shielded from incident light except at edges. Accordingly, heating such roll articles may be accomplished without necessarily shielding the oven chamber from incident light. However, to avoid light degradation proximal to edges of the rolled up photovoltaic article, it is still preferred to isolate even rolls during the heat treatment.

[0054] Conventional wisdom is that exposure to light, electric load, and heat induces degradation of the p-type chalcogenide semiconductor(s). An aspect of the present invention is to appreciate that an initial, extended heat treatment in the absence of light, preferably the absence of light band portions that induce degradation, actually can make the material substantially more robust against later light degradation even if exposed to light at high temperature.

[0055] In roll-to-roll manufacturing processes, the photovoltaic is manufactured in web form and often taken up on a single roll. Other times, the web may be pre-slit into two or more lanes, and each lane of web is then stored as separate roll on one large or two or more take up rolls. In still other modes of practice, the web may be further subdivided in to smaller sections, e.g., individual solar cells. The heat treatment may occur at any stage after the initial photovoltaic article is formed. For example, the entire take up roll may be heat treated prior to the roll being subdivided into lanes or smaller sections. Alternatively, heat treating of one or more sub-rolls may occur after the initial web is slit into two or more lanes. As another alternative, heat treating may occur after the web is subdivided into smaller sections such as individual solar cells. As still another alternative, heat treatment may occur at two or more of these stages.

[0056] Fig. 2 schematically shows how the principles of the present invention can be integrated into a roll-to-roll manufacturing system 200 to provide a web-based

photovoltaic article 10 of Fig. 1 that is slit into multiple rolls 220, and then the rolls 220 are individually or collectively heated treated in accordance with the present invention. According to system 200, a supply of support 17 is conveyed from supply roll 202 to slitting station 204. At station 205, the back electrode 18 is sputtered onto support 17 to thereby provide substrate 15. Next, one or more precursor layers of the desired chalcogenide-based semiconductor region are formed at stations 206 and 208. Annealing and chalcogenization of the one or more precursor layers then occur at station 210 to convert the precursor structure 104 into the p-type chalcogenide semiconductor region 20. The n-type chalcogenide region 22 is then formed at station 212. The TC region 24 is then formed at station 214. Optionally, grid 30 may be formed at station 216. In some modes of practice, the photovoltaic article is heat treated first, after which grid 30 is provided. Some embodiments do not include grid 30 at all. The resultant photovoltaic article is then conveyed to optional slitting station 218, where the web is slit into two or more lanes. For purposes of illustration, web is slit into 4 lanes 219. In actual practice, the web-based photovoltaic article may be slit into 2 to 50, often 4 to 15, or even 10 lanes. Each lane may then be stored in separate take up rolls 220 or in combination with one or more other lanes on a take-up roll with a common core. As shown, each lane is stored on a separate take up roll 220. One or more of the take up rolls 220 are then heat treated in oven 222 in accordance with the present invention. After heat treatment, the treated rolls may be stored or otherwise handled for storage or further processing.

[0057] The present invention will now be further described with respect to the following illustrative examples.

Example 1

Preparation of CIGS-based Photovoltaic Modules

[0058] A flexible, stainless steel support is provided. The web is supplied from a supply or pay out roll and is conveyed to a take up roll. Optional surface treatments may be used to clean or wipe the stainless steel prior to any subsequent coating. The bottom of the support is coated with Mo as a barrier to help isolate the stainless steel from high temperature exposure to Se. Sputtering is used to deposit the Mo coating.

[0059] Next, a back electrode is formed on the top of the stainless steel support. The back electrode is formed by sputtering Ti and Mo layers, respectively onto the support.

[0060] Next, a layer of NaF is formed on the back electrode, and then a precursor structure corresponding to the desired p-type chalcogenide region is formed on the NaF layer. During the formation of the precursor structure, it is likely that at least a portion of the Na from the NaF layer is incorporated into the precursor structure. [0061] The precursor structure is then heat treated in the presence of selenium created by evaporation of elemental Se to convert the precursor structure to a p-type chalcogenide Cu(In, Ga)Se₂ (CIGS) semiconductor containing Na content. It is likely that at least a portion of the Na from the NaF layer is incorporated into the semiconductor at this stage of processing.

[0062] Next, an n-type buffer layer of CdS is formed on the CIGS semiconductor. A layer of oxygen-doped AlZnO is formed on the CdS layer. A transparent conductive oxide (InSnO) layer is then formed on the AlZnO) layer.

[0063] The resultant web-based photovoltaic article is slit into ten lanes. The slit lanes are stored on ten take up rolls, respectively. A portion of the resultant rolls were heat treated in an oven as described in examples below prior to being used to carry out light degradation testing. Other portions of the resultant rolls were used to carry out light degradation testing without any post-fabrication heat treatment.

[0064] The samples that were heat treated as well as the samples that are not heat treated are further prepared for light degradation testing by applying a metal collection grid to the top surface of the cell material and subsequently dividing the roll into individual solar cells. The resulting solar cells are connected serially and are then constructed into a solar module consisting of a top moisture barrier, glass or equivalent, a back moisture barrier consisting of polymers with an embedded metallic layer, and adhesive materials connecting the top barrier, cells, and back barrier.

Example 2

Post-Fabrication Heat Treatment and Light Degradation Testing

[0065] Module samples of the present invention were prepared in accordance with Example 1 using rolls that were subjected to a post-fabrication heat treatment in ambient air at 160°C for 72 hours in an enclosed oven in the absence of light without any electric load being placed on the articles. Eight sample sets were subjected to light degradation testing. Each sample set included 6 modules. Each module included 6 individual cells. The initial output of each module was measured prior to the module being stressed under light exposure and electric load. For each sample set, the average initial output of the modules in that set was computed. Each module was then stressed under light exposure and electric load at 55°C at 1000 W/m² illumination and an electric load set to the maximum power point of the sample being tested for a period of 170 hours. This tended to provide an internal sample temperature of greater than about 80°C during the course of the stress exposure. After the stress exposure, the stressed output of each module was then measured. For each sample set, the average stressed output of the modules in that set was computed. The average final output of each sample set was compared to the average initial output of that sample set. An illustrative test criterion is that, on average, samples must retain greater than 92% of the original efficiency after 170 hours of exposure to pass the test.

[0066] The results of the test are shown in Fig. 3. The data shows data points and interconnecting lines plotted for each sample set. The data point on each line at 0 hours indicates the average initial output for the sample set. The data point at 170 hours shows the average final output after stress exposure. A line interconnects the two data points for each sample set to help visually show the change in average output for each sample set. The data shows that 100% of the heat treated sample sets passed the test. All the sample sets on average retained greater than 92% efficiency after 170 hours of light degradation testing.

Comparison Example A

Light Degradation Testing of Comparison Samples Without Heat Treatment

[0067] Comparison module samples were prepared in accordance with Example 1 using rolls without any post-fabrication heat treatment. Twenty three sample sets were subjected to light degradation testing as described in Example 2 and evaluated to compare the average initial output of each sample set to the average final output. Each sample set included 6 modules of 6 individual sample cells each.

[0068] The results of the test of the comparison samples are shown in Fig. 4. The data shows data points and interconnecting lines plotted for each sample set. The data point on each line at 0 hours indicates the average initial output for the sample set. The data point at 170 hours shows the average final output after stress exposure. A line interconnects the two data points for each sample set to help visually show the change in average output for each sample set. The data show that over half the comparison sample sets showed power levels that on average dropped under 92% as a result of light degradation, thus failing the test criteria applied to the light degradation test. The results show that CIGS-based solar cells are vulnerable to light degradation when under electric load. Comparison Example B

Brief heat treatment and Light Degradation Testing

[0069] Comparison module samples were prepared in accordance with Example 1 using rolls that were subjected to a post-fabrication heat treatment for a short duration of 12 hours in ambient air at 160°C for 72 hours in an enclosed oven in the absence of light without any electric load being placed on the articles. Each module included 6 individual cells. Four sample sets were subjected to light degradation testing as described in Example 2 and evaluated to compare the average initial output of each sample set to the average final output. Each sample set included 6 modules of 6 individual sample cells each.

[0070] The results are shown on the left half of Fig. 5 in the column corresponding to a post-fabrication heat treatment occurring for 12 hours. The data shows data points and interconnecting lines plotted for each sample set. The data point on each line at 0 hours indicates the average initial output for the sample set. The data point at 170 hours shows the average final output after stress exposure. A line interconnects the two data points for each sample set to help visually show the change in average output for each sample set. For comparison, the data for a portion of the sample sets of Example 2 are shown on the right side of the graph of Fig. 5 in the column corresponding to a post-fabrication heat treatment for 72 hours.

[0071] The data shows that on average nearly all of the sample sets baked for only 12 hours failed the test, falling below the 92% specification. In contrast and as further shown in Figs. 3 and 5, 100% of the sample sets of the present invention passed the test, remaining well above the 92% threshold. The ability of an extended, post-fabrication heat treatment to improve resistance to light degradation is surprising, when normally light exposure and heat in combination tend to accelerate light degradation.

[0072] All patents, patent applications, and publications cited herein are incorporated by reference as if individually incorporated. Unless otherwise indicated, all parts and percentages are by weight and all molecular weights are number average molecular weights. The foregoing detailed description has been given for clarity of understanding only. No unnecessary limitations are to be understood therefrom. The invention is not limited to the exact details shown and described, for variations obvious to one skilled in the art will be included within the invention defined by the claims.

Claims

WHAT IS CLAIMED IS:

1. A method of treating a photovoltaic article, comprising the steps of:

a) providing a photovoltaic article, said photovoltaic article comprising:

1) a support;

2) a first electrical contact region provided on the support;

b) heating at least a portion of the photovolatic article at a temperature in the range of 100°C to 200°C for a time period of at least 15 hours.

2. The method of claim 1, wherein the p-type chalcogenide further comprises sodium, potassium, lithium, or combinations thereof.

3. The method of claim 1, wherein step (a) comprises sputtering a precursor of the p-type chalcogenide semiconductor and converting the precursor into the p-type chalcogenide semiconductor.

4. The method of claim 1, wherein step (a) comprises (i) using an evaporation technique to form a precursor of the p-type chalcogenide semiconductor and (ii) converting the precursor into the p-type chalcogenide semiconductor.

5. The method of claim 1, wherein step (a) comprises using an evaporation technique to form the p-type chalcogenide semiconductor.

6. The method of claim 1, wherein the p-type chalcogenide semiconductor comprises Se and/or S.

7. The method of claim 1, wherein step (b) comprises heating the solar cell at a temperature in the range from 150°C to 200°C.

8. The method of claim 1, wherein step (b) comprises heating the solar cell for a time period in the range from 15 hours to 350 hours.

9. The method of claim 1, wherein step (b) comprises heating the solar cell for a time period in the range from 50 hours to 170 hours.

10. The method of claim 1, wherein step (b) comprises heating the solar cell in the presence of ambient air.

11. The method of claim 1, wherein step (b) comprises heating the solar cell in the presence of an inert, non-ambient atmosphere.

12. The method of claim 1, wherein step (b) comprises heating the solar cell in the presence of a reducing atmosphere.

13. The method of claim 1, wherein step (b) comprises heating the solar cell in the presence of a reducing atmosphere comprising hydrogen.

14 The method of claim 1, wherein step (b) comprises heating the solar cell at a pressure greater than 1 atm.

15. The method of claim 1, wherein step (b) comprises heating the solar cell at a pressure in the range from greater than 1 atm to 300 atm.

16. The method of claim 1, wherein the n-type chalcogenide semiconductor layer comprises a cadmium chalcogenide.

17. The method of claim 1, wherein the photovoltaic article is a web, and wherein the method further comprises the step of, after step (b), subdividing the heated web to provide at least one solar cell.

18. The method of claim 1, wherein the photovoltaic article is a web, and wherein the method further comprises the step of, prior to step (b), dividing the web to provide at least one solar cell, and wherein step (b) comprises heating the solar cell.

19. The method of claim 1, wherein the heating step occurs in a heating chamber under conditions of limited light intensity such that the light intensity in the chamber is under 200 lux.

20. The method of claim 1, wherein the heating step occurs in a heating chamber under conditions of limited light intensity such that the light intensity in the chamber is under 1 lux.