WO2017139008A1 - Spectromètre visible-infrarouge à ondes courtes à large bande - Google Patents

Spectromètre visible-infrarouge à ondes courtes à large bande Download PDF

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Publication number
WO2017139008A1
WO2017139008A1 PCT/US2016/064585 US2016064585W WO2017139008A1 WO 2017139008 A1 WO2017139008 A1 WO 2017139008A1 US 2016064585 W US2016064585 W US 2016064585W WO 2017139008 A1 WO2017139008 A1 WO 2017139008A1
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Prior art keywords
light
semiconductor region
wavelength component
lenses
shortwave infrared
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Application number
PCT/US2016/064585
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English (en)
Inventor
Jae Hyung Lee
Juhyung KANG
Youngsik Kim
Yeul Na
Wooshik JUNG
Original Assignee
Stratio
Stratio, Inc.
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Application filed by Stratio, Stratio, Inc. filed Critical Stratio
Publication of WO2017139008A1 publication Critical patent/WO2017139008A1/fr
Priority to US15/821,591 priority Critical patent/US10281327B2/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/02—Details
    • G01J3/0205—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows
    • G01J3/0208—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows using focussing or collimating elements, e.g. lenses or mirrors; performing aberration correction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/02—Details
    • G01J3/0205—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows
    • G01J3/021—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows using plane or convex mirrors, parallel phase plates, or particular reflectors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/12—Generating the spectrum; Monochromators
    • G01J3/14—Generating the spectrum; Monochromators using refracting elements, e.g. prisms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/12—Generating the spectrum; Monochromators
    • G01J3/18—Generating the spectrum; Monochromators using diffraction elements, e.g. grating
    • G01J3/1838—Holographic gratings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/28—Investigating the spectrum
    • G01J3/2803—Investigating the spectrum using photoelectric array detector
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/28—Investigating the spectrum
    • G01J3/2823—Imaging spectrometer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/0225—Shape of the cavity itself or of elements contained in or suspended over the cavity
    • G01J5/024—Special manufacturing steps or sacrificial layers or layer structures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14649—Infrared imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/12—Generating the spectrum; Monochromators
    • G01J3/18—Generating the spectrum; Monochromators using diffraction elements, e.g. grating
    • G01J2003/1842—Types of grating
    • G01J2003/1861—Transmission gratings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G01J3/28—Investigating the spectrum
    • G01J3/2823—Imaging spectrometer
    • G01J2003/2826—Multispectral imaging, e.g. filter imaging

Definitions

  • This application relates generally to apparatus for analyzing light, such as spectrometers. More particularly, the disclosed embodiments relate to apparatus for analyzing visible and shortwave infrared light.
  • Shortwave infrared provides information not available in visible light.
  • Collecting and analyzing both shortwave infrared light and visible light can enhance detection, recognition, identification, and further analysis of objects that emit, reflect, or absorb shortwave infrared and visible light.
  • some embodiments involve an apparatus for concurrently analyzing visible and shortwave infrared light.
  • the apparatus includes an input aperture for receiving light that includes a visible wavelength component and a shortwave infrared wavelength component; a first set of one or more lenses configured to relay light from the input aperture; one or more dispersive optical elements configured to disperse light, from the first set of one or more lenses, that includes the visible wavelength component and the shortwave infrared wavelength component; a second set of one or more lenses configured to focus the dispersed light, from the one or more dispersive optical elements, that includes the visible wavelength component and the shortwave infrared wavelength component; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals that include electrical signals indicating intensity of the visible wavelength component and electrical signals indicating intensity of the shortwave infrared wavelength component.
  • a method for concurrently analyzing visible and shortwave infrared light includes receiving light that includes a visible wavelength component and a shortwave infrared wavelength component with any apparatus described herein so that at least a portion of the visible wavelength component and at least a portion of the shortwave infrared wavelength component concurrently impinge on the array detector of the apparatus; and processing the electrical signals from the array detector to obtain the intensity of the visible wavelength component and the intensity of the shortwave infrared wavelength component.
  • a device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type.
  • the second semiconductor region is positioned above the first semiconductor region; and the first type is distinct from the second type.
  • the device includes a gate insulation layer positioned above the second semiconductor region; a gate positioned above the gate insulation layer; a source electrically coupled with the second semiconductor region; and a drain electrically coupled with the second semiconductor region.
  • the second semiconductor region has a top surface that is positioned toward the gate insulation layer, and the second semiconductor region has a bottom surface that is positioned opposite to the top surface of the second semiconductor region.
  • the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region.
  • the second semiconductor region also has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion.
  • the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
  • the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
  • a method of forming a device for sensing light includes forming a first semiconductor region, above a silicon substrate, doped with a dopant of a first type and forming a second semiconductor region, above the silicon substrate, doped with a dopant of a second type.
  • the second semiconductor region is positioned above the first semiconductor region.
  • the first type is distinct from the second type.
  • the method also includes forming a gate insulation layer above the second semiconductor region. One or more portions of the second semiconductor region are exposed from the gate insulation layer to define a source and a drain.
  • the second semiconductor region has a top surface that faces the gate insulation layer.
  • the second semiconductor region has a bottom surface that is opposite to the top surface of the second semiconductor region.
  • the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region.
  • the second semiconductor region has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion.
  • the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
  • the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
  • the method further includes forming a gate positioned above the gate insulation layer.
  • a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate using any of the above-described methods.
  • a sensor circuit includes a photo- sensing element, the photo-sensing element having a source terminal, a gate terminal, a drain terminal, and a body terminal.
  • the sensor circuit also includes a selection transistor having a source terminal, a gate terminal, and a drain terminal. The drain terminal of the selection transistor is electrically coupled with the source terminal of the photo-sensing element or the source terminal of the selection transistor is electrically coupled with the drain terminal of the photo-sensing element.
  • a converter circuit includes a first transimpedance amplifier having an input terminal electrically coupled with the source terminal or the drain terminal, of the selection transistor of a first sensor circuit that corresponds to any of the above-described sensor circuits, that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element.
  • the first transimpedance amplifier is configured to convert a current input from the photo-sensing element into a voltage output.
  • the converter circuit also includes a differential amplifier having two input terminals, a first input terminal of the two input terminals electrically coupled with the voltage output of the first transimpedance amplifier and a second input terminal of the two input terminals electrically coupled with a voltage source that is configured to provide a voltage corresponding to a base current provided by the photo- sensing element.
  • the differential amplifier is configured to output a voltage based on a voltage difference between the voltage output and the voltage provided by the voltage source.
  • an image sensor device includes an array of sensors.
  • a respective sensor in the array of sensors includes any of the above- described sensor circuits.
  • a method includes exposing the photo- sensing element of any of the above-described sensor circuits. The method also includes providing a fixed voltage to the source terminal of the photo-sensing element; and measuring a drain current of the photo-sensing element.
  • a method includes exposing the array of sensors of any of the above-described image sensor devices to a pattern of light. The method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo-sensing element of the respective sensor; and measuring a drain current of the photo-sensing element.
  • described methods, devices, and apparatuses provide efficient, compact, and low-cost apparatuses in analyzing visible and shortwave infrared light. Such methods, devices, and apparatuses may complement or replace conventional methods, devices, and apparatuses for analyzing visible and shortwave infrared light.
  • Figure 1A is a partial cross-sectional view of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure IB is a partial cross-sectional view of the semiconductor optical sensor device illustrated in Figure 1 A, in accordance with some embodiments.
  • Figure 2A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 2B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated in Figure 2A, in accordance with some embodiments.
  • Figure 3 illustrates exemplary band diagrams in accordance with some embodiments.
  • Figure 4A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 4B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 5 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments.
  • Figure 6 illustrates an exemplary sensor circuit in accordance with some embodiments.
  • Figure 7 A illustrates an exemplary 3T-APS circuit in accordance with some embodiments.
  • Figure 7B illustrates an exemplary IT-MAPS circuit in accordance with some embodiments.
  • Figures 8A-8H illustrate exemplary sensor circuits in accordance with some embodiments.
  • Figures 9A-9C illustrate exemplary converter circuits in accordance with some embodiments.
  • Figure 10 illustrates an exemplary image sensor device in accordance with some embodiments.
  • Figures 11A-11E illustrate an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments.
  • Figures 12A-12E illustrate spectrometers in accordance with some embodiments.
  • CMOS complementary metal-oxide- semiconductor
  • charge modulation devices suffer from dark current and a trade-off between a quantum efficiency and a weak channel modulation.
  • Infrared sensors made of Indium Gallium Arsenide (InGaAs) and Germanium
  • Ga suffer from high dark current.
  • Many InGaAs and sensors are cooled to operate in a low temperature (e.g., -70 °C).
  • cooling is disadvantageous for many reasons, such as cost of the cooling unit, an increased size of the device due to the cooling unit, an increased operation time for cooling the device, and increased power consumption for cooling the device.
  • traditional instruments for analyzing both visible light and infrared light typically have separate detectors and separate optical components for different wavelength ranges.
  • such instruments include visible light detectors and associated optical components for analyzing visible light and separately include infrared light detectors and associated optical components for analyzing infrared light.
  • Such instruments are bulky, heavy, and expensive, which has limited applications of traditional instruments.
  • Devices, apparatuses, and methods that address the above problems are described herein.
  • apparatuses that include array detectors configured for converting both visible light and shortwave infrared light to electrical signals
  • compact, light, and reduced-cost devices and apparatuses can be provided for analyzing visible and shortwave infrared light.
  • such devices and apparatuses are used for hyperspectral imaging, thereby allowing spatial analysis of collected light (e.g., analysis of spatial distribution of collected light).
  • first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • a first semiconductor region could be termed a second semiconductor region, and, similarly, a second semiconductor region could be termed a first semiconductor region, without departing from the scope of the claims.
  • the first semiconductor and the second semiconductor region are both semiconductor regions, but they are not the same semiconductor regions.
  • Figure 1A is a partial cross-sectional view of a semiconductor optical sensor device 100 in accordance with some embodiments.
  • the device 100 is called a gate-controlled charge modulated device (GCMD) (also called herein a gate-controlled charge modulation device).
  • GCMD gate-controlled charge modulated device
  • the device 100 includes a first semiconductor region 104 doped with a dopant of a first type (e.g., an n-type semiconductor, such as phosphorus or arsenic) and a second semiconductor region 106 doped with a dopant of a second type (e.g., a high concentration of a p-type semiconductor, such as boron, which is often indicated using a p+ symbol).
  • the second semiconductor region 106 is positioned above the first semiconductor region 104.
  • the first type e.g., n-type
  • the second semiconductor region 106 is positioned over the first semiconductor region 104.
  • the device includes a gate insulation layer 110 positioned above the second semiconductor region 106 and a gate 112 positioned above the gate insulation layer 110.
  • the gate insulation layer 110 is positioned over the second semiconductor region 106.
  • the gate insulation layer 110 is in contact with the second semiconductor region 106.
  • the gate 112 positioned over the gate insulation layer 110.
  • the gate 112 is in contact with the gate insulation layer 110.
  • the device also includes a source 114 electrically coupled with the second semiconductor region 106 and a drain 116 electrically coupled with the second semiconductor region 106.
  • the second semiconductor region 106 has a top surface 120 that is positioned toward the gate insulation layer 110.
  • the second semiconductor region 106 also has a bottom surface 122 that is positioned opposite to the top surface 120 of the second semiconductor region 106.
  • the second semiconductor region 106 has an upper portion 124 that includes the top surface 120 of the second semiconductor region 106.
  • the second semiconductor region 106 also has a lower portion 126 that includes the bottom surface 122 of the second semiconductor region 106.
  • the lower portion 126 is mutually exclusive with the upper portion 124.
  • the upper portion 124 and the lower portion 126 refer to different portions of the second semiconductor region 106. Thus, in some embodiments, there is no physical separation of the upper portion 124 and the lower portion 126.
  • the lower portion 126 refers to a portion of the second semiconductor region 106 that is not the upper portion 124.
  • the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
  • the upper portion 124 has a uniform thickness from the source 114 to the drain 116.
  • the upper portion 124 and the lower portion 126 have a same thickness at a horizontal location directly below the gate 112.
  • the first type is an n-type and the second type is a p- type.
  • the first semiconductor region is doped with an n-type semiconductor and the source 114, the drain 116, and a channel between the source 114 and the drain 116 are doped with a p-type semiconductor, which is called a PMOS structure.
  • the first type is a p-type and the second type is an n- type.
  • the first semiconductor region is doped with a p-type semiconductor and the source 114, the drain 116, and a channel between the source 114 and the drain 116 are doped with an n-type semiconductor, which is called an MOS structure.
  • the first semiconductor region 104 includes germanium.
  • the second semiconductor region 106 includes germanium.
  • the direct band gap energy of germanium is around 0.8 eV at room temperature, which corresponds to a wavelength of 1550 nm.
  • the gate insulation layer 110 includes an oxide layer
  • the gate insulation layer 110 includes an oxynitride layer (e.g., SiON).
  • the gate insulation layer 110 includes a high- ⁇ dielectric material, such as Hf0 2 , HfSiO, or A1 2 0 3 .
  • the device includes a substrate insulation layer 108 positioned below the first semiconductor region 104.
  • the substrate insulation layer includes one or more of: Si0 2 , GeO x , ZrO x , HfO x , Si x N y , Si x O y N z , Ta x O y , Sr x O y and Al x O y .
  • the substrate insulation layer 108 includes a high- ⁇ dielectric material.
  • the first semiconductor region 104 is positioned over the substrate insulation layer 108.
  • the first semiconductor region 104 is in contact with the substrate insulation layer 108.
  • the substrate insulation layer 108 is positioned over the substrate 102 (e.g., a silicon substrate). In some embodiments, the substrate insulation layer 108 is in contact with the substrate 102.
  • the device includes a third semiconductor region 108 that includes germanium doped with a dopant of the second type (e.g., p-type).
  • the third semiconductor region 108 is positioned below the first semiconductor region 104.
  • a doping concentration of the dopant of the second type in the second semiconductor region 106 is higher than a doping concentration of the dopant of the second type in the third semiconductor region 108.
  • the second semiconductor region 106 has a p+ doping (e.g., at a concentration of one dopant atom per ten thousand atoms or more) and the third semiconductor region 108 has a p doping (e.g., at a concentration of one dopant atom per hundred million atoms).
  • the device includes a silicon substrate 102.
  • the third semiconductor region 108, the first semiconductor region 104, and the second semiconductor region 106 are formed over the silicon substrate 102.
  • the gate 112 includes one or more of: polysilicon, amorphous silicon, silicon carbide, and metal. In some embodiments, the gate 112 consists of one or more of: polygermanium, amorphous germanium, polysilicon, amorphous silicon, silicon carbide, and metal.
  • the second semiconductor region 106 extends from the source 114 to the drain 116.
  • the first semiconductor region 104 extends from the source 114 to the drain 116.
  • the gate insulation layer 110 extends from the source
  • the second semiconductor region 106 has a thickness less than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 1 nm than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 5 nm than 50 nm. In some embodiments, the second semiconductor region 106 has a thickness between 50 nm than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 40 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 30 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 20 nm.
  • the second semiconductor region 106 has a thickness between 20 nm than 30 nm. In some embodiments, the second semiconductor region 106 has a thickness between 30 nm than 40 nm. In some embodiments, the second semiconductor region 106 has a thickness between 40 nm than 50 nm.
  • the first semiconductor region 104 has a thickness less than 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 1 nm and 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 5 nm and 500 nm. In some embodiments, the first semiconductor region 104 has a thickness between 500 nm and 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 500 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 300 nm.
  • the first semiconductor region 104 has a thickness between 10 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 100 nm.
  • Figure 1A also indicates plane AA upon which the view illustrated in Figure
  • Figure IB is a partial cross-sectional view of the semiconductor optical sensor device illustrated in Figure 1 A, in accordance with some embodiments.
  • the first semiconductor region 104 is in contact with both the upper portion 124 and the lower portion 126 of the second semiconductor region 106.
  • the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 at least at a location positioned under the gate 112.
  • the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 at least at a location positioned directly under the gate 112.
  • the first semiconductor region 104 is in contact with the top surface 120 of the second semiconductor region 106 at least on an edge of the top surface 120 of the second semiconductor region 106. In some embodiments, the first semiconductor region 104 is in contact with the top surface 120 of the second semiconductor region 106 at least on an edge of the top surface 120 of the second semiconductor region 106 at a location directly under the gate 112.
  • the second semiconductor region 106 has a first lateral surface (e.g., a combination of a lateral surface 128 of the upper portion 124 and a lateral surface 130 of the lower portion 126) that extends from the source 114 (Figure 1A) to the drain 116 ( Figure 1A) and is distinct from the top surface 120 and the bottom surface 122.
  • the second semiconductor region 106 has a second lateral surface (e.g., a combination of a lateral surface 132 of the upper portion 124 and a lateral surface 134 of the lower portion 126) that extends from the source 114 ( Figure 1 A) to the drain 116 ( Figure 1 A) and is distinct from the top surface 120 and the bottom surface 122.
  • the first lateral surface and the second lateral surface are located on opposite sides of the second semiconductor region 106.
  • the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 128 of the first lateral surface.
  • the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 132 of the second lateral surface.
  • the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 128 of the first lateral surface at a location directly under the gate 112 and the first semiconductor region 104 is also in contact with the upper portion 124 of the second semiconductor region 106 through a portion 132 of the second lateral surface at a location directly under the gate 112.
  • the lateral surface 128 of the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, the lateral surface 132 of the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, the lateral surface 128 of the upper portion 124 has a thickness less a thickness of the lateral surface 130 of the lower portion 126. In some embodiments, the lateral surface 132 of the upper portion 124 has a thickness less a thickness of the lateral surface 134 of the lower portion 126.
  • Figures 2A-2B are used below to illustrate operational principles of the semiconductor optical sensor device in accordance with some embodiments. However, Figures 2A-2B and the described principles are not intended to limit the scope of claims.
  • Figure 2A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments.
  • the first semiconductor region 104 is doped with an n-type semiconductor.
  • the second semiconductor region 106 is heavily doped with a p-type semiconductor.
  • the third semiconductor region 108 is doped with a p-type semiconductor. In some embodiments, the third semiconductor region 108 is lightly doped with the p-type semiconductor.
  • a potential well 202 is formed between the second semiconductor region 106 and the gate insulation layer 110. While the device (in particular, the first semiconductor region 104) is exposed to light, photo-generated carriers are generated. While voltage VG is applied to the gate 112, the photo-generated carriers migrate to the potential well 202.
  • Figure 2B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated in Figure 2A, in accordance with some embodiments.
  • Figure 2B is similar to Figure 2A. For brevity, the description of the same elements described above with respect to Figure IB is not repeated herein.
  • FIG. 2B the migration path of the photo-generated carriers to the potential well 202 located between the second semiconductor region 106 and the gate insulation layer 110 is indicated.
  • the photo-generated carriers get into the potential well 202 through lateral surfaces of second semiconductor region 106.
  • at least a portion of the photo-generated carriers directly pass through a bottom surface of the second semiconductor region 106 to reach the potential well 202. This is possible because the second semiconductor region 106 is thin and the barrier between the second semiconductor region 106 and the potential well 202 is low (e.g., less than band gap of Ge).
  • carrier recombination may take place in the second semiconductor region 106.
  • This direct contact between the first semiconductor region 104 and the potential well 202 significantly increases migration of the photo-generated carriers from the first semiconductor region 104 to the potential well 202.
  • a thick first semiconductor region 104 may be used for increasing the quantum efficiency, while the photo-generated carriers are effectively transported to the potential well 202 for increasing the on/off signal modulation.
  • the device In the absence of an exposure to light, the device would have a certain drain current (called herein I off ). However, when the device is exposed to light, the photo-generated carriers modulate the drain current (e.g., the drain current increases to I on ).
  • Figure 3 illustrates exemplary band diagrams in accordance with some embodiments. Although Figure 3 is used to illustrate operational principles of the semiconductor optical sensor device, Figure 3 and the described principles are not intended to limit the scope of claims.
  • the band diagrams in Figure 3 represent electron energy levels from the gate of the semiconductor optical sensor device to the substrate of the semiconductor optical sensor device.
  • a GCMD can be represented as having a small capacitance and a large capacitance connected around a channel.
  • the band diagram (a) represents that the device is in the off state.
  • the band diagram (b) represents that the incident light is absorbed in the substrate region, and carriers are photo-generated in the small capacitance. There is a quasi- Fermi level split in the buried hole channel and substrate.
  • the band diagram (c) represents that the photo-generated carriers from the low capacitance region are transferred to the large capacitance region (oxide-surface interface) automatically with a proper gate bias. The transferred photo-generated carriers in the oxide- surface interface reduce band bending between the source/drain and the buried hole channel, ultimately increasing the drain current.
  • the band of the channel with incident light is similar to the band with a lower gate voltage, which is represented in the band diagram (d).
  • Figures 4A and 4B are schematic diagrams illustrating a single channel configuration and a multi-channel configuration of a semiconductor optical sensor device.
  • the schematic diagrams in Figures 4A and 4B are based on top-down views of the semiconductor optical sensor device. However, it should be noted that the schematic diagrams in Figures 4A and 4B are used to represent relative sizes and positions of various elements and that the schematic diagrams in Figures 4A and 4B are not cross-sectional views.
  • Figure 4A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 4A illustrates that the device has a gate 406, a source 402, and a drain
  • the device also includes a channel 412 that extends from the source 402 to the drain 404.
  • the channel 412 is typically defined by the second semiconductor region.
  • the shape of the channel 412 is determined by a pattern of ion implantation in forming the second semiconductor region.
  • the source 402 has multiple contacts 408 with the channel 412 and the drain 404 has multiple contacts 410 with the channel 412.
  • Figure 4B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 4B is similar to Figure 4A except that the device has multiple channels
  • FIG. 4 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments.
  • Figure 5 illustrates that a plurality of semiconductor optical sensor devices
  • the sensor array may include more than two semiconductor optical sensor devices.
  • the sensor array includes a two-dimensional array of semiconductor optical sensor devices.
  • Figure 5 also illustrates that vias 506 are formed to connect the gate 112, the source, and the drain of the devices 502-1 and 502-2.
  • the plurality of devices (e.g., devices 502-1 and 502-2) has the first semiconductor region 104 on a common plane.
  • the first semiconductor region 104 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of the first semiconductor region 104).
  • the plurality of devices (e.g., devices 502-1 and 502-2) has the second semiconductor region 106 on a common plane.
  • the second semiconductor region 106 of the plurality of devices is formed concurrently (e.g., using ion implantation).
  • the plurality of devices (e.g., devices 502-1 and 502-2) has the third semiconductor region 108 on a common plane.
  • the third semiconductor region 108 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of germanium islands).
  • the plurality of devices is separated by one or more trenches.
  • the device 502-1 and the device 502-2 are separate by a trench.
  • the one or more trenches are filled with an insulator.
  • a trench is a shallow trench isolator.
  • the plurality of devices is positioned on separate germanium islands formed on the common silicon substrate 102.
  • third semiconductor regions 108 e.g., germanium islands
  • the rest of devices 502-1 and 502-2 are formed over the third semiconductor regions 108.
  • the sensor array includes a passivation layer over the plurality of devices.
  • the passivation layer 504 is positioned over the devices 502-1 and 502-2 in Figure 5.
  • the sensor array includes a passivation layer 504 between the plurality of devices.
  • the passivation layer 504 is positioned between the devices 502-1 and 502-2 in Figure 5.
  • Figure 6 illustrates an exemplary sensor circuit in accordance with some embodiments.
  • the sensor circuit includes a photo-sensing element 602.
  • the photo-sensing element 602 has a source terminal, a gate terminal, a drain terminal, and a body terminal.
  • the sensor circuit also includes a selection transistor 604 having a source terminal, a gate terminal, and a drain terminal.
  • the drain terminal of the selection transistor 604 is electrically coupled (e.g., at a point 606) with the source terminal of the photo-sensing element 602.
  • the source terminal of the selection transistor 604 is electrically coupled (e.g., at the point 606) with the drain terminal of the photo-sensing element 602.
  • the photo-sensing element is a GCMD (e.g., the device 100, Figure 1A).
  • the source terminal or the drain terminal, of the photo- sensing element 602, that is not electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is connected to a ground.
  • V 2 is connected to a ground.
  • the source terminal or the drain terminal, of the photo- sensing element 602, that is electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is not connected to a ground.
  • the point 606 is not connected to a ground.
  • the source terminal or the drain terminal, of the photo- sensing element 602, that is not electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is electrically coupled with a first voltage source.
  • V 2 is connected to the first voltage source.
  • the first voltage source provides a first fixed voltage, such as a voltage that is distinct from the ground.
  • the source terminal or the drain terminal, of the selection transistor 604, that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element 620 is electrically coupled with a second voltage source.
  • Vi is connected to the second voltage source.
  • the second voltage source provides a second fixed voltage.
  • the sensor circuit includes no more than two transistors, the two transistors including the selection transistor 604. In some embodiments, the sensor circuit also includes a gate control transistor that is electrically coupled to the gate of the photo-sensing element.
  • the sensor circuit includes no more than one transistor, the one transistor being the selection transistor 604.
  • the sensor circuit in Figure 6 is called herein one-transistor modified active- pixel sensor (IT-MAPS), because the sensor circuit includes a single transistor and a modified active-pixel sensor.
  • IT-MAPS one-transistor modified active-pixel sensor
  • 3T-APS three-transistor active-pixel sensor
  • Figure 7A illustrates an exemplary 3T-APS circuit in accordance with some embodiments.
  • the 3T-APS circuit includes a photo-sensing element (e.g., a photodiode) and three transistors: a reset transistor Mrst, a source-follower transistor Msf, and a select transistor Msel.
  • a photo-sensing element e.g., a photodiode
  • three transistors e.g., a reset transistor Mrst, a source-follower transistor Msf, and a select transistor Msel.
  • the reset transistor Mrst works as a reset switch.
  • Mrst receives a gate signal RST, which allows a reset voltage, Vrst, to be provided to the photo-sensing element to reset the photo-sensing element.
  • the source-follower transistor Msf acts as a buffer.
  • Msf receives an input (e.g., a voltage input) from the photo-sensing element, which allows a high voltage Vdd to be output to the source of the select transistor Msel.
  • the select transistor Msel works as a readout switch.
  • Msel receives a row selection signal ROW, which allows an output from the source-follower transistor Msf to be provided to a column line.
  • Figure 7B illustrates an exemplary IT-MAPS circuit in accordance with some embodiments.
  • the IT-MAPS circuit includes one photo-sensing element (e.g., GCMD) and one transistor, namely a select transistor Msel.
  • GCMD photo-sensing element
  • Msel select transistor
  • the select transistor Msel receives a row selection signal ROW, which allows a current from the column line to flow to an input of the photo-sensing element.
  • the row selection signal ROW provided to the select transistor Msel, allows a current from the photo-sensing element to flow to the column line.
  • the column line is set to a fixed voltage.
  • the IT-MAPS circuit does not require a reset switch, because photo-generated carriers stored in the GCMD dissipate in a short period of time (e.g., 0.1 second).
  • MAPS circuit illustrated in Figure 7B shows that the IT-MAPS circuit has a much smaller size than the 3T-APS circuit.
  • a IT-MAPS circuit is more cost advantageous than a 3T- APS circuit made of a same material.
  • more IT-MAPS circuits can be placed on a same area of a die than 3T-APS circuits, thereby increasing a number of pixels on the die.
  • Figures 8A-8H illustrate exemplary sensor circuits in accordance with some embodiments.
  • a switch symbol represents a select transistor.
  • Figures 8A-8D illustrate exemplary sensor circuits that include a PMOS-type
  • the gate of the GCMD is connected to a ground VG, and the drain of the GCMD is connected to a low voltage source Vi (e.g., ground).
  • the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, cons t anc-
  • the body is connected to a high voltage source V DD -
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the drain of the GCMD is connected to a low voltage source Vi (e.g., ground).
  • the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V const ant2- In some embodiments, the body is connected to a high voltage source V DD .
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the source of the GCMD is connected to a high voltage source V DD -
  • the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, constanc-
  • the body is connected to a high voltage source V DD 2-
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the source of the GCMD is connected to a high voltage source V DD -
  • the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, Viable-
  • the body is connected to a high voltage source V DD 2-
  • Figures 8E-8H illustrate exemplary sensor circuits that include MOS type
  • the gate and the drain of the GCMD are connected to a high voltage source V DD -
  • the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V CO nstant2-
  • the body is connected to a ground.
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the drain of the GCMD is connected to a high voltage source V DD -
  • the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V CO nstant2-
  • the body is connected to a ground.
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the source of the GCMD is connected to a ground.
  • the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V CO nstant2- In some embodiments, the body is connected to a ground.
  • the gate of the GCMD is connected to a fixed voltage V CO nstanti, and the source of the GCMD is connected to a ground.
  • the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, V var i ab i e - In some embodiments, the body is connected to a ground.
  • the drain current in the GCMD changes depending on whether the GCMD is exposed to light.
  • the GCMD is modeled as a current source that provides I on when the GCMD is exposed to light and provide I 0ff when the GCMD is not exposed to light.
  • Figures 9A-9C illustrate exemplary converter circuits in accordance with some embodiments.
  • Figure 9A illustrates an exemplary converter circuit 902 in accordance with some embodiments.
  • the converter circuit 902 includes a first transimpedance amplifier 904 (e.g., an operational amplifier) that has an input terminal (e.g., an input terminal receiving IGC MD from the photo-sensing element, such as the GCMD) electrically coupled with the source terminal or the drain terminal of the selection transistor of a first sensor circuit (e.g., the sensor circuit in Figure 6), that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element (e.g., the terminal having a voltage Vi in Figure 6).
  • the first transimpedance amplifier 904 is configured to convert a current input (e.g., IGC MD ) from the photo-sensing element into a voltage output (e.g., Vtamp)-
  • the converter circuit 902 also includes a differential amplifier 906 having two input terminals.
  • a first input terminal of the two input terminals is electrically coupled with the voltage output (e.g., Vtamp) of the first transimpedance amplifier 904 and a second input terminal of the two input terminals is electrically coupled with a voltage source that is configured to provide a voltage (e.g., V B AS E ) corresponding to a base current provided by the photo-sensing element.
  • the differential amplifier is configured to output a voltage (e.g., damp) based on a voltage difference between the voltage output (e.g., Vtamp) and the voltage provided by the voltage source (e.g., V B AS E )-
  • the differential amplifier 906 includes an operational amplifier.
  • the differential amplifier 906 includes a transistor long tailed pair.
  • the converter circuit 922 includes an analog-to-digital converter 908 electrically coupled to an output of the differential amplifier 906 (e.g., Vtamp), the analog-to-digital converter configured to convert the output (e.g., a voltage output) of the differential amplifier 906 (e.g., Vtamp) into a digital signal.
  • Figure 9B illustrates an exemplary converter circuit 912 in accordance with some embodiments.
  • the converter circuit 912 is similar to the converter circuit 902 illustrated in Figure 9A. Some of the features described with respect to Figure 9A are applicable to the converter circuit 912. For brevity, the description of such features is not repeated herein.
  • Figure 9B illustrates that, in some embodiments, the first transimpedance amplifier 904 in the converter circuit 912 includes an operational amplifier 910.
  • the operational amplifier 910 has a non-inverting input terminal that is electrically coupled with the source terminal or the drain terminal of the selection transistor of the first sensor circuit (E.g., the terminal having a voltage Vi in Figure 6).
  • the operational amplifier 910 also has an inverting input terminal that is electrically coupled with a reference voltage source that provides a reference voltage V REF -
  • the operational amplifier 910 has an output terminal, and a resistor with a resistance value R is electrically coupled to the non-inverting input terminal on a first end of the resistor and to the output terminal on the second end, opposite to the first end, of the resistor.
  • V t am p the voltage output V t am p is determined as follows:
  • Vtamp REF + R ⁇ IGCMD
  • the current from the GCMD can be modeled as follows:
  • IGCMD I 0 ff (no light)
  • IGCMD ⁇ + I 0 ff (light)
  • the base current corresponds to a current provided by the photo-sensing element while the photo-sensing element receives substantially no light (e.g., I 0ff ).
  • I 0ff is converted by the first transimpedance amplifier 904
  • V B AS E is determined as follows:
  • Vtamp - VBASE R ⁇ ⁇
  • V d am p of the differential amplifier 906 is as follows:
  • Vdamp A ⁇ R ⁇ ⁇ ⁇
  • A is a differential gain of the differential amplifier 906.
  • the differential gain is one of: one, two, three, five, ten, twenty, fifty, and one hundred.
  • Figure 9B also illustrates that, in some embodiments, the voltage source is a digital-to-analog converter (DAC) 916.
  • the DAC 916 is configured to provide VBASE.
  • Figure 9C illustrates an exemplary converter circuit 922 in accordance with some embodiments.
  • the converter circuit 922 is similar to the converter circuit 902 illustrated in Figure 9 A and the converter circuit 912 illustrated in Figure 9B. Some of the features described with respect to Figures 9A and 9B are applicable to the converter circuit 922.
  • the converter circuit 922 includes the digital-to- analog converter 916.
  • the first transimpedance amplifier 904 includes an operational amplifier 910. For brevity, the description of such features is not repeated herein.
  • Figure 9C illustrates that the voltage source (that provides VBASE) is a second transimpedance amplifier 914 having an input terminal electrically coupled with a second sensor circuit that is distinct from the first sensor circuit.
  • the input terminal of the second transimpedance amplifier 914 is electrically coupled with the source terminal or the drain terminal of the selection transistor of the second sensor circuit.
  • the photo-sensing element of the second sensor circuit is optically covered so that the photo-sensing element of the second sensor circuit is prevented from receiving light.
  • the second sensor circuit provides Ioff to the second transimpedance amplifier 914.
  • the second transimpedance amplifier 914 converts Ioff to VBASE.
  • the second transimpedance amplifier 914 includes an operational amplifier.
  • the first transimpedance amplifier 904 is configured to electrically couple with a respective sensor circuit of a plurality of sensor circuits through a multiplexer.
  • the converter circuit 922 is coupled to a multiplexer 916.
  • the multiplexer receives a column address to select one of a plurality of column lines. Each column line is connected to multiple sensor circuits, each having a selection transistor that receives a ROW signal. Thus, based on a column address and a ROW signal, one sensor circuit in a two-dimensional array of sensor circuits is selected, and a current output from the selected sensor circuit is provided to the first transimpedance amplifier 904 through the multiplexer 916.
  • a converter circuit may include a subset of the features described in Figures 9A-9C (e.g., the converter circuit 922 may be coupled with the multiplexer 916 without having the second transimpedance amplifier 914). In some embodiments, a converter circuit includes additional features not described with respect to Figures 9A-9C.
  • Figure 10 illustrates an exemplary image sensor device in accordance with some embodiments.
  • the image sensor device includes an array of sensors.
  • a respective sensor in the array of sensors includes a sensor circuit (e.g., Figures 8A-8H).
  • the image sensor device includes a converter circuit
  • the array of sensors includes multiple rows of sensors
  • gate terminals of selection transistors are electrically coupled to a common selection line.
  • gate terminals of sensor circuits in a top row are electrically coupled to a same signal line.
  • the array of sensors includes multiple columns of sensors (e.g., at least three columns of sensors are illustrated in Figure 10).
  • sensors in a respective column one of source terminals or drain terminals of selection transistors (i.e., either the source terminals of the selection transistors or the drain terminals of the selection transistors) are electrically coupled to a common column line.
  • the drain terminals of the selection transistors in a left column of sensors are electrically coupled to a same column line.
  • Figures 11 A-l IE illustrates an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments.
  • Figure 11A illustrates forming the semiconductor optical sensor device includes forming a third semiconductor region 108 on a silicon substrate 102.
  • the third semiconductor region 108 is epitaxially grown on the substrate 102.
  • Figure 11B illustrates forming a first semiconductor region 104, above the silicon substrate 102, doped with a dopant of a first type.
  • the first semiconductor region 104 is formed by epitaxially growing the first semiconductor region 104.
  • the first semiconductor region 104 is doped in-situ with the dopant of the first type (e.g., n-type) while the first semiconductor region 104 is grown.
  • the dopant of the first type e.g., n-type
  • the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process or a gas phase diffusion process. In some embodiments, the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process. In some embodiments, the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using a gas phase diffusion process.
  • Figure 11C illustrates forming a second semiconductor region 106, above the silicon substrate 102, doped with a dopant of a second type.
  • the second semiconductor region 106 is positioned above the first semiconductor region 104.
  • the first type e.g., n-type
  • the second type e.g., p-type
  • the second semiconductor region 106 is formed by epitaxially growing the second semiconductor region 106.
  • the second semiconductor region 106 is doped in-situ with the dopant of the second type (e.g., p-type, and in particular, p+) while the second semiconductor region 106 is grown.
  • the dopant of the second type e.g., p-type, and in particular, p+
  • the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process or a gas phase diffusion process. In some embodiments, the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process. In some embodiments, the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using a gas phase diffusion process.
  • the dopant of the second type e.g., p-type, and in particular, p+
  • the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process.
  • the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using an ion implantation process.
  • the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using a gas phase diffusion process.
  • the dopant of the second type e.g., p-type, and in particular, p+
  • Figure 11D illustrates forming a gate insulation layer 110 above the second semiconductor region 106.
  • One or more portions of the second semiconductor region 106 are exposed from the gate insulation layer 110 to define a source and a drain.
  • the gate insulation layer 110 is pattern etched (e.g., using a mask) to expose the source and the drain.
  • the second semiconductor region 106 has a top surface that faces the gate insulation layer 110.
  • the second semiconductor region 106 has a bottom surface that is opposite to the top surface of the second semiconductor region 106.
  • the second semiconductor region 106 has an upper portion that includes the top surface of the second semiconductor region 106.
  • the second semiconductor region 106 has a lower portion that includes the bottom surface of the second semiconductor region 106 and is mutually exclusive with the upper portion.
  • the first semiconductor region 104 is in contact with both the upper portion and the lower portion of the second semiconductor region 106.
  • the first semiconductor region 104 is in contact with the upper portion of the second semiconductor region 106 at least at a location positioned under the gate 112.
  • Figure HE illustrates forming a gate 112 positioned above the gate insulation layer 110.
  • a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate. For example, third semiconductor regions of multiple devices may be formed concurrently in a single epitaxial growth process. Subsequently, first semiconductor regions of the multiple devices may be formed concurrently in a single epitaxial growth process. Thereafter, second semiconductor regions of the multiple devices may be formed concurrently in a single ion implantation process. Similarly, gate insulation layers of the multiple devices may be formed concurrently, and gates of the multiple devices may be formed concurrently.
  • a method for sensing light includes exposing a photo-sensing element (e.g., GCMD in Figure 6) to the light.
  • a photo-sensing element e.g., GCMD in Figure 6
  • the method also includes providing a fixed voltage to the source terminal of the photo-sensing element (e.g., by applying a fixed voltage V 1 and applying V R to the selection transistor 604 ( Figure 6). Based on an intensity of light on the GCMD, a drain current of the GCMD changes.
  • the method includes determining an intensity of the light based on the drain current of the photo-sensing element (e.g., GCMD).
  • a change in the drain current indicates whether light is detected by the photo-sensing element.
  • measuring the drain current includes converting the drain current to a voltage signal (e.g., converting the drain current IGC MD to Vtamp, Figure 9A).
  • converting the drain current to the voltage signal includes using a transimpedance amplifier (e.g., transimpedance amplifier 904, Figure 9A) to convert the drain current to the voltage signal.
  • a transimpedance amplifier e.g., transimpedance amplifier 904, Figure 9A
  • measuring the drain current includes using any converter circuit described herein (e.g., Figures 9A-9C).
  • the method includes activating the selection transistor of the sensor circuit (e.g., the selection transistor 604, Figure 6). Activating the selection transistor allows a drain current to flow through the selection transistor, thereby allowing a measurement of the drain current.
  • the selection transistor of the sensor circuit e.g., the selection transistor 604, Figure 6
  • the fixed voltage is provided to the source terminal of the photo-sensing element prior to exposing the photo-sensing element to light.
  • the selection transistor 604 is activated before exposing the photo-sensing element 602 to light.
  • the fixed voltage is provided to the source terminal of the photo-sensing element subsequent to exposing the photo-sensing element to light.
  • the selection transistor 604 is activated after exposing the photo-sensing element 602 to light.
  • a method for detecting an optical image includes exposing any array of sensors described herein (e.g., Figure 10) to a pattern of light.
  • the method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo- sensing element of the respective image sensor.
  • a selection transistor e.g., the selection transistor 604, Figure 6
  • the respective sensor is activated to provide the respective voltage, thereby allowing a measurement of a drain current of the respective sensor.
  • the method further includes measuring a drain current of the photo-sensing element (e.g., the photo-sensing element 602).
  • the source terminals of the photo-sensing elements in the array of sensors concurrently receive respective voltages.
  • respective voltages are concurrently applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same row) for a concurrent reading of the multiple photo-sensing elements.
  • the source terminals of the photo-sensing elements in the array of sensors sequentially receive respective voltages.
  • respective voltages are sequentially applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same column) for sequential reading of the multiple photo-sensing elements.
  • the source terminals of photo-sensing elements in the array of sensors receive a same voltage.
  • the drain currents of the photo-sensing elements in the array of sensors are measured in batches.
  • the drain currents of photo-sensing elements in a same row are measured in a batch (e.g., as a set).
  • the drain currents of the photo-sensing elements in the array of sensors are concurrently measured.
  • the drain currents of the photo- sensing elements in a same row are concurrently measured.
  • the drain currents of the photo-sensing elements in the array of sensors are sequentially measured. For example, the drain currents of the photo- sensing elements in a same column are concurrently measured.
  • Figures 12A-12E illustrate spectrometers in accordance with some embodiments.
  • spectrometers include input aperture 1106 for receiving light that includes a visible wavelength component (e.g., light having a visible wavelength, such as 600 nm) and shortwave infrared wavelength component (e.g., light having a shortwave infrared wavelength, such as 1500 nm).
  • a visible wavelength component e.g., light having a visible wavelength, such as 600 nm
  • shortwave infrared wavelength component e.g., light having a shortwave infrared wavelength, such as 1500 nm
  • the light received by input aperture 1106 has a continuous spectrum ranging from a visible wavelength to a shortwave infrared wavelength (e.g., light from 600 nm to 1500 nm).
  • the light received by input aperture 1106 has discrete peaks in one or more visible wavelengths and/or one or more shortwave infrared wavelengths.
  • input aperture 1106 includes a substrate with a first portion of the substrate coated to block transmission of the light received on the input aperture and a second portion, distinct from the first portion, of the substrate configured to allow transmission of at least a portion of the light received on the input aperture (e.g., the second portion does not overlap with the first portion).
  • input aperture 1106 includes a glass substrate.
  • input aperture 1106 includes a sapphire substrate.
  • input aperture 1106 includes a plastic substrate (e.g., polycarbonate substrate) that is optically transparent to visible and shortwave infrared light.
  • the coating is located on a surface, of the substrate, facing the incoming light (e.g., light from a sample or a target object). In some embodiments, the coating is located on a surface, of the substrate, facing away from the incoming light.
  • input aperture 1106 is a linear aperture (e.g., an entrance slit). Input aperture 1106 is configured to transmit both the visible wavelength component and the shortwave infrared wavelength component. For example, input aperture 1106 is transparent to both the visible wavelength component and the shortwave infrared wavelength component (e.g., input aperture 1106 has a transmittance of at least 60% in the visible and shortwave infrared wavelength range). In some embodiments, input aperture 1106 is configured to reduce transmission of light in a particular wavelength range (e.g., input aperture 1106 is configured to reduce transmission of ultraviolet light).
  • the spectrometers also include first set 1107 of one or more lenses configured to relay light from the input aperture.
  • first set 1107 of one or more lenses is configured to collimate the light from the input aperture.
  • first set 1107 of one or more lenses includes a doublet that is configured to reduce one or more aberrations (e.g., chromatic aberration) in visible and shortwave infrared wavelengths.
  • first set 1107 of one or more lenses includes a triplet or any other combination of multiple lenses (e.g., multiple lenses cemented together or multiple separate lenses).
  • First set 1107 of one or more lenses is configured to transmit both the visible wavelength components and the shortwave infrared wavelength component.
  • the spectrometers further include one or more dispersive optical elements, such as dispersive optical element 1108 (e.g., a prism), configured to disperse light from first set 1107 of one or more lenses.
  • the light from first set 1107 of one or more lenses includes the visible wavelength component and the shortwave infrared wavelength component.
  • the one or more dispersive optical elements include one or more transmission dispersive optical elements (e.g., a volume holographic transmission grating). The one or more dispersive optical elements are configured to transmit both the visible wavelength components and the shortwave infrared wavelength component.
  • the one or more dispersive optical elements include one or more prisms.
  • Diffraction gratings are configured to disperse light multiple orders, and light of a particular wavelength is dispersed into multiple directions.
  • two different wavelength components can be dispersed into a same direction (e.g., a second order diffraction of 500 nm light and a first order diffraction of 1000 nm light overlap; and similarly, a third order diffraction of 500 nm light, a second order diffraction of 750 nm light, and a first order diffraction of 1500 nm light overlap). This limits a wavelength range that can be concurrently analyzed by the spectrometer.
  • the Prisms do not disperse light of a particular wavelength into multiple directions. Thus, the use of a prism can significantly increase the wavelength range of light that can be concurrently analyzed.
  • the one or more prisms include one or more equilateral prisms.
  • the spectrometers include second set 1109 of one or more lenses configured to focus the dispersed light.
  • second set 1109 of one or more lenses includes a doublet that is configured to reduce one or more aberrations (e.g., chromatic aberration) in visible and shortwave infrared wavelengths.
  • second set 1109 of one or more lenses includes a triplet or any other combination of multiple lenses (e.g., multiple lenses cemented together or multiple separate lenses).
  • Second set 1109 of one or more lenses is configured to transmit both the visible wavelength components and the shortwave infrared wavelength component.
  • the light focused by second set 1109 of one or more lenses includes light of a wavelength range from 600 nm to 1500 nm.
  • the spectrometers include array detector 1112 configured for converting the light from second set 1109 of one or more lenses to electrical signals (e.g., a two-dimensional array of gate-controlled charge modulation devices described herein, such as the image sensor device illustrated in Figure 10).
  • the electrical signals include electrical signals indicating intensity of the visible wavelength component and electrical signals indicating intensity of the shortwave infrared wavelength component.
  • array detector 1112 includes a contiguous detector array that is capable of converting the visible wavelength component and the shortwave infrared wavelength component to electrical signals (e.g., a single detector array generates both electrical signals indicating the intensity of the visible wavelength component and electrical signals indicating the intensity of the shortwave infrared wavelength component).
  • the contiguous detector array has a quantum efficiency of at least 20% for light of 1500 nm wavelength. In some embodiments, the contiguous detector array has a quantum efficiency of at least 20% for light of 600 nm wavelength. In some embodiments, the contiguous detector array is a germanium detector array.
  • the contiguous detector array includes a two- dimensional array of devices for sensing light (e.g., 100 x 100 array of devices for sensing light). In some embodiments, each device of the two-dimensional array of devices is a charge modulation device. In some embodiments, each device of the two-dimensional array of devices is a charge modulation device. In some embodiments, the contiguous detector array includes a one-dimensional array of devices for sensing light (e.g., 100 x 1 array of devices for sensing light).
  • array detector 1112 is a two-dimensional array of devices for sensing light.
  • the spectrometer can be used for hyperspectral imaging.
  • array detector 1112 is positioned parallel to a plane defined by optical paths from input aperture 1106 to second set 1 109 of one or more lenses (e.g., a plane that encompasses an optical path from input aperture 1106 to first set 1107 of one or more lenses, an optical path from first set 1107 of one or more lenses to dispersive optical element 1108, an optical path from dispersive optical element 1108 to second set 1109 of one or more lenses).
  • a plane defined by optical paths from input aperture 1106 to second set 1 109 of one or more lenses e.g., a plane that encompasses an optical path from input aperture 1106 to first set 1107 of one or more lenses, an optical path from first set 1107 of one or more lenses to dispersive optical element 1108, an optical path from dispersive optical element 1108 to second set 1109 of one or more lenses.
  • array detector 1112 is substantially parallel to any of the optical paths from input aperture 1106 to second set 1109 of one or more lenses (e.g., an angle defined by a surface normal of array detector 1112 and a respective optical path is more than, for example, 45 degrees, 60 degrees, or 75 degrees).
  • array detector 1112 is laid down flat on a bottom of the spectrometer. This further reduces a size of the spectrometer.
  • the spectrometers optionally include detection window 1101, one or more light sources (e.g., visible light source 1102 and/or infrared light source 1103) for
  • third set 1104 of one or more lenses for focusing light from an object (or a sample) onto the input aperture.
  • third set 1104 of one or more lenses focus diffuse reflection from the object onto the input aperture.
  • Detection window 1101 and third set 1104 of one or more lenses are configured to transmit both the visible wavelength components and the shortwave infrared wavelength component.
  • the one or more light sources include a broadband light source configured to concurrently emit light that corresponds to the visible wavelength component and light that corresponds to the shortwave infrared wavelength component.
  • the one or more light sources include one or more visible light sources (e.g., visible light source 1102) configured to emit light that corresponds to the visible wavelength component and one or more shortwave infrared light sources (e.g., shortwave infrared light source 1103) configured to emit light that corresponds to the shortwave infrared wavelength component.
  • visible light source 1102 configured to emit light that corresponds to the visible wavelength component
  • shortwave infrared light sources e.g., shortwave infrared light source 1103
  • the spectrometers include one or more mirrors for directing light.
  • the spectrometer includes mirror 1110 configured to reflect the light from second set 1109 of one or more lenses toward array detector 1112.
  • an optical axis of light from mirror 1110 is substantially parallel (e.g., an angle formed by the optical axis of light from mirror 1110 and the optical axis between first set 1107 of one or more lenses and the one or more dispersive optical elements is 30 degrees or less) to an optical axis between first set 1107 of one or more lenses and the one or more dispersive optical elements (e.g., dispersive optical element 1108).
  • the spectrometer includes mirror 1110 and mirror 1111 between second set 1109 of one or more lenses and array detector 1112.
  • Mirror 1110 is configured to relay light from second set 1109 of one or more lenses to mirror 1111.
  • mirror 1111 is configured to reflect the light from mirror 1110 by 90 degrees toward array detector 1112.
  • the spectrometer also includes mirror 1 105 for relaying light from third set 1104 of one or more lenses toward input aperture 1106.
  • the size of the entire spectrometer illustrated in Figure 12 A, including detector array 1112, is 4.3 cm in length by 3.3 cm in width by 0.7 cm in height, or smaller.
  • Figure 12B is a schematic diagram, in a perspective view, of the spectrometer shown in Figure 12 A.
  • FIG 12B additional components not shown in Figure 12A are also depicted.
  • one or more baffles located adjacent to visible light source 1102 and infrared light source 1103.
  • the spectrometer illustrated in Figure 12C is similar to the spectrometer illustrated in Figure 12A, except that input aperture 1106 is positioned between third set 1104 of one or more lenses and mirror 1105. Thus, mirror 1105 is configured to reflect the light from input aperture 106 toward first set 107 of one or more lenses.
  • the spectrometer illustrated in Figure 12D is similar to the spectrometers illustrated in Figures 12A and 12C except that mirrors 1105 and 1110 are not used. Instead, input aperture 1106 and first set 1107 of one or more lenses are linearly positioned (e.g., an optical axis of first set 1107 of one or more lenses is aligned with input aperture 1106).
  • the spectrometer includes one or more mirrors configured to reflect the light from the first set of one or more lenses toward the one or more dispersive optical elements so that the dispersed light from the one or more dispersive optical elements is substantially parallel to the light from the first set of one or more lenses (e.g., the light from the first set of one or more lenses and the dispersed light from the one or more dispersive optical elements form an angle that is less than 30 degrees, 20 degrees, 15 degrees, 10 degrees, or 5 degrees).
  • the spectrometer includes at least two mirrors configured to reflect the light from the first set of one or more lenses toward the one or more dispersive optical elements so that the dispersed light from the one or more dispersive optical elements is substantially parallel to the light from the first set of one or more lenses.
  • the spectrometer illustrated in Figure 12E is similar to the spectrometers illustrated in Figure 12D except that the spectrometer illustrated in Figure 12E includes mirrors 1113 and 1114 configured to reflect the light from first set 1107 of one or more lenses toward one or more dispersive optical elements 1108 so that the dispersed light from one or more dispersive optical elements 1108 is substantially parallel to the light from first set 1107 of one or more lenses.
  • the configuration shown in Figure 12E allows a compact spectrometer.
  • the size of the spectrometer shown in Figure 12E is 10 cm in length by 1.5 cm in width by 0.7 cm in height, or smaller.
  • the spectrometer includes one or more mirrors configured to reflect the light from the first set of one or more lenses toward the one or more dispersive optical elements so that the light from the second set of one or more lenses is substantially parallel to the light from the first set of one or more lenses (e.g., an optical axis of the first set of one or more lenses and an optical axis of the second set of one or more lenses form an angle that is less than 30 degrees, 20 degrees, 15 degrees, 10 degrees, or 5 degrees).
  • the spectrometer includes at least two mirrors configured to reflect the light from the first set of one or more lenses toward the one or more dispersive optical elements so that the light from the second set of one or more lenses is substantially parallel to the light from the first set of one or more lenses.
  • the spectrometer illustrated in Figure 12E includes mirrors 1113 and 1114 that reflect the light from first set 1107 of one or more lenses toward one or more dispersive optical elements 1108 so that the dispersed light from one or more dispersive optical elements 1108 is substantially parallel to the light from first set 1107 of one or more lenses.
  • a method for concurrently analyzing visible and shortwave infrared light includes receiving light that includes a visible wavelength component and a shortwave infrared wavelength component with any embodiment of the apparatus described above so that at least a portion of the visible wavelength component and at least a portion of the shortwave infrared wavelength component concurrently impinge on the array detector of the apparatus; and processing the electrical signals from the array detector to obtain the intensity of the visible wavelength component and the intensity of the shortwave infrared wavelength component.

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Abstract

L'invention concerne un appareil d'analyse de lumière visible et infrarouge à ondes courtes comprenant une ouverture d'entrée pour recevoir une lumière qui comprend une composante de longueur d'onde visible et une composante de longueur d'onde infrarouge à ondes courtes ; un premier ensemble d'une ou plusieurs lentilles conçues pour relayer la lumière provenant de l'ouverture d'entrée ; un ou plusieurs éléments optiques dispersifs conçus pour disperser la lumière venant du premier ensemble d'une ou plusieurs lentilles ; un second ensemble d'une ou plusieurs lentilles conçus pour focaliser la lumière dispersée venant du ou des éléments optiques dispersifs ; et un détecteur à réseau conçu pour convertir la lumière venant du second ensemble d'une ou plusieurs lentilles en signaux électriques qui comprennent des signaux électriques indiquant l'intensité de la composante de longueur d'onde visible et des signaux électriques indiquant l'intensité de la composante de longueur d'onde infrarouge à ondes courtes.
PCT/US2016/064585 2016-02-11 2016-12-02 Spectromètre visible-infrarouge à ondes courtes à large bande WO2017139008A1 (fr)

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