WO2017133478A1 - Procédé et horloge pour synchronisation temporelle - Google Patents

Procédé et horloge pour synchronisation temporelle Download PDF

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Publication number
WO2017133478A1
WO2017133478A1 PCT/CN2017/071738 CN2017071738W WO2017133478A1 WO 2017133478 A1 WO2017133478 A1 WO 2017133478A1 CN 2017071738 W CN2017071738 W CN 2017071738W WO 2017133478 A1 WO2017133478 A1 WO 2017133478A1
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Prior art keywords
clock
information
time
master
level
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PCT/CN2017/071738
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English (en)
Chinese (zh)
Inventor
吕京飞
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network

Definitions

  • the present invention relates to the field of communications, and more particularly to a method and clock for time synchronization.
  • each device has its own clock.
  • the device's clock needs to be synchronized.
  • the time deviation of the clocks of the two devices that need to communicate cannot exceed a certain range.
  • Clock synchronization includes frequency synchronization and time synchronization.
  • the two devices may be two base stations. One is to install a satellite antenna for each device, and the clock of the device is synchronized with the clock of the synchronous satellite in the air. The other is that each device's clock is synchronized to a common clock source through a transport network, enabling clock synchronization between the two devices.
  • the frequency synchronization path selection algorithm may be a Synchronization status message (SSM) algorithm defined by the International Telecommunication Union (ITU) G.781 and G.8264.
  • the time synchronization path selection algorithm may be the Best Master Clock Algorithm (BMCA) defined by the Institute of Electrical and Electronics Engineers (IEEE) 1588-2008 or the ITU G.8275.1 based on IEEE 1588-2008.
  • BMCA Best Master Clock Algorithm
  • IEEE Institute of Electrical and Electronics Engineers
  • A-BMCA Alternative Best Master Clock Algorithm
  • the existing SSM frequency synchronization algorithm may be an algorithm defined by ITU G.781 and G.8264.
  • the peer device (or the clock in the device) sends a message containing frequency level information to the local device (or the clock in the device).
  • the local device compares the frequency level of the peer device with the frequency class of the local device according to the received message, so that the device with the higher frequency class is used as the master clock. If the frequency levels are the same, you need to compare the configuration information to determine the master clock. For details, see Chapter 5.22 of ITU G.781.
  • the time synchronization path between the two clocks can be determined according to the prior art.
  • the time synchronization path between device A and device B can be determined according to the BMCA algorithm of IEEE 1588-2008 or the A-BMCA algorithm defined by ITU G.8275.1.
  • the time synchronization path between the device A and the device B is determined by comparing the configuration information of the device A and the device B. After device A uses device B as the master clock of device A, device A synchronizes to device B. Or, after device B uses device A as the master clock of device B, device B synchronizes to device A.
  • the method of comparing the configuration information of two clocks after determining the time grades of the two clocks may result in the selection of a better quality master clock. Or, it may be impossible to avoid selecting a poor quality master clock.
  • Embodiments of the present invention provide a method and clock for time synchronization, which can select a master clock with better quality. Or, avoid choosing a poor quality master clock.
  • a method for time synchronization comprising:
  • the first clock receives the first information and the second information sent by the second clock, where the first information is used to indicate a time level of the second clock, and the second information is used to indicate a frequency level of the second clock;
  • the first clock After determining that the time level of the first clock is equal to the time level of the second clock, the first clock compares the frequency level of the first clock with the frequency level of the second clock to obtain a first comparison result;
  • the first clock determines whether the second clock is used as the master clock of the first clock according to the first comparison result.
  • the embodiment of the present invention compares the frequency level of the clock by the same time level of the two clocks, and determines whether one clock is used as the master clock of the other clock according to the comparison result. That is to say, the factor of the frequency level is considered before the main clock is determined. Therefore, the above technical solution helps to select a higher quality master clock. Alternatively, the above technical solution helps to avoid selecting a lower quality master clock. After the master clock is determined from the master clock of the clock, the time synchronization path of the slave clock is also determined. Therefore, the above technical solution helps to establish a high quality time synchronization path. Alternatively, the above technical solution helps to avoid establishing a low quality time synchronization path.
  • a message message for time synchronization including time level information and frequency level information is mutually transmitted between the first clock and the second clock. Then, time tracking is performed. For example, the angle of the first clock is taken as an example.
  • the first clock will receive the time quality level of the second clock and the local device (first clock).
  • first clock tracks the time of the second clock, and conversely, when the time quality level of the first clock is higher than the second clock At the time quality level, the second clock tracks the time of the first clock.
  • the first clock will synchronize the frequency synchronization quality level of the first clock with the frequency synchronization quality level of the second clock. Comparing, obtaining the first comparison result; and determining, according to the comparison result, whether the second clock is used as the master clock of the first clock, that is, whether the time of the second clock is actually tracked according to the comparison result.
  • first information in the embodiment of the present invention may also be described as time level information, and the second information may also be described as frequency level information. Embodiments of the invention are not limited thereto.
  • the time synchronization according to the time level may adopt the A-BMCA algorithm defined in ITU G.8275.1 or the BMCA algorithm defined in IEEE 1588-2008, which will not be described in detail herein.
  • the first comparison result may indicate that the frequency level of the first clock is greater than, less than, or equal to the frequency level of the second clock.
  • Corresponding time tracking methods for these three cases are also different, which will be described separately below.
  • Determining, according to the first comparison result, whether the second clock is the master clock of the first clock, the first clock includes:
  • the first clock uses the second clock as the master clock of the first clock according to the first comparison result.
  • Determining, according to the first comparison result, whether the second clock is the master clock of the first clock, the first clock includes:
  • the first clock determines, according to the first comparison result, to avoid using the second clock as the master clock of the first clock.
  • the second clock needs to use the first clock as the master clock of the second clock.
  • the method further includes:
  • the second configuration information includes a priority level 1 of the large master clock of the second clock, a priority level 2 of the large master clock of the second clock, and the first At least one of the identity of the big master clock of the two clocks,
  • the first clock determines, according to the first comparison result, whether the second node is the master of the first node.
  • Clock including:
  • the first clock compares the first configuration information of the first clock with the second configuration information to obtain a second comparison result
  • the second clock Determining, according to the second comparison result, whether the second clock is the master clock of the first clock, where the first configuration information includes a priority 1 of the large master clock of the first clock, and the first clock At least one of the priority level 2 of the big master clock and the identity of the big master clock of the first clock.
  • the first clock also needs to compare the configuration information and perform time synchronization based on the comparison result.
  • the first clock compares the first configuration information with the second configuration information
  • the values of the same type are correspondingly compared, and the values of different types are not compared. For example, comparing the priority one of the big master clock of the first clock with the priority one of the big master clock of the second clock, the identity of the big master clock of the first clock and the identity of the big master clock of the second clock Do comparisons and so on.
  • the configuration information may include the priority of the big master clock, the main master. At least one of the priority of the clock, the identity of the major master clock, and the local priority of the port. Specifically, how to perform time synchronization according to the configuration information may refer to the two standards, and details are not described herein again.
  • time level information and the frequency level information in the embodiment of the present invention may be carried by a message, or may be carried by different messages, which is not limited by the embodiment of the present invention.
  • the first clock, the first clock and the second information sent by the second clock include:
  • the first clock receives a message for time synchronization sent by the second clock, the message including the first information and the first Two information.
  • the message is a notification Announce message
  • the second information of the second clock is carried in the reserved byte of the message header of the Announce message.
  • the second information of the second clock is carried in a reserved byte of the message field of the Announce message.
  • the second information of the second clock is carried in a type length value TLV field in the Announce message.
  • the method further includes:
  • the first clock stores the second information of the second clock in a clock quality clockQuality data set.
  • the second information of the second clock is sent to the third clock.
  • the clock quality data set may be a clock quality data set defined by a precision time protocol PTP.
  • the PTP may be IEEE 1588v1 or IEEE 1588-2008.
  • the frequency level information of the second clock is stored in the first clock local clockQuality data set, and then the synchronization is determined, when the first clock determines the tracking.
  • the frequency level information of the second clock is retained in the local clockQuality data set of the first clock, and when the first clock is time synchronized with the third clock, the third clock is sent to the third clock.
  • the frequency level information of the second clock is used to trigger the third clock to perform time synchronization processing according to the frequency level information of the second clock.
  • the frequency level information of the second clock is deleted from the local clockQuality data set of the first clock, and when the first clock is time synchronized with the third clock, Transmitting the frequency level information of the first clock to the third clock to trigger the third clock to perform time synchronization processing according to the frequency level information of the first clock.
  • the first information includes: a level of a large master clock of the second clock, an accuracy of a large master clock of the second clock, and At least one of variance values of time offsets of the large master clock of the second clock.
  • a first clock for time synchronization is provided, the first clock being capable of implementing any of the first aspect and implementations thereof, the operation of each of the first clocks and/or
  • the functions are respectively used for the first aspect of the implementation and the corresponding method features in the implementation manner, and are not described herein for brevity.
  • an apparatus for time synchronization comprising a memory and a processor storing instructions, wherein the processor executes the instructions to perform any of the first aspect and various implementations thereof A method for time synchronization.
  • a processing apparatus is provided that is applied to a communication system.
  • the processing device can be one or more processors or chips. In other possible cases, the processing device may also be a physical device or a virtual device in a communication system.
  • the processing device is configured to perform any of the methods provided above for the time synchronization provided by the first aspect and various implementations thereof.
  • a computer program product comprising: computer program code,
  • the computer program code When the computer program code is executed by a computing unit, processing unit or processor of the communication device, the communication device is caused to perform any of the methods described above for the first aspect and its various implementations for time synchronization.
  • a computer readable storage medium in a sixth aspect, storing a program causing the communication device to perform any of the first aspect and various implementations thereof described above for time synchronization method.
  • a first apparatus comprising a first clock as provided by the second aspect.
  • the first device may be a base station, a terminal or a transmission node.
  • a network system comprising a first device and a second device, the first device comprising a first clock provided by the second aspect, and the second device comprising a second clock involved in the second aspect.
  • the clock refers to a node capable of transmitting or receiving a message for time synchronization.
  • the message for time synchronization may be an accurate clock protocol message as defined by IEEE 1588-2008.
  • the master clock is a type of clock.
  • the master clock is a source of time.
  • the slave clock can be synchronized to the source of the time.
  • the time precision of the clock represents the error of the clock's time relative to the standard time source.
  • the higher the time accuracy of the clock the smaller the error of the clock's time relative to the standard time source.
  • the frequency accuracy of the clock represents the magnitude of the error of the clock's frequency relative to the standard frequency source. The higher the frequency accuracy of the clock, the smaller the error of the clock's frequency relative to the standard frequency source.
  • FIG. 1 is a schematic diagram of a clock synchronization system in accordance with an embodiment of the present invention.
  • FIG. 2 is a flowchart of a BMCA algorithm according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of an A-BMCA algorithm according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing an example of time synchronization provided by an embodiment of the present invention.
  • Figure 5 is a schematic flow diagram of a method for time synchronization in accordance with one embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of a method for time synchronization in accordance with another embodiment of the present invention.
  • FIG. 7 is a schematic flow chart of a method for time synchronization in accordance with another embodiment of the present invention.
  • FIG. 8 is a schematic block diagram of a clock for time synchronization, in accordance with one embodiment of the present invention.
  • FIG. 9 is a schematic block diagram of a clock for time synchronization, in accordance with one embodiment of the present invention.
  • Embodiments of the present invention are applicable to various communication systems. Therefore, the application scenario of the technical solution provided by the embodiment of the present invention is not limited to a specific communication system.
  • the communication system used in the application scenario of the technical solution may be a Global System of Mobile communication ("GSM”) system, a Code Division Multiple Access (“CDMA”) system, and a wideband code division multiple access.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • LTE frequency division duplex The Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 is a schematic diagram of a clock synchronization system in accordance with an embodiment of the present invention.
  • the system shown in Figure 1 includes a base station, a base station controller, a transmission node, and a common clock source.
  • the base station controller schedules services between the base stations through the transmission node.
  • the transport node may be an Ethernet switch, an internet protocol (IP) router, a packet transport network (PTN), a microwave microwave device, or an optical transport network (OTN).
  • IP internet protocol
  • PDN packet transport network
  • OTN optical transport network
  • the base station may be a device for communicating with the terminal device.
  • the base station may be a base station (Base Transceiver Station, BTS) in a GSM system or a CDMA system, or may be a base station (NodeB, NB) in a WCDMA system, or may be an evolved base station (eNB) in an LTE system. Or eNodeB).
  • BTS Base Transceiver Station
  • NodeB NodeB
  • eNB evolved base station
  • the base station may be a relay station, an access point, an in-vehicle device, or a network side device in a future 5G network.
  • the clock of each base station in the system shown in Figure 1 can be synchronized to a common clock source (a standard clock) to achieve synchronization between base stations.
  • a common clock source a standard clock
  • the transmission node transmits the clock signal of the common clock source to the terminal station at the end through the transmission of the transmission node.
  • the intermediate transmission node brings a loss of the clock signal when the clock signal is transmitted. Therefore, when the transmission node transmits the clock signal, a better time synchronization path can be selected. For example, a better time synchronization path can be the shortest time synchronization path.
  • device A and device B are respectively two clocks that need to perform time synchronization.
  • the clock referred to herein refers to a node capable of transmitting or receiving a message for time synchronization.
  • the message for time synchronization may be a precision time protocol message defined by IEEE 1588-2008.
  • the clocks mentioned herein are capable of providing a measure of passage of time.
  • the clock referred to herein may be the clock defined in Chapter 3 of IEEE 1588-2008.
  • the clock includes a crystal oscillator and a phase locked loop.
  • the master clock is a clock.
  • the master clock is a source of time.
  • the slave clock can be synchronized to the source of the time.
  • the master clock can be the master clock defined in Chapter 3 of IEEE 1588-2008.
  • the temporal level in embodiments of the present invention is used to describe the accuracy of the time of the clock.
  • the accuracy of the time of the clock with a high time level is higher than the accuracy of the time of the clock with a low time level.
  • the frequency level is used to describe the accuracy of the frequency of the clock.
  • the accuracy of the frequency of the clock with a high frequency level is higher than the accuracy of the frequency of the clock with a low frequency level.
  • the time precision of the clock in the embodiment of the present invention represents the error of the time of the clock relative to the standard time source.
  • the higher the time precision of the clock indicates that the error of the time of the clock relative to the standard time source is smaller.
  • the frequency accuracy of the clock represents the magnitude of the error of the clock's frequency relative to the standard frequency source. The higher the frequency accuracy of the clock, the smaller the error of the clock's frequency relative to the standard frequency source.
  • At least one of the time precision and the frequency accuracy of the slave clock is considered to be lower than the master clock. That is to say, the time from the clock is not accurate enough relative to the main clock.
  • the slave clock can determine the time offset (Offset) based on the message for time synchronization sent with the master clock, and then calibrate the time of the slave clock according to the Offset.
  • device A tracks the time of device B (ie, the synchronization paths are A to B).
  • the time synchronized with device A to device B represents the same meaning.
  • the message for time synchronization may be a Precision Clock Synchronization Protocol (PTP) message, such as a Sync message, a Follow_Up message, a Delay-Req message, and a Delay response (Delay_Resp). At least one of the messages.
  • PTP Precision Clock Synchronization Protocol
  • the time offset (Offset) can be calculated based on the message for time synchronization. After device A obtains Offset, it can calibrate the time of device A according to Offset.
  • the time when device B tracks device A and the time when device B synchronizes to device A represent the same meaning.
  • device B and device A exchange messages for time synchronization.
  • the message for time synchronization may be a Precision Clock Synchronization Protocol (PTP) message.
  • PTP Precision Clock Synchronization Protocol
  • the PTP message may include a Sync message, a Follow_Up message, a Delay-Req message, and a Delay_Resp message.
  • the time offset (Offset) of device B and device A can be calculated. After Device B obtains Offset, it can calibrate the time of Device B according to Offset.
  • the time synchronization path decision algorithm may be the BMCA algorithm defined by IEEE 1588-2008 mentioned above and the A-BMCA algorithm defined by ITU G.8275.1. The details will be described below in conjunction with FIGS. 2 and 3, respectively.
  • FIG. 2 is a flowchart of a BMCA algorithm provided by an embodiment of the present invention.
  • the device A and the device B respectively receive a message for time synchronization from the other party including time level information and configuration information.
  • Device A and Device B compare the time levels of Device A and Device B according to the received messages, respectively. And after the time level is the same, the level of the configuration information is compared to determine the time synchronization path.
  • Device A and device B perform time synchronization (tracking) after determining the synchronization path.
  • the time level information includes: a major master clock level (GM class), a large master clock accuracy (GM accuracy), and a large master clock deviation variance value (GM offsetScaledLogVariance).
  • the configuration information includes: priority 1 of the big master clock (GM priroty1), priority 2 of the master clock (GM priority2), and ID of the big master clock (GM identity). Specifically, as shown in FIG. 2, device A and device B may perform the following steps:
  • step 201 Determine whether the IDs of the large master clocks of the device A and the device B are equal. If they are equal, time synchronization can be determined according to the existing manner, and details are not described herein again. If they are not equal, step 202 is performed.
  • one level of information for device A and device B such as the priority one of the big master clock.
  • Use A>B to indicate that the value of priority 1 of the major clock of device A is greater than the value of priority 1 of the big master clock of device B. It is used to indicate that the time level of device A is less than the time level of device B. That is, the time accuracy of device B is higher than the time precision of device A.
  • the value of the priority 1 of the large master clock of the device A is smaller than the value of the priority 1 of the big master clock of the device B, and is used to indicate that the time level of the device A is greater than the time level of the device B. That is, the time accuracy of device A is higher than the time precision of device B.
  • step 207 Compare the values of the IDs of the large master clocks of the device A and the device B. If A>B, then step 208 is performed. If A ⁇ B, then step 209 is performed.
  • Device A tracks the time of device B.
  • device B tracks the time of device A.
  • FIG. 3 is a flowchart of an A-BMCA algorithm according to an embodiment of the present invention.
  • the device A and the device B mutually receive a message for time synchronization of the other party including time level information and configuration information.
  • the device A and the device B determine the time synchronization path by comparing the time levels of the device A and the device B according to the received messages, respectively, and comparing the levels of the configuration information after the time levels are the same.
  • Device A and device B perform time synchronization (tracking) after determining the synchronization path.
  • the time level information includes: a big master clock The clock level (GM clockClass), the clock accuracy of the GM clockAccuracy and the deviation of the large master clock (GM offsetScaledLogVariance); the configuration information includes: GM priority2 of the big master clock, port Local priority (localPriority), local priority of the local clock, and clock ID of the big master clock (GM clockIdentity).
  • the local priority of a port is the local priority assigned to the port.
  • the local priority of the local clock is the local priority assigned to the local clock.
  • the device A and the device B need to perform the following steps of time synchronization:
  • step 308 is performed. If the local priority of the port of the A is equal to the local priority of the device A, step 306 is performed. If the local priority of the port of the A is lower than the local priority of the device A, step 309 is performed.
  • device A tracks the time of device B.
  • device B tracks the time of device A.
  • the slave clock can determine the Offset based on the interactive message.
  • the slave clock can calibrate the time of the slave clock. That is to say, from the determination of the master clock to the calibration of the slave clock, it is necessary to go through a process. This process takes a certain amount of time. It will be appreciated that the accuracy of the time of the calibrated slave clock is affected by the time level of the master clock. In addition, since the process from the determination of the master clock to the calibration of the slave clock takes a certain length of time, the accuracy of the time of the calibrated slave clock is also affected by the frequency level of the master clock.
  • the quality of the clock signal output by the clock with a high frequency level is higher than the quality of the clock signal of the clock output with a low frequency level.
  • the scheme of using a clock with a low frequency level as the master clock relative to a clock having a low frequency level as a master clock helps to obtain a more accurate calibrated time from the clock.
  • Current time synchronization algorithms (such as the BMCA algorithm or the A-BMCA algorithm) do not consider the frequency level when selecting a time synchronization path. Thus, there is a possibility of causing a clock with a high frequency level Tracks clocks with low frequency levels.
  • the current time synchronization algorithm may result in: the time synchronization path is A tracking B. This makes it impossible for device A to obtain a more accurate calibrated time.
  • the frequency levels of the two devices are different, and the time levels are the same as an example.
  • the frequency level of the device A is a synchronous Ethernet Equipment Clock (EEC) (the frequency accuracy is generally 10 -6 , that is, the error per second is 10 -6 s), and the device B frequency level is the primary reference clock.
  • EEC synchronous Ethernet Equipment Clock
  • PRC Primary Reference Clock
  • Both the time class of device A and the time class of device B are 187, but the clock ID (clockID) is different, and the clockID size is preset, which does not represent the synchronization accuracy.
  • the frequency synchronization path is A tracking B.
  • the BMCA algorithm defined in IEEE 1588-2008 in FIG. 2 and the A-BMCA algorithm defined in ITU G.8275.1 in FIG. 3 since the time class clockClass is 187, both the BMCA algorithm and the A-BMCA algorithm compare the smallest clockID. .
  • the clock ID of device A is 0x0001, which is smaller than the clockID of device B: 0x0002, so that the time synchronization path is B tracking A.
  • the time of device B will be synchronized with the time of device A, and the time precision of the output is also 10 -6 instead of the accuracy of 10 -11 of device B itself.
  • the terminal base station device is implemented to receive poor time synchronization accuracy.
  • the embodiments of the present invention propose to consider the influence of the frequency level in the time synchronization algorithms BMCA, A-BMCA and other time synchronization algorithms.
  • Synchronization method may be such that the upper path in FIG 4 is also in the time synchronization tracking A is B, so that the time precision of the device B and device A are output from the order of 10-11.
  • FIG. 5 is a schematic diagram of a method of time synchronization according to an embodiment of the present invention.
  • the method as shown in Figure 5 is performed by the first clock.
  • the first clock can be located in the first node and the second clock can be located in the second node.
  • the first node and the second node may be two adjacent transmission nodes in the scenario of FIG. 1.
  • the method as shown in FIG. 5 may include:
  • the first clock receives the first information and the second information sent by the second clock, where the first information is used to indicate a time level of the second clock, and the second information is used to indicate a frequency level of the second clock.
  • the first clock After determining that the time level of the first clock is equal to the time level of the second clock, the first clock compares the frequency level of the first clock with the frequency level of the second clock to obtain a first comparison result. .
  • the first clock determines, according to the first comparison result, whether the second clock is used as a master clock of the first clock.
  • the first clock compares the frequency level of the first clock with the frequency level of the second clock, the first clock determines a time level of the first clock, and the The time level of the second clock is equal after execution. Additionally, the first clock obtains the first comparison result by comparing a frequency level of the first clock with a frequency level of the second clock.
  • the embodiment of the present invention compares the frequency level of the clock by the same time level of the two clocks, and determines whether one clock is used as the master clock of the other clock according to the comparison result. In other words, before the master clock is determined The factor of frequency level is considered. Therefore, the above technical solution helps to select a higher quality master clock. Alternatively, the above technical solution helps to avoid selecting a lower quality master clock. After the slave clock determines the master clock, the time synchronization path of the slave clock is also determined. Therefore, the above technical solution helps to establish a high quality time synchronization path. Alternatively, the above technical solution helps to avoid establishing a low quality time synchronization path.
  • the time level involved may include: a clock level of a large master clock (GM clockClass), a clock precision of a large master clock (GM clockAccuracy), and a variance value of a deviation of a large master clock (GM) offsetScaledLogVariance).
  • GM clockClass a clock level of a large master clock
  • GM clockAccuracy a clock precision of a large master clock
  • GM variance value of a deviation of a large master clock offsetScaledLogVariance
  • the first information in the embodiment of the present invention may also be referred to as time level information, and the second information may also be referred to as frequency level information.
  • a message for time synchronization including time level information and frequency level information is mutually transmitted between the first clock and the second clock. Then, time tracking is performed. For example, the angle of the first clock is taken as an example.
  • the time quality level of the received second clock and the local device (the first clock) The time level is compared.
  • the time level of the second clock is higher than the time level of the first clock
  • the first clock tracks the time of the second clock.
  • the second clock tracks the time of the first clock.
  • the first clock compares the frequency level of the first clock with the frequency level of the second clock to obtain a first comparison result.
  • the first clock determines whether to use the second clock as the master clock of the first clock according to the first comparison result. That is, whether the time of the second clock is actually tracked according to the first comparison result.
  • the first clock tracks the time of the second clock.
  • the first clock and the second clock can be used interchangeably.
  • Time synchronized message may be a Precision Clock Synchronization Protocol (PTP) message.
  • PTP Precision Clock Synchronization Protocol
  • the PTP message may include a Sync message, a Follow_Up message, a Delay-Req message, and a Delay_Resp message.
  • the time offset value can be calculated. After the first clock obtains Offset, the time of the first clock can be calibrated according to Offset.
  • the time synchronization according to the time level may adopt the A-BMCA algorithm defined in ITU G.8275.1 or the BMCA algorithm defined in IEEE 1588-2008, which will not be described in detail herein.
  • the time level information and the frequency level information sent by the second clock may specifically be time level information and frequency level information of the second clock itself.
  • the time level information and the frequency level information transmitted by the second clock may be time level information and frequency level information of the clock tracked by the second clock. That is, it may be time level information and frequency level information of the other clock itself.
  • the time level information and the frequency level information transmitted by the second clock in the above two cases in the example of the present invention may be referred to as time level information and frequency level information of the second clock.
  • the first comparison result may indicate that the frequency level of the first clock is greater than, less than, or equal to the frequency level of the second clock.
  • Corresponding time tracking methods for these three cases are also different, the following will be described separately Said.
  • the first comparison result indicates that the frequency level of the first clock is lower than the frequency level of the second clock.
  • the first clock uses the second clock as the master clock of the first clock according to the first comparison result.
  • the first comparison result indicates that the frequency level of the first clock is higher than the frequency level of the second clock.
  • the first clock avoids using the second clock as the master clock of the first clock according to the first comparison result.
  • the frequency level of the first clock is higher than the frequency level of the second clock.
  • the time precision of the first clock is higher than the time precision of the second clock. Therefore, the second clock needs to use the first clock as the master clock of the second clock.
  • the first comparison result indicates that the frequency level of the first clock is equal to the frequency level of the second clock.
  • the method of the embodiment of the present invention further includes: receiving, by the first clock, second configuration information that is sent by the second clock, where the second configuration information includes a priority of the big master clock of the second clock, and a priority of the big master clock. And at least one of the identity of the big master clock.
  • the first clock compares the first configuration information of the first clock with the second configuration information to obtain a second comparison result. And determining, according to the second comparison result, whether the second clock is the master clock of the first clock.
  • the first configuration information includes at least one of a priority level 1 of the large master clock of the first clock, a priority level 2 of the big master clock, and an identity identifier of the big master clock.
  • the first clock also needs to compare the configuration information and perform time synchronization based on the comparison result.
  • the first clock compares the first configuration information with the second configuration information
  • the values of the same type are correspondingly compared, and the values of different types are not compared. For example, comparing the priority one of the big master clock of the first clock with the priority one of the big master clock of the second clock, the identity of the big master clock of the first clock and the identity of the big master clock of the second clock Do comparisons and so on.
  • the configuration information may include the priority of the big master clock, the main master. At least one of the priority of the clock, the identity of the major master clock, and the local priority of the local clock and the local priority of the port. Specifically, how to perform time synchronization according to the configuration information may refer to the two standards, and details are not described herein again.
  • time level information and the frequency level information in the embodiment of the present invention may be carried by a message, or may be carried by different messages, which is not limited by the embodiment of the present invention.
  • time level information and the frequency level information can be carried by one message.
  • the first node receives the time level information and the frequency level information sent by the second node, and the first node receives the message for time synchronization sent by the second node, where the message includes the time level information and the frequency level information.
  • the message for time synchronization in the embodiment of the present invention may be a notification Announce News
  • the second information of the second clock is carried in the reserved byte of the message header of the Announce message.
  • the second information of the second clock is carried in a reserved byte of the message field of the Announce message.
  • the second information of the second clock is carried in a Type, Length, Value, TLV field in the Announce message.
  • the time level information and other information used by IEEE 1588-2008 and ITU G.8275.1 for comparison are delivered to the peer device through the Announce message.
  • the format of the Announce message is shown in Table 1 and Table 2, where Table 1 is the content of the message header of the Announce message (see IEEE 18588-2008 Table 18).
  • Table 2 shows the contents of the message header and message field of the Announce message (see IEEE 25 of IEEE 1588-2008).
  • the second information that is, the frequency level information
  • the embodiments of the present invention provide the following three implementation manners:
  • the second information is placed in the message header of the Announce message.
  • the 5th byte and the 16th to 19th bytes of the Announce message header are reserved bytes, and one of the bytes can be selected for transmitting the second information of the clock.
  • the second information is placed in the message field of the Announce message.
  • the 46th byte of the Announce message is a reserved byte that can be used to pass the second information of the clock.
  • a TLV field (ie, a defined private TLV) may be predefined in the Announce message, and the field is used to transmit the second information.
  • IEEE 1588-2008 defines that other standards based on IEEE 1588-2008 can define private TLVs.
  • the TLV format requirements for standard organization extensions are shown in Table 3 (see Form 35 of IEEE 1588-2008):
  • Type length value type (tlvType): According to Table 34 of IEEE 1588-2008, this field takes a value of 3.
  • Organization ID Generated according to the OUI code of the standard organization or device.
  • This field is the second information (which can be 1 byte).
  • the specific value refers to ITU G.781.
  • the second information may also be multiple bytes.
  • TLV format of the TLV described above is only illustrative, and the TLV in the embodiment of the present invention may also follow other formats.
  • the experimental TLV defined in Section 14.2 of IEEE 1588-2008, the embodiment of the present invention is not limited thereto.
  • the method of the embodiment of the present invention may further include:
  • the first clock stores the frequency level information of the second clock in a clock quality clockQuality data set.
  • the frequency level information of the second clock is sent to the third clock.
  • the time synchronization processing is performed according to the frequency level information of the second clock by triggering the third clock.
  • the clock quality data set may be a clock quality data set defined by a Precision Time Protocol (PTP).
  • PTP may be IEEE 1588v1 or IEEE 1588-2008.
  • the frequency level information of the second clock is stored in the first clock local clockQuality data set.
  • the levels of the first clock and the second clock are then compared.
  • the frequency level information of the second clock is retained in the local clockQuality data sets of the first clock.
  • the frequency level information of the second clock is sent to the third clock.
  • the time synchronization processing is performed according to the frequency level information of the second clock by triggering the third clock.
  • the first clock determines that the time of the second clock is not tracked, the frequency level information of the second clock is deleted from the first clock local clockQuality data set.
  • the frequency level information of the first clock is still sent to the third clock.
  • the time synchronization processing is performed according to the frequency level information of the first clock by triggering the third clock.
  • the embodiment of the present invention can add the second information to the clockQuality data set.
  • the clockQuality in the example of the present invention is as follows:
  • time level information and the configuration information for example, storage, deletion, etc.
  • configuration information for example, storage, deletion, etc.
  • FIG. 6 is a schematic diagram of a method of time synchronization according to another embodiment of the present invention.
  • time tracking is performed after the device A and the device B receive each other's message for time synchronization including the first information (time level information), the second information (frequency level information), and the configuration information.
  • the first information includes: a major master clock level (GM class), a large master clock accuracy (GM accuracy), and a large master clock time deviation variance value (GM offsetScaledLogVariance).
  • the second information includes: a frequency synchronization quality level of the big master clock (GM SSM); the configuration information includes: priority 1 of the big master clock (GM priroty1), priority 2 of the master clock (GM priority2), and a large master clock GM identity (GM ID).
  • the device A and the device B need to perform the following steps of time synchronization:
  • step 608 Compare the values of the IDs of the primary clock sources of device A and device B. If A>B, step 609 is performed. If A ⁇ B, then step 610 is performed.
  • device A tracks the time of device B.
  • device B tracks the time of device A.
  • steps 601-605 correspond to steps 201-205 in FIG. 2, and 607-610 corresponds to 206-209, and details are not described herein again. Since the accuracy of the frequency is taken into consideration when performing time synchronization, a path with better accuracy can be selected, thereby improving the time synchronization accuracy of the output.
  • FIG. 7 is a schematic diagram of a method for time synchronization according to another embodiment of the present invention.
  • the time tracking is performed after the device A and the device B receive each other's message for time synchronization including the first information (time level information), the second information (frequency level information), and the configuration information.
  • the first information includes: a clock level of the big master clock (GM clockClass), a clock precision of the big master clock (GM clockAccuracy), and a variance value of the deviation of the big master clock (GM offsetScaledLogVariance).
  • the second information includes: a frequency synchronization quality level (GM SSM) of the large master clock.
  • GM SSM frequency synchronization quality level
  • the configuration information includes: GM priority2 of the big master clock, local priority of the port (localPriority), and clock ID of the big master clock (GM identity).
  • GM priority2 of the big master clock local priority of the port
  • localPriority local priority of the port
  • GM identity clock ID of the big master clock
  • device A tracks the time of device B.
  • device B tracks the time of device A.
  • steps 701-703 correspond to steps 301-303 in FIG. 3, and 705-708 correspond to 304-307, and details are not described herein again. Since the accuracy of the frequency is taken into consideration when performing time synchronization, a path with better accuracy can be selected, thereby improving the time synchronization accuracy of the output.
  • FIG. 6 and FIG. 7 are only intended to assist those skilled in the art in understanding the embodiments of the present invention, and are not intended to limit the embodiments of the present invention to the specific numerical values or specific examples illustrated. It will be obvious to those skilled in the art that various modifications and changes can be made without departing from the scope of the invention.
  • the time synchronization method of the embodiment of the present invention is described in detail above with reference to FIGS. 1 through 7.
  • the time synchronization device of the embodiment of the present invention will be described below with reference to FIGS. 8 through 9.
  • FIG. 8 is a schematic block diagram of a clock for time synchronization, in accordance with one embodiment of the present invention.
  • the clock shown in FIG. 8 is the first clock, and the first clock may be the clock in any one of the first transmission nodes in the scenario of FIG. 1.
  • the second clock may be a clock in the second node in the scenario of FIG. 1, and the first node and the second node may be any two adjacent intermediate transmission nodes in the scenario of FIG.
  • first clock 800 shown in FIG. 8 can implement the various processes involved in the time synchronization method involved in the embodiment of FIG. 5.
  • the operations and/or functions of the various modules in the first clock 800 are respectively implemented to implement the corresponding processes in the method embodiment of FIG.
  • the detailed description is omitted here.
  • the first clock 800 shown in FIG. 8 includes a first receiving unit 810 and a comparing unit 820 and a determining unit 830.
  • the first receiving unit 810 is configured to receive first information and second information that are sent by the second clock, where the first information is used to indicate a time level of the second clock, and the second information is used to indicate a frequency level of the second clock. .
  • the comparing unit 820 is configured to compare the frequency level of the first clock with the frequency level of the second clock after determining that the time level of the first clock is equal to the time level of the second clock, to obtain a first comparison result.
  • the determining unit 830 is configured to determine, according to the first comparison result, whether the second clock is the master clock of the first clock.
  • the embodiment of the present invention compares the frequency level of the clock by the same time level of the two clocks, and determines whether one clock is used as the master clock of the other clock according to the comparison result. That is to say, the factor of the frequency level is considered before the main clock is determined. Therefore, the above technical solution helps to select a higher quality master clock. Alternatively, the above technical solution helps to avoid selecting a lower quality master clock. After the slave clock determines the master clock, the time synchronization path of the slave clock is also determined. Therefore, the above technical solution helps to establish a high quality time synchronization path. Alternatively, the above technical solution helps to avoid establishing a low quality time synchronization path.
  • the determining unit 830 when the first comparison result indicates that the frequency level of the first clock is lower than the frequency level of the second clock, the determining unit 830 is specifically configured to use the first comparison result according to the first comparison result.
  • the second clock serves as the master clock of the first clock.
  • the determining unit 830 when the first comparison result indicates that the frequency level of the first clock is higher than the frequency level of the second clock, the determining unit 830 is specifically configured to determine to avoid according to the first comparison result.
  • the second clock is used as the master clock of the first clock.
  • the first clock further includes: a second receiving unit, configured to receive second configuration information sent by the second clock, where the second configuration information includes a large master clock of the second clock a priority level 1, at least one of a priority second of the big master clock of the second clock and an identity of the big master clock of the second clock,
  • the determining unit 830 is specifically configured to: after the comparing unit obtains the first comparison result, the first clock Comparing the first configuration information with the second configuration information, obtaining a second comparison result, and determining, according to the second comparison result, whether the second clock is used as a master clock of the first clock, where the first configuration information includes the The priority of the large master clock of the first clock, the priority second of the large master clock of the first clock, and the identity of the big master clock of the first clock.
  • the first receiving unit 810 is specifically configured to receive a message for time synchronization sent by the second clock, where the message includes the first information and the second information.
  • the message is a notification Announce message, where the second information of the second clock is carried in a reserved byte of the message header of the Announce message; or the second information bearer of the second clock In the reserved byte of the message field of the Announce message; or the second information of the second clock is carried in the type length value TLV field in the Announce message.
  • the first clock further includes:
  • a storage unit configured to store the second information of the second clock in a clock quality clockQuality data set of the precision time protocol PTP;
  • a sending unit configured to send the second information of the second clock to the third clock after the time that the first clock tracks the second clock.
  • the first information includes: a level of a large main clock of the second clock, an accuracy of a large main clock of the second clock, and a time deviation of a large main clock of the second clock. At least one of the variance values.
  • FIG. 9 is a schematic block diagram of an apparatus for time synchronization, in accordance with one embodiment of the present invention.
  • the clock shown in FIG. 9 is the first clock
  • the first clock may be the clock in any one of the first transmission nodes in the scenario of FIG. 1
  • the second clock may be the clock in the second node in the scenario of FIG.
  • the node and the second node may be any two adjacent intermediate transfer nodes in the scenario of FIG.
  • first clock 900 shown in FIG. 9 can implement various processes in the time synchronization method involved in the embodiment of FIG. 5, and the operations and/or functions of the respective modules in the first clock 900 are respectively implemented in FIG.
  • the corresponding process in the method embodiment refer to the description in the foregoing method embodiments. To avoid repetition, the detailed description is omitted here.
  • the first clock 900 shown in FIG. 9 includes a processor 910 and a memory 920, and optionally, a bus system 930 and a transceiver 940.
  • the transceiver 940 is configured to receive the first information and the second information that are sent by the second clock, where the first information is used to indicate a time level of the second clock, and the second information is used to indicate a frequency of the second clock. grade.
  • the processor 910 and the memory 920 are connected by a bus system 930 for storing instructions, and the processor 910 is configured to execute the instructions stored in the memory 920 to determine the time level of the first clock and the time level of the second clock. After being equal, the frequency level of the first clock is compared with the frequency level of the second clock to obtain a first comparison result; and determining, according to the first comparison result, whether the second clock is used as the master clock of the first clock .
  • the embodiment of the present invention compares the frequency level of the clock by the same time level of the two clocks, and determines whether one clock is used as the master clock of the other clock according to the comparison result. That is to say, the factor of the frequency level is considered before the main clock is determined. Therefore, the above technical solution helps to select a higher quality master clock. Alternatively, the above technical solution helps to avoid selecting a lower quality master clock. After the slave clock determines the master clock, the time synchronization path of the slave clock is also determined. Therefore, the above technical solution helps to establish a high quality time synchronization path. Alternatively, the above technical solution helps to avoid establishing a low quality time synchronization path.
  • Processor 910 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 910 or an instruction in a form of software.
  • the processor 910 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read only memory or an electrically erasable programmable memory, a register, etc.
  • RAM random access memory
  • ROM read-only memory
  • programmable read only memory or an electrically erasable programmable memory
  • register etc.
  • the storage medium is located in the memory 920, and the processor 910
  • the information in the memory 920 is read, and the steps of the above method are completed in combination with the hardware.
  • the bus system 930 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses
  • the processor 910 when the first comparison result indicates that the frequency level of the first clock is lower than the frequency level of the second clock, the processor 910 is specifically configured to: according to the first comparison result The second clock serves as the master clock of the first clock.
  • the processor 910 when the first comparison result indicates that the frequency level of the first clock is higher than the frequency level of the second clock, the processor 910 is specifically configured to determine, according to the first comparison result, to avoid The second clock serves as the master clock of the first clock.
  • the transceiver 940 is further configured to receive second configuration information that is sent by the second clock, where the second configuration information includes a priority of the large clock of the second clock, the first At least one of the priority second of the big master clock of the two clocks and the identity of the big master clock of the second clock.
  • the processor 910 is specifically configured to: after the comparing unit obtains the first comparison result, the first clock Comparing the first configuration information with the second configuration information, obtaining a second comparison result, and determining, according to the second comparison result, whether the second clock is used as a master clock of the first clock, where the first configuration information includes the The priority of the large master clock of the first clock, the priority second of the large master clock of the first clock, and the identity of the big master clock of the first clock.
  • the transceiver 940 is specifically configured to receive a message for time synchronization sent by the second clock, where the message includes the first information and the second information.
  • the message is a notification Announce message, where the second information of the second clock is carried in a reserved byte of the message header of the Announce message; or the second information of the second clock is The second information of the second clock is carried in the type length value TLV field in the Announce message.
  • the processor 910 is configured to store the second information of the second clock in a clock quality clockQuality data set of the precision time protocol PTP.
  • the transceiver 940 is further configured to send the second information of the second clock to the third clock after the time that the first clock tracks the second clock.
  • the first information includes: a level of a large main clock of the second clock, an accuracy of a large main clock of the second clock, and a time deviation of a large main clock of the second clock. At least one of the variance values.
  • the embodiment of the present invention further provides a first device, including the first clock in FIG. 8 or FIG.
  • the first device may be a base station, a terminal, a transmission node, or the like in the scenario of FIG. 1.
  • a network system comprising a first device and a second device, the first device comprising a first clock as in FIG. 8 or FIG. 9, the second device comprising transmitting to the first time for time synchronization The second clock of the message.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, magnetic A disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of an instruction or data structure and that can be accessed by a computer.
  • Any connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

La présente invention concerne un procédé et une horloge pour synchronisation temporelle. Le procédé comporte les étapes suivantes: une première horloge reçoit un premier message et un deuxième message émis par une deuxième horloge, le premier message étant utilisé pour indiquer une strate de temps de la deuxième horloge et le deuxième message étant utilisé pour indiquer une strate de fréquence de la deuxième horloge; après que la première horloge a déterminé qu'une strate de temps de la première horloge et la strate de temps de la deuxième horloge sont les mêmes, une strate de fréquence de la première horloge et la strate de fréquence de la deuxième horloge sont comparées, et un premier résultat de comparaison est obtenu; et la première horloge détermine, d'après le premier résultat de comparaison, s'il convient de sélectionner la deuxième horloge en tant qu'horloge maîtresse de la première horloge. Le procédé fait intervenir une strate de fréquence en tant que facteur à prendre en considération lors de la sélection d'une horloge maîtresse. Le procédé technique peut par conséquent sélectionner une horloge maîtresse de qualité plus élevée ou éviter de sélectionner une horloge maîtresse de qualité plus basse.
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