WO2017118181A1 - 一种内存访问装置和方法 - Google Patents

一种内存访问装置和方法 Download PDF

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Publication number
WO2017118181A1
WO2017118181A1 PCT/CN2016/103886 CN2016103886W WO2017118181A1 WO 2017118181 A1 WO2017118181 A1 WO 2017118181A1 CN 2016103886 W CN2016103886 W CN 2016103886W WO 2017118181 A1 WO2017118181 A1 WO 2017118181A1
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data
cache
state
memory
cache line
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PCT/CN2016/103886
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English (en)
French (fr)
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蒋晨磊
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上海斐讯数据通信技术有限公司
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Publication of WO2017118181A1 publication Critical patent/WO2017118181A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

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  • the present invention relates to the field of computer networks, and in particular, to a memory access device and method.
  • ARM's Trustzone technology is a system-wide security approach for a wide range of applications on high-performance computing platforms, including secure payments, digital rights management and web-based services. Its basic idea is: Trustzone divides system memory and peripherals into security domains and non-security domains, and secures the resources of the security domain by extending the Advanced Microcontroller Bus Architecture (AMBA)-3 bus (memory and external). Set) not to be accessed by processes in non-secure domains. At the same time, the processor core extends a status bit, NS, to mark the security state of the kernel.
  • ABA Advanced Microcontroller Bus Architecture
  • NS status bit
  • the purpose of Trustzone technology is to ensure that a kernel in an unsecured state can only access resources in a non-secure world, and a kernel in a secure state can access any resource. In this way, the hardware resources and software resources of the secure world and the non-secure world can be isolated to protect the sensitive data of users.
  • the technical problem to be solved by the present invention is to provide a memory access device and method capable of improving system performance.
  • a technical solution adopted by the present invention is: providing a memory access device, the device comprising an instruction receiving module, configured to receive a memory access instruction, where the memory access instruction includes a memory address to be accessed; and a state acquisition module Used to get the current security state of the system; memory An access processing module, configured to determine, in the cache, whether a cache line having the same state as the current security state of the system and containing data in the memory address to be accessed is returned, and if present, returning to the cache line The data, if not present, reads the data of the memory address to be accessed from the memory into the cache, and sets the state of the cache line storing the data to the current security state of the system.
  • a technical solution adopted by the present invention is to provide a memory access method, which includes receiving a memory access instruction, where the memory access instruction includes a memory address to be accessed; and acquiring a current security state of the system; Determining, in the cache, whether there is a cache line having the same state as the current security state of the system and containing data in the memory address to be accessed, and if so, returning data in the cache line, if not present
  • the data of the memory address to be accessed is read from the memory into the cache, and the state of the cache line storing the data is set to the current security state of the system.
  • the memory access device of the present invention receives a memory access instruction, the memory access instruction includes a memory address to be accessed; acquires a current security state of the system; determines whether a state exists in the cache, and the system a cache line having the same current security status and containing data in the memory address to be accessed, returning data in the cache line if present, and reading the memory address to be accessed from memory if not present
  • the data is cached and the state of the cache line holding the data is set to the current security state of the system; thereby improving system performance.
  • FIG. 1 is a schematic structural view of a first embodiment of a memory access device of the present invention
  • FIG. 2 is a schematic structural diagram of a second embodiment of a memory access device of the present invention.
  • FIG. 3 is a schematic flow chart of a first embodiment of a memory access method of the present invention.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a memory access device provided by the present invention, which can be used in a system based on Trustzone technology.
  • the memory access device 100 includes an instruction receiving module 110, a state acquiring module 120, and a memory access processing module 130.
  • the instruction receiving module 110 is configured to receive a memory access instruction, where the memory access instruction includes a memory address to be accessed. For example, during the running of an application, the system needs to access data of a specified memory address, and the processor will receive the memory access instruction.
  • the state obtaining module 120 is configured to acquire a current security state of the system.
  • the state of the system may be a safe state or an unsafe state.
  • the current security status of the system is indicated by the status bit of the processor core, that is, the NS status bit.
  • the system can only access resources in non-secure state, including memory and external devices, and perform operations that are not critical to security, such as accessing normal web pages, and when in a secure state, access all resources. And perform operations such as bank payments that require high security.
  • the memory access processing module 130 is configured to determine, in the cache, whether there is a cache line whose state is the same as the current security state of the system, and includes data in the memory address to be accessed, and if yes, return the cache The data in the row, if not present, reads the data of the memory address to be accessed from the memory into the cache, and sets the state of the cache line storing the data to the current security state of the system.
  • the cache contains TLB and cache; in order to speed up the memory access speed, some commonly used memory data is loaded into the cache in advance, and the unit for storing the memory data is called a cache line (Line). Lines extend a tag to identify the status of the line (safe or unsafe); for data that has already been loaded, the cache also contains the logical address of the data in memory, for partially loaded data, cache It also contains the logical address and physical address of the data in the data that is not loaded in the memory.
  • Lines extend a tag to identify the status of the line (safe or unsafe)
  • the cache also contains the logical address of the data in memory, for partially loaded data, cache It also contains the logical address and physical address of the data in the data that is not loaded in the memory.
  • it may be a line scan of the cache to find a cache line whose state is the same as the current security state of the system and includes the memory address to be accessed. If a cache line that satisfies the condition is found, the data has been Loaded into the cache, can be directly accessed, then returned to the processor core; if the description data is still in memory, you need to load the data into the cache from the memory's pending address in real time, and store the real-time load. The status of the cache line of the data is set to Current security status.
  • both secure and insecure data can exist in the cache, and isolated from each other, the system can be flexibly invoked, thereby avoiding the need to flush all data out each time the system switches state, and improve the next time. The speed at which data is loaded, thereby improving system performance.
  • the memory access device of the present invention receives a memory access instruction, the memory access instruction includes a memory address to be accessed; acquires a current security state of the system; determines whether a state exists in the cache, and the system a cache line having the same current security status and containing data in the memory address to be accessed, returning data in the cache line if present, and reading the memory address to be accessed from memory if not present
  • the data is cached and the state of the cache line holding the data is set to the current security state of the system; thereby improving system performance.
  • FIG. 2 is a schematic structural diagram of a second embodiment of a memory access device provided by the present invention, which can be used in a system based on Trustzone technology.
  • the memory access device 200 includes an instruction receiving module 210, a state obtaining module 220, and a memory access processing module 230.
  • the instruction receiving module 210 is configured to receive a memory access instruction, where the memory access instruction includes a memory address to be accessed. For example, during the running of an application, the system needs to access data of a specified memory address, and the processor will receive the memory access instruction.
  • the state obtaining module 220 is configured to acquire a current security state of the system, where the system identifies a current security state by using a status bit of the processor core, and the state obtaining module 220 includes a status bit acquiring unit 221, configured to acquire a processor core.
  • the system When the system is in an unsecured state, it can only access resources in non-secure state, including memory and external devices, and perform operations that are not critical to security, such as accessing normal web pages, and when in a secure state, access all resources. And perform operations such as bank payments that require high security.
  • the memory access processing module 230 is configured to determine, in the cache, whether there is a cache line whose state is the same as the current security state of the system, and includes data in the memory address to be accessed, and if yes, return the cache The data in the row, if not present, reads the data of the memory address to be accessed from the memory into the cache, and sets the state of the cache line storing the data to The current security status of the system.
  • the cache contains TLB and cache.
  • some commonly used memory data is loaded into the cache in advance.
  • the unit for storing the memory data is called a cache line.
  • This scheme extends a tag for each line. Identifies the status of the line (secure or insecure); for data that has already been loaded, the cache also contains the logical address of the data in memory. For partially loaded data, the cache also contains the unloaded portion of the data. The logical address and physical address of the data in memory. It can be through a line scan of the cache to find a cache line whose state is the same as the current security state of the system and contains the memory address to be accessed. If a cache line that satisfies the condition is found, the data has been loaded.
  • the cache can be directly accessed and returned to the processor core. If the description data is not found in the memory, the data needs to be loaded into the cache from the memory to be accessed in real time, and the real-time loading data will be stored.
  • the state of the cache line is set to the current security state of the system.
  • the memory access processing module 230 includes a first determining unit 231, a first cache direct reading unit 232, and a first cache indirect reading unit 233; a determining unit 231, configured to determine, in the cache, whether there is a cache line whose tag value is the same as a current security state of the system, and includes data in the memory address to be accessed; the first cache directly The reading unit 232 is configured to return the data in the cache line when the determination result of the first determining unit 231 is YES; the first cache indirect reading unit 233 is configured to determine the result when the first determining unit 231 To otherwise read the data of the memory address to be accessed from the memory to the cache, and set the state of the cache line storing the data to the current security state of the system.
  • the memory access processing module 230 includes a second determining unit 234, a second cache direct reading unit 235, a second cache indirect reading unit 236, and a second determining unit 234 for Determining, in the cache, whether there is a cache line having the same state and current security status of the system and including data in the memory address to be accessed; the second cache direct reading unit 235, when the The second determination unit 234 returns the data in the cache line if the determination result is YES; the second cache indirect reading unit 236 includes the space state determination sub-unit 2361, the space shortage processing sub-unit 2362, and the space sufficient processing sub- Unit 2363.
  • the space state determining sub-unit 2361 is configured to determine whether the current cache is full when the determination result of the second determining unit 234 is negative; the space shortage processing sub-unit 2362 is configured to: When the judgment result of the space state judging subunit 2361 is YES, the data in the cache line whose state is different from the current security state of the system is preferentially discarded, and the memory address to be accessed is read from the memory.
  • the cache space is full, and if it is full, the data in the cache line whose state is different from the current security state of the system is first flushed, for example, current If it is in a safe state, the data of the non-secure state is first brushed out. If the data is currently in an unsecured state, the data of the security state is first flushed out.
  • the memory access processing module 230 includes a third determining unit 237, a third cache direct reading unit 238, a third cache indirect reading unit 239, and a third determining unit 237 for
  • the current security status of the system is security, and the memory address to be accessed belongs to a memory address of an unsecure type, it is determined in the cache whether the status is unsafe and includes the memory address to be accessed.
  • a cache line of the data the third cache direct reading unit 238, configured to return data in the cache line when the determination result of the third determining unit 237 is YES;
  • the third The cache indirect reading unit 239 is configured to read the data of the memory address to be accessed from the memory into the cache when the determination result of the third determining unit 237 is negative, and store the data.
  • the state of the cache line is set to the current security state of the system. Because the state of the security process can access the memory in the non-secure state, in this case, the state of the security process needs to be treated as an unsafe state in order to find the correct data
  • both secure and insecure data can exist in the cache, and isolated from each other, the system can be flexibly invoked, thereby avoiding the need to flush all data out each time the system switches state, and improve the next time. The speed at which data is loaded, thereby improving system performance.
  • the memory access device of the present invention receives a memory access instruction, the memory access instruction includes a memory address to be accessed; acquires a current security state of the system; determines whether a state exists in the cache, and the system a cache line having the same current security status and containing data in the memory address to be accessed, returning data in the cache line if present, and reading the memory address to be accessed from memory if not present Data into the cache and will store the The state of the cache line of data is set to the current security state of the system; thus, the performance of the system can be improved.
  • FIG. 3 is a schematic flowchart of a first embodiment of a memory access method provided by the present invention, which can be used in a system based on Trustzone technology.
  • the steps of the method include:
  • S301 Receive a memory access instruction, where the memory access instruction includes a memory address to be accessed.
  • the system needs to access data of a specified memory address, and the processor will receive the memory access instruction.
  • the system identifies a current security state by using a status bit of the processor core, where the method for obtaining a current security state of the system is specifically acquiring a value of a status bit in the processor core.
  • the state of the system may be a security state or an unsafe state;
  • the status bit of the processor core is, for example, an NS.
  • the system can only access resources in non-secure state, including memory and external devices, and perform operations that are not critical to security, such as accessing normal web pages, and when in a secure state, access all resources. And perform operations such as bank payments that require high security.
  • S303 determining, in the cache, whether there is a cache line whose state is the same as the current security state of the system and containing data in the memory address to be accessed, and if yes, returning data in the cache line, if If not, the data of the memory address to be accessed is read from the memory into the cache, and the state of the cache line storing the data is set to the current security state of the system.
  • the cache line identifies the status by using a tag, where the cache determines whether the presence status is the same as the current security status of the system, and the cache line that includes the data in the memory address to be accessed is specifically : determining, in the cache, whether there is a cache line whose tag value is the same as the current security state of the system and that contains data in the memory address to be accessed.
  • the cache contains TLB and cache.
  • some commonly used memory data is loaded into the cache in advance.
  • the unit for storing the memory data is called a cache line.
  • This scheme extends a tag for each line. Identifies the status of the line (safe or unsafe); for data that has already been loaded, the cache will also contain the data in memory
  • the logical address, for partially loaded data the cache also contains the logical address and physical address of the data in the data that is not loaded in the memory. It can be through a line scan of the cache to find a cache line whose state is the same as the current security state of the system and contains the memory address to be accessed. If a cache line that satisfies the condition is found, the data has been loaded.
  • the cache can be directly accessed and returned to the processor core. If the description data is not found in the memory, the data needs to be loaded into the cache from the memory to be accessed in real time, and the real-time loading data will be stored.
  • the state of the cache line is set to the current security state of the system.
  • the data is read from the memory into the cache, specifically: determining whether the current cache is full; if yes, the state is preferentially different from the current security state of the system. Data in the cache line is discarded, the data of the memory address to be accessed read from the memory is saved to the cache line; if not, the read from the memory is read The data accessing the memory address is saved to the free cache line.
  • the cache space is full, and if it is full, the data in the cache line whose state is different from the current security state of the system is first flushed, for example, current If it is in a safe state, the data of the non-secure state is first brushed out. If the data is currently in an unsecured state, the data of the security state is first flushed out.
  • the determining, in the cache, whether a state exists and a current security status of the system is specifically: determining whether there is a cache line in the cache that is in an unsafe state and containing data in the memory address to be accessed. Because the state of the security process can access the memory in the non-secure state, in this case, the state of the security process needs to be treated as an unsafe state in order to find the correct data.
  • both secure and insecure data can exist in the cache, and isolated from each other, the system can be flexibly invoked, thereby avoiding the need to flush all data out each time the system switches state, and improve the next time. The speed at which data is loaded, thereby improving system performance.
  • the Trustzone technology-based memory access device of the present invention receives a memory access instruction, where the memory access instruction includes a memory address to be accessed; acquires a current security state of the system; and determines whether a state exists in the cache.
  • a cache line that is the same as the current security state of the system and that contains data in the memory address to be accessed, returns data in the cache line if present, and reads the memory from memory if not present Data to be accessed to the memory address to high speed
  • the state of the cache line storing the data is set to the current security state of the system; thereby improving system performance.

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Abstract

一种内存访问装置和方法，该装置包括：指令接收模块（100），用于接收内存访问指令，所述内存访问指令包含待访问内存地址；状态获取模块（120），用于获取系统的当前安全性状态；内存访问处理模块（130），用于在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。上述装置和方法能够提高系统性能。

Description

一种内存访问装置和方法 技术领域
本发明涉及计算机网络领域，特别是涉及一种内存访问装置和方法。
背景技术
ARM的可信域(Trustzone)技术是系统范围的安全方法，针对高性能计算平台上的大量应用，包括安全支付，数字版权管理和基于WEB的服务。它的基本思想是：Trustzone将系统内存及外设划分为安全域及非安全域，通过扩展高级微控制总线架构(Advanced Microcontroller Bus Architecture，AMBA)-3总线来确保安全域的资源(内存及外设)不被非安全域的进程访问。同时，处理器核扩展了一个状态位，即NS，用来标记内核的安全性状态。Trustzone技术的目的，即确保处在非安全状态的内核只能访问非安全世界的资源，安全状态的内核可以访问任意资源。通过这种方式，可将安全世界及非安全世界的硬件资源及软件资源进行隔离，从而保护用户的敏感数据安全。
由于这种安全世界及非安全世界的划分的存在，就意味着系统会频繁在安全世界及非安全世界之间进行切换。由于安全世界及非安全世界的进程地址内存映射是完全独立，即拥有独立的内存映射表。因此，在切换世界的过程中，并不需要刷新内存映射表。然而，对于传输后备缓冲器(Translation Lookaside Buffer，TLB)及高速缓冲存储器(cache)等高速缓存来说，这些资源在两个世界中是共享的。因此，当切换世界时，TLB及cache需要不停地刷出，这会严重影响系统的性能。可见，现有技术中，采用Trustzone技术的系统因为涉及到安全世界及非安全世界之间的切换，系统的性能会明显降低。
发明内容
本发明主要解决的技术问题是提供一种内存访问装置和方法，能够提高系统性能。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种内存访问装置，该装置包括指令接收模块，用于接收内存访问指令，所述内存访问指令包含待访问内存地址；状态获取模块，用于获取系统的当前安全性状态；内存 访问处理模块，用于在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种内存访问方法，该方法包括接收到内存访问指令，所述内存访问指令包含待访问内存地址；获取系统的当前安全性状态；在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
区别于现有技术，本发明的内存访问装置，接收到内存访问指令，所述内存访问指令包含待访问内存地址；获取系统的当前安全性状态；在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态；从而能够提高系统性能。
附图说明
图1是本发明内存访问装置的第一实施方式的结构示意图；
图2是本发明内存访问装置的第二实施方式的结构示意图；
图3是本发明内存访问方法的第一实施方式的流程示意图。
具体实施方式
下面结合具体实施方式对本发明的技术方案作进一步更详细的描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
参阅图1，图1是本发明提供的内存访问装置的第一实施方式的结构示意图，该内存访问装置可用于基于Trustzone技术的系统中。
该内存访问装置100包括：指令接收模块110，状态获取模块120和内存访问处理模块130。
其中，指令接收模块110，用于接收内存访问指令，所述内存访问指令包含待访问内存地址。例如，系统在运行应用程序的过程中，需要访问指定内存地址的数据，处理器将接收到该内存访问指令。
状态获取模块120，用于获取系统的当前安全性状态。具体的，系统的状态可以是安全状态或者不安全状态。通常的，通过处理器核的状态位来指示系统的当前安全性状态，即NS状态位，当NS＝1时标识当前系统处于非安全状态，NS＝0标识当前系统处于安全状态。当系统处于非安全状态时，仅可以访问非安全状态的资源，包括内存和外部设备，并执行对安全性要求不高的操作，例如访问普通网页，而当处于安全状态时，可以访问所有资源，并执行例如银行支付等要求安全性高的操作。
内存访问处理模块130，用于在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
其中，高速缓存包含TLB和cache；为了加快内存的访问速度，会将部分常用的内存数据提前加载到高速缓存中，用于存放内存数据的单位称为高速缓存行(Line)，本方案为每个Line扩展了一个tag，用于标识该Line的状态(安全或者不安全)；对于已经加载的数据，高速缓存中同时会包含该数据在内存中的逻辑地址，对于部分加载的数据，高速缓存中还包含该数据中未加载部分数据在内存中的逻辑地址和物理地址。
具体的，可以是对高速缓存逐行(Line)扫描，查找其状态和系统当前安全性状态相同、且包含待访问内存地址的高速缓存行，如果找到了满足条件的高速缓存行，说明数据已经加载到高速缓存，可以直接访问、则返回给处理器核；如果找不到说明数据还在内存中，需要实时从内存的待访问地址中将数据加载到高速缓存中，同时将存放该实时加载数据的高速缓存行的状态设置为系 统当前安全性状态。
通过为高速缓存行增加状态，高速缓存中可以同时存在安全和不安全的数据，并且互相隔离，系统可以灵活调用，从而避免了系统每次切换状态时都需要将数据全部刷出，提高下次加载数据的速度，从而提高到了系统性能。
区别于现有技术，本发明的内存访问装置，接收到内存访问指令，所述内存访问指令包含待访问内存地址；获取系统的当前安全性状态；在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态；从而能够提高系统性能。
参阅图2，图2是本发明提供的内存访问装置的第二实施方式的结构示意图，该内存访问装置可用于基于Trustzone技术的系统中。
该内存访问装置200包括：指令接收模块210，状态获取模块220，内存访问处理模块230。
其中，指令接收模块210用于接收内存访问指令，所述内存访问指令包含待访问内存地址。例如，系统在运行应用程序的过程中，需要访问指定内存地址的数据，处理器将接收到该内存访问指令。
状态获取模块220用于获取系统的当前安全性状态，其中，所述系统通过处理器核的状态位来标识当前安全性状态，状态获取模块220包括状态位获取单元221，用于获取处理器核中状态位的值。具体的，系统的状态可以是安全状态或者不安全状态；处理器核的状态位，例如是NS，当NS＝1时标识当前系统处于非安全状态，NS＝0标识当前系统处于安全状态。当系统处于非安全状态时，仅可以访问非安全状态的资源，包括内存和外部设备，并执行对安全性要求不高的操作，例如访问普通网页，而当处于安全状态时，可以访问所有资源，并执行例如银行支付等要求安全性高的操作。
内存访问处理模块230，用于在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为 所述系统的当前安全性状态。
其中，高速缓存包含TLB和cache。为了加快内存的访问速度，会将部分常用的内存数据提前加载到高速缓存中，用于存放内存数据的单位称为高速缓存行(Line)，本方案为每个Line扩展了一个tag，用于标识该Line的状态(安全或者不安全)；对于已经加载的数据，高速缓存中同时会包含该数据在内存中的逻辑地址，对于部分加载的数据，高速缓存中还包含该数据中未加载部分数据在内存中的逻辑地址和物理地址。可以是通过对高速缓存逐行(Line)扫描，查找其状态和系统当前安全性状态相同、且包含待访问内存地址的高速缓存行，如果找到了满足条件的高速缓存行，说明数据已经加载到高速缓存，可以直接访问、则返回给处理器核；如果找不到说明数据还在内存中，需要实时从内存的待访问地址中将数据加载到高速缓存中，同时将存放该实时加载数据的高速缓存行的状态设置为系统当前安全性状态。
可选的，当所述高速缓存行通过tag来标识状态时，内存访问处理模块230包括第一判断单元231，第一高速缓存直接读取单元232，第一高速缓存间接读取单元233；第一判断单元231，用于在所述高速缓存中确定是否存在其tag值和所述系统的当前安全性状态相同，且包含所述待访问内存地址中数据的高速缓存行；第一高速缓存直接读取单元232，用于当第一判断单元231的确定结果为是则返回所述高速缓存行中的数据；第一高速缓存间接读取单元233，用于当第一判断单元231的确定结果为否则从内存中读取所述待访问内存地址的数据至高速缓存，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
可选的，内存访问处理模块230包括第二判断单元234，第二高速缓存直接读取单元235，第二高速缓存间接读取单元236；所述第二判断单元234，用于在所述高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行；所述第二高速缓存直接读取单元235，用于当所述第二判断单元234的确定结果为是则返回所述高速缓存行中的数据；所述第二高速缓存间接读取单元236包括空间状态判断子单元2361，空间不足处理子单元2362，空间充足处理子单元2363。
所述空间状态判断子单元2361，用于在所述第二判断单元234的确定结果为否时判断当前高速缓存是否空间满了；所述空间不足处理子单元2362，用于 在所述空间状态判断子单元2361的判断结果为是时，优先将其状态和所述系统当前安全性状态不同的高速缓存行中的数据抛弃，从内存中读取所述待访问内存地址的数据保存到所述高速缓存行，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态；所述空间充足处理子单元2363，用于在所述空间状态判断子单元2361的判断结果为否时，从内存中读取所述待访问内存地址的数据保存到空闲的高速缓存行，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。因此，当需要实时从内存中加载数据到高速缓存时，首先判断高速缓存的空间是否满，如果满了则首先将状态和系统当前安全性状态不同的高速缓存行中的数据刷出，例如当前处于安全状态，则首先将非安全状态的数据刷出，当前处于非安全状态，则首先将安全状态的数据刷出。
可选的，所述内存访问处理模块230包括第三判断单元237，第三高速缓存直接读取单元238，第三高速缓存间接读取单元239；所述第三判断单元237，用于在当所述系统的当前安全性状态为安全，且所述待访问内存地址属于不安全类型的内存地址时，在所述高速缓存中确定是否存在状态为不安全状态、且包含所述待访问内存地址中数据的高速缓存行；所述第三高速缓存直接读取单元238，用于在所述第三判断单元237的确定结果为是时则返回所述高速缓存行中的数据；所述第三高速缓存间接读取单元239，用于在所述第三判断单元237的确定结果为否时则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。因为安全状态的进程可以访问非安全状态的内存，此时，需要将安全进程的状态也当做非安全状态来操作，以便找到正确的数据。
通过为高速缓存行增加状态，高速缓存中可以同时存在安全和不安全的数据，并且互相隔离，系统可以灵活调用，从而避免了系统每次切换状态时都需要将数据全部刷出，提高下次加载数据的速度，从而提高到了系统性能。
区别于现有技术，本发明的内存访问装置，接收到内存访问指令，所述内存访问指令包含待访问内存地址；获取系统的当前安全性状态；在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述 数据的高速缓存行的状态设置为所述系统的当前安全性状态；从而能够提高系统的性能。
参阅图3，图3是本发明提供的内存访问方法第一实施方式的流程示意图，该方法可用于基于Trustzone技术的系统中。
该方法的步骤包括：
S301：接收到内存访问指令，所述内存访问指令包含待访问内存地址。
例如，系统在运行应用程序的过程中，需要访问指定内存地址的数据，处理器将接收到该内存访问指令。
S302：获取系统的当前安全性状态。
具体的，所述系统通过处理器核的状态位来标识当前安全性状态，所述获取系统的当前安全性状态的方法具体为获取处理器核中状态位的值。
具体的，系统的状态可以是安全状态或者不安全状态；处理器核的状态位，例如是NS，当NS＝1时标识当前系统处于非安全状态，NS＝0标识当前系统处于安全状态。当系统处于非安全状态时，仅可以访问非安全状态的资源，包括内存和外部设备，并执行对安全性要求不高的操作，例如访问普通网页，而当处于安全状态时，可以访问所有资源，并执行例如银行支付等要求安全性高的操作。
S303：在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
其中，所述高速缓存行通过tag来标识状态，所述在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行具体为：在所述高速缓存中确定是否存在其tag值和所述系统的当前安全性状态相同，且包含所述待访问内存地址中数据的高速缓存行。
其中，高速缓存包含TLB和cache。为了加快内存的访问速度，会将部分常用的内存数据提前加载到高速缓存中，用于存放内存数据的单位称为高速缓存行(Line)，本方案为每个Line扩展了一个tag，用于标识该Line的状态(安全或者不安全)；对于已经加载的数据，高速缓存中同时会包含该数据在内存中 的逻辑地址，对于部分加载的数据，高速缓存中还包含该数据中未加载部分数据在内存中的逻辑地址和物理地址。可以是通过对高速缓存逐行(Line)扫描，查找其状态和系统当前安全性状态相同、且包含待访问内存地址的高速缓存行，如果找到了满足条件的高速缓存行，说明数据已经加载到高速缓存，可以直接访问、则返回给处理器核；如果找不到说明数据还在内存中，需要实时从内存的待访问地址中将数据加载到高速缓存中，同时将存放该实时加载数据的高速缓存行的状态设置为系统当前安全性状态。
进一步可选的，所述如果不存在则从内存中读取数据至高速缓存中具体为：确定当前高速缓存是否空间满了；如果是，则优先将其状态和所述系统当前安全性状态不同的高速缓存行中的数据抛弃，将所述从内存中读取的所述待访问内存地址的数据保存到所述高速缓存行；如果否，则将所述从内存中读取的所述待访问内存地址的数据保存到空闲的高速缓存行。
因此，当需要实时从内存中加载收据到高速缓存时，首先判断高速缓存的空间是否满，如果满了则首先将状态和系统当前安全性状态不同的高速缓存行中的数据刷出，例如当前处于安全状态，则首先将非安全状态的数据刷出，当前处于非安全状态，则首先将安全状态的数据刷出。
可选的，如果所述系统的当前安全性状态为安全，且所述待访问内存地址属于不安全类型的内存地址；所述在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行具体为：在高速缓存中确定是否存在状态为不安全状态、且包含所述待访问内存地址中数据的高速缓存行。因为安全状态的进程可以访问非安全状态的内存，此时，需要将安全进程的状态也当做非安全状态来操作，以便找到正确的数据。
通过为高速缓存行增加状态，高速缓存中可以同时存在安全和不安全的数据，并且互相隔离，系统可以灵活调用，从而避免了系统每次切换状态时都需要将数据全部刷出，提高下次加载数据的速度，从而提高到了系统性能。
区别于现有技术，本发明的基于Trustzone技术的内存访问装置，接收到内存访问指令，所述内存访问指令包含待访问内存地址；获取系统的当前安全性状态；在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速 缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态；从而能够提高系统性能。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种内存访问装置，其特征在于，包括：
    指令接收模块，用于接收内存访问指令，所述内存访问指令包含待访问内存地址；
    状态获取模块，用于获取系统的当前安全性状态；
    内存访问处理模块，用于在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
  2. 根据权利要求1所述的内存访问装置，其特征在于，所述系统通过处理器核的状态位来标识当前安全性状态，所述状态获取模块包括状态位获取单元，用于获取处理器核中状态位的值。
  3. 根据权利要求1或2所述的内存访问装置，其特征在于，所述高速缓存行通过tag来标识状态，所述内存访问处理模块包括第一判断单元，第一高速缓存直接读取单元，第一高速缓存间接读取单元；
    所述第一判断单元，用于在所述高速缓存中确定是否存在其tag值和所述系统的当前安全性状态相同，且包含所述待访问内存地址中数据的高速缓存行；
    所述第一高速缓存直接读取单元，用于当所述第一判断单元的确定结果为是则返回所述高速缓存行中的数据；
    所述第一高速缓存间接读取单元，用于当所述第一判断单元的确定结果为否则从内存中读取所述待访问内存地址的数据至高速缓存，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
  4. 根据权利要求1或2所述的内存访问装置，其特征在于，所述内存访问处理模块包括第二判断单元，第二高速缓存直接读取单元，第二高速缓存间接读取单元；
    所述第二判断单元，用于在所述高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行；
    所述第二高速缓存直接读取单元，用于当所述第二判断单元的确定结果为是则返回所述高速缓存行中的数据；
    所述第二高速缓存间接读取单元包括空间状态判断子单元，空间不足处理 子单元，空间充足处理子单元；
    所述空间状态判断子单元，用于在所述第二判断单元的确定结果为否时判断当前高速缓存是否空间满了；
    所述空间不足处理子单元，用于在所述空间状态判断子单元的判断结果为是时，优先将其状态和所述系统当前安全性状态不同的高速缓存行中的数据抛弃，从内存中读取所述待访问内存地址的数据保存到所述高速缓存行，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态；
    所述空间充足处理子单元，用于在所述空间状态判断子单元的判断结果为否时，从内存中读取所述待访问内存地址的数据保存到空闲的高速缓存行，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
  5. 根据权利要求1或2所述的内存访问装置，其特征在于，所述内存访问处理模块包括第三判断单元，第三高速缓存直接读取单元，第三高速缓存间接读取单元；
    所述第三判断单元，用于在当所述系统的当前安全性状态为安全，且所述待访问内存地址属于不安全类型的内存地址时，在所述高速缓存中确定是否存在状态为不安全状态、且包含所述待访问内存地址中数据的高速缓存行；
    所述第三高速缓存直接读取单元，用于在所述第三判断单元的确定结果为是时则返回所述高速缓存行中的数据；
    所述第三高速缓存间接读取单元，用于在所述第三判断单元的确定结果为否时则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
  6. 一种内存访问方法，其特征在于，包括：
    接收到内存访问指令，所述内存访问指令包含待访问内存地址；
    获取系统的当前安全性状态；
    在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行，如果存在则返回所述高速缓存行中的数据，如果不存在则从内存中读取所述待访问内存地址的数据至高速缓存中，并将存放所述数据的高速缓存行的状态设置为所述系统的当前安全性状态。
  7. 根据权利要求6所述的内存访问方法，其特征在于，所述系统通过处理器核的状态位来标识当前安全性状态，所述获取系统的当前安全性状态的方法 具体为获取处理器核中状态位的值。
  8. 根据权利要求6或7所述的内存访问方法，其特征在于，所述高速缓存行通过tag来标识状态，所述在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行具体为：在所述高速缓存中确定是否存在其tag值和所述系统的当前安全性状态相同，且包含所述待访问内存地址中数据的高速缓存行。
  9. 根据权利要求6或7所述的内存访问方法，其特征在于，所述如果不存在则从内存中读取数据至高速缓存中具体为：确定当前高速缓存是否空间满了；如果是，则优先将其状态和所述系统当前安全性状态不同的高速缓存行中的数据抛弃，将所述从内存中读取的所述待访问内存地址的数据保存到所述高速缓存行；如果否，则将所述从内存中读取的所述待访问内存地址的数据保存到空闲的高速缓存行。
  10. 根据权利要求6或7所述的内存访问方法，其特征在于，如果所述系统的当前安全性状态为安全，且所述待访问内存地址属于不安全类型的内存地址；所述在高速缓存中确定是否存在状态和所述系统的当前安全性状态相同、且包含所述待访问内存地址中数据的高速缓存行具体为：在高速缓存中确定是否存在状态为不安全状态、且包含所述待访问内存地址中数据的高速缓存行。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105677581A (zh) * 2016-01-05 2016-06-15 上海斐讯数据通信技术有限公司 一种内存访问装置和方法
US10831664B2 (en) * 2017-06-16 2020-11-10 International Business Machines Corporation Cache structure using a logical directory
US10606762B2 (en) 2017-06-16 2020-03-31 International Business Machines Corporation Sharing virtual and real translations in a virtual cache
US10698836B2 (en) 2017-06-16 2020-06-30 International Business Machines Corporation Translation support for a virtual cache
CN111221775B (zh) * 2018-11-23 2023-06-20 阿里巴巴集团控股有限公司 处理器、缓存处理方法及电子设备
CN111767536B (zh) * 2019-04-01 2024-03-22 中国农业大学 一种抵抗处理器投机访问漏洞的cache防护方法及装置
CN113835615A (zh) * 2020-09-17 2021-12-24 北京焱融科技有限公司 一种基于分布式文件存储的智能分层方法和系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101303721A (zh) * 2007-05-02 2008-11-12 Arm有限公司 减少共享高速缓存的进程之间的信息泄漏
CN101438290A (zh) * 2006-05-01 2009-05-20 联发科技股份有限公司 用于包括处理器和缓存虚拟存储器的系统中的安全语境切换的方法和装置
CN102346715A (zh) * 2010-07-30 2012-02-08 国际商业机器公司 保护内存中应用程序的方法、内存控制器和处理器
CN104573565A (zh) * 2015-01-23 2015-04-29 宇龙计算机通信科技(深圳)有限公司 一种TrustZone上的内存管理方法及装置
US20150301957A1 (en) * 2014-04-16 2015-10-22 Elliptic Technologies Inc. Secured memory system and method therefor
CN105677581A (zh) * 2016-01-05 2016-06-15 上海斐讯数据通信技术有限公司 一种内存访问装置和方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0226874D0 (en) * 2002-11-18 2002-12-24 Advanced Risc Mach Ltd Switching between secure and non-secure processing modes
CN103902470B (zh) * 2012-12-25 2017-10-24 华为技术有限公司 读缺失时的处理方法、设备和系统
CN104252392B (zh) * 2013-06-28 2019-06-18 华为技术有限公司 一种访问数据缓存的方法和处理器
CN104834608B (zh) * 2015-05-12 2017-09-29 华中科技大学 一种异构内存环境下的缓存替换方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101438290A (zh) * 2006-05-01 2009-05-20 联发科技股份有限公司 用于包括处理器和缓存虚拟存储器的系统中的安全语境切换的方法和装置
CN101303721A (zh) * 2007-05-02 2008-11-12 Arm有限公司 减少共享高速缓存的进程之间的信息泄漏
CN102346715A (zh) * 2010-07-30 2012-02-08 国际商业机器公司 保护内存中应用程序的方法、内存控制器和处理器
US20150301957A1 (en) * 2014-04-16 2015-10-22 Elliptic Technologies Inc. Secured memory system and method therefor
CN104573565A (zh) * 2015-01-23 2015-04-29 宇龙计算机通信科技(深圳)有限公司 一种TrustZone上的内存管理方法及装置
CN105677581A (zh) * 2016-01-05 2016-06-15 上海斐讯数据通信技术有限公司 一种内存访问装置和方法

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