WO2017113191A1 - 头戴式显示设备 - Google Patents

头戴式显示设备 Download PDF

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Publication number
WO2017113191A1
WO2017113191A1 PCT/CN2015/099871 CN2015099871W WO2017113191A1 WO 2017113191 A1 WO2017113191 A1 WO 2017113191A1 CN 2015099871 W CN2015099871 W CN 2015099871W WO 2017113191 A1 WO2017113191 A1 WO 2017113191A1
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WO
WIPO (PCT)
Prior art keywords
voltage
circuit
display device
output
power input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/099871
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English (en)
French (fr)
Inventor
施宏艳
郭继龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Royole Technologies Co Ltd
Original Assignee
Shenzhen Royole Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to CN201580075340.3A priority Critical patent/CN107209379B/zh
Priority to PCT/CN2015/099871 priority patent/WO2017113191A1/zh
Publication of WO2017113191A1 publication Critical patent/WO2017113191A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/01—Head-up displays
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones

Definitions

  • the present invention relates to display devices, and more particularly to a head mounted display device.
  • the embodiment of the invention discloses a head-mounted display device, which can charge the head-mounted display device anytime and anywhere by using a portable solar panel, satisfies the requirement of battery life and does not increase the volume of the head-mounted display device and weight.
  • a head-mounted display device includes a display device, an earphone device, a solar panel disposed on a surface of the display device and/or the earphone device, and a voltage stabilization control disposed inside the display device or the earphone device Circuit.
  • the solar panel is configured to convert solar energy into electrical energy
  • the voltage stabilizing control circuit is configured to voltage the power voltage output by the solar panel to a predetermined voltage, and supply the display device and the earphone device with the predetermined voltage.
  • the head-mounted display device of the present invention supplies power through the solar panel, improves the endurance capability, and only needs a small-capacity built-in battery, which is advantageous for the lightness of the head-mounted display device.
  • the head-mounted display device of the present invention can charge the head-mounted display device anytime and anywhere by using a portable solar panel, which satisfies the requirements of battery life without increasing the size and weight of the head-mounted display device.
  • FIG. 1 is a perspective view of a head mounted display device in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a solar panel of a head mounted display device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a light path of a solar panel of a head mounted display device according to an embodiment of the invention
  • FIG. 4 is a structural block diagram of a voltage stabilizing control circuit of a head mounted display device according to an embodiment of the present invention
  • FIG. 5 is a specific circuit diagram of a voltage stabilizing control circuit of a head mounted display device according to an embodiment of the present invention.
  • FIG. 1 is a perspective view of a head mounted display device 100 according to an embodiment of the invention.
  • the head mounted display device 100 includes a display device 10, an earphone device 20, a solar panel 30 disposed on a surface of the display device 10 and/or the earphone device 20, and a voltage stabilizing control circuit 40 (shown in FIG. 4).
  • the solar panel 30 is configured to convert solar energy into electrical energy.
  • the voltage stabilizing control circuit 40 is configured to regulate the electrical energy output by the solar panel 30 to a predetermined voltage, and supply power to the display device 10 and the earphone device 20 at the predetermined voltage.
  • the predetermined voltage is a normal operating voltage of the display device 10 and the earphone device 20, for example, 5 volts.
  • the solar panel 30 by using the solar panel 30, charging or pairing can be performed anytime and anywhere
  • the head mounted display device 100 is powered, and the battery of the head mounted display device 100 can be made smaller, improving the endurance and facilitating the head mounted display device 100 to reduce the size and weight.
  • the earphone device 20 includes an endless belt 21 and an earpiece 22 disposed at both ends of the endless belt 21.
  • the number of the solar panels 30 is at least two, which are respectively disposed on an outer surface of the display device 10 and an outer surface of the endless belt 21 of the earphone device 20, and the solar panels are respectively disposed. 30 parallel or series to form a solar battery pack.
  • the voltage stabilizing control circuit 40 is coupled to all of the solar panels 30 for converting the total output electrical energy of all of the solar panels 30 to a predetermined voltage to power the display device 10 and the earphone device 20.
  • the solar cell panel 30 includes aspherical microlens layer 31 and a photoelectric conversion layer 32 which are stacked.
  • the aspherical microlens layer 31 is used to conduct solar light convergence to the photoelectric conversion layer 32.
  • the photoelectric conversion layer 32 is used for photoelectric conversion to convert sunlight into electrical energy.
  • the aspherical microlens layer 31 has a wavy aspherical surface on the outer surface thereof, which can increase the light-receiving area.
  • each microlens has a small focusing spot and a high energy density, and the light is effectively concentrated.
  • the photoelectric conversion efficiency of the photoelectric conversion layer 32 is improved.
  • the aspherical microlens layer 31 can be made of a highly transparent material (polymer material or glass) material, and both sides of the aspherical microlens layer 31 are plated with a visible-near infrared antireflection film for increasing visible light and near infrared. Light penetration rate.
  • the photoelectric conversion layer 32 may include a plurality of semiconductor photodiodes arranged in an array, and when the sunlight is conducted to the semiconductor photodiode through the aspherical microlens layer 31, the semiconductor photodiode converts the light energy into electrical energy.
  • the voltage regulator control circuit 40 includes a power input interface 41, a voltage detecting unit 42, a boosting circuit 43, a step-down circuit 44, a circuit selecting unit 45, and a power output interface 46.
  • the power input interface 41 is for connecting to the solar panel 30 and receiving the electrical energy converted by the solar panel 30.
  • the voltage detecting unit 42 is configured to detect the voltage of the power input by the power input interface 41.
  • the boosting circuit 43 and the step-down circuit 44 are electrically connected in parallel between the power input interface 41 and the power output interface 46.
  • the circuit selecting unit 45 is configured to compare the voltage detected by the voltage detecting unit 42 with a predetermined voltage, and establish a connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is less than the predetermined voltage.
  • the connection between the buck circuit 44 and the power input interface 41 is disconnected.
  • the boosting circuit 43 boosts the power voltage input by the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the earphone devices 20 through the power output interface 46.
  • Functional components are configured to compare the voltage detected by the voltage detecting unit 42 with a predetermined voltage, and establish a connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is less than the predetermined voltage.
  • the connection between the buck circuit 44 and the power input interface 41 is disconnected.
  • the boosting circuit 43 boosts the power voltage input by the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the
  • the circuit selecting unit 45 establishes a connection between the step-down circuit 44 and the power input interface 41 to disconnect the connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is greater than the predetermined voltage.
  • the step-down circuit 44 steps down the power voltage connected to the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the earphone devices 20 through the power output interface 46.
  • the boosting circuit 43 or the step-down circuit 44 can be automatically operated in accordance with the level of the voltage output from the solar panel 30, and the output voltage is maintained at a predetermined voltage, thereby maintaining a stable voltage supply.
  • the voltage stabilization control circuit 40 further includes a first path switch 47 and a second path switch 48.
  • the first path switch 47 is electrically connected between the power input interface 41 and the boost circuit 43.
  • the second path switch 48 is electrically connected between the power input interface 41 and the step-down circuit 44.
  • the circuit selection unit 45 is connected to the first path switch 47 and the second path switch 48. When it is determined that the detected voltage is less than the predetermined voltage, the first path switch 47 is controlled to be turned on and the second path switch 48 is turned off. A connection between the booster circuit 43 and the power input interface 41 is established to disconnect the buck circuit 44 from the power input interface 41.
  • the circuit selecting unit 45 controls the first path switch 47 to be turned off and the second path switch 48 to be turned on when determining that the detected voltage is greater than the predetermined voltage, thereby establishing a connection between the step-down circuit 44 and the power input interface 41. The connection between the booster circuit 43 and the power input interface 41 is disconnected.
  • FIG. 5 is a specific circuit diagram of the voltage stabilization control circuit 40 according to an embodiment of the present invention.
  • the voltage detecting unit 42 includes resistors R1, R2 connected in series between the positive terminal V+ and the ground terminal V- of the power input interface 41.
  • the circuit selection unit 45 includes a detection terminal AD_IN, a first enable terminal EN1, and a second enable terminal. EN2.
  • the detecting terminal AD_IN is connected to the connection node of the resistor R1 and the resistor R2 for obtaining the voltage of the connection node of the resistor R1 and the resistor R2.
  • the circuit selection unit 45 compares the voltage received by the detection terminal AD_IN with a first reference voltage Vr1, and determines the output of the power input interface 41 when the voltage received by the comparison detection terminal AD_IN is greater than the first reference voltage Vr1.
  • the voltage is greater than the predetermined voltage, and the second enable terminal EN2 is controlled to output a high level enable signal, and the first enable terminal EN1 outputs a low level signal.
  • the circuit selecting unit 45 determines that the voltage output by the power input interface 41 is less than the predetermined voltage when the voltage received by the detecting terminal AD_IN is less than the first reference voltage Vr1, and controls the second enabling terminal EN2 to output a low level signal. , EN1 outputs a high level enable signal.
  • the first reference voltage Vr1 predetermined voltage*R2/(R1+R2), so that when the voltage output by the power input interface 41 is greater than the predetermined voltage, the voltage received by the detecting terminal AD_IN will also be greater than the first The reference voltage Vr1, when the voltage output by the power input interface 41 is less than the predetermined voltage, the voltage received by the detecting terminal AD_IN will also be less than the first reference voltage Vr1.
  • the first path switch 47 includes a PMOS transistor Q1 and an NPN transistor Q2.
  • the source of the PMOS transistor Q1 is connected to the positive terminal V+ of the power input interface 41, the drain is connected to the boosting circuit 43, and the gate is connected to the NPN transistor Q2.
  • the emitter of the NPN transistor Q2 is grounded, and the base is connected to the first enable terminal EN1 of the circuit selection unit 45.
  • the NPN transistor Q2 receives the high level enable signal from the first enable terminal EN1
  • the NPN transistor Q2 is turned on, and the gate of the PMOS transistor Q1 is grounded through the turned-on NPN transistor Q2 and is also turned on.
  • the first path switch 47 turns on the electrical connection between the positive terminal V+ of the power input interface 41 and the boosting circuit 43.
  • the second path switch 48 includes a PMOS transistor Q3 and an NPN transistor Q4.
  • the source of the PMOS transistor Q3 is connected to the positive terminal V+ of the power input interface 41, the drain is connected to the step-down circuit 44, and the gate is connected to the NPN transistor Q4.
  • the emitter of the NPN transistor Q4 is grounded, and the base is connected to the second enable terminal EN2 of the circuit selection unit 45.
  • the NPN transistor Q4 receives the high level enable signal from the second enable terminal EN2
  • the NPN transistor Q4 is turned on, the PMOS
  • the gate of the transistor Q3 is also turned on by the conduction of the turned-on NPN transistor Q4.
  • the second path switch 48 turns on the electrical connection between the positive terminal V+ of the power input interface 41 and the step-down circuit 44.
  • the booster circuit 43 includes a boost controller 431, an NMOS transistor Q5, an inductor L1, a capacitor C1, a diode D1, and an output terminal Vcc1.
  • the inductor L1 and the capacitor C1 form an LC filter tank circuit.
  • the boost controller 431 includes a voltage terminal vin1 and a PWM (plus width modulation) output terminal sw1.
  • the voltage terminal vin1 is used to connect to the positive terminal V+ of the power input interface 41 to receive the operating voltage.
  • the PWM output terminal sw1 is connected to the gate of the NMOS transistor Q5 for outputting a PWM signal to the NMOS transistor Q5.
  • the first end P11 of the inductor L1 is electrically connected to the source of the PMOS transistor Q1 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the second end P12 of the inductor L1 is connected to the anode of the diode D1 and the source of the NMOS transistor Q5.
  • the cathode of the diode D1 is connected to the output terminal Vcc1.
  • the drain of the NMOS transistor Q5 is grounded through a resistor R3.
  • the boost controller 431 controls the PMOS transistor Q1 to be turned on to establish an electrical connection between the power input interface 41 and the booster circuit 43, the PWM output Sw1 outputs A PWM signal having a certain duty cycle causes the NMOS transistor Q5 to be turned on and off periodically.
  • the PWM signal is at a high level
  • the NMOS transistor Q5 is turned on, and at this time, the inductor L1 forms a current loop through the turned-on NMOS transistor Q5, and current flows from the power input interface 41 through the PMOS transistor Q1.
  • the D1 cutoff does not conduct, and the voltage across the capacitor C2 is equal to the output voltage Vcc1.
  • the NMOS transistor Q5 When the PWM signal is at a low level, the NMOS transistor Q5 is turned off, and the inductor L1 generates a right positive left negative negative electromotive force, and the back electromotive force is superimposed with the voltage output from the power input interface 41 and larger than the voltage output by the power input interface 41.
  • the output voltage of the second terminal P12 of the inductor L1 is substantially equal to the sum of the voltage output from the power input interface 41 and the counter electromotive force generated by the inductor L1.
  • the output voltage of the second terminal P12 of the inductor L1 will be approximately equal to the 0V voltage for a period of time, and for a further period of time greater than the voltage output by the power input interface 41.
  • the equivalent voltage of the voltage outputted by the output terminal Vcc1 will be greater than the voltage outputted by the power input interface 41, and the boosting effect is exerted.
  • the functional element 50 of the head mounted display device 100 is thereby powered by the power output interface 46.
  • the functional component 50 is a respective power consuming component in the display device 10 and the earphone device 20.
  • the boosting circuit 43 further includes a capacitor C2 connected between the cathode of the diode D1, the output terminal Vcc1 and the ground for filtering and further regulating the voltage outputted by the output terminal Vcc1.
  • the booster circuit 43 further includes a resistor R4 and a resistor R5 connected in series between the output terminal Vcc1 and the ground.
  • the boost controller 431 is further configured to control a duty ratio of the PWM signal output by the PWM output terminal sw1 according to the feedback voltage Vref1 received by the feedback terminal F1, so that the output voltage of the output terminal Vcc1 is maintained at the predetermined voltage, for example, Maintain at 5V.
  • the boost controller 431 compares the feedback voltage Vref1 with the second reference voltage Vr2. If the feedback voltage Vref1 is greater than the second reference voltage Vr2, it is determined that the output voltage of the output terminal Vcc1 is greater than the predetermined voltage.
  • the boost controller 431 controls the duty ratio of the PWM signal that reduces the output such that the time greater than the voltage output by the power input interface 41 in one cycle becomes shorter, thereby reducing the output voltage of the output terminal Vcc1.
  • the boost controller 431 controls the duty ratio of the PWM signal that increases the output, so that one cycle The time larger than the voltage output from the power input interface 41 becomes longer, thereby increasing the output voltage of the output terminal Vcc1.
  • the output voltage of the output terminal Vcc1 is maintained at the predetermined voltage.
  • the second reference voltage Vr2 predetermined voltage*R4/(R3+R4).
  • the boost controller 431 further includes a detecting end Dt1 connected to the connection node of the NMOS transistor Q5 and the resistor R3 for detecting the current flowing through the NMOS transistor Q5, and detecting according to the detected The current is overcurrent protected to avoid damage to the NMOS transistor Q5. Specifically, when the current detected by the detecting terminal Dt1 is greater than an overcurrent protection value, the boost controller 431 controls to reduce the duty ratio of the PWM signal output by the PWM output terminal sw1 or directly turn off the output of the PWM waveform. Therefore, the current flowing through the NMOS transistor Q5 becomes small.
  • the buck circuit 44 includes a buck controller 441, an NMOS transistor Q6, and an inductor. L2, capacitor C3, diode D2 and output terminal Vcc2. This capacitor C3 is used for energy storage filtering.
  • the buck controller 441 includes a voltage terminal vin2 and a PWM output terminal sw2. The voltage terminal vin2 is used to connect to the positive terminal V+ of the power input interface 41 to receive an operating voltage.
  • the PWM output terminal sw2 is connected to the gate of the NMOS transistor Q6 for outputting a PWM signal to the NMOS transistor Q6.
  • the source of the NMOS transistor Q6 is connected to the drain of the PMOS transistor Q3 and one end of the capacitor C3, and the drain of the NMOS transistor Q6 is connected to the first terminal P21 of the inductor L2 and the cathode of the diode D2.
  • the other end of the capacitor C3 is grounded to the anode of the diode D2.
  • the second end P22 of the inductor L2 is electrically connected to the output terminal Vcc2.
  • the circuit selection unit 45 controls the PMOS transistor Q3 to be turned on to establish an electrical connection between the power input interface 41 and the step-down circuit 44, and the PWM output terminal sw2 has an output.
  • a certain duty cycle PWM signal causes the NMOS transistor Q6 to be turned on and off periodically.
  • the NMOS transistor Q6 is turned on.
  • the current output from the power input interface 41 passes through the PMOS transistor Q3, the NMOS transistor Q6 flows to the inductor L2, and passes through the inductor.
  • L2 is output to the output terminal Vcc2.
  • the sum of the voltage of the second terminal P22 of the inductor L2 and the voltage output by the power input interface 41 is equal to V+ of the power input interface 41.
  • the NMOS transistor Q6 When the PWM signal is at a low level, the NMOS transistor Q6 is turned off, the electrical connection between the power input interface 41 and the inductor L2 is broken, and the inductor L2 generates a right positive left negative negative electromotive force, which is substantially equal to the output voltage Vcc2. At this time, the output voltage of the second terminal P22 of the inductor L2 is smaller than the voltage output by the power input interface 41. Thus, during one PWM signal period, the output voltage of the second terminal P22 of the inductor L2 will be equal to the output voltage Vcc2 for a period of time, and less than the voltage output by the power input interface 41 for another period of time.
  • the equivalent voltage of the voltage outputted by the output terminal Vcc2 will be smaller than the voltage output by the power input interface 41, and the voltage drop effect is achieved.
  • the voltage output by the output terminal Vcc2 supplies power to the functional elements 50 of the head mounted display device 100 through the power output interface 46.
  • the buck circuit 44 further includes a capacitor C4 connected between the second end P22 of the inductor L2, the output terminal Vcc2 and the ground for filtering and further regulating the voltage outputted by the output terminal Vcc2. .
  • the step-down circuit 44 further includes a resistor R6 and a resistor R7 connected in series between the output terminal Vcc2 and the ground.
  • the buck controller 441 further includes a feedback terminal F2, the feedback terminal F2 and the resistor R6 and the resistor
  • the buck controller 441 is further configured to control the duty ratio of the PWM signal output by the PWM output terminal sw2 according to the feedback voltage Vref2 received by the feedback terminal F2, so that the output voltage of the output terminal Vcc2 is maintained at the predetermined voltage, for example, Maintain at 5V.
  • the buck controller 441 compares the feedback voltage Vref2 with the third reference voltage Vr3. If the feedback voltage Vref2 is greater than the third reference voltage Vr3, it is determined that the output voltage of the output terminal Vcc2 is greater than the predetermined voltage.
  • the buck controller 441 controls the duty ratio of the PWM signal that reduces the output such that the time less than the voltage output by the power input interface 41 in one cycle becomes longer, thereby reducing the output voltage of the output terminal Vcc2.
  • the buck controller 441 controls the duty ratio of the PWM signal to increase the output so that one cycle
  • the sum of the internal inductor voltage and the output voltage Vcc2 is equal to the time of the voltage outputted by the power input interface 41, thereby increasing the output voltage of the output terminal Vcc2.
  • the output voltage of the output terminal Vcc2 is maintained at the predetermined voltage.
  • the third reference voltage Vr3 predetermined voltage*R7/(R6+R7).
  • the power output terminal 46 of the voltage regulator control circuit 40 can be a USB interface, and the output terminal Vcc1 of the boosting circuit 43 and the output terminal Vcc2 of the voltage reducing circuit 44 are both connected to the power supply pin VCC of the power output terminal 46. connection.
  • the head mounted display device 100 further includes a battery 60.
  • the power output 46 is also connected to the battery 60.
  • the boost circuit 43 or the step-down circuit 44 boosts or steps down the power voltage of the solar panel 30.
  • the battery 60 is charged.
  • the circuit selection unit 45 further includes a voltage terminal Vin connected to the battery 60 to receive an operating voltage from the battery 60.
  • the battery 60 can be a battery with a small capacity, so that it can be made thin and light. Since the solar panel 30 can be charged at any time, it does not affect the endurance of the head mounted display device 100.
  • the MOS tube of the present invention can be replaced by a BJT transistor, an IGBT, etc.
  • the triode can be replaced by a MOS tube and an IGBT, and the types of the MOS tube and the triode are also interchangeable.
  • the PMOS tube Q1 and Q3 can also be NMOS transistors.
  • the NPN transistors Q2 and Q4 can be PNP transistors, and the NMOS transistors Q5 and Q6 can also be PMOS transistors.

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Abstract

一种头戴式显示设备，包括显示装置(10)、耳机装置(20)、设置于显示装置(10)和/或耳机装置(20)的表面上的太阳能电池板(30)以及设置于显示装置(10)或耳机装置(20)内部的稳压控制电路(40)。该太阳能电池板(30)用于将太阳能转换为电能，该稳压控制电路(40)用于将太阳能电池板(30)输出的电能电压稳压成一预定电压，并以所述预定电压为显示装置(10)及耳机装置(20)供电。该头戴式显示设备通过太阳能电池板(30)进行供电，提高了续航能力，且仅需要小容量的内置电池即可，有利于头戴式显示设备的轻巧化。

Description

头戴式显示设备 技术领域
本发明涉及显示设备，尤其涉及一种头戴式显示设备。
背景技术
目前的头戴式显示设备，为了让用户穿戴方便或携带方便，往轻便方向发展是趋势。然而，由于头戴式显示设备的功耗较大，为了保持续航能力，又需要配备较大容量的电池，则将增加头戴式显示设备的重量与体积。因此，续航能力和轻便成了难以调和的矛盾。目前有些处理方式为通过对硬件设计进行改进而减小功耗，然而，该种硬件的设计较复杂，造成了成本的增加且会带来一定的不稳定因素。
发明内容
本发明实施例公开一种头戴式显示设备，通过采用轻便的太阳能电板，可随时随地对头戴式显示设备进行充电，满足了续航的要求且不会增加头戴式显示设备的体积和重量。
本发明实施例公开的一种头戴式显示设备，包括显示装置、耳机装置、设置于显示装置和/或耳机装置的表面上的太阳能电池板以及设置于显示装置或耳机装置内部的稳压控制电路。该太阳能电池板用于将太阳能转换为电能，该稳压控制电路用于将太阳能电池板输出的电能电压稳压成一预定电压，并以所述预定电压为显示装置及耳机装置供电。本发明的头戴式显示设备通过太阳能电池板进行供电，提高了续航能力，且仅需要小容量的内置电池即可，有利于头戴式显示设备的轻巧化。
本发明的头戴式显示设备，通过采用轻便的太阳能电板，可随时随地对头戴式显示设备进行充电，满足了续航的要求且不会增加头戴式显示设备的体积和重量。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的明显变形方式。
图1为本发明一实施例中的头戴式显示设备的立体示意图；
图2为本发明一实施例中的头戴式显示设备的太阳能电池板的结构示意图；
图3为本发明一实施例中的头戴式显示设备的太阳能电池板的光线光路示意图；
图4为本发明一实施例中的头戴式显示设备的稳压控制电路的结构框图；
图5为本发明一实施例中的头戴式显示设备的稳压控制电路的具体电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，为本发明一实施例中的头戴式显示设备100的立体示意图。该头戴式显示设备100包括显示装置10、耳机装置20、设置于显示装置10和/或耳机装置20的表面上的太阳能电池板30以及稳压控制电路40(如图4所示)。该太阳能电池板30用于将太阳能转换为电能，该稳压控制电路40用于将太阳能电池板30输出的电能稳压成一预定电压，并以该预定电压为显示装置10及耳机装置20供电。该预定电压为显示装置10及耳机装置20的正常工作电压，例如为5伏。
从而，本发明中，通过采用太阳能电池板30，可随时随地进行充电或对 头戴式显示设备100供电，头戴式显示设备100的电池可以做的比较小，提高了续航能力且有利于头戴式显示设备100减小体积和重量。
该耳机装置20包括环带21及设置于环带21两端的听筒22。在本实施例中，如图1所示，该太阳能电池板30的数量为至少两个，分别设置于显示装置10的外表面和耳机装置20的环带21的外表面，该些太阳能电池板30并联或串联而构成一太阳能电池组。该稳压控制电路40与所有太阳能电池板30连接，用于将所有太阳能电池板30的总输出电能转换成预定电压为显示装置10及耳机装置20供电。
请一并参阅图2，为太阳能电池板30的结构示意图。该太阳能电池板30包括层叠设置的非球面微透镜层31以及光电转换层32。该非球面微透镜层31用于将太阳光汇聚传导至光电转换层32。该光电转换层32用于进行光电转换，将太阳光转换成电能。
请一并参阅图3，为太阳光经过非球面微透镜层31传输的光线光路图。该非球面微透镜层31的外表面上为波浪形的非球面，可增大采光面积；另外，由于采用非球面，每个微透镜对应的聚焦光斑小，能量密度高，将光线有效的汇聚在光电转换层32上，提高光电转换层32的光电转换效率。
其中，该非球面微透镜层31可为高透材料(高分子材料或玻璃)材料制成，非球面微透镜层31的两面均镀可见-近红外增透膜，用于增加可见光与近红外光的穿透率。
其中，该光电转换层32可包括呈阵列式排列的若干半导体光电二极管，当太阳光通过非球面微透镜层31传导至半导体光电二极管时，半导体光电二极管将光能转换成电能。
请一并参阅图4，为稳压控制电路40的结构框图。该稳压控制电路40包括电源输入接口41、电压侦测单元42、升压电路43、降压电路44、电路选择单元45以及电源输出接口46。
该电源输入接口41用于与太阳能电池板30连接，接收太阳能电池板30所转换出的电能。电压侦测单元42用于侦测电源输入接口41所接入的电能的电压。所述升压电路43与降压电路44以并联的方式电连接于电源输入接口41与电源输出接口46之间。
该电路选择单元45用于将该电压侦测单元42侦测的电压与预定电压进行比较，当判断侦测的电压小于该预定电压时，建立升压电路43与电源输入接口41之间的连接而断开降压电路44与电源输入接口41之间的连接。此时，升压电路43将电源输入接口41所接入的电能电压升压至该预定电压，并通过电源输出接口46提供给头戴式显示设备100的显示装置10以及耳机装置20中的各个功能元件。
该电路选择单元45在判断侦测的电压大于该预定电压时，建立降压电路44与电源输入接口41之间的连接而断开升压电路43与电源输入接口41之间的连接。此时，降压电路44将电源输入接口41所接入的电能电压降压至该预定电压，并通过电源输出接口46提供给头戴式显示设备100的显示装置10以及耳机装置20中的各个功能元件。
从而，本发明中，可自动根据太阳能电池板30输出的电压的高低选择升压电路43或降压电路44工作，维持输出的电压为预定电压，维持了稳定的电压供应。
其中，如图4所示，该稳压控制电路40还包括第一路径开关47以及第二路径开关48。该第一路径开关47电连接于该电源输入接口41与该升压电路43之间。该第二路径开关48电连接于该电源输入接口41与该降压电路44之间。
该电路选择单元45与该第一路径开关47以及第二路径开关48连接，在判断侦测的电压小于该预定电压时，控制第一路径开关47导通以及第二路径开关48断开，从而建立升压电路43与电源输入接口41之间的连接而断开降压电路44与电源输入接口41之间的连接。
该电路选择单元45在判断侦测的电压大于该预定电压时，控制第一路径开关47断开以及第二路径开关48导通，从而建立降压电路44与电源输入接口41之间的连接而断开升压电路43与电源输入接口41之间的连接。
请参阅图5，为本发明一实施例中的稳压控制电路40的具体电路图。如图5所示，该电压侦测单元42包括串联于电源输入接口41的正极端V+以及接地端V-之间的电阻R1、R2。
电路选择单元45包括侦测端AD_IN、第一使能端EN1以及第二使能端 EN2。该侦测端AD_IN与该电阻R1与电阻R2的连接节点连接，用于获取该电阻R1与电阻R2的连接节点的电压。其中，该电阻R1与电阻R2的连接节点的电压与电源输入接口41的正极端V+输出的电压成正比例关系。设电源输入接口41的正极端V+输出的电压为V1，电阻R1与电阻R2的连接节点的电压为V2，则V2＝R2*V1/(R1+R2)。
该电路选择单元45将该侦测端AD_IN接收的电压与一第一参考电压Vr1进行比较，当比较侦测端AD_IN接收的电压大于该第一参考电压Vr1时，判断该电源输入接口41输出的电压大于该预定电压，并控制该第二使能端EN2输出高电平使能信号，第一使能端EN1输出低电平信号。
该电路选择单元45比较侦测端AD_IN接收的电压小于该第一参考电压Vr1时，判断该电源输入接口41输出的电压小于该预定电压，并控制该第二使能端EN2输出低电平信号，EN1输出高电平使能信号。其中，该第一参考电压Vr1＝预定电压*R2/(R1+R2)，从而，当电源输入接口41输出的电压大于该预定电压时，该侦测端AD_IN接收的电压也将大于该第一参考电压Vr1，当电源输入接口41输出的电压小于该预定电压时，该侦测端AD_IN接收的电压也将小于该第一参考电压Vr1。
该第一路径开关47包括PMOS管Q1以及NPN三极管Q2，该PMOS管Q1的源极与电源输入接口41的正极端V+连接，漏极与该升压电路43连接，栅极与NPN三极管Q2的集电极连接。该NPN三极管Q2的射极接地，基极与该电路选择单元45的第一使能端EN1连接。当该NPN三极管Q2接收到第一使能端EN1发出的高电平使能信号时，该NPN三极管Q2导通，该PMOS管Q1的栅极通过该导通的NPN三极管Q2接地而同样导通。此时，该第一路径开关47导通该电源输入接口41的正极端V+与该升压电路43之间的电连接。
该第二路径开关48包括PMOS管Q3以及NPN三极管Q4，该PMOS管Q3的源极与电源输入接口41的正极端V+连接，漏极与该降压电路44连接，栅极与NPN三极管Q4的集电极连接。该NPN三极管Q4的射极接地，基极与该电路选择单元45的第二使能端EN2连接。当该NPN三极管Q4接收到第二使能端EN2发出的高电平使能信号时，该NPN三极管Q4导通，该PMOS 管Q3的栅极通过该导通的NPN三极管Q4接地而同样导通。此时，该第二路径开关48导通该电源输入接口41的正极端V+与该降压电路44之间的电连接。
如图5所示，该升压电路43包括升压控制器431、NMOS管Q5、电感L1、电容C1、二极管D1及输出端Vcc1。该电感L1与电容C1构成一LC滤波储能电路。该升压控制器431包括一电压端vin1以及一PWM(plus width modulation，脉冲宽度调制)输出端sw1。该电压端vin1用于与该电源输入接口41的正极端V+连接而接收工作电压。该PWM输出端sw1与NMOS管Q5的栅极连接，用于输出PWM信号至该NMOS管Q5。
电感L1的第一端P11与PMOS管Q1的源极及电容C1的一端电连接，电容C1的另一端接地，电感L1的第二端P12与二极管D1的阳极以及该NMOS管Q5的源极连接，二极管D1的阴极与该输出端Vcc1连接。该NMOS管Q5的漏极通过一电阻R3接地。
当该电源输入接口41输出的电压小于该预定电压，该升压控制器431控制该PMOS管Q1导通而建立该电源输入接口41与升压电路43的电连接时，该PWM输出端sw1输出具有一定占空比的PWM信号使得NMOS管Q5周期性地导通及截止。其中，在一个周期内，当PWM信号处于高电平时，NMOS管Q5导通，此时电感L1通过该导通的NMOS管Q5构成一电流回路，电流从电源输入接口41流经该PMOS管Q1、该电感L1以及该NMOS管Q5。同时，D1截止不导通，电容C2两端电压等于输出电压Vcc1。
当PWM信号处于低电平时，NMOS管Q5截止，电感L1产生右正左负的反电动势，该反电动势与该电源输入接口41输出的电压叠加而大于该电源输入接口41输出的电压。此时，电感L1的第二端P12的输出电压大致等于该电源输入接口41输出的电压与电感L1产生的反电动势之和。从而，在一个PWM信号周期内，电感L1的第二端P12的输出电压将在一段时间内大致等于0V电压，另一段时间内大于该电源输入接口41输出的电压。因此，该输出端Vcc1输出的电压的等效电压将大于该电源输入接口41输出的电压，而起到了升压的效果。从而通过电源输出接口46为头戴式显示设备100的功能元件50供电。该功能元件50为显示装置10与耳机装置20中的各个耗电元件。
其中，该升压电路43还包括电容C2，该电容C2连接于该二极管D1的阴极、该输出端Vcc1以及地之间，用于对输出端Vcc1输出的电压进行滤波和进一步稳压。
其中，该升压电路43还包括串联于输出端Vcc1及地之间的电阻R4及电阻R5。该升压控制器431还包括一反馈端F1，该反馈端F1与电阻R4及电阻R5的连接节点连接，用于接收一反映输出端Vcc1所输出电压的反馈电压Vref1。其中，设输出端Vcc1所输出电压为Vcc1，则该反馈电压Vref1＝Vcc1*R5/(R4+R5)。
该升压控制器431还用于根据该反馈端F1接收的反馈电压Vref1控制调节该PWM输出端sw1输出的PWM信号的占空比，使得该输出端Vcc1所输出电压维持为该预定电压，例如维持为5V。
其中，该升压控制器431将该反馈电压Vref1与第二参考电压Vr2进行比较，如果该反馈电压Vref1大于该第二参考电压Vr2，则判断为该输出端Vcc1所输出电压大于该预定电压，该升压控制器431控制减小该输出的PWM信号的占空比，使得一个周期内大于该电源输入接口41输出的电压的时间变短，从而减小该输出端Vcc1所输出电压。
如果该反馈电压Vref1小于该第二参考电压Vr2，则判断为该输出端Vcc1所输出电压小于该预定电压，该升压控制器431控制增加该输出的PWM信号的占空比，使得一个周期内大于该电源输入接口41输出的电压的时间变长，从而增大该输出端Vcc1所输出电压。
如此，维持该输出端Vcc1所输出电压稳定在该预定电压。其中，该第二参考电压Vr2＝预定电压*R4/(R3+R4)。
其中，该升压控制器431还包括一侦测端Dt1，该侦测端Dt1与NMOS管Q5及电阻R3的连接节点连接，用于侦测流过NMOS管Q5的电流，并根据所侦测的电流进行过流保护，避免超过损坏该NMOS管Q5。具体的，该升压控制器431在侦测端Dt1侦测到的电流大于一过流保护值时，控制减小该PWM输出端sw1输出的PWM信号的占空比或者直接关闭PWM波形的输出，从而使得流过该NMOS管Q5的电流变小。
如图5所示，该降压电路44包括降压控制器441、NMOS管Q6、电感 L2、电容C3、二极管D2及输出端Vcc2。该电容C3用于储能滤波。该降压控制器441包括电压端vin2以及PWM输出端sw2。该电压端vin2用于与该电源输入接口41的正极端V+连接而接收工作电压。该PWM输出端sw2与NMOS管Q6的栅极连接，用于输出PWM信号至该NMOS管Q6。
该NMOS管Q6的源极与该PMOS管Q3的漏极以及电容C3的一端连接，NMOS管Q6的漏极与电感L2的第一端P21及二极管D2的阴极连接。该电容C3的另一端与二极管D2的阳极接地。电感L2的第二端P22与输出端Vcc2电连接。
当该电源输入接口41输出的电压大于该预定电压，该电路选择单元45控制该PMOS管Q3导通而建立该电源输入接口41与降压电路44的电连接时，该PWM输出端sw2输出具有一定占空比的PWM信号使得NMOS管Q6周期性地导通及截止。其中，在一个周期内，当PWM信号处于高电平时，NMOS管Q6导通，此时，电源输入接口41输出的电流经过该PMOS管Q3、该NMOS管Q6流至该电感L2，并经过电感L2输出至输出端Vcc2。此时电感L2的第二端P22的电压与该电源输入接口41输出的电压之和等于该电源输入接口41的V+。
当PWM信号处于低电平时，NMOS管Q6截止，该电源输入接口41与电感L2之间的电连接断开，电感L2产生右正左负的反电动势，该反电动势大致等于输出电压Vcc2。此时，电感L2的第二端P22的输出电压小于该电源输入接口41输出的电压。从而，在一个PWM信号周期内，电感L2的第二端P22的输出电压将在一段时间内等于输出的电压Vcc2，另一段时间内小于该电源输入接口41输出的电压。因此，该输出端Vcc2输出的电压的等效电压将小于该电源输入接口41输出的电压，而起到了降压的效果。该输出端Vcc2输出的电压通过电源输出接口46为头戴式显示设备100的功能元件50供电。
其中，该降压电路44还包括电容C4，该电容C4连接于该电感L2的第二端P22、该输出端Vcc2以及地之间，用于对输出端Vcc2输出的电压进行滤波和进一步稳压。
其中，该降压电路44还包括串联于输出端Vcc2及地之间的电阻R6及电阻R7。该降压控制器441还包括一反馈端F2，该反馈端F2与电阻R6及电阻 R7的连接节点连接，用于接收一反映输出端Vcc2所输出电压的反馈电压Vref2。其中，设输出端Vcc2所输出电压为Vcc2，则该反馈电压Vref2＝Vcc2*R7/(R6+R7)。
该降压控制器441还用于根据该反馈端F2接收的反馈电压Vref2控制调节该PWM输出端sw2输出的PWM信号的占空比，使得该输出端Vcc2所输出电压维持为该预定电压，例如维持为5V。
其中，该降压控制器441将该反馈电压Vref2与第三参考电压Vr3进行比较，如果该反馈电压Vref2大于该第三参考电压Vr3，则判断为该输出端Vcc2所输出电压大于该预定电压，该降压控制器441控制减小该输出的PWM信号的占空比，使得一个周期内小于该电源输入接口41输出的电压的时间变长，从而减小该输出端Vcc2所输出电压。
如果该反馈电压Vref2小于该第三参考电压Vr3，则判断为该输出端Vcc2所输出电压小于该预定电压，该降压控制器441控制增大该输出的PWM信号的占空比，使得一个周期内电感电压与输出电压Vcc2之和等于该电源输入接口41输出的电压的时间变长，从而增大该输出端Vcc2所输出电压。
如此，维持该输出端Vcc2所输出电压稳定在该预定电压。其中，该第三参考电压Vr3＝预定电压*R7/(R6+R7)。
其中，该稳压控制电路40的电源输出端46可为一USB接口，该升压电路43的输出端Vcc1以及该降压电路44的输出端Vcc2均与该电源输出端46的电源引脚VCC连接。该头戴式显示设备100还包括一电池60，该电源输出端46还与该电池60连接，所述升压电路43或降压电路44将太阳能电池板30的电能电压升压或降压后为所述电池60充电。
其中，该电路选择单元45还包括电压端Vin，该电压端Vin与电池60连接，从电池60接收工作电压。
其中，该电池60可以为容量较小的电池，从而可做到轻薄短小。由于采用太阳能电池板30可随时充电，因此不会影响头戴式显示设备100的续航能力。
其中，本发明的MOS管可被BJT三极管、IGBT等代替，三极管可被MOS管及IGBT代替，而MOS管和三极管的类型也可互换。例如，该PMOS管 Q1、Q3也可为NMOS管，该NPN三极管Q2、Q4可为PNP三极管，该NMOS管Q5、Q6也可为PMOS管。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (18)

  1. 一种头戴式显示设备，包括显示装置以及耳机装置，其特征在于，所述头戴式显示设备还包括设置于显示装置和/或耳机装置的表面上的太阳能电池板以及设置于显示装置或耳机装置内部的稳压控制电路，所述太阳能电池板用于将太阳能转换为电能，所述稳压控制电路用于将太阳能电池板输出的电能电压稳压成一预定电压，并以所述预定电压为显示装置及耳机装置供电。
  2. 如权利要求1所述的头戴式显示设备，其特征在于，所述太阳能电池板包括层叠设置的非球面微透镜层以及光电转换层，所述非球面微透镜层用于将太阳光汇聚传导至光电转换层，所述光电转换层用于进行光电转换，将太阳光能转换成电能。
  3. 如权利要求2所述的头戴式显示设备，其特征在于，所述非球面微透镜层的外表面上为波浪形的非球面，且非球面微透镜层的两面均镀可见-近红外增透膜。
  4. 如权利要求2所述的头戴式显示设备，其特征在于，所述光电转换层包括呈阵列式排列的若干半导体光电二极管，当太阳光通过非球面微透镜层传导至半导体光电二极管时，半导体光电二极管将太阳光能转换成电能。
  5. 如权利要求2所述的头戴式显示设备，其特征在于，所述耳机装置包括环带及设置于环带两端的听筒，所述太阳能电池板的数量为至少两个，分别设置于显示装置的外表面和耳机装置的环带的外表面，该些太阳能电池板并联或串联而构成一太阳能电池组，所述稳压控制电路与所有太阳能电池板连接，用于将所有太阳能电池板的总输出电能转换成预定电压为显示装置及耳机装置供电。
  6. 如权利要求2所述的头戴式显示设备，其特征在于，所述稳压控制电路包括电源输入接口、电压侦测单元、升压电路、降压电路、电路选择单元以及电源输出接口，所述电源输入接口用于与太阳能电池板连接，接收太阳能电池板所转换出的电能，所述电压侦测单元用于侦测电源输入接口所接入的电能的电压，所述升压电路与降压电路以并联的方式电连接于电源输入接口与电源输出接口之间，所述电路选择单元用于将该电压侦测单元侦测的电压与预定电 压进行比较，并根据比较结果建立电源输入接口与升压电路或降压电路之间的连接，所述升压电路或降压电路将电源输入接口所接入的电能电压升压或降压至该预定电压，并通过电源输出接口提供给头戴式显示设备的显示装置以及耳机装置中的各个功能元件。
  7. 如权利要求6所述的头戴式显示设备，其特征在于，所述电路选择单元当判断侦测的电压小于该预定电压时，建立升压电路与电源输入接口之间的连接而断开降压电路与电源输入接口之间的连接；所述电路选择单元在判断侦测的电压大于该预定电压时，建立降压电路与电源输入接口之间的连接而断开升压电路与电源输入接口之间的连接。
  8. 如权利要求7所述的头戴式显示设备，其特征在于，所述稳压控制电路还包括第一路径开关以及第二路径开关，所述第一路径开关电连接于所述电源输入接口与所述升压电路之间，所述第二路径开关电连接于所述电源输入接口与所述降压电路之间；所述电路选择单元与所述第一路径开关以及第二路径开关连接，所述电路选择单元在判断侦测的电压小于该预定电压时，控制第一路径开关导通以及第二路径开关断开，从而建立升压电路与电源输入接口之间的连接而断开降压电路与电源输入接口之间的连接，所述电路选择单元在判断侦测的电压大于该预定电压时，控制第一路径开关断开以及第二路径开关导通，从而建立降压电路与电源输入接口之间的连接而断开升压电路与电源输入接口之间的连接。
  9. 如权利要求8所述的头戴式显示设备，其特征在于，所述电压侦测单元包括串联于电源输入接口的正极端以及接地端之间的第一电阻及第二电阻，所述第一电阻与第二电阻的连接节点的电压与电源输入接口的正极端输出的电压成正比例关系；所述电路选择单元包括侦测端、第一使能端以及第二使能端；该侦测端与所述第一电阻与第二电阻的连接节点连接，用于获取第一电阻与第二电阻的连接节点的电压，并将该侦测端获取的电压与第一参考电压进行比较，当比较侦测端接收的电压大于该第一参考电压时，判断该电源输入接口输出的电压大于该预定电压，并控制该第二使能端输出高电平使能信号，第一使能端输出低电平信号，所述电路选择单元比较侦测端接收的电压小于所述第一参考电压时，判断所述电源输入接口输出的电压小于该预定电压，并控制所 述第二使能端输出低电平信号，第一使能端输出高电平使能信号。
  10. 如权利要求9所述的头戴式显示设备，其特征在于，所述第一路径开关包括第一PMOS管以及第一NPN三极管，所述第一PMOS管的源极与电源输入接口的正极端连接，漏极与所述升压电路连接，栅极与所述第一NPN三极管的集电极连接，所述第一NPN三极管的发射极接地，基极与所述电路选择单元的第一使能端连接。
  11. 如权利要求10所述的头戴式显示设备，其特征在于，当所述NPN三极管的基极接收到第一使能端发出的高电平使能信号时，所述NPN三极管导通，所述第一PMOS管的栅极通过所述导通的NPN三极管接地而同样导通，从而建立所述该电源输入接口的正极端与所述升压电路之间的电连接。
  12. 如权利要求9所述的头戴式显示设备，所述第二路径开关包括第二PMOS管以及第二NPN三极管，所述第二PMOS管的源极与电源输入接口的正极端连接，漏极与所述降压电路连接，栅极与所述第二NPN三极管的集电极连接，所述第二NPN三极管的发射极接地，基极与电路选择单元的第二使能端连接。
  13. 如权利要求12所述的头戴式显示设备，当所述第二NPN三极管接收到第二使能端发出的高电平使能信号时，所述第二NPN三极管导通，所述第二PMOS管的栅极通过导通的第二NPN三极管接地而同样导通，从而导通电源输入接口的正极端与所述降压电路之间的电连接。
  14. 如权利要求11所述的头戴式显示设备，其特征在于，所述升压电路包括升压控制器、第一NMOS管、第一电感、第一电容、第一二极管及第一输出端，所述升压控制器包括第一电压端以及第一PWM输出端；所述第一电压端用于与该电源输入接口的正极端连接而接收工作电压，所述第一PWM输出端与第一NMOS管的栅极连接，用于输出PWM信号至所述第一NMOS管，所述第一电感的第一端与第一PMOS管的漏极及第一电容的一端电连接，所述第一电容的另一端接地，第一电感的第二端与第一二极管的阳极以及所述第一NMOS管的源极连接，所述第一二极管的阴极与所述第一输出端连接，所述第一NMOS管的漏极通过第三电阻接地，所述第一输出端与该电源输出端电连接。
  15. 如权利要求14所述的头戴式显示设备，其特征在于，所述升压电路还包括串联于第一输出端及地之间的第四电阻及第五电阻，所述升压控制器还包括一第一反馈端，所述第一反馈端与第四电阻及第五电阻的连接节点连接，用于接收一反映第一输出端所输出电压的反馈电压；所述升压控制器还用于根据该第一反馈端接收的反馈电压控制调节该第一PWM输出端输出的PWM信号的占空比，使得所述第一输出端所输出电压维持为该预定电压。
  16. 如权利要求13所述的头戴式显示设备，其特征在于，所述降压电路包括降压控制器、第二NMOS管、第二电感、第三电容、第二二极管及第二输出端，所述第三电容用于储能滤波，所述降压控制器包括第二电压端以及第二PWM输出端，所述第二电压端用于与该电源输入接口的正极端连接而接收工作电压，所述第二PWM输出端与第二NMOS管的栅极连接，用于输出PWM信号至该第二NMOS管；所述第二NMOS管的源极与所述第二PMOS管的漏极以及所述第三电容的一端连接，第二NMOS管的漏极与第二电感的第一端及第二二极管的阴极连接，所述第三电容的另一端与第二二极管的阳极接地，所述第二电感的第二端与第二输出端电连接。
  17. 如权利要求16所述的头戴式显示设备，其特征在于，所述降压电路还包括串联于第二输出端及地之间的第六电阻及第七电阻，所述降压控制器还包括一第二反馈端，所述第二反馈端与第六电阻及第七电阻的连接节点连接，用于接收一反映第二输出端所输出电压的反馈电压；所述降压控制器还用于根据该第二反馈端接收的反馈电压控制调节该第二PWM输出端输出的PWM信号的占空比，使得该第二输出端所输出电压维持为该预定电压。
  18. 如权利要求6所述的头戴式显示设备，其特征在于，所述头戴式显示设备还包括一电池，所述电源输出端还与所述电池连接，所述升压电路或降压电路将太阳能电池板的电能电压升压或降压后为所述电池充电。
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CN115549271A (zh) * 2021-06-30 2022-12-30 北京小米移动软件有限公司 电子设备
KR20240033983A (ko) * 2022-09-06 2024-03-13 주식회사 피앤씨솔루션 태양광 패널을 활용한 전력생산이 가능한 증강현실 글래스 장치
KR102800654B1 (ko) * 2022-09-06 2025-04-30 주식회사 피앤씨솔루션 태양광 패널을 활용한 전력생산이 가능한 증강현실 글래스 장치
CN115603575A (zh) * 2022-10-17 2023-01-13 珠海格力电器股份有限公司（Cn） 调压电路及其控制方法、调压设备
CN116094097A (zh) * 2022-12-23 2023-05-09 宁波麦度智联科技股份有限公司 降低穿戴设备输入功耗的电路

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