WO2017112035A1

WO2017112035A1 - Through-hole interconnect network and method of making same

Info

Publication number: WO2017112035A1
Application number: PCT/US2016/056641
Authority: WO
Inventors: Boon Keat Tan; Andrew Soon Aun ONG; Jackson Chung Peng Kong; Bok Eng Cheah; Jingbo Li
Original assignee: Intel Corporation
Priority date: 2015-12-23
Filing date: 2016-10-12
Publication date: 2017-06-29
Also published as: MY172393A

Abstract

Techniques and mechanisms for providing connectivity between traces disposed on opposite sides of a substrate such as that of a printed circuit board. In an embodiment, through-hole interconnects (TIs) each extend from a first side of a substrate to a second side of the substrate. A first node and a second node are disposed at the first side and at the second side, respectively. Each of the plurality of TIs is coupled to propagate a respective portion of a signal between the first node and the second node. In another embodiment, a material of the substrate, disposed between two of the TIs, provides for a capacitance that improves signal characteristics.

Description

THROUGH-HOLE INTERCONNECT NETWORK

AND METHOD OF MAKING SAME

BACKGROUND

1. Technical Field

Embodiments of the invention relate generally to structures that provide connectivity across a substrate and more particularly, but not exclusively, to techniques for providing capacitance to improve signal characteristics.

2. Background Art

Digital signals are generally defined as signals that have two states (e.g., a high state and a low state) in which the voltage level of each of the states is within its own predetermined range. For example, a signal in a high state may have a voltage level equal to approximately Vcc, while a low voltage level may have a voltage equal to approximately Vss. Ideally, a transition between digital states occurs instantaneously, resulting in a vertical line that has an infinite slope. In actuality, a digital signal changes state over a specified period of time, providing a non-infinite slope that is equal to the time rate of change of the signal voltage. The time rate of change from one state to another state for a digital signal is defined as the slew rate, and it is typically measured in units of volts/time.

Excessive and/or non-linear slew rate, such as that caused by an over-amplified source circuit, typically results in double clocking, signal crosstalk coupling and/or other signal integrity complications. As successive generations of integrated circuit technologies continue to trend toward smaller scales and faster data rates, the sensitivity of such technology to slew rate characteristics is expected to increase. Accordingly, conventional techniques for mitigating the effects of poor slew rate are expected to be inadequate for the future demands of manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

FIG. 1 shows a perspective view and plan view diagrams variously illustrating elements of through-hole interconnect structures according to an embodiment.

FIG. 2 is a flow diagram illustrating elements of a method for providing connectivity through a substrate according to an embodiment.

FIG. 3 shows perspective view and cross-sectional view diagrams variously illustrating elements of respective through-hole interconnect structures each according to a corresponding embodiment. FIG. 4 shows perspective view and cross-sectional view diagrams variously illustrating elements of respective through-hole interconnect structures each according to a corresponding embodiment.

FIG. 5 shows perspective view and plan view diagrams variously illustrating elements of through-hole interconnect structures according to an embodiment.

FIG. 6 shows perspective view and plan view diagrams variously illustrating elements of through-hole interconnect structures according to an embodiment.

FIG. 7 is a circuit diagram illustrating elements of a system including interconnect structures according to an embodiment.

FIG. 8 is a circuit diagram illustrating elements of a system including interconnect structures according to an embodiment.

FIG. 9 is a functional block diagram illustrating a computing device in accordance with one embodiment.

FIG. 10 is a functional block diagram illustrating an exemplary computer system, in accordance with one embodiment.

DETAILED DESCRIPTION

Embodiments discussed herein variously include techniques and/or mechanisms for providing electrical connection through a substrate such as that of a printed circuit board (PCB). In some embodiments, two or more hole structures (referred to herein a "through-holes") each extend from one side of a substrate through to a second side of the substrate, where an insulation material is disposed between the two or more holes within the substrate. Conductive material disposed in the through-holes provide for electrical connection between the opposite sides of the substrate. Nodes, disposed each on a different respective one of the opposite sides, may be variously coupled to one another via a network of the interconnected conductors.

As used herein, "through-hole interconnect" (or, for brevity, "TI") refers to a conductive structure, formed within a through-hole, which enables electrical coupling through the substrate in which the through-hole is formed. Also, "through-hole interconnect network," "TI network" and "network of TIs" refers herein to two or more TIs that are coupled to one another at a first side of a substrate, and further coupled to one another at a second side of the substrate (opposite the first side), wherein first branch portions disposed on the first side variously couple the two or more TIs to a first node and wherein second branch portions disposed on the second side variously couple the two or more TIs to a second node. "Trace portion" refer herein to a conductive interconnect structure, having a predominant linear extension in one direction, that is configured to exchange a signal between respective ends thereof. "Branch portion" is used herein to refer to a trace portion that is one of multiple trace portions each extending between a common node and a respective TI. Such multiple trace portions may each be considered a branch portion. A trace portion directly coupling two TIs of a TI network to one another might not be a branch portion - e.g., where any other trace portion is coupled to that trace portion only via a TI.

Certain embodiments result from a realization that a substrate, having traces, vias and/or other interconnect structures formed therein or thereon, may serve as a source of capacitance for improved signaling characteristics. Where existing technologies use one TI for communicating a signal through a substrate, various embodiments couple multiple TIs in a network to exploit capacitive properties of substrate materials. For example, one or more capacitive structures may be formed by the location - between one or more pairs of TIs - of a substrate material that has dielectric properties (even weakly so). Such capacitive structures may provide for improved characteristics of a signal that is exchanged via a network including the one or more pairs of TIs. In one illustrative embodiment, non-linear and/or high frequency signal components - such as that occurring during a noisy transition between logical states - may be at least partially filtered out to smooth a signal.

The technologies described herein may be implemented in one or more electronic devices. Non- limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a substrate having formed therein a through-hole interconnect network. Certain features of various embodiments are described herein with reference to the formation of through- hole interconnect network in a substrate of a printed circuit board. However, such description may be extended to additionally or alternatively apply to the formation of through-hole interconnect network in any of a variety of other substrates. FIG. 1 shows features of a device 100 including a network of through-hole interconnects according to an embodiment. Device 100 is one example of an embodiment that includes a network of TIs configured, relative to one another, to provide a capacitance that is applied to a signal exchanged through a substrate and between two nodes. Device 100 may include, or function as a component of, a computer (e.g., a server, desktop computer, laptop computer, tablet or the like), smart phone or any of a variety of other hardware platforms including circuitry disposed in or on a substrate.

In the illustrative embodiment shown, device 100 includes a substrate 150 having formed therein two or more TIs 116a,..., 116b each extending from a first side 152 of substrate 150 to a second side 154 of substrate 150 that is opposite side 152. In one embodiment, one or each of sides 152, 154 is a respective exposed surface of substrate 150. Alternatively, one or more additional layers of material (not shown) may be disposed on substrate 150 - e.g., including a layer on side 152 and/or a layer on side 154. To avoid obscuring certain features of various embodiments, substrate 150 is represented only in a cross-sectional side view 104 (along a x- axis) - but not in the perspective view (showing an x, y, z coordinate system) or the top plan view 102 (along a z-axis) of FIG. 1.

Substrate 150 may include any of a variety of insulator materials that, for example, are used in a printed circuit board (PCB) or other circuit devices. For example, substrate 150 may include an epoxy, resin and/or a glass (e.g., fiberglass). In another embodiment, substrate 150 is an interposer or other substrate of a packaged circuit device. Alternatively or in addition, substrate 150 may be integrated into a connector that is to couple to a chassis, PCB or other mounting hardware. Substrate 150 may be a monolithic material or, alternatively, may include multiple laminated layers (not shown). In some embodiments, substrate 150 includes an insulation (e.g., dielectric) material that is disposed between TIs 116a,..., 116b. Such a material may define at least in part - e.g., adjoin and surround - one or both of the respective through- holes for TIs 116a,..., 116b. Although some embodiments are not limited in this regard, the material may extend across the entirety of a distance between TIs 116a,..., 116b.

Formation of TIs 116a,..., 116b may include drilling or otherwise forming respective through-holes between sides 152, 154 - e.g., using operations adapted from convention laser etching and/or other such techniques. Such formation may further comprise deposition of conductive material in such through-holes. For example, copper and/or another metal (e.g., including an alloy) may be plated or otherwise deposited by operations adapted from any of a variety of conventional metallization techniques. Some examples of such techniques include, but are not limited to, paste printing, electroless deposition and vapor deposition. TIs 116a, ..., 116b are merely one example of a network of two or more TIs that, according to one embodiment, are coupled to facilitate an exchange of a signal between nodes disposed on different respective sides of a substrate. For each of the two nodes, the node may be coupled to multiple TIs of the TI network each via a respective branch portion disposed on that side of the substrate. One or more characteristics of the signal may be affected by capacitance resulting from dielectric properties of a substrate material that is disposed between a given pair of the TIs in the TI network. In an illustrative embodiment, a TI network provides a capacitance that is in a range between 2.0 picoFarads (pF) and 5.0 pF - e.g., for a 100 MHz signal. However, various other capacitances may be achieved by a TI network, according to different embodiments.

By way of illustration and not limitation, side 152 may have disposed therein or thereon a trace portion 110, branch portions 114a,..., 114b and a node 112 where trace portion 110 and branch portions 114a, ... , 114b couple to each other. Similarly, side 154 may have disposed therein or thereon a trace portion 124, branch portions 120a,..., 120b and a node 122 where trace portion 124 and branch portions 120a,..., 120b couple to each other. At side 152, TIs 116a,..., 116b may couple to branch portions 114a,..., 114b, respectively. TIs 116a,..., 116b may further couple, at side 154, to respective trace portions 118a, ... , 118b. In one embodiment, trace portions 118a,..., 118b are each integral with (part of) a respective one of branch portions 120a,..., 120b. Alternatively, some or all of trace portions 118a,..., 118b may be variously coupled each to a respective one of branch portions 120a, ..., 120b via one or more other TIs (not shown) of the TI network.

FIG. 2 shows operations of a method 200 to fabricate a network of through-hole interconnect structures according to an embodiment. Method 200 may include operations to fabricate device 100, for example. In an embodiment, method 200 includes, at 210, forming through-holes each extending from a first side of a substrate to a second side of the substrate. Such through-holes may be formed at 210 by mechanical drilling, laser etching and/or other processes adapted from conventional fabrication techniques. The holes may have respective cross-sectional profiles that, for example, are round, elliptical, rectilinear or otherwise shaped. The particular dimensions of such through-holes may vary in different embodiments, according to implementation- specific details. In an illustrative scenario according to one embodiment, a TI network is formed in a PCB - e.g., wherein a width (e.g., diameter) of an individual through-hole is in a range between 0.2 mm and 1.2 mm. Alternatively or in addition, a cross-sectional area of such a through-hole may be in a range between 0.04 mm² and 1.0 mm². In some embodiments, a length of through-hole, between opposite sides of a PCB, is in a range between 0.2 mm and 3.2 mm. However, through-hole geometries may scale to smaller (or larger) dimensions - e.g., where a TI network according to another embodiment is formed in a substrate of a packaged IC device. Although some embodiments are not limited in this regard, a distance between two TIs may be less than a width of one of the TIs, for example.

Method 200 may further comprise, at 220, forming a plurality of through-hole

interconnects (TIs), wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs. The forming at at 220 may include depositing a conductor - such as copper or any of various other metals, alloys, etc. - in at least some the through-holes formed at 210. Such depositing may be performed with an electroplating or other deposition process that, for example, is adapted from conventional metallization techniques. For example, a TI may include a conductor that fills a through-hole or, alternatively, is merely disposed around the sidewalls of the through-hole.

Method 200 may further comprise, at 230, forming first branch portions on the first side, wherein the first branch portions each extend from a first node to a respective one of the plurality of TIs. Method 200 may further include, at 240, forming second branch portions on the second side, wherein the second branch portions each extend from a respective one of the plurality of TIs to a second node. The plurality of TIs may be configured, after the forming at 230 and 240, each to propagate a respective portion of a signal between the first node and the second node.

The total number of TIs and/or the configuration of such TIs relative to one another may vary, according to different embodiments. For example, of the TIs in a TI network, each such TI may be coupled directly to a respective one or more branch portions. Alternatively, a TI network may include a TI that is coupled to a branch portion only via another one or more TIs. In some embodiments, a TI network includes TIs that are coupled to one another via a trace portion on one side of a substrate and, in some embodiments, also via a trace portion on an opposite side of the substrate. A TI network may include TIs coupled in parallel between an input node and an output node. In some embodiments, a TI network further includes TIs that are coupled in series between such nodes.

In an embodiment, the first node is offset from a straight line that extends between two of the TIs - e.g., where the first node is not positioned between the two TIs. For example, the first node may be offset from any straight line that extends between any two of the plurality of TIs. In some embodiments, an end of a first TI forms the first node, wherein the first TI is not located between any two other TIs that are coupled between the first node and the second node. Similar to the first node, the second node may be offset from a straight line that extends between two TIs. For example, one or both of nodes 112, 122 may be offset from a straight line extending through two of more of TIs 116a, ... , 116b. FIG. 3 illustrates features of devices 300, 302, 304 each including a respective TI network according to a corresponding embodiment. One or more of devices 300, 302, 304 may include features of device 100, for example. In an embodiment, fabrication of some or all of devices 300, 302, 304 includes operations of method 200.

Device 300 may include structures - including nodes 310, 318 - that are variously formed on opposite sides of a substrate 320 through which extend TIs 313, 314. As illustrated by the cross-sectional view 301 of device 300, TIs 313, 314 may provide for coupling of nodes 310, 318 to one another. For example, at a first side of substrate 320, branch portions 311, 312 may variously extend from node 310 to respective ends of TIs 313, 314. At an opposing, second side of substrate 320, branch portions 315, 316 may variously extend each from a respective opposite end of one of TIs 313, 314 to node 318. In an embodiment, a material of substrate 320 - e.g., a epoxy resin, glass, etc. - has at least some dielectric properties that contribute to a capacitance between TIs 313, 314.

In the embodiment of device 302, structures are variously formed on opposite sides of a substrate 340 through which extend TIs 333, 334. Device 302 is an example of an embodiment wherein a node, from which extend multiple branch portions, is formed by an end of another TI that also extends through such a substrate. For example, as shown in cross-sectional view 303 of device 302, TIs 333, 334 may provide for coupling of a node 330 to another node that is formed by an end of a TI 338. At one side of substrate 340, branch portions 331, 332 may extend from node 330 to respective ends of TIs 333, 334. Opposite ends of TI 333 may each be coupled - by a respective one of branch portions 335 - to a corresponding one of the opposite ends of TI 338. Similarly, opposite ends of TI 334 may each be coupled - by a respective one of branch portions 336 - to a corresponding one of the opposite ends of TI 338. It is noted that branch portions 335 do not both extend from the same node, but rather from different respective nodes formed by opposite ends of TI 338. Similarly, branch portions 336 do not both extend from the same node. A dielectric property of substrate 340 may cause capacitance between various pairs of TIs 333, 334, 338. Such capacitance may mitigate effects of poor characteristics of a signal to be exchanged between node 330 and the node formed by TI 338 at the opposite side of substrate 340.

Device 304 is an example of an embodiment wherein a TI network, disposed in a substrate, is to facilitate a signal exchange between two nodes, where such two nodes are each formed by a respective TI that extends through the substrate. For example, device 304 includes a substrate 360, TIs 353, 354, branch portions 355, branch portions 356 and TIs 358, the functionality of which may correspond, respectively, to that of substrate 340, TIs 333, 334, branch portions 335, branch portions 336 and TIs 338. Device 305 may further include a TI 350, wherein an end of TI 350 forms a node on one side of substrate 360, and wherein another end of TI 350 forms another node at an opposite side of substrate 360. A TI network including TIs 350, 353, 354, 358 may be coupled to exchange a signal between such nodes. For example, as illustrated by the cross-sectional view 305 of device 304, opposite ends of TI 350 may each be coupled - by a respective one of branch portions 351 - to a corresponding one of the opposite ends of TI 353. Similarly, opposite ends of TI 350 may each be further coupled - by a respective one of branch portions 352 - to a corresponding one of the opposite ends of TI 354.

FIG. 4 shows features of devices 400, 402, 404 each including a respective TI network according to a corresponding embodiment. Respective cross-sectional views 401, 403, 405 of devices 400, 402 404 are provided to further illustrate certain features of various embodiments. One or more of devices 400, 402, 404 may include features of device 100. In some

embodiments, fabrication of some or all of devices 400, 402, 404 is according to operations of method 200.

Device 400 comprises structures - including nodes 410, 420 - that are variously formed on opposite sides of a substrate 422 through which extend TIs 413, 414, 417, 418. Device 400 is one example of an embodiment wherein a TI network includes both an arrangement of series - connected TIs and an arrangement of parallel-connected TIs. For example, at a first side of substrate 422, branch portions 411, 412 may variously extend from node 410 to respective ends of TIs 413, 414. At an opposing second side of substrate 422, TIs 417, 418 may be coupled via respective branch portions to a node 420. Opposite ends of TI 413 may each be coupled - by a respective one of trace portions 415 - to a corresponding one of the opposite ends of TI 417. Similarly, opposite ends of TI 414 may each be coupled - by a respective one of trace portions 416 - to a corresponding one of the opposite ends of TI 418. In an embodiment, an at least nominally dielectric material of substrate 422 contributes to the formation of capacitance structures each between a respective pair of TIs 413, 414, 417, 418.

Device 402 is an example of an embodiment that is similar to device 400 in some respects, but where a node is formed by an end of a TI that extends through a substrate. For example, device 402 may include a substrate 444, TIs 433, 434, 437, 438, branch portions 431, 432, trace portions 435, 436 and a node 430, the functionality of which may correspond, respectively, to that of substrate 422, TIs 413, 414, 417, 418, branch portions 411, 412, trace portions 415, 416 and node 410. Device 405 may further include a TI 442, wherein an end of TI 442 forms a node on one side of substrate 444, and wherein another end of TI 442 forms another node at an opposite side of substrate 444. The TI network including TIs 433, 434, 437, 438 may be coupled to exchange a signal between such nodes. For example, opposite ends of TI 437 may each be coupled - by a respective one of branch portions 439 - to a corresponding one of the opposite ends of TI 442. Similarly, opposite ends of TI 438 may each be further coupled - by a respective one of branch portions 440 - to a corresponding one of the opposite ends of TI 442.

Device 404 is an example of an embodiment having some features of device 402, for example, where two nodes are formed each by an end of a different respective TI. For example, device 404 may include a substrate 464, TIs 453, 454, 457, 458, 462, trace portions 455, 456 and branch portions 459, 460, the functionality of which may correspond, respectively, to that of substrate 444, TIs 433, 434, 437, 438, 442, trace portions 435, 436 and branch portions 439, 440. Device 405 may further include a TI 450, wherein an end of TI 450 forms a node on one side of substrate 464, and wherein another end of TI 450 forms another node at an opposite side of substrate 464. Opposite ends of TI 450 may each be coupled - by a respective one of branch portions 451 - to a corresponding one of the opposite ends of TI 453. Similarly, opposite ends of TI 450 may each be further coupled - by a respective one of branch portions 452 - to a corresponding one of the opposite ends of TI 454.

FIG. 5 illustrates features of a device 500 comprising interconnect structures according to one embodiment. Device 500 may include features of one of devices 100, 300, for example. In an embodiment, device 500 is fabricated according to operations of method 200. In FIG. 5, a top plan view 504, detail top plan view 502 and cross-sectional view 506 also illustrate structures of device 500.

Device 500 may include a substrate 500 having disposed therein conductive structures (represented by the illustrative ground planes 510, 512) that are to provide a ground voltage, or other reference potential, to circuitry (not shown) that is included in, or is to couple to, device 500. The providing of such a reference potential may be enabled by one or more vias 530 that extend between ground planes 510, 512. Device 500 may include more, fewer and/or differently arranged ground planes, in other embodiments. As shown in view 506, a first side of substrate 550 may be positioned over ground plane 510, where a second side of substrate 550 is positioned below ground plane 512. In top plan view 504, structures on a left hand side of line A-A' are disposed on the first side of substrate 550, and structures on a right hand side of line A-A' are disposed on the second side of substrate 550.

Structures formed on the first side of substrate 550 may include a trace portion 520 and branch portions 522 that extend from a first node, at an end of trace portion 520, to TIs 524 of device 500. Although some embodiments are not limited in this regard, branch portions 522 may include five branch structures each coupling to a respective one of five TIs 524. TIs 524 may extend through substrate 550 - e.g., wherein one or both of ground planes 510, 512 form one or more holes 540 to accommodate such extension of TIs 524. In such an embodiment, structures formed on the second side of substrate 550 may include a trace portion 528 and branch portions 526 that each extend from a respective one of TIs 524 and join with one another and with trace portion 528 at a second node. A TI network including TIs 524 may function as a set of capacitive structures - each including a respective pair of TIs 524 - that result at least in part from a dielectric property of substrate 550.

FIG. 6 shows a device 600 comprising interconnect structures according to another embodiment. Device 600 may include features of one of devices 100, 304 - e.g., device 600 is fabricated according to operations of method 200. In FIG. 6, a top plan view 604 and a detail cross-sectional view 602 also illustrate structure of device 600.

Device 600 may include a substrate (not shown) having disposed therein ground planes 610, 612 coupled to provide a reference potential - e.g., using one or more vias 640 that extend between ground planes 610, 612. A first side of the substrate may be positioned over ground plane 610, and a second side of the substrate positioned below ground plane 612. In top plan view 604, structures shown on a left hand side of line B-B' are disposed on the first side of the substrate, and structures shown on a right hand side of line B-B' are disposed on the second side of the substrate.

Structures formed on the first side of the substrate may include a trace portion 620 and branch portions 624 that extend from a first node, at an end of a TI 622, each to a respective one of TIs 628. Although some embodiments are not limited in this regard, branch portions 624 may include three branch structures each coupling to a respective one of three TIs 628. TIs 628 may extend through the substrate - e.g., wherein ground planes 610, 612 form respective holes 650, 652 to accommodate such extension of TIs 628. Additional structures formed on the first side of the substrate may include branch portions 630 that each extend from a respective one of TIs 628 to another node at an end of a TI 634. In such an embodiment, structures formed on the second side of the substrate may include branch portions 626 that extend from another end of a TI 622, each to a respective other end of one of TIs 628. Additional structures formed on the second side of the substrate may include a trace portion 636 and branch portions 632 that each extend from a respective one of TIs 628 and join with one another and with trace portion 636 at an end of TI 634.

FIG. 7 illustrates feature system 700 including interconnect structures configured to provide improved signal communication according to an embodiment. System 700 is one example of an embodiment wherein a first device is coupled to a second device, where the first device is to function as a source of, and the second device as a sink for, a signal that is received with a TI network. The two devices may be distinct hardware platforms or, alternatively, different respective components of the same hardware platform.

By way of illustration and not limitation, system 700 may include a source 710 and a sink 750 coupled to one another via a cable 730 (or other such interconnection hardware). Integrated circuity (IC) 712 of source 710 may output (e.g., via a hardware interface 714 such as that of a packaged IC device) a signal for transmission from a connector 720 that couples source 710 to cable 730. IC 712 may include one or more IC chips such including transmitter circuitry Tx (and in some embodiments, receiver circuitry Rx) such as that of a physical layer interface (PHY). Although certain embodiments are not limited in this regard, the signal from IC 712 may propagate through a trace 716 of a breakout board and/or a trace 718 of a motherboard.

However, any of a variety of one or more additional or alternative trace structures of source 710 may transmit the signal, according to different embodiments.

In the illustrative embodiment shown, the signal from source 710 may be received at a connector 740 that couples sink 750 to cable 730. A trace portion 752 of sink 750 may communicate the signal from connector 740 to a TI network 760. TI network 760 may include some or all of the features of device 100 or any of various other TI network circuitry described herein. In an embodiment, TI network 760 passes the signal through a substrate (not shown) using multiple through-substrate interconnects that are variously coupled to each other at each of the two opposite sides of the substrate. TI network 760 may provide a capacitance that aids in mitigating noise and/or other undesirable components from the signal. In an embodiment, signal processing by TI network 760 may reduce excessive electromagnetic coupling between adjacent signals that is caused, for example, by over amplification of transmitter circuitry Tx. Such processing may additionally or alternatively result in improved monotonicity - e.g., including a smoother rising edge and/or falling edge - for logic state transitions of a clock signal or other type of signal.

Although certain embodiments are not limited in this regard, TI network 760 may output the processed signal to a branch topology of a receiver circuit - e.g., wherein the branch topology includes stages 754, 756, 758 each variously coupled to ground via respective ones of receiver device capacitances Ca, Cb, Cc, Cd. In one illustrative embodiment, TI network 760 is to receive and process a signal representing audio information, and stages 754, 756, 758 are part of a microphone array PCB - e.g., where the receiver device capacitances Ca, Cb, Cc, Cd are each in a range of 2-5 picoFarads (pF). However, some embodiments are not limited with respect to a particular type of signal that might be exchanged between sink 710 and source 750. FIG. 8 illustrates feature of a system 800 including interconnect structures according to another embodiment. System 800 is an example of an alternative embodiment wherein a signal is exchanged from a sink device to a source device, and wherein circuitry of one such device - or circuitry coupled between the devices - includes a TI network to process the signal as it is transmitted through a substrate.

System 800 may include a transmitter Tx2 and a receiver Rx2 coupled to exchange communications using a differential pair of signals. In such an embodiment, system 800 may further comprise, for example, two TI networks 850, 852 variously coupled to each to process a different respective signal of the differential pair. Although certain embodiments are not limited in this regard, system 800 may further include a transmitter Txl and a receiver Rxl coupled to exchange other differential signal communications. For example, Tx2 and Rxl may implement a communication channel 804 that is distinct from another communication channel 802 provided with Txl and Rx2. The channels 802, 804 may differ from one another with respect to one or more characteristics such as signal type, bandwidth and/or the like. By way of illustration and not limitation, channel 802 may be configured to provide relatively high bandwidth signaling of display data - e.g., where channel 802 supports 8.1 Gbps DisplayPort High Bit Rate (HBR) 3 communications. In such an embodiment, channel 804 function as an auxiliary, or sideband, channel that supports a lower bandwidth (e.g., 720 Mbps) exchange of control signals. However, some embodiments are not limited with respect to the number and/or type of channels that may be supported by a device that includes a TI network.

In the illustrative embodiment shown, Txl and Rxl are disposed in a first packaged IC device of system 800, where a second packaged IC device of system 800 includes Txs and Rx2. A hardware interface 810 of the first packaged IC device may be coupled to a connector 830 by differential transmit path 820 and by a differential receive path 822. Alternatively or in addition, a hardware interface 850 of the second packaged IC device may be coupled to a connector 834 by differential receive path 840 and by a differential transmit path 842. In turn, connectors 830, 834 may be coupled to one another via a cable 832 that supports communication of at least two pairs of differential signals. Paths 820, 822, 840, 842 may variously include any of a variety of combinations of circuit elements, via structures, traces and/or other such structures adapted from conventional techniques to communicate differential signaling.

FIG. 9 illustrates a computing device 900 in accordance with one embodiment. The computing device 900 houses a board 902. The board 902 may include a number of

components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Some embodiments may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

FIG. 10 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system 1000 within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative

embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system 1000 includes a processor 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 1018 (e.g., a data storage device), which communicate with each other via a bus 1030.

Processor 1002 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 1002 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 1002 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 1002 is configured to execute the processing logic 1026 for performing the operations described herein.

The computer system 1000 may further include a network interface device 1008. The computer system 1000 also may include a video display unit 1010 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), and a signal generation device 1016 (e.g., a speaker).

The secondary memory 1018 may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) 1032 on which is stored one or more sets of instructions (e.g., software 1022) embodying any one or more of the methodologies or functions described herein. The software 1022 may also reside, completely or at least partially, within the main memory 1004 and/or within the processor 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processor 1002 also constituting machine-readable storage media. The software 1022 may further be transmitted or received over a network 1020 via the network interface device 1008.

While the machine-accessible storage medium 1032 is shown in an exemplary embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any of one or more embodiments. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

In one implementation, a device comprises a substrate, a plurality of through-hole interconnects (TIs) each extending from a first side of the substrate to a second side of the substrate, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs, first branch portions each extending on the first side from a first node to a respective one of the plurality of TIs, and second branch portions each extending on the second side from a respective one of the plurality of TIs to a second node. The device further comprises a first trace portion extending on the first side, the first trace portion to provide a signal to the first node, wherein each of the plurality of TIs propagates a respective portion of the signal between the first node and the second node, and a second trace portion extending on the second side, the second trace portion to receive the signal from the second node.

In one embodiment, the device comprises a first TI including the first node. In one embodiment, the device comprises a second TI including the second node. In one embodiment, the plurality of TIs includes TIs coupled in series with each other between the first node and the second node. In one embodiment, the plurality of TIs includes a first TI and a second TI coupled to the first TI, wherein a first trace portion is coupled directly to each of the first TI and the second TI at the first side, and wherein a second trace portion is coupled directly to each of the first TI and the second TI at the second side. In one embodiment, the plurality of TIs includes a first TI and a second TI, and wherein a distance between the first TI and the second TI is less than a width of the first TI. In one embodiment, the substrate includes a conductive plane disposed between the first side and the second side, the conductive plane to provide a reference potential to circuitry of the device, wherein one of the plurality of TIs extend through a hole formed by the conductive plane. In one embodiment, the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions. In one embodiment, the plurality of TIs includes five TIs each coupled directly to a respective one of the first branch portions.

In another implementation, a method comprises forming through-holes each extending from a first side of a substrate to a second side of the substrate, and forming a plurality of through-hole interconnects (TIs), including depositing a conductor in the through-holes, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs. The method further comprises forming first branch portions on the first side, wherein the first branch portions each extend from a first node to a respective one of the plurality of TIs, and forming second branch portions on the second side, wherein the second branch portions each extend from a respective one of the plurality of TIs to a second node, wherein the plurality of TIs are configured to propagate a respective portion of a signal between the first node and the second node.

In one embodiment, an end of a first TI includes the first node. In another embodiment, an end of a second TI includes the second node. In another embodiment, the method further comprises coupling multiple TIs of the plurality of TIs in series with each other between the first node and the second node. In another embodiment, the plurality of TIs includes a first TI and a second TI coupled to the first TI, and the method further comprises coupling a first trace portion directly to each of the first TI and the second TI at the first side, and coupling a second trace portion directly to each of the first TI and the second TI at the second side. In another embodiment, the plurality of TIs includes a first TI and a second TI, wherein a distance between the first TI and the second TI is less than a width of the first TI. In another embodiment, the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions. In another embodiment, the plurality of TIs includes five TIs each coupled directly to a respective one of the first branch portions.

In another implementation, a system comprises an interconnect device including a substrate, and a plurality of through-hole interconnects (TIs) each extending from a first side of the substrate to a second side of the substrate, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs. The interconnect device further comprises first branch portions each extending on the first side from a first node to a respective one of the plurality of TIs, second branch portions each extending on the second side from a respective one of the plurality of TIs to a second node, a first trace portion extending on the first side, the first trace portion to provide a signal to the first node, wherein each of the plurality of TIs propagates a respective portion of the signal between the first node and the second node, and a second trace portion extending on the second side, the second trace portion to receive the signal from the second node. The system further comprises a display device coupled to the interconnect device, the display device to display an image based on signals exchanged with the one or more IC chips.

In one embodiment, the interconnect device comprises a first TI including the first node. In another embodiment, the interconnect device comprises a second TI including the second node. In another embodiment, the plurality of TIs includes TIs coupled in series with each other between the first node and the second node. In another embodiment, the plurality of TIs includes a first TI and a second TI coupled to the first TI, wherein a first trace portion is coupled directly to each of the first TI and the second TI at the first side, and wherein a second trace portion is coupled directly to each of the first TI and the second TI at the second side. In another embodiment, the plurality of TIs includes a first TI and a second TI, and wherein a distance between the first TI and the second TI is less than a width of the first TI. In another

embodiment, the substrate includes a conductive plane disposed between the first side and the second side, the conductive plane to provide a reference potential to circuitry of the system, wherein one of the plurality of TIs extend through a hole formed by the conductive plane. In another embodiment, the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions. In another embodiment, the plurality of TIs includes five TIs each coupled directly to a respective one of the first branch portions.

Techniques and architectures for connecting nodes through a substrate are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

Besides what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.

Claims

CLAIMS What is claimed is:

1. A device comprising:

a substrate;

a plurality of through-hole interconnects (TIs) each extending from a first side of the substrate to a second side of the substrate, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs;

first branch portions each extending on the first side from a first node to a respective one of the plurality of TIs;

second branch portions each extending on the second side from a respective one of the plurality of TIs to a second node;

a first trace portion extending on the first side, the first trace portion to provide a signal to the first node, wherein each of the plurality of TIs propagates a respective portion of the signal between the first node and the second node;

a second trace portion extending on the second side, the second trace portion to receive the signal from the second node.

2. The device of claim 1, wherein the device comprises a first TI including the first node.

3. The device of any of claims 1 and 2, wherein the device comprises a second TI including the second node.

4. The device any of claims 1 through 3, wherein the plurality of TIs includes TIs coupled in series with each other between the first node and the second node.

5. The device of claim 1, wherein the plurality of TIs includes a first TI and a second TI coupled to the first TI, wherein a first trace portion is coupled directly to each of the first TI and the second TI at the first side, and wherein a second trace portion is coupled directly to each of the first TI and the second TI at the second side.

6. The device of claim 1, wherein the plurality of TIs includes a first TI and a second TI, and wherein a distance between the first TI and the second TI is less than a width of the first TI.

7. The device any of claims 1 through 6, wherein the substrate includes a conductive plane disposed between the first side and the second side, the conductive plane to provide a reference potential to circuitry of the device, wherein one of the plurality of TIs extend through a hole formed by the conductive plane.

8. The device any of claims 1 through 7, wherein the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions.

9. The device of claim 8, wherein the plurality of TIs includes five TIs each coupled directly to a respective one of the first branch portions

10. A method comprising:

forming through-holes each extending from a first side of a substrate to a second side of the substrate;

forming a plurality of through-hole interconnects (TIs), including depositing a conductor in the through-holes, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs;

forming first branch portions on the first side, wherein the first branch portions each extend from a first node to a respective one of the plurality of TIs; and

forming second branch portions on the second side, wherein the second branch portions each extend from a respective one of the plurality of TIs to a second node, wherein the plurality of TIs are configured to propagate a respective portion of a signal between the first node and the second node.

11. The method of claim 10, wherein an end of a first TI includes the first node.

12. The method of any of claims 10 and 11, wherein an end of a second TI includes the second node.

13. The method any of claims 10 through 12, further comprising coupling multiple TIs of the plurality of TIs in series with each other between the first node and the second node.

14. The method of claim 10, wherein the plurality of TIs includes a first TI and a second TI coupled to the first TI, the method further comprising:

coupling a first trace portion directly to each of the first TI and the second TI at the first side; and

coupling a second trace portion directly to each of the first TI and the second TI at the second side.

15. The method of claim 10, wherein the plurality of TIs includes a first TI and a second TI, and wherein a distance between the first TI and the second TI is less than a width of the first TI.

16. The method any of claims 10 through 15, wherein the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions.

17. The method of claim 16, wherein the plurality of TIs includes five TIs each coupled directly to a respective one of the first branch portions

18. A system comprising:

an interconnect device including:

a substrate; a plurality of through-hole interconnects (TIs) each extending from a first side of the substrate to a second side of the substrate, wherein an insulator of the substrate is disposed between two TIs of the plurality of TIs;

a second trace portion extending on the second side, the second trace portion to receive the signal from the second node; and

a display device coupled to the interconnect device, the display device to display an image based on signals exchanged with the one or more IC chips.

19. The system of claim 18, wherein the interconnect device comprises a first TI including the first node.

20. The system of any of claims 18 and 19, wherein the interconnect device comprises a second TI including the second node.

21. The system any of claims 18 through 20, wherein the plurality of TIs includes TIs coupled in series with each other between the first node and the second node.

22. The system of claim 18, wherein the plurality of TIs includes a first TI and a second TI coupled to the first TI, wherein a first trace portion is coupled directly to each of the first TI and the second TI at the first side, and wherein a second trace portion is coupled directly to each of the first TI and the second TI at the second side.

23. The system of claim 18, wherein the plurality of TIs includes a first TI and a second TI, and wherein a distance between the first TI and the second TI is less than a width of the first TI.

24. The system any of claims 18 through 23, wherein the substrate includes a conductive plane disposed between the first side and the second side, the conductive plane to provide a reference potential to circuitry of the system, wherein one of the plurality of TIs extend through a hole formed by the conductive plane.

25. The system any of claims 18 through 24, wherein the plurality of TIs includes three TIs each coupled directly to a respective one of the first branch portions.