WO2017111925A1 - Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point - Google Patents

Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point Download PDF

Info

Publication number
WO2017111925A1
WO2017111925A1 PCT/US2015/067198 US2015067198W WO2017111925A1 WO 2017111925 A1 WO2017111925 A1 WO 2017111925A1 US 2015067198 W US2015067198 W US 2015067198W WO 2017111925 A1 WO2017111925 A1 WO 2017111925A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
overlay
shift
underlying layer
providing
Prior art date
Application number
PCT/US2015/067198
Other languages
English (en)
Inventor
Shakul TANDON
Charles H. Wallace
Paul A. Nyhus
Martin N. Weiss
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/067198 priority Critical patent/WO2017111925A1/fr
Publication of WO2017111925A1 publication Critical patent/WO2017111925A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • Embodiments of the invention are in the field of semiconductor structures and processing and, in particular, multi-pitch or variable pitch grating structures for overlay, dose, or focus information extraction.
  • shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity.
  • the drive for ever-more capacity, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias.
  • Vias are typically formed by a lithographic process.
  • a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer.
  • an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening.
  • the via opening may be filled with one or more metals or other conductive materials to form the via.
  • the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.).
  • One measure of the size of the vias is the critical dimension of the via opening.
  • One measure of the spacing of the vias is the via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.
  • a further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners.
  • EUV extreme ultraviolet
  • commonly two, three, or more different lithographic masks may be used, which tend to increase the costs.
  • pitches continue to decrease it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.
  • Figures 1 A-1D illustrate cross-sectional views and corresponding top-down views representing various operations a patterning processing scheme using pre-patterned hard masks, in accordance with an embodiment of the present invention, where:
  • Figure 1 A illustrates a starting structure with a first pre-pattemed hardmask and a second pre-pattemed hardmask formed above an underlying layer, and openings formed in locations between the first pre-patterned hardmask and a second pre-patterned hardmask;
  • Figure IB illustrates the structure of Figure 1A following the formation of a plurality of photoresist layer portions in the openings;
  • Figure 1C illustrates the structure of Figure IB following exposure of select ones of the plurality of photoresist layer portions by a lithographic exposure; and [0014] Figure ID illustrates the structure of Figure 3C following clearing of exposed photo-resist from the select locations to provide select openings.
  • Figure 2 includes cross-section scanning electron microscope images showing a structure having photoresist removed from a photobucket and showing a photobuckets with photoresist remaining, in accordance with an embodiment of the present invention.
  • Figure 3A illustrates a top-down view of an overlay scenario where a current layer is perfectly overlay ed on an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • Figure 3B illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • Figure 3C illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of half pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • Figure 3D illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value ⁇ with respect to an underlying pre-pattemed hard mask grid, in accordance with an embodiment of the present invention.
  • Figure 3E illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value ⁇ with respect to an underlying pre-pattemed hard mask grid, where a measurable ⁇ is made as small as needed by changing s resist sensitivity and/or the drawn feature size, in accordance with an embodiment of the present invention.
  • Figure 4 illustrates an exemplary metrology structure suitable for the approaches described above in association with Figures 3A-3E, in accordance with an embodiment of the present invention.
  • Figure 5A illustrates a top-down view of a dose scenario where the dose is on target, in accordance with an embodiment of the present invention.
  • Figure 5B illustrates a top-down view of a dose scenario where the dose is decreased from the target, in accordance with an embodiment of the present invention.
  • Figure 5C illustrates a top-down view of a dose scenario where the dose is increased from the target, in accordance with an embodiment of the present invention.
  • Figure 5D illustrates a top-down view of a focus scenario where the focus is on target, in accordance with an embodiment of the present invention.
  • Figure 5E illustrates a top-down view of a focus scenario where the focus is increased from the target, in accordance with an embodiment of the present invention.
  • Figure 6 illustrates an exemplary metrology structure suitable for the approaches described above in association with Figures 5A-5E, in accordance with an embodiment of the present invention.
  • Figure 7 illustrates a computing device in accordance with one implementation of the invention.
  • Figure 8 is an interposer implementing one or more embodiments of the invention.
  • Multi-pitch or variable pitch grating structures for overlay, dose, or focus information extraction are described.
  • numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention.
  • One or more embodiments described herein are directed to approaches involving the use of multi-pitch grating structures on a layer to extract overlay information relative to an underlying layer.
  • One or more embodiments involve the use of variable pitch grating structures to extract dose and focus information.
  • Embodiments may be manifested in the context of one or more of lithography, metrology, overlay, dose or focus.
  • Figures 1A-1D illustrate cross-sectional views and corresponding top-down views representing various operations a patterning processing scheme using pre-patterned hard masks, in accordance with an embodiment of the present invention.
  • a first pre-patterned hardmask 102 and a second pre- patterned hardmask 104 are formed above an underlying layer 106. All possible via or plug locations are exposed as openings 108 in the pre-patterned hardmask 102 and the second pre- patterned hardmask 104.
  • a plurality of photoresist layer portions 110 is formed in the openings 108 of Figure 1A.
  • select ones 1 12 of the plurality of photoresist layer portions 1 10 are exposed by a lithographic exposure 114.
  • the select ones 1 12 of the plurality of photoresist layer portions 1 10 exposed by the lithographic exposure 1 14 may represent the via or plug locations that will ultimately be opened or selected.
  • the lithographic exposure 1 14 has an overlay error in the X-direction of Figure 1C.
  • the exposed photoresist layer 112 on the left hand-side of the cross-section view is shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure 1 14.
  • All exposed photoresist layers 1 12 of the top-down view are shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure 114.
  • the shift may be substantial enough to partially expose neighboring locations, as is depicted in Figure 1C.
  • the select locations 112 are cleared of exposed photoresist to provide openings 116.
  • the openings 1 16 may be used for subsequent via or plug fabrication, depending on the specific layer of the semiconductor structure.
  • openings 116 may catastrophically not be completely opened.
  • the exposure 1 14 must provide a critical number of electrons or photons to completely clear the select ones 1 12 of the plurality of photoresist layer portions 110 to provide openings 116.
  • Some overlay error may be tolerated, but substantial overlay error may not be tolerated.
  • successful fabrication of a next layer may require an overlay measurement based at least to some extent on the openings 1 16.
  • approaches described herein build on approaches using so-called "photobuckets," in which every possible feature, e.g. via or plug, is re-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation.
  • the photobucket approach allows for larger error tolerance in overlay while retaining the ability to choose the via or plug of interest.
  • Lithographic approaches for selecting particular photobuckets may include, but may not be limited to, 193nm immersion lithography (193i), extreme ultra-violet (EUV) and/or e-beam direct write (EBDW) lithography. It is also to be appreciated that embodiments are not limited to the concept of photobuckets, but have far reaching applications to structures having pre-formed features.
  • Figure 2 includes cross-section scanning electron microscope images showing a structure having photoresist removed from a photobucket (image 200) and showing a photobuckets with photoresist remaining (image 202), in accordance with an embodiment of the present invention.
  • embodiments described herein may be implemented to solve issues associated with measuring overlay between a layer patterned on top of a pre-pattemed hard mask (e.g., via or plug) and the underlying pre-patterned hard mask layer (e.g., photobucket) by using an optical metrology tool.
  • gratings are patterned at two or more pitches that are different from the underlying pre-patterned gratings, but parallel to one of the underlying gratings.
  • a shift in overlay of the current layer versus the hard mask pattern results in an optical signal that moves with the overlay and is proportional to the overlay error.
  • optical overlay typically involves real features, thus providing an analogue response.
  • movement is quantized as opposed moving in analogue motion. That is, the response is digital (e.g., digitized and magnified motion) in that it is based on steps.
  • a "fringe" pattern is measured.
  • Figures 3A-3E described below demonstrate the generation of optical signals using photobuckets that respond to a change in overlay. It is to be appreciated that conventional optical metrology tools measure relatively large targets (e.g., 20-30 microns). For embodiments described herein, structures are generated from arrays of lines/spaces that are below the resolution limit of an inspection tool and which leverage the photobuckets concept to create moving edges that can be detected/measured with conventional overlay measurement algorithms. The final pattern seen by the metrology tool shows measurable optical edges due to diffraction and scattering of light from sub-resolution patterns that move with overlay. Figure 4 shows a possible optical metrology mark for use in association with Figures 3A-3E.
  • Figure 3A illustrates a top-down view of an overlay scenario where a current layer is perfectly overlay ed on an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a current layer is represented by overlay images 300A.
  • the overlay images 300A have an overlay shift of zero and a pitch delta of P/4.
  • the pitch of the overlay images 300A of the current layer shown as 25% larger (in the top half region 302A) and 25% smaller (in the bottom half region 304A) as an exemplary embodiment.
  • Wide unexposed features 306A and 308A are included in the current layer, as is depicted in Figure 3A.
  • Figure 3B illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a current layer is represented by overlay images 300B.
  • the overlay images 300B have a positive (+ve) overlay shift of P/4.
  • Wide unexposed features 306B and 308B are included in the current layer, with movement of the wide unexposed features 306B and 308B as depicted in Figure 3B.
  • Figure 3C illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of half pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a current layer is represented by overlay images 300C.
  • the overlay images 300C have a positive (+ve) overlay shift of P/2.
  • Wide unexposed features 306C and 308C are included in the current layer, with movement of the wide unexposed features 306C and 308C as depicted in Figure 3C.
  • Figure 3D illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value ⁇ with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.
  • an underlying layer includes a first pre-pattemed hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a current layer is represented by overlay images 300D.
  • the overlay images 300D have an overlay shift of zero and a pitch delta of P + ⁇ . Wide unexposed features 306D and 308D are included in the current layer, as is depicted in Figure 3D.
  • Figure 3E illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value ⁇ with respect to an underlying pre-pattemed hard mask grid, where a measurable ⁇ is made as small as needed by changing s resist sensitivity and/or the drawn feature size, in accordance with an embodiment of the present invention.
  • an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a current layer is represented by overlay images 300E.
  • the overlay images 300E have an overlay shift of + ⁇ and a pitch delta of P + ⁇ .
  • Wide unexposed features 306E and 308E are included in the current layer, with movement of the wide unexposed features 306E and 308E as depicted in Figure 3E.
  • the measured signal is amplified to the order of P, and ⁇ can be as small as needed.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer comprising a pre-pattemed grating structure having a pitch.
  • An overlying layer is provided on the underlying layer.
  • the overlying layer includes a grating pattern having two or more pitches different from the pitch of the pre-pattemed grating structure of the underlying layer.
  • a shift in overlay of the overlying layer relative to the pre-pattemed grating structure of the underlying layer is measured for using optical metrology.
  • a shift in dose of the overlying layer relative to the pre-patterned grating structure of the underlying layer is also measured for, an example of which is described below in association with Figures 5A-5C.
  • a shift in focus of the overlying layer relative to the pre-pattemed grating structure of the underlying layer is also measured for, an example of which is described below in association with Figures 5D and 5E.
  • Figure 4 illustrates an exemplary metrology structure suitable for the approaches described above in association with Figures 3A-3E, in accordance with an embodiment of the present invention.
  • a metrology structure 400 includes both layer 1 features 402 (e.g., underlying layer) and layer 2 features 404 (e.g., current layer).
  • the width of each of the features is approximately 20-30 microns, as is depicted in Figure 4.
  • a completed die may include a region having a beat frequency of wide features formed by an array of vias or plugs in a collection of narrow features.
  • the presence of two different beat frequencies in any direction may imply the use of the above described technique to measure overlay.
  • the approach described above may enable accurate measurement of overlay in photobuckets for every via or plug patterning layer that uses the technique. Embodiments may enhance accuracy for future generations of technology while using current technology overlay measurement tools.
  • embodiments described herein may be implemented to solve issues associated with the problem of measuring dose and focus of a layer patterned on a pre-patterned hard mask (e.g., via or plug) by using an optical metrology tool.
  • gratings are patterned with varying critical dimensions (CDs).
  • An optical contrast is generated at a certain critical CD size.
  • a change in either dose or focus changes the critical CD size, resulting in a change in position of the contrast signal.
  • the use of two gratings amplifies the signal resulting in a higher accuracy.
  • the standard tool used to characterize dose and focus is a scanning electron microscope that measures the change in the critical dimension (CD) of a feature versus dose and focus. Since the CD change in patterning using pre-patterned hard mask (photobuckets) is both binary, and quantized, that method may no longer be appropriate. By using a sufficiently small CD step size, both dose and focus can be measured very accurately. Moreover, by using an optical metrology tool instead of a scanning electron microscope, the processing time is reduced as both overlay and CDs on the wafer can be measured in one operation. Furthermore, a cost savings associated with the use of fewer tools may be realized, both from fab space as well as tool costs perspective.
  • CD critical dimension
  • Figure 5A illustrates a top-down view of a dose scenario where the dose is on target, in accordance with an embodiment of the present invention.
  • a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a dose is represented by images 500A.
  • the dose 500A is on target in this scenario.
  • Wide exposed features 506A and 508A are included, as depicted in Figure 5A.
  • the edge of the wide exposed area 506A or 508A generates good optical contrast.
  • CD critical dimension
  • Figure 5B illustrates a top-down view of a dose scenario where the dose is decreased from the target, in accordance with an embodiment of the present invention.
  • a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a dose is represented by images 500B.
  • the dose 500B is decreased from the target by an amount ⁇ , i.e., dose is target - ⁇ .
  • Wide exposed features 506B and 508B are included, as depicted in Figure 5B. In an embodiment, as dose decreases, the contrast generating edge moves in opposite directions.
  • Figure 5C illustrates a top-down view of a dose scenario where the dose is increased from the target, in accordance with an embodiment of the present invention.
  • a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a dose is represented by images 500C.
  • the dose 500C is increased from the target by an amount ⁇ , i.e., dose is target + ⁇ .
  • Wide exposed features 506C and 508C are included, as depicted in Figure 5C. In an embodiment, as dose increases, the contrast generating edge moves in reverse direction.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure.
  • An overlying layer is provided on the underlying layer.
  • the overlying layer includes a grating pattern having multiple critical dimensions (CDs).
  • CDs critical dimensions
  • a shift in dose of the overlying layer relative to the underlying layer is measured using optical metrology.
  • a shift in focus of the overlying layer relative to the pre-patterned grating structure of the underlying layer is also measured for, an example of which is described below in association with Figures 5D and 5E.
  • Figure 5D illustrates a top-down view of a focus scenario where the focus is on target, in accordance with an embodiment of the present invention.
  • a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 110 and a plurality of openings 116 are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a focus is represented by images 500D. The focus 500D is on target in this scenario.
  • Wide exposed features 506D and 508D are included, as depicted in Figure 5D.
  • the edge of the wide exposed feature 506A or 508A generates good optical contrast.
  • CD critical dimension
  • Figure 5E illustrates a top-down view of a focus scenario where the focus is increased from the target, in accordance with an embodiment of the present invention.
  • a layer includes a first pre-pattemed hardmask 102 and a second pre-patterned hardmask 104.
  • a plurality of photoresist layer portions 1 10 and a plurality of openings 116 are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures.
  • a focus is represented by images 500E.
  • the focus 500E is increased from the target in this scenario by an amount ⁇ , e.g., focus is target + ⁇ .
  • Wide exposed features 506E and 508E are included, as depicted in Figure 5E.
  • the contrast generating edges moves in opposite directions for the gratings at the top (region 502E) and bottom (region 504E. It is to be appreciated that a similar effect occurs when the dose is decreased from the target.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. An overlying layer is provided on the underlying layer. The overlying layer includes a grating pattem having multiple critical dimensions (CDs). A shift in focus of the overlying layer relative to the underlying layer is measured for using optical metrology.
  • CDs critical dimensions
  • FIG. 6 illustrates an exemplary metrology structure suitable for the approaches described above in association with Figures 5A-5E, in accordance with an embodiment of the present invention.
  • a metrology structure 600 includes both layer 1 features 602 (e.g., underlying layer) and layer 2 features 604 (e.g., current layer).
  • layer 1 features 602 e.g., underlying layer
  • layer 2 features 604 e.g., current layer
  • the center-of-mass 606 of the layer 2 (604) edge and the center-of-mass 608 of the layer 1 (602) edge is as depicted in Figure 6.
  • Such a structure may be included in a scribe line or on die in a drop-in cell, for example.
  • a completed die may include a region having a beat frequency of wide features formed by an array of vias or plugs in a collection of narrow features.
  • the approaches described above may enable accurate measurement of overlay in photobuckets for every via or plug patterning layer that uses the technique. Embodiments may enhance accuracy for future generations of technology while using current technology overlay measurement tools. [0072]
  • issues associated with across die/wafer etch non-uniformity can reduce yield and/or performance of fabricated semiconductor structures.
  • One or more embodiments described herein offer a more efficient approach to patterning by maximizing the overlay process window, minimizing the size and shape of required pattems, and increasing the efficiency of the lithography process to pattem holes or plugs.
  • a pattern needed to open a pre-formed via or plug location can be made to be relatively small, enabling an increase in the overlay margin of a lithographic process.
  • the pattern features can be made of uniform size, which can reduce scan time on direct write ebeam and/or optical proximity correction (OPC) complexity with optical lithography.
  • OPC optical proximity correction
  • the pattern features can also be made to be shallow or deep.
  • a subsequently performed etch process may be an isotropic chemically selective etch. Such an etch process mitigates otherwise associated with profile and critical dimension and mitigates anisotropic issues typically associated with dry etch approaches. Such an etch process is also relatively much less expensive from an equipment and throughput perspective as compared to other selective removal approaches.
  • embodiments described herein involve the fabrication of metal and via patterns based on the positions of an underlying layer. That is, in contrast to conventional top-down patterning approaches, a metal interconnect process is effectively reversed and built from the previous layer up. This is in contrast to a conventional approach such as dual damascene metallization where an interlay er dielectric (ILD) is first deposited, with a pattern for metal and via layers subsequently patterned therein. In the conventional approach, alignment to a previous layer is performed using a lithography scanner alignment system. The ILD is then etched.
  • ILD interlay er dielectric
  • one or more embodiments are directed to an approach that employs an underlying metal as a template to build the conductive vias and non-conductive spaces or interruptions between metals (referred to as "plugs"). Vias, by definition, are used to land on a previous layer metal pattern.
  • embodiments described herein enable a more robust interconnect fabrication scheme since alignment by lithography equipment is no longer relied on. Such an interconnect fabrication scheme can be used to save numerous
  • alignment/exposures can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches.
  • One or more embodiment described herein involves the use of a subtractive method to pre-form every via or via opening using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations is illustrated above using "photobuckets," although the selection process may also be performed using a more conventional resist expose and ILD backfill approach.
  • an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits.
  • the semiconductor substrate often includes a wafer or other piece of silicon or another
  • Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials.
  • SOI silicon on insulator
  • the semiconductor substrate depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like.
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • the structures described above may be fabricated on underlying lower level interconnect layers.
  • interlayer dielectric In an embodiment, as used throughout the present description, interlayer dielectric
  • ILD inorganic dielectric
  • suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (S1O 2 )), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof.
  • the interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-on deposition, or by other deposition methods.
  • interconnect material is composed of one or more metal or other conductive structures.
  • a common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material.
  • metal includes alloys, stacks, and other combinations of multiple metals.
  • the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc.
  • the interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect.
  • top surfaces of the lower interconnect lines may be used for self-aligned via and plug formation.
  • patterned features may be patterned in a grating-like pattern with lines, holes or trenches spaced at a constant pitch and having a constant width.
  • the partem may be fabricated by a pitch halving or pitch quartering approach.
  • a blanket film is patterned using lithography and etch processing which may involve, e.g., spacer- based-quadruple-patterning (SBQP) or pitch quartering.
  • SBQP spacer- based-quadruple-patterning
  • a grating pattern of lines can be fabricated by numerous methods, including 193nm immersion litho (193i), EUV and/or EBDW lithography, directed self-assembly, etc.
  • hardmask materials are composed of dielectric materials different from the interlayer dielectric material.
  • different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers.
  • a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof.
  • Other suitable materials may include carbon-based materials.
  • a hardmask material includes a metal species.
  • a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride), or a metal oxide.
  • hardmask layers may be used depending upon the particular implementation.
  • the hardmask layers maybe formed by CVD, PVD, ALD, or by other deposition methods.
  • a final structure layer described above may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers.
  • the structure layer may represent the final metal interconnect layer in an integrated circuit.
  • the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed.
  • the resulting structures enable fabrication of, e.g., vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein.
  • Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
  • Figure 7 illustrates a computing device 700 in accordance with one
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706.
  • the processor 704 is physically and electrically coupled to the board 702.
  • the at least one communication chip 706 is also physically and electrically coupled to the board 702.
  • the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706.
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the integrated circuit die of the processor is fabricated using a metrology operation involving a multi-pitch or variable pitch grating structure for overlay, dose, or focus information extraction at some stage in the manufacturing process, in accordance with implementations of the invention.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the integrated circuit die of the communication chip is fabricated using a metrology operation involving a multi-pitch or variable pitch grating structure for overlay, dose, or focus information extraction at some stage in the manufacturing process, in accordance with implementations of the invention.
  • another component housed within the computing device 700 may contain an integrated circuit die that is fabricated using a metrology operation involving a multi-pitch or variable pitch grating structure for overlay, dose, or focus information extraction at some stage in the manufacturing process, in accordance with implementations of the invention.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • FIG 8 illustrates an interposer 800 that includes one or more embodiments of the invention.
  • the interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804.
  • the first substrate 802 may be, for instance, an integrated circuit die.
  • the second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804.
  • BGA ball grid array
  • first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.
  • the interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812.
  • the interposer 800 may further include embedded devices 814, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800.
  • RF radio- frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.
  • embodiments of the present invention include multi-pitch or variable pitch grating structures for overlay, dose, or focus information extraction.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer comprising a pre-patterned grating structure having a pitch. The method also includes providing an overlying layer on the underlying layer, the overlying layer including a grating pattern having two or more pitches different from the pitch of the pre-patterned grating structure of the underlying layer. The method also includes measuring for a shift in overlay of the overlying layer relative to the pre-patterned grating structure of the underlying layer.
  • measuring for the shift in overlay includes obtaining an optical signal that moves with the shift in overlay and is proportional to an overlay error between the underlying layer and the overlying layer.
  • obtaining the optical signal that moves with the shift in overlay includes obtaining an optical signal that moves in a digitized and magnified motion with the shift in overlay.
  • obtaining the optical signal that moves with the shift in overlay includes obtaining a fringe pattern.
  • providing the semiconductor structure having the underlying layer includes providing the underlay er having a plurality of filled photobuckets.
  • providing the semiconductor structure having the underlying layer further includes providing the underlayer having a plurality of unfilled photobuckets.
  • providing the overlying layer on the underlying layer includes providing the overlying layer including a grating pattern having multiple critical dimensions (CDs).
  • measuring for the shift in overlay further includes measuring for a shift in dose of the overlying layer relative to the pre-patterned grating structure of the underlying layer.
  • measuring for the shift in overlay further includes measuring for a shift in focus of the overlying layer relative to the pre-patterned grating structure of the underlying layer.
  • measuring for the shift in overlay further includes measuring for a shift in dose of the overlying layer relative to the pre-patterned grating structure of the underlying layer and measuring for a shift in focus of the overlying layer relative to the pre- patterned grating structure of the underlying layer.
  • the overlying layer comprises at least two different beat frequencies in any direction.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. The method also includes providing an overlying layer on the underlying layer, the overlying layer including a grating pattern having multiple critical dimensions (CDs). The method also includes measuring for a shift in dose of the overlying layer relative to the underlying layer.
  • CDs critical dimensions
  • measuring for the shift in dose comprises detecting a change in position of an optical contrast signal.
  • providing the semiconductor structure having the underlying layer includes providing the underlay er having a plurality of filled photobuckets.
  • providing the semiconductor structure having the underlying layer further includes providing the underlayer having a plurality of unfilled photobuckets.
  • measuring for the shift in dose further includes measuring for a shift in focus of the overlying layer relative to the underlying layer.
  • a method of performing optical metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. The method also includes providing an overlying layer on the underlying layer, the overlying layer including a grating pattern having multiple critical dimensions (CDs). The method further includes measuring for a shift in focus of the overlying layer relative to the underlying layer.
  • CDs critical dimensions
  • measuring for the shift in focus includes detecting a change in position of an optical contrast signal.
  • providing the semiconductor structure having the underlying layer includes providing the underlayer having a plurality of filled photobuckets. [00113] In one embodiment, providing the semiconductor structure having the underlying layer further includes providing the underlayer having a plurality of unfilled photobuckets.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

L'invention décrit des structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point. Selon un exemple, un procédé de conduite de métrologie optique d'une structure semi-conductrice consiste à réaliser une structure semi-conductrice dont une couche sous-jacente comprend une structure de réseau à prémotif comportant un pas. Le procédé consiste également à appliquer une couche sus-jacente sur la couche sous-jacente, la couche sus-jacente incluant un motif de réseau dont deux pas ou plus sont différents du pas de la structure de réseau à prémotif de la couche sous-jacente. Le procédé consiste également à mesurer un décalage dans la superposition de la couche sus-jacente par rapport à la structure de réseau à prémotif de la couche sous-jacente.
PCT/US2015/067198 2015-12-21 2015-12-21 Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point WO2017111925A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/067198 WO2017111925A1 (fr) 2015-12-21 2015-12-21 Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/067198 WO2017111925A1 (fr) 2015-12-21 2015-12-21 Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point

Publications (1)

Publication Number Publication Date
WO2017111925A1 true WO2017111925A1 (fr) 2017-06-29

Family

ID=59091015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/067198 WO2017111925A1 (fr) 2015-12-21 2015-12-21 Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point

Country Status (1)

Country Link
WO (1) WO2017111925A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020115125A1 (fr) * 2018-12-04 2020-06-11 Asml Netherlands B.V. Cible pour mesurer un paramètre d'un processus lithographique
CN111324019A (zh) * 2020-02-25 2020-06-23 上海华力集成电路制造有限公司 一种同时获得多层间套刻精度的量测标识及量测方法
US10892223B2 (en) 2016-12-23 2021-01-12 Intel Corporation Advanced lithography and self-assembled devices
US20220121129A1 (en) * 2019-02-19 2022-04-21 Asml Netherlands B.V. Metrology system, lithographic apparatus, and method
US11748869B1 (en) 2019-07-08 2023-09-05 Intel Corporation Image-based overlay targets incorporating features for pattern recognition and moire fringe patterns for measurement

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070081170A1 (en) * 2002-07-03 2007-04-12 Tokyo Electron Limited Overlay metrology method and apparatus using more than one grating per measurement direction
US7440105B2 (en) * 2002-12-05 2008-10-21 Kla-Tencor Technologies Corporation Continuously varying offset mark and methods of determining overlay
KR20130109822A (ko) * 2012-03-28 2013-10-08 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
US20150179513A1 (en) * 2013-12-20 2015-06-25 Alan M. Myers Diagonal hardmasks for improved overlay in fabricating back end of line (beol) interconnects
WO2015090838A1 (fr) * 2013-12-19 2015-06-25 Asml Netherlands B.V. Procédés d'inspection, substrats ayant des cibles de métrologie, système lithographique et procédé de fabrication de dispositif

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070081170A1 (en) * 2002-07-03 2007-04-12 Tokyo Electron Limited Overlay metrology method and apparatus using more than one grating per measurement direction
US7440105B2 (en) * 2002-12-05 2008-10-21 Kla-Tencor Technologies Corporation Continuously varying offset mark and methods of determining overlay
KR20130109822A (ko) * 2012-03-28 2013-10-08 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
WO2015090838A1 (fr) * 2013-12-19 2015-06-25 Asml Netherlands B.V. Procédés d'inspection, substrats ayant des cibles de métrologie, système lithographique et procédé de fabrication de dispositif
US20150179513A1 (en) * 2013-12-20 2015-06-25 Alan M. Myers Diagonal hardmasks for improved overlay in fabricating back end of line (beol) interconnects

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892223B2 (en) 2016-12-23 2021-01-12 Intel Corporation Advanced lithography and self-assembled devices
US11373950B2 (en) 2016-12-23 2022-06-28 Intel Corporation Advanced lithography and self-assembled devices
US11854787B2 (en) 2016-12-23 2023-12-26 Intel Corporation Advanced lithography and self-assembled devices
WO2020115125A1 (fr) * 2018-12-04 2020-06-11 Asml Netherlands B.V. Cible pour mesurer un paramètre d'un processus lithographique
US12019377B2 (en) 2018-12-04 2024-06-25 Asml Netherlands B.V. Target for measuring a parameter of a lithographic process
US20220121129A1 (en) * 2019-02-19 2022-04-21 Asml Netherlands B.V. Metrology system, lithographic apparatus, and method
US11748869B1 (en) 2019-07-08 2023-09-05 Intel Corporation Image-based overlay targets incorporating features for pattern recognition and moire fringe patterns for measurement
CN111324019A (zh) * 2020-02-25 2020-06-23 上海华力集成电路制造有限公司 一种同时获得多层间套刻精度的量测标识及量测方法
CN111324019B (zh) * 2020-02-25 2022-11-29 上海华力集成电路制造有限公司 一种同时获得多层间套刻精度的量测标识及量测方法

Similar Documents

Publication Publication Date Title
US9553018B2 (en) Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
US9793163B2 (en) Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects
US9548269B2 (en) Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
US11276581B2 (en) Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
US11854882B2 (en) Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
US10522402B2 (en) Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom
US10319625B2 (en) Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
US10770291B2 (en) Methods and masks for line end formation for back end of line (BEOL) interconnects and structures resulting therefrom
WO2017111868A1 (fr) Approches pour la formation des motifs d'extrémités de lignes métalliques pour interconnexions de type « fin de ligne » (beol)
WO2017111925A1 (fr) Structures de réseau à pas multiple ou variable pour l'extraction d'informations de superposition, de dose ou de mise au point
US11953826B2 (en) Lined photobucket structure for back end of line (BEOL) interconnect formation
WO2017111923A1 (fr) Approches pour mesurer le recouvrement, la dose ou la focalisation sur des structures de masque dur à motif préformé à l'aide de la microscopie électronique à balayage (meb)

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15911609

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15911609

Country of ref document: EP

Kind code of ref document: A1