WO2017111923A1

WO2017111923A1 - Approaches for measuring overlay, dose or focus on pre-patterned hardmask structures using scanning electron microscopy (sem)

Info

Publication number: WO2017111923A1
Application number: PCT/US2015/067195
Authority: WO
Inventors: Shakul TANDON; Charles H. Wallace; Paul A. Nyhus
Original assignee: Intel Corporation
Priority date: 2015-12-21
Filing date: 2015-12-21
Publication date: 2017-06-29

Abstract

Approaches for measuring overlay, dose, or focus on pre-patterned hardmask structures using scanning electron microscopy (SEM) are described. In an example, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure having a pitch. The method also includes providing an overlying layer on the underlying layer, the overlying layer including a grating pattern having a pitch different from the pitch of the pre-patterned grating structure of the underlying layer. The method also includes measuring for an overlay mismatch of the overlying layer relative to the pre-patterned grating structure of the underlying layer by detecting a location of a first cleared photobucket of the underlying layer.

Description

APPROACHES FOR MEASURING OVERLAY, DOSE, OR FOCUS ON PRE-PATTERNED HARDMASK STRUCTURES USING SCANNING ELECTRON MICROSCOPY (SEM)

TECHNICAL FIELD

[0001] Embodiments of the invention are in the field of semiconductor structures and processing and, in particular, approaches for measuring overlay, dose, or focus on pre-patterned hardmask structures using scanning electron microscopy (SEM).

BACKGROUND

[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

[0003] Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

[0004] In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension of the via opening. One measure of the spacing of the vias is the via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.

[0005] When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves, especially when the pitches are around 70 nanometers (nm) or less and/or when the critical dimensions of the via openings are around 35nm or less. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

[0006] Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be modeled sufficiently accurately, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).

[0007] Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

[0008] A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.

[0009] Improvements are needed in the area of back end metallization manufacturing and metrology technologies for fabricating metal lines, metal vias, and dielectric plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 A-1D illustrate cross-sectional views and corresponding top-down views representing various operations a patterning processing scheme using pre-patterned hardmasks, in accordance with an embodiment of the present invention, where:

[0011] Figure 1 A illustrates a starting structure with a first pre-pattemed hardmask and a second pre-pattemed hardmask formed above an underlying layer, and openings formed in locations between the first pre-patterned hardmask and a second pre-patterned hardmask;

[0012] Figure IB illustrates the structure of Figure 1A following the formation of a plurality of photoresist layer portions in the openings;

[0013] Figure 1C illustrates the structure of Figure IB following exposure of select ones of the plurality of photoresist layer portions by a lithographic exposure; and [0014] Figure ID illustrates the structure of Figure 3C following clearing of exposed photo-resist from the select locations to provide select openings.

[0015] Figure 2 includes cross-section scanning electron microscope images showing a structure having photoresist removed from a photobucket and showing a photobuckets with photoresist remaining, in accordance with an embodiment of the present invention.

[0016] Figure 3A illustrates a top-down view of an overlay scenario where a current layer is perfectly overlaid on an underlying pre-patterned hardmask, in accordance with an embodiment of the present invention.

[0017] Figure 3B illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

[0018] Figure 3C illustrates a top-down view of an overlay scenario where a current layer has a negative overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

[0019] Figure 3D illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present invention.

[0020] Figure 3E illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-pattemed hardmask grid in the X-direction and has a positive overlay of quarter pitch with respect to the underlying pre- patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present invention.

[0021] Figure 4A illustrates a top-down view of a dose scenario where the dose is on target, in accordance with an embodiment of the present invention.

[0022] Figure 4B illustrates a top-down view of a dose scenario where the dose is increased from the target, in accordance with an embodiment of the present invention.

[0023] Figure 4C illustrates a top-down view of a dose scenario where the dose is decreased from the target, in accordance with an embodiment of the present invention.

[0024] Figure 4D illustrates a top-down view of a focus scenario where the focus is increased or decreased from the target, in accordance with an embodiment of the present invention.

[0025] Figure 5 illustrates a computing device in accordance with one implementation of the invention.

[0026] Figure 6 is an interposer implementing one or more embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS [0027] Approaches for measuring overlay, dose, or focus on pre-patterned hardmask structures using scanning electron microscopy (SEM) are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0028] One or more embodiments described herein are directed to approaches involving measuring overlay on pre-patterned hardmask (e.g., photobuckets) using critical dimension scanning electron microscopy (CDSEM) techniques. One or more embodiments involve measuring dose and/or focus of layers on pre-patterned hardmask structures (e.g., photobuckets) using CDSEM. Embodiments may be manifested in the context of one or more of lithography, metrology, overlay, dose, focus, or process control. It is to be appreciated that since the application is to CDSEM, fringe patterns are not measured, as would otherwise be the case for optical metrology techniques.

[0029] To provide context, current fabrication techniques for vias involves a "blind" process in which a via opening is patterned in a stack far above an ILD trench. The via opening pattern is then etched deep down into the trench. Overlay errors accumulate and can cause various problems, e.g., shorts to neighboring metal lines. In an example, patterning and aligning of features at less than approximately 50 nanometer pitch requires many reticles and critical alignment strategies that are otherwise extremely expensive for a semiconductor manufacturing process. In an embodiment, by contrast, approaches described herein involve metrology of fabricated self-aligned plugs and/or vias, greatly simplifying the web of overlay errors, and leaving only one critical overlay step (Mx+1 grating). In an embodiment, then, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the processes described herein.

[0030] To provide a structural framework for concepts described herein, Figures 1A-1D illustrate cross-sectional views and corresponding top-down views representing various operations a patterning processing scheme using pre-patterned hardmasks, in accordance with an embodiment of the present invention.

[0031] Referring to Figure 1A, a first pre-patterned hardmask 102 and a second pre- patterned hardmask 104 are formed above an underlying layer 106. All possible via or plug locations are exposed as openings 108 in the pre-patterned hardmask 102 and the second pre- patterned hardmask 104.

[0032] Referring to Figure IB, a plurality of photoresist layer portions 110 is formed in the openings 108 of Figure 1A.

[0033] Referring to Figure 1 C, select ones 1 12 of the plurality of photoresist layer portions 1 10 are exposed by a lithographic exposure 114. The select ones 1 12 of the plurality of photoresist layer portions 1 10 exposed by the lithographic exposure 1 14 may represent the via or plug locations that will ultimately be opened or selected.

[0034] However, in accordance with an embodiment of the present invention, the lithographic exposure 1 14 is has an overlay error in the X-direction of Figure 1C. For example, the exposed photoresist layer 1 12 on the left hand-side of the cross-section view is shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure 1 14. All exposed photoresist layers 1 12 of the top-down view are shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure 114. Furthermore, the shift may be substantial enough to partially expose neighboring locations, as is depicted in Figure 1C.

[0035] Referring to Figure ID, the select locations 1 12 are cleared of exposed photoresist to provide openings 116. The openings 1 16 may be used for subsequent via or plug fabrication, depending on the specific layer of the semiconductor structure.

[0036] However, in the case that an insufficient exposure of the locations 112 is performed due to overlay error, some openings 116 may catastrophically not be completely opened. In general, the exposure 1 14 must provide a critical number of electrons or photons to completely clear the select ones 1 12 of the plurality of photoresist layer portions 110 to provide openings 116. Some overlay error may be tolerated, but substantial overlay error may not be tolerated. Additionally, as described in greater detail below, even in the case that all openings 1 16 are completely opened, successful fabrication of a next layer may require an overlay measurement based at least to some extent on the openings 1 16.

[0037] In an exemplary embodiment, approaches described herein build on approaches using so-called "photobuckets," in which every possible feature, e.g. via or plug, is pre-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation. The photobucket approach allows for larger error tolerance in overlay while retaining the ability to choose the via or plug of interest. Lithographic approaches for selecting particular photobuckets may include, but may not be limited to, 193nm immersion lithography (il 93), extreme ultra-violet (EUV) and/or e-beam direct write (EBDW) lithography. It is also to be appreciated that embodiments are not limited to the concept of photobuckets, but have far reaching applications to structures having pre-formed features.

[0038] To exemplify the concepts above, and as a foundation for the embodiments described below, Figure 2 includes cross-section scanning electron microscope images showing a structure having photoresist removed from a photobucket (image 200) and showing a photobuckets with photoresist remaining (image 202), in accordance with an embodiment of the present invention.

[0039] In a first aspect, with an emphasis on overlay, embodiments described herein may be implemented to solve issues associated with measuring overlay between a via and/or plug layer patterned on top of a pre-patterned hardmask layer (e.g., photobucket layer) and the underlying pre-patterned hardmask layer by using a scanning electron microscope (e.g., CDSEM). In an embodiment, via or plug locations are patterned at pitches that are slightly different from the underlying pre-patterned hardmask pitch. Due to an overlay mismatch, the position of the photobucket that clears depends on the amount of overlay mismatch.

[0040] It is to be appreciated that the use of a pre-patterned hardmask to define a lithographic partem can render overlay measurements challenging since the response to exposure of such patterning is binary and feature sizes are quantized. Hence, the size of the underlying mask pitch becomes the minimum measurable unit of overlay, which is often too large for effective process control. One or more embodiments described herein enable an overlay measure that is much smaller than an underlying pre-patterned hardmask pitch size. As exemplary embodiments, Figures 3A-3E described below show how signals can be generated using photobuckets that change with overlay. In one such embodiment, pattern is a function of the pitch.

[0041] Figure 3A illustrates a top-down view of an overlay scenario where a current layer is perfectly overlaid on an underlying pre-patterned hardmask, in accordance with an embodiment of the present invention.

[0042] Referring to Figure 3A, an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures. A current layer is represented by overlay images 300A. The overlay images 300A have an overlay shift in X of zero and in Y of zero. The pitch of the overlay images 300A of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 350A highlights a location of a "photobucket cluster" at zero overlay shift (PB_0io). [0043] Figure 3B illustrates a top-down view of an overlay scenario where a current layer has a positive overlay shift of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

[0044] Referring to Figure 3B, an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures. A current layer is represented by overlay images 300B. The overlay images 300B have an overlay shift in X of Ρχ/4 and in Y of zero. The pitch of the overlay images 300B of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 350B highlights a location of X = -2P_X and Y = 0 for a photobucket cluster with respect to ΡΒ₀ ο· The region 350B and corresponding open/closed vertical column move left by an amount equal to twice the pitch. It is to be appreciated that the open/closed column will have a different contrast from the other columns due to the fact that the exposed photobucket density is different from the other columns in the region.

[0045] Figure 3C illustrates a top-down view of an overlay scenario where a current layer has a negative overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

[0046] Referring to Figure 3C, an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures. A current layer is represented by overlay images 300C. The overlay images 300C have an overlay shift in X of -Ρχ/4 and in Y of zero. The pitch of the overlay images 300C of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 350C highlights a location of X = +2P_X and Y = 0 for a photobucket cluster with respect to PB₀ o The region 350C and corresponding open/closed vertical column move right by an amount equal to twice the pitch.

[0047] Figure 3D illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present invention.

[0048] Referring to Figure 3D, an underlying layer includes a first pre-pattemed hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures. A current layer is represented by overlay images 300D. The overlay images 300D have an overlay shift in X of zero and in Y of Ργ/4. The pitch of the overlay images 300D of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 350D highlights a location of X = 0 and Y = -2P_Y for a photobucket cluster with respect to PB₀ o The region 350D and corresponding open/closed horizontal row move down by an amount equal to twice the pitch.

[0049] Figure 3E illustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-pattemed hardmask grid in the X-direction and has a positive overlay of quarter pitch with respect to the underlying pre- patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present invention.

[0050] Referring to Figure 3E, an underlying layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-patterned hardmask 102 and the second pre-patterned hardmask 104 structures. A current layer is represented by overlay images 300E. The overlay images 300E have an overlay shift in X of Ρχ/4 and in Y of Ργ/4. The pitch of the overlay images 300E of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 350E highlights a location of X = -2Ρχ and Y = -2Ργ for a photobucket cluster with respect to ΡΒ_0ιο· The region 350E and corresponding open/closed horizontal row move down by an amount equal to twice the pitch. Additionally, the region 350E and corresponding open/closed vertical column move left by an amount equal to twice the pitch.

[0051] Referring again to Figures 3A-3E, in an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure having a pitch. An overlying layer is provided on the underlying layer. The overlying layer includes a grating pattern having a pitch different from the pitch of the pre-patterned grating structure of the underlying layer. An overlay mismatch of the overlying layer relative to the pre- patterned grating structure of the underlying layer is measured for by detecting a location of a first cleared photobucket of the underlying layer. In an embodiment, a shift in dose of the overlying layer relative to the pre-patterned underlying layer is also measured for, an example of which is described below in association with Figures 4A-4C. In an embodiment, a shift in focus of the overlying layer relative to the pre-pattemed underlying layer is also measured for, an example of which is described below in association with Figure 4D.

[0052] With reference again to Figures 3A-3E, it is to be appreciated that cross-sectional analysis of a semiconductor chip may reveal an alignment mark that includes vertical and horizontal arrays of vias and/or plugs among a plurality of gridded vias and plugs as indicative of the application of one or more embodiments described herein. Such structures may be included in a scribe line or on die in a drop-in cell, for example. The application of such an approach may enable accurate measurement of overlay in photobuckets for every via and/or plug patterning layer that is intended for use with CDSEM metrology. It is also to be appreciated that conventional overlay techniques will not work with this style of patterning.

[0053] In a second aspect, with an emphasis on dose or focus or both, embodiments described herein may be implemented to solve issues associated with measuring dose and focus of a via and/or plug layer patterned on a pre-patterned hardmask structure (e.g., photobucket layer) by using a scanning electron microscope (e.g., CDSEM). In an embodiment, vias/plug areas are patterned with varying sizes. A minimum critical dimension (CD) size is required to clear the photobucket. A change in either dose or focus, or both, changes the critical CD size, resulting in a change in position of a contrast signal observable by CDSEM metrology.

[0054] It is to be appreciated that the use of a pre-patterned hardmask to define lithographic partem can render dose and/or focus measurements challenging because the response to dose/focus of such patterning is binary and feature sizes are quantized. In an embodiment, by using a sufficiently small CD step size with the procedure outlined below, dose or focus, or both, can be measured very accurately using a CDSEM technique. As exemplary embodiments, Figures 4A-4D described below illustrate how signals can be generated using photobuckets that change with dose and focus.

[0055] Figure 4A illustrates a top-down view of a dose scenario where the dose is on target, in accordance with an embodiment of the present invention.

[0056] Referring to Figure 4A, a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures. A dose is represented by images 400A. The dose 400A is on target in this scenario. Also, the via schematic

(photobuckets) is patterned with variable feature size, as shown as increasing from left to right. At any given dose 400 A, there is a minimum exposed feature size at which the photobuckets clear out. For example, region 45 OA illustrates a first cleared photobucket (from left to right) for the case where dose is on target. The effect is observable on a CDSEM.

[0057] Figure 4B illustrates a top-down view of a dose scenario where the dose is increased from the target, in accordance with an embodiment of the present invention.

[0058] Referring to Figure 4B, a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures. A dose is represented by images 400B. In this scenario, the dose 400B is increased from the target by an amount Δ, i.e., dose is target + Δ. The via schematic (photobuckets) is patterned with variable feature size, as shown as increasing from left to right. At any given dose 400B, there is a minimum critical feature size at which the photobuckets clear out. For example, region 45 OB illustrates a first cleared photobucket (from left to right) for the case where dose is target + Δ. That is, as the dose increases (as compared with Figure 4A), the minimum critical feature size decreases. Hence, the edge of the cleared photobuckets 400B shifts to the left, as is depicted in Figure 4B. The effect is observable on a CDSEM.

[0059] Figure 4C illustrates a top-down view of a dose scenario where the dose is decreased from the target, in accordance with an embodiment of the present invention.

[0060] Referring to Figure 4C, a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures. A dose is represented by images 400C. In this scenario, the dose 400C is decreased from the target by an amount Δ, i.e., dose is target - Δ. The via schematic (photobuckets) is patterned with variable feature size, as shown as increasing from left to right. At any given dose 400C, there is a minimum critical feature size at which the photobuckets clear out. For example, region 450C illustrates a first cleared photobucket (from left to right) for the case where dose is target - Δ. That is, as the dose decreases (as compared with Figure 4A), the minimum critical feature size increases. Hence, the edge of the cleared photobuckets 400C shifts to the right, as is depicted in Figure 4C. The effect is observable on a CDSEM.

[0061] Referring again to Figures 4A-4C, in an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. An overlying layer is provided on the underlying layer. The overlying layer includes pre- patterned locations of varying size. A shift in dose of the overlying layer relative to the underlying layer is measured for by detecting a minimum feature size of a cleared photobucket of the underlying layer. In an embodiment, a shift in focus of the overlying layer relative to the pre-patterned underlying layer is also measured for, an example of which is described below in association with Figure 4D.

[0062] Figure 4D illustrates a top-down view of a focus scenario where the focus is increased or decreased from the target, in accordance with an embodiment of the present invention. [0063] Referring to Figure 4D, a layer includes a first pre-patterned hardmask 102 and a second pre-patterned hardmask 104. A plurality of photoresist layer portions 110 and a plurality of openings 116 (having been exposed and developed) are among the first pre-pattemed hardmask 102 and the second pre-patterned hardmask 104 structures. A focus is represented by images 400D. In this scenario, the focus 400D is increased or decreased from the target focus by an amount Δ, i.e., focus is target - Δ or focus is target + Δ. The via schematic (photobuckets) is patterned with variable feature size, as shown as increasing from left to right. At any given focus 400D, there is a minimum critical feature size at which the photobuckets clear out. For example, region 450D illustrates a first cleared photobucket (from left to right) for the case where focus is target - Δ or target + Δ. That is, as the focus increases or decreases from, the minimum critical feature size to open a photobucket increases. Hence, the edge of the cleared photobuckets 400D shifts to the right, as is depicted in Figure 4D, as compared to a scenario where focus is on target. The effect is observable on a CDSEM. To measure focus at any given dose, as the focus moves away from the best focus in either direction, and the minimum critical feature size needed to clear the photobuckets increases to move the edge of the cleared photobuckets to the right. In an embodiment, then, the best focus for a given dose is that which provides a cleared edge for smallest photobucket size.

[0064] Referring again to Figure 4D, in an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. An overlying layer is provided on the underlying layer, the overlying layer including pre- patterned locations of varying size. A shift in focus of the overlying layer is measured for by detecting a minimum feature size to clear a photobucket of the underlying layer.

[0065] With reference again to Figures 4A-4D, it is to be appreciated that cross-sectional analysis of a semiconductor chip may reveal a presence of an alignment mark that includes vertical or horizontal arrays of vias and/or plugs next to regions without any as indicative of the application of one or more embodiments described herein. Such structures may be included in a scribe line or on die in a drop-in cell, for example. The application of such an approach may enable accurate measurement of dose and/or focus in photobuckets for every via and/or plug patterning layer that is intended for use with CDSEM metrology. It is also to be appreciated that conventional overlay techniques will not work with this style of patterning due to the quantized nature of the CD response to both dose and focus.

[0066] To provide more general context for embodiments described above, issues associated with across die/wafer etch non-uniformity can reduce yield and/or performance of fabricated semiconductor structures. One or more embodiments described herein offer a more efficient approach to patterning by maximizing the overlay process window, minimizing the size and shape of required patterns, and increasing the efficiency of the lithography process to pattern holes or plugs.

[0067] In a more specific embodiment, a pattern needed to open a pre-formed via or plug location can be made to be relatively small, enabling an increase in the overlay margin of a lithographic process. The pattern features can be made of uniform size, which can reduce scan time on direct write ebeam and/or optical proximity correction (OPC) complexity with optical lithography. The pattern features can also be made to be shallow or deep. A subsequently performed etch process may be an isotropic chemically selective etch. Such an etch process mitigates issues otherwise associated with profile and critical dimension and mitigates anisotropic issues typically associated with dry etch approaches. Such an etch process is also relatively much less expensive from an equipment and throughput perspective as compared to other selective removal approaches.

[0068] To provide further context, patterning and aligning of features at less than approximately 50 nanometer pitch requires many reticles and critical alignment strategies that are extremely expensive for a semiconductor manufacturing process. Generally, embodiments described herein involve the fabrication of metal and via patterns based on the positions of an underlying layer. That is, in contrast to conventional top-down patterning approaches, a metal interconnect process is effectively reversed and built from the previous layer up. This is in contrast to a conventional approach such as dual damascene metallization where an interlay er dielectric (ILD) is first deposited, with a pattern for metal and via layers subsequently patterned therein. In the conventional approach, alignment to a previous layer is performed using a lithography scanner alignment system. The ILD is then etched.

[0069] More specifically, one or more embodiments are directed to an approach that employs an underlying metal as a template to build the conductive vias and non-conductive spaces or interruptions between metals (referred to as "plugs"). Vias, by definition, are used to land on a previous layer metal pattern. In this vein, embodiments described herein enable a more robust interconnect fabrication scheme since alignment by lithography equipment is no longer relied on. Such an interconnect fabrication scheme can be used to save numerous

alignment/exposures, can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches. One or more embodiment described herein involves the use of a subtractive method to pre-form every via or via opening using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations is illustrated above using "photobuckets," although the selection process may also be performed using a more conventional resist expose and ILD backfill approach. [0070] It is to be appreciated that the layers and materials described above are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another

semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures described above may be fabricated on underlying lower level interconnect layers.

[0071] In an embodiment, as used throughout the present description, interlayer dielectric

(ILD) material is composed of or includes a layer of a dielectric or insulating material.

Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (S1O₂)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-on deposition, or by other deposition methods.

[0072] In an embodiment, as is also used throughout the present description, interconnect material is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. The interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect. As an example, top surfaces of the lower interconnect lines may be used for self-aligned via and plug formation.

[0073] As described above, patterned features may be patterned in a grating-like pattern with lines, holes or trenches spaced at a constant pitch and having a constant width. The partem, for example, may be fabricated by a pitch halving or pitch quartering approach. In an example, a blanket film is patterned using lithography and etch processing which may involve, e.g., spacer- based-quadruple-patterning (SBQP) or pitch quartering. It is to be appreciated that a grating pattern of lines can be fabricated by numerous methods, including 193nm immersion litho (il93), EUV and/or EBDW lithography, directed self-assembly, etc. [0074] In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride), or a metal oxide.

Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods.

[0075] A final structure layer described above may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure layer may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In some embodiments, the resulting structures enable fabrication of, e.g., vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein.

[0076] Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein. [0077] Figure 5 illustrates a computing device 500 in accordance with one

implementation of the invention. The computing device 500 houses a board 502. The board 502 may include a number of components, including but not limited to a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the board 502. In some implementations the at least one communication chip 506 is also physically and electrically coupled to the board 502. In further implementations, the communication chip 506 is part of the processor 504.

[0078] Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the board 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0079] The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0080] The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of the invention, the integrated circuit die of the processor is fabricated using a metrology operation involving measuring overlay, dose, or focus on pre-pattemed hardmask structures using scanning electron microscopy (SEM) at some stage in the manufacturing process, in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0081] The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with another implementation of the invention, the integrated circuit die of the communication chip is fabricated using a metrology operation involving measuring overlay, dose, or focus on pre-pattemed hardmask structures using scanning electron microscopy (SEM) at some stage in the manufacturing process, in accordance with implementations of the invention.

[0082] In further implementations, another component housed within the computing device 500 may contain an integrated circuit die that is fabricated using a metrology operation involving measuring overlay, dose, or focus on pre-pattemed hardmask structures using scanning electron microscopy (SEM) at some stage in the manufacturing process, in accordance with implementations of the invention.

[0083] In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

[0084] Figure 6 illustrates an interposer 600 that includes one or more embodiments of the invention. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

[0085] The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. [0086] The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

[0087] Thus, embodiments of the present invention include approaches for measuring overlay, dose, or focus on pre-pattemed hardmask structures using scanning electron microscopy (SEM).

[0088] In an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure having a pitch. The method also includes providing an overlying layer on the underlying layer, the overlying layer including a grating pattern having a pitch different from the pitch of the pre-patterned grating structure of the underlying layer. The method also includes measuring for an overlay mismatch of the overlying layer relative to the pre-pattemed grating structure of the underlying layer by detecting a location of a first cleared photobucket of the underlying layer.

[0089] In one embodiment, detecting the location of the first cleared photobucket of the underlying layer includes using a critical dimension scanning electron microscope (CD-SEM).

[0090] In one embodiment, detecting the location of the first cleared photobucket of the underlying layer includes detecting a first cleared via location.

[0091] In one embodiment, detecting the location of the first cleared photobucket of the underlying layer includes detecting a first cleared plug location.

[0092] In one embodiment, measuring for the overlay mismatch of the overlying layer relative to the pre-patterned grating structure of the underlying layer includes measuring in a scribe line region of a wafer.

[0093] In one embodiment, measuring for the overlay mismatch of the overlying layer relative to the pre-patterned grating structure of the underlying layer includes measuring in a drop-in cell region of a wafer.

[0094] In an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. The method also includes providing an overlying layer on the underlying layer, the overlying layer including pre-pattemed locations of varying size. The method also includes measuring for a shift in dose of the overlying layer relative to the underlying layer by detecting a minimum feature size of a cleared photobucket of the underlying layer.

[0095] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes using a critical dimension scanning electron microscope (CD-SEM).

[0096] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes detecting a minimum feature size of a first cleared via location.

[0097] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes detecting a minimum feature size of a first cleared plug location.

[0098] In one embodiment, measuring for the shift in dose of the overlying layer relative to the underlying layer includes measuring in a scribe line region of a wafer.

[0099] In one embodiment, measuring for the shift in dose of the overlying layer relative to the underlying layer includes measuring in a drop-in cell region of a wafer.

[00100] In an embodiment, a method of performing scanning electron microscope (SEM) metrology of a semiconductor structure includes providing a semiconductor structure having an underlying layer including a pre-patterned grating structure. The method also includes providing an overlying layer on the underlying layer, the overlying layer including pre-pattemed locations of varying size. The method also includes measuring for a shift in focus of the overlying layer relative to the underlying layer by detecting a minimum feature size of a cleared photobucket of the underlying layer.

[00101] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes using a critical dimension scanning electron microscope (CD-SEM).

[00102] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes detecting a minimum feature size of a first cleared via location.

[00103] In one embodiment, detecting the minimum feature size of the cleared photobucket of the underlying layer includes detecting a minimum feature size of a first cleared plug location.

[00104] In one embodiment, measuring for the shift in focus of the overlying layer relative to the underlying layer incudes measuring in a scribe line region of a wafer.

[00105] In one embodiment, measuring for the shift in focus of the overlying layer relative to the underlying layer includes measuring in a drop-in cell region of a wafer. [00106] In an embodiment, an alignment mark for scanning electron microscope (SEM) metrology of a semiconductor structure includes one or more vertical arrays of pre-pattemed features. The alignment mark also includes one or more horizontal arrays of pre-patterned features. The one or more vertical arrays of pre-pattemed features and the one or more horizontal arrays of pre-patterned features are adjacent a region of differing partem.

[00107] In one embodiment, the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-patterned features are included in a plurality of gridded pre-patterned features.

[00108] In one embodiment, the region of differing partem does not include a vertical array of pre-pattemed features or a horizontal array of pre-patterned features.

[00109] In one embodiment, the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-pattemed features are arrays of via locations.

[00110] In one embodiment, the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-pattemed features are arrays of plug locations.

[00111] In one embodiment, the alignment mark is located in a scribe line region of a wafer.

[00112] In one embodiment, the alignment mark is located in a drop-in cell region of a wafer.

Claims

CLAIMS What is claimed is:

1. A method of performing scanning electron microscope (SEM) metrology of a semiconductor structure, the method comprising:

providing a semiconductor structure having an underlying layer comprising a pre-pattemed grating structure having a pitch;

providing an overlying layer on the underlying layer, the overlying layer comprising a

grating pattern having a pitch different from the pitch of the pre-pattemed grating structure of the underlying layer; and

measuring for an overlay mismatch of the overlying layer relative to the pre-patterned

grating structure of the underlying layer by detecting a location of a first cleared photobucket of the underlying layer.

2. The method of claim 1, wherein detecting the location of the first cleared photobucket of the underlying layer comprises using a critical dimension scanning electron microscope (CD-SEM).

3. The method of claim 1, wherein detecting the location of the first cleared photobucket of the underlying layer comprises detecting a first cleared via location.

4. The method of claim 1, wherein detecting the location of the first cleared photobucket of the underlying layer comprises detecting a first cleared plug location.

5. The method of claim 1, wherein measuring for the overlay mismatch of the overlying layer relative to the pre-pattemed grating structure of the underlying layer comprises measuring in a scribe line region of a wafer.

6. The method of claim 1, wherein measuring for the overlay mismatch of the overlying layer relative to the pre-pattemed grating structure of the underlying layer comprises measuring in a drop-in cell region of a wafer.

7. A method of performing scanning electron microscope (SEM) metrology of a semiconductor structure, the method comprising:

providing a semiconductor structure having an underlying layer comprising a pre-pattemed grating structure; providing an overlying layer on the underlying layer, the overlying layer comprising pre- pattemed locations of varying size; and

measuring for a shift in dose of the overlying layer relative to the underlying layer by

detecting a minimum feature size of a cleared photobucket of the underlying layer.

8. The method of claim 7, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises using a critical dimension scanning electron microscope (CD-SEM).

9. The method of claim 7, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises detecting a minimum feature size of a first cleared via location.

10. The method of claim 7, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises detecting a minimum feature size of a first cleared plug location.

11. The method of claim 7, wherein measuring for the shift in dose of the overlying layer relative to the underlying layer comprises measuring in a scribe line region of a wafer.

12. The method of claim 7, wherein measuring for the shift in dose of the overlying layer relative to the underlying layer comprises measuring in a drop-in cell region of a wafer.

13. A method of performing scanning electron microscope (SEM) metrology of a semiconductor structure, the method comprising:

providing a semiconductor structure having an underlying layer comprising a pre-pattemed grating structure;

providing an overlying layer on the underlying layer, the overlying layer comprising pre- pattemed locations of varying size; and

measuring for a shift in focus of the overlying layer relative to the underlying layer by

14. The method of claim 13, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises using a critical dimension scanning electron microscope (CD-SEM).

15. The method of claim 13, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises detecting a minimum feature size of a first cleared via location.

16. The method of claim 13, wherein detecting the minimum feature size of the cleared photobucket of the underlying layer comprises detecting a minimum feature size of a first cleared plug location.

17. The method of claim 13, wherein measuring for the shift in focus of the overlying layer relative to the underlying layer comprises measuring in a scribe line region of a wafer.

18. The method of claim 13, wherein measuring for the shift in focus of the overlying layer relative to the underlying layer comprises measuring in a drop-in cell region of a wafer.

19. An alignment mark for scanning electron microscope (SEM) metrology of a semiconductor structure, the alignment mark comprising:

one or more vertical arrays of pre-patterned features; and

one or more horizontal arrays of pre-pattemed features, the one or more vertical arrays of pre-pattemed features and the one or more horizontal arrays of pre-pattemed features adjacent a region of differing pattern.

20. The alignment mark of claim 19, wherein the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-patterned features are included in a plurality of gridded pre-pattemed features.

21. The alignment mark of claim 19, wherein the region of differing pattern does not include a vertical array of pre-patterned features or a horizontal array of pre-pattemed features.

22. The alignment mark of claim 19, wherein the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-patterned features are arrays of via locations.

23. The alignment mark of claim 19, wherein the one or more vertical arrays of pre-patterned features and the one or more horizontal arrays of pre-patterned features are arrays of plug locations.

24. The alignment mark of claim 19, wherein the alignment mark is located in a scribe line region of a wafer.

25. The alignment mark of claim 19, wherein the alignment mark is located in a drop-in cell region of a wafer.