WO2017111844A1 - Dispositifs mémoires comprenant une diode tunnel intégrée en contact et leurs techniques de fabrication - Google Patents

Dispositifs mémoires comprenant une diode tunnel intégrée en contact et leurs techniques de fabrication Download PDF

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Publication number
WO2017111844A1
WO2017111844A1 PCT/US2015/000403 US2015000403W WO2017111844A1 WO 2017111844 A1 WO2017111844 A1 WO 2017111844A1 US 2015000403 W US2015000403 W US 2015000403W WO 2017111844 A1 WO2017111844 A1 WO 2017111844A1
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Prior art keywords
diode
source
rram
doped
rram device
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PCT/US2015/000403
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English (en)
Inventor
Ravi Pillarisetty
Prashant Majhi
Niloy Mukherjee
Elijah V. KARPOV
Uday Shah
Original Assignee
Intel Corporation
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/000403 priority Critical patent/WO2017111844A1/fr
Priority to TW105138460A priority patent/TW201735326A/zh
Publication of WO2017111844A1 publication Critical patent/WO2017111844A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • a typical resistive random-access memory (RRAM) cell includes a switching material disposed between two electrodes. Ions in the switching material migrate in response to an appropriate bias provided across the electrodes. This ion movement produces a measurable change in device resistance, effectively causing the switching material to transition from an insulator to a conductor. As such, the switching material can be electrically switched between high and low resistivity states, allowing for programming of the RRAM cell, wherein the low resistivity state represents a binary ' ⁇ ', and the high resistivity state represents a binary ' , for example.
  • Figure 1 is a flow diagram illustrating a process of fabricating a memory device, in accordance with an embodiment of the present disclosure.
  • Figure 2A is a side cross-sectional view of a memory device formed via the process of Figure 1 , in accordance with an embodiment of the present disclosure.
  • Figure 2B is a side cross-sectional view of a memory device formed via the process of Figure 1 , in accordance with another embodiment of the present disclosure.
  • Figure 3 is a graph of a current-voltage (I-V) curve qualitatively showing performance of an example tunnel diode configured in accordance with an example embodiment of the present disclosure.
  • Figure 4 is a partial schematic view of a memory device formed via the process of Figure 1, in accordance with an embodiment of the present disclosure.
  • Figure 5 illustrates an example embedded bi-directional memory circuit configured in accordance with an embodiment of the present disclosure.
  • Figure 6 illustrates a computing system implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • the tunnel diode can be connected in series with the RRAM cell, so as to provide current control.
  • the p-n junction of the diode can be formed, for example, using the source/drain material and an additional diode material layer provided there over.
  • the diode material may be, for example, an epitaxial p-type or n-type material that is doped opposite the underlying source/drain material.
  • a source contact may be formed over the diode portion and configured for electronic contact with the source portion through the diode portion.
  • the oppositely doped source region and diode portion may constitute at least a portion of a P+/N+ tunnel diode, which, in accordance with some embodiments, provides a negative differential resistance (NDR) that serves to clamp current and protect against overshoot during FORMING and SET operations of the RRAM device, preventing (or otherwise reducing) RRAM filament damage.
  • NDR negative differential resistance
  • the tunnel diode may be configured to provide high conductance in an opposite polarity during a RESET operation of the RRAM device. Numerous configurations and variations will be apparent in light of this disclosure.
  • RRAM R resistive random-access memory
  • the tunnel diode can be connected in series with the RRAM cell, so as to provide current control.
  • the p-n junction of the diode can be formed, for example, using the source/drain material and an additional diode material layer provided there over.
  • the diode material may be, for example, an epitaxial p-type or n-type material that is doped opposite the underlying source/drain material.
  • a source contact may be formed over the diode portion and configured for electronic contact with the source portion through the diode portion.
  • the oppositely doped source region and diode portion may constitute at least a portion of a P+ N+ tunnel diode, which, in accordance with some embodiments, provides a negative differential resistance (NDR) that serves to clamp current and protect against overshoot during FORMING and SET operations of the RRAM device, preventing (or otherwise reducing) RRAM filament damage.
  • NDR negative differential resistance
  • the tunnel diode may be configured to provide high conductance in an opposite polarity during a RESET operation of the RRAM device.
  • inclusion of a tunnel diode configured as described herein may improve current control and variation for a host 1 T-1 R RRAM bit cell as compared to existing architectures. This may be, at least in part, because the NDR effectively shuts off the write current to the RRAM device, providing a current clamp without requiring extrinsic circuit elements to do so. In some instances, use of the techniques disclosed herein may reduce array level variability.
  • a tunnel diode provided as described herein can be utilized in any of a wide range of non-volatile RRAM architectures, including oxide-based RRAM devices, metal-based RRAM (metal-RRAM) devices, and spin-transfer torque magnetic random-access memory (STTMRAM) devices, to name a few. Numerous other suitable uses and variations will be apparent in light of this disclosure.
  • use of the disclosed techniques may be detected, for example, by any one, or combination, of scanning electron microscopy (SEM), transmission electron microscopy (TEM), or other suitable inspection of a given memory device or other integrated circuit structure having a tunnel diode configured as variously described herein.
  • SEM scanning electron microscopy
  • TEM transmission electron microscopy
  • Figure 1 is a flow diagram illustrating a process 100 of fabricating a memory device, in accordance with an embodiment of the present disclosure.
  • the methodology can be used in conjunction with both planar and non-planar (e.g., fin-based field-effect transistor, or FinFET, and nanowire) transistor architectures.
  • Figure 2A is a side cross-sectional view of a memory device 200 formed via the process 100 of Figure 1 , in accordance with an embodiment of the present disclosure.
  • Figure 2B is a side cross-sectional view of a memory device 200 formed via the process 100 of Figure 1 , in accordance with another embodiment of the present disclosure. Note that the cross-sections are relevant to both planar and non-planar transistor configurations.
  • the cross-sections are taken through the drain-channel-source, as generally can be seen.
  • the depicted cross-sections are, again, taken through the drain-channel- source.
  • the depicted cross-sections are taken parallel to, and through, the fin.
  • the fins may be original (e.g., native) to the substrate in some such embodiments, but in other embodiments may be replacement fins or otherwise formed of a semiconductor material different from that of the underlying substrate.
  • the channel may be configured with one or more nanowires, in still other embodiments.
  • Figure 2B provides a rendition of a memory device 200 that is representative of some more real- world structural features and configurations, and the description provided herein with respect to Figure 2A is equally applicable to Figure 2B.
  • the process 100 may begin as in block 102 with forming a gate dielectric layer 204 over channel 202a of semiconductor substrate 202, and forming a gate 206 over gate dielectric layer 204.
  • Semiconductor substrate 202 may have any of a wide range of configurations.
  • semiconductor substrate 202 may be a bulk semiconductor substrate, a semiconductor-on-insulator (XOI, where X represents a semiconductor material), a semiconductor wafer of any standard, custom, or other desired size (e.g., a standard 300 mm wafer), or a multi-layered structure.
  • the material composition of semiconductor substrate 202 may be customized, as desired for a given target application or end-use.
  • semiconductor substrate 202 may be formed from any one, or combination, of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), among others.
  • semiconductor substrate 202 may be formed, at least in part, from Si having a crystal lographic orientation of ⁇ 1 1 1>, generally referred to as Si(l l l).
  • Other suitable materials and configurations for semiconductor substrate 202 will depend on a given application and will be apparent in light of this disclosure.
  • gate dielectric layer 204 may be customized, as desired for a given target application or end-use.
  • gate dielectric layer 204 may be formed from any one, or combination, of high- ⁇ dielectric materials, such as, for example, aluminum oxide (A1 2 0 3 ), hafnium oxide (Hf0 2 ), silicon dioxide (Si0 2 ), silicon nitride (Si 3 N 4 ), and zirconium dioxide (Zr0 2 ), among others.
  • Gate dielectric layer 204 can be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • gate dielectric layer 204 may be formed via any one, or combination, of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process. Also, the geometry and dimensions of gate dielectric layer 204 may be customized, as desired for a given target application or end-use. In some cases, gate dielectric layer 204 may have a thickness (a y- thickness in the y-direction), for example, in the range of about 1-10 nm (e.g., about 1-5 nm, about 5-10 nm, or any other sub-range in the range of about 1-10 nm). Other suitable materials, formation techniques, and configurations for gate dielectric layer 204 will depend on a given application and will be apparent in light of this disclosure.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • gate 206 may be customized, as desired for a given target application or end-use.
  • gate 206 may be formed from any one, or combination, of electrically conductive materials, such as, for example, copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and doped or undoped polysilicon (poly-Si), among others.
  • Gate 206 can be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • gate 206 may be formed via any one, or combination, of a physical vapor deposition (PVD) process, a CVD process, an electroplating process, and an electroless deposition process. Also, the geometry and dimensions of gate 206 may be customized, as desired for a given target application or end-use. Other suitable materials, formation techniques, and configurations for gate 206 will depend on a given application and will be apparent in light of this disclosure.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • electroplating electroplating
  • electroless deposition process electroless deposition
  • the process 100 may continue as in block 104 with forming source portion 208 and drain portion 210 adjacent channel 202a of semiconductor substrate 202.
  • either (or both) of source portion 208 and drain portion 210 may be formed over semiconductor substrate 202, such that a given portion 208/210 is in contact with or otherwise disposed over an upper surface of semiconductor substrate 202.
  • either (or both) of source portion 208 and drain portion 210 may be formed at least partially within semiconductor substrate 202, such that a given portion 208/210 at least partially extends below an upper surface of semiconductor substrate 202.
  • either (or both) of source portion 208 and drain portion 210 may be formed both over and at least partially within semiconductor substrate 202, such that a given portion 208/210 is at least partially in contact with or otherwise disposed over an upper surface of semiconductor substrate 202 and at least partially extends below the upper surface of semiconductor substrate 202. Numerous configurations and variations will be apparent in light of this disclosure.
  • each of source portion 208 and drain portion 210 may be customized, as desired for a given target application or end-use.
  • at least one of source portion 208 and drain portion 210 may be formed, for example, from any one, or combination, of Si, SiGe, and Ge, any of which may be highly doped with an n-type or p-type dopant, as desired.
  • Arsenic (As) and phosphorous (P) are some examples of suitable n-type dopants.
  • Boron (B) is an example of a suitable p-type dopant.
  • both source portion 208 and drain portion 210 may be highly doped with an n-type dopant, resulting in N+ source and drain portions 208 and 210.
  • both source portion 208 and drain portion 210 may be highly doped with a p-type dopant, resulting in P+ source and drain portions 208 and 210.
  • the dopant type and concentration, as well as the doping profile e.g., dopant gradient or other variation, if any
  • the doping profile e.g., dopant gradient or other variation, if any
  • Source portion 208 and drain portion 210 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In some cases, either (or both) of source portion 208 and drain portion 210 may be formed via any one, or combination, of an implant process and an epitaxial deposition process. Also, the geometry and dimensions of source portion 208 and drain portion 210 may be customized, as desired for a given target application or end-use. In some cases, either (or both) of source portion 208 and drain portion 210 may extend above the plane of the upper surface of channel 202a of semiconductor substrate 202.
  • source portion 208 and drain portion 210 may be substantially co-planar with the upper surface of channel 202a of semiconductor substrate 202 (e.g., such as is generally shown in Figures 2A-2B). Furthermore, as will be appreciated in light of this disclosure, and in accordance with some other embodiments, source portion 208 and drain portion 210 may be transposed, such that drain r
  • source portion 210 resides instead where source portion 208 is currently depicted in Figures 2A-2B, and source portion 208 resides instead where drain portion 210 is currently depicted in Figures 2A- 2B.
  • Other suitable materials, formation techniques, and configurations for source portion 208 and drain portion 210 will depend on a given application and will be apparent in light of this disclosure.
  • one or more spacers may be provided adjacent sidewalls of the stack of gate dielectric layer 204 and gate 206.
  • the material composition, geometry, and dimensions of the optional spacer(s) may be customized, and any suitable standard, custom, or proprietary technique(s) can be used in formation thereof.
  • either (or both) of source portion 208 and drain portion 210 may have a tip portion 208a/210a that extends under any one, or combination, of a given optional spacer, gate dielectric layer 204, and gate 206. Numerous such configurations and variations will be apparent in light of this disclosure.
  • the process 100 may continue as in block 106 with forming, at least in part, a dielectric layer 212 over the resultant topography of memory device 200 (e.g., provided by semiconductor substrate 202, gate dielectric layer 204, gate 206, source portion 208, and drain portion 210) and patterning one or more features (e.g., trenches; through-holes; single-damascene openings; double-damascene openings) therein.
  • the material composition of dielectric layer 212 may be customized, as desired for a given target application or end-use.
  • dielectric layer 212 may be formed from any one, or combination, of dielectric materials, such as, for example, silicon dioxide (Si0 2 ), aluminum oxide (A1 2 0 3 ), hafnium oxide (HfO 2 ), zirconium dioxide (Zr0 2 ), tantalum pentoxide (Ta 2 O s ), titanium dioxide (Ti0 2 ), and lanthanum oxide (La 2 0 3 ), among others.
  • dielectric layer 212 may be formed, for example, from a carbon (C)-doped oxide.
  • dielectric layer 212 may be formed from a nitride, such as silicon nitride (Si 3 N 4 ), or a carbide, such as silicon carbide (SiC). In a more general sense, and in accordance with some embodiments, dielectric layer 212 may be formed from any one, or combination, of the aforementioned materials. Dielectric layer 212 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In some cases, dielectric layer 212 may be formed, for example, via any one, or combination, of a CVD process and a PVD process.
  • dielectric layer 212 may be customized, as desired for a given target application or end-use, and in some cases dielectric layer 212 may be formed at this point in the process 100 up to a first thickness D/ over memory device 200, as generally shown by the first dashed line in Figures 2A-2B.
  • dielectric layer 212 may be configured to serve, in a general sense, as an inter-layer dielectric (ILD).
  • ILD inter-layer dielectric
  • Other suitable materials, formation techniques, and configurations for dielectric layer 212 will depend on a given application and will be apparent in light of this disclosure.
  • Patterning of feature(s) within dielectric layer 212 may be provided via any suitable standard, custom, or proprietary lithography and etching technique(s), as will be apparent in light of this disclosure.
  • either (or both) of an anisotropic and an isotropic etch process may be employed in patterning the feature(s), and the etch chemistry (dry; wet) may be customized based, at least in part, on the material composition of dielectric layer 212 and the underlying source portion 208 and drain portion 210.
  • a feature over source portion 208 may be formed via a highly direction anisotropic wet etch process and an anisotropic wet etch process that causes the feature to flare or otherwise extend outwardly (e.g., in the x-direction), allowing diode portion 214 (discussed below) to have a greater width in that bottom region of the host feature than otherwise would be permitted by the dimensional confines of a host feature formed only by a highly direction etch process.
  • Figure 2B shows an example case of this type of configuration for diode portion 214 and its host feature in dielectric layer 212.
  • a given feature may be customized, and in some cases, a given feature may have a profile of tapered sidewall, such as is generally shown in Figures 2A-2B. In other cases, however, a given feature may have a profile of substantially straight sidewall (e.g., within about 2° of vertical).
  • a given feature formed in dielectric layer 212 can be of any uniform or nonuniform profile desired. Patterning of a given feature may terminate, in some instances, upon reaching source portion 208 or drain portion 210 (or both). Numerous configurations and variations will be apparent in light of this disclosure.
  • the process 100 may continue as in block 108 with masking off feature(s) within dielectric layer 212 (e.g., over drain portion 210) where formation of a diode portion 214 is not desired and forming the diode portion 214 in feature(s) within dielectric layer 212 (e.g., over source portion 208) where formation is desired.
  • Masking may be performed via any suitable standard, custom, or proprietary masking technique(s), as will be apparent in light of this disclosure, and the material composition of the mask(s) may be customized, as desired for a given target application or end-use.
  • diode portion 214 may be customized, as desired for a given target application or end-use.
  • the dopant concentration, as well as the doping profile (e.g., dopant gradient or other variation, if any), for diode portion 214 may be customized.
  • diode portion 214 may have a dopant concentration, for example, in the range of about 1E19-1 E21 cm “3 (e.g., about 1E19-1E20 cm “3 , about 1 E20-1E21 cm “3 , or any other sub-range in the range of about 1 E19-1E21 cm “3 ).
  • diode portion 214 may be any one, or combination, of highly p-doped Si, SiGe, and Ge, resulting in a P+ diode portion 214. If instead source portion 208 is p-doped, for example, then diode portion 214 may be any one, or combination, of highly n-doped Si, SiGe, and Ge, resulting in an N+ diode portion 214.
  • the N+ source portion 208 and P+ diode portion 214, together, or the P+ source portion 208 and N+ diode portion 214, together, may provide a tunnel diode, as generally shown in the dotted ellipse at the interface of source portion 208 and diode portion 214 in each of Figures 2A-2B, in accordance with some embodiments.
  • Diode portion 214 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In some cases, diode portion 214 may be formed via any one, or combination, of a molecular beam epitaxy (MBE) process and a metalorganic vapor phase epitaxy (MOVPE) process. Also, the dimensions of diode portion 214 may be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on dimensions of the feature of dielectric layer 212 in which it resides.
  • MBE molecular beam epitaxy
  • MOVPE metalorganic vapor phase epitaxy
  • the width (x-width in the x-direction) of diode portion 214 may be about equal (e.g., within about 5%) to the width of the bottom of the feature over source portion 208 in which it resides.
  • diode portion 214 may have a width (x-width), for example, in the range of about 5-1 ,000 nm (e.g., about 5-500 nm, about 500- 1 ,000 nm, or any other sub-range in the range of about 5-1 ,000 nm).
  • diode portion 214 may have a width (x-width) in the range of about 20-30 nm.
  • diode portion 214 may have a thickness (y-thickness in the y-direction) in the range of about 5-500 nm (e.g., about 5-250 nm, about 250-500 nm, or any other sub-range in the range of about 5- 500 nm). In some instances, diode portion 214 may have a thickness (y-thickness), for example, in the range of about 20-50 nm. In some instances, diode portion 214 may have a substantially uniform y-thickness over the topography provided, for example, by underlying source portion 208. In other instances, diode portion 214 may be provided with a non-uniform or otherwise varying y-thickness over such topography.
  • a first portion of diode portion 214 may have a y-thickness within a first range, whereas a second portion thereof may have a y-thickness within a second, different range.
  • diode portion 214 may have first and second portions, for example, having average y-thicknesses that are different from one another by about 20% or less, about 15% or less, about 10% or less, or about 5% or less.
  • diode portion 214 may be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the geometry of the feature of dielectric layer 212 in which it resides.
  • diode portion 214 may have angled or tapered sidewalls, resulting in a generally trapezoidal cross-sectional geometry, such as generally can be seen in Figure 2 A.
  • diode portion 214 may be wider at one point (e.g., at its bottom) than at another point (e.g., at its top), in some embodiments.
  • diode portion 214 may have substantially straight, vertical sidewalls, resulting in a generally rectangular or square cross-sectional geometry.
  • diode portion 214 may be about as wide at one point (e.g., at its bottom) as at another point (e.g., at its top). In some still other cases, diode portion 214 may have one or more curvilinear surfaces (top, sidewalls, or other). Other suitable materials, formation techniques, and configurations for diode portion 214 will depend on a given application and will be apparent in light of this disclosure.
  • the process 100 may continue as in block 1 10 with removing the mask from feature(s) within dielectric layer 212 (e.g., over drain portion 210) and forming: (1 ) a source contact 216 over diode portion 214 in a feature within dielectric layer 212 over source portion 208; and (2) a drain contact 21 8 in a feature within dielectric layer 212 over drain portion 210.
  • the material composition of source contact 216 and drain contact 218 may be customized, as desired for a given target application or end-use.
  • source contact 216 may be formed from any suitable electrically conductive material(s), as will be apparent in light of this disclosure.
  • either or both of source contact 216 and drain contact 218 may be formed from any one, or combination, of electrically conductive materials, such as, for example, nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), and tungsten (W), among others.
  • Source contact 216 and drain contact 218 can be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • the geometry and dimensions of each of source contact 216 and drain contact 218 can be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the geometry of the features of dielectric layer 212 in which they reside.
  • source contact 216 may be configured, for example, for electronic contact with underlying source portion 208 through diode portion 214.
  • Other suitable materials, formation techniques, and configurations for source contact 216 and drain contact 218 will depend on a given application and will be apparent in light of this disclosure.
  • RRAM device 220 may include a first electrode layer 222, a dielectric layer 224 adjacent (e.g., directly on or otherwise over) first electrode layer 222, an exchange layer 226 adjacent (e.g., directly on or otherwise over) dielectric layer 224, and a second electrode layer 228 adjacent (e.g., directly on or otherwise over) exchange layer 226.
  • RRAM device 220 may be configured as any one, or combination, of an oxide-based RRAM device, a metal-based RRAM (metal-RRAM) device, and a spin-transfer torque magnetic random-access memory (STTMRAM) device, to name a few. Numerous suitable configurations and variations will be apparent in light of this disclosure.
  • first and second electrode layers 222 and 228 may be customized, as desired for a given target application or end-use.
  • first and second electrode layers 222 and 228 may be formed from any one, or combination, of electrically conductive materials, such as, for example, tungsten (W), iridium (Ir), ruthenium (Ru), titanium nitride (TiN), and tantalum nitride (TaN), among others.
  • First and second electrode layers 222 and 228 can be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. Also, the geometry and dimensions of first and second electrode layers 222 and 228 can be customized, as desired for a given target application or end-use.
  • first and second electrode layers 222 and 228 may have a thickness (y-thickness in the y-direction), for example, in the range of about 5- 500 nm (e.g., about 5-250 nm, about 250-500 nm, or any other sub-range in the range of about 5-500 nm). In some instances, either or both of first and second electrode layers 222 and 228 may have a thickness (y-thickness), for example, in the range of about 10-15 nm. Other suitable materials, formation techniques, and configurations for first and second electrode layers 222 and 228 will depend on a given application and will be apparent in light of this disclosure.
  • dielectric layer 224 may be customized, as desired for a given target application or end-use.
  • dielectric layer 224 may be formed from any one, or combination, of sub-stoichiometric oxides, such as, for example, hafnium oxide (HfO x ), titanium oxide (TiO x ), tantalum oxide (TaO x ), aluminum oxide (A10 x ), and tungsten oxide (WO x ), among others.
  • dielectric layer 224 may include a sub-stoichiometric oxide with subscript x in the range of about 1.7-1.9 (e.g., about 1.7-1.8, about 1.8-1.9, or any other sub-range in the range of about 1.7-1.9).
  • Dielectric layer 224 can be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • dielectric layer 224 may be formed via any one, or combination, of an ALD process and a PVD process (e.g., such as sputter deposition).
  • ALD process e.g., atomic layer deposition
  • PVD process e.g., such as sputter deposition
  • use of either or both of these processes may allow for a given degree of control over the ratio of constituent elements (e.g., controlling subscript x as a variable) in providing a sub-stoichiometric oxide.
  • the geometry and dimensions of dielectric layer 224 can be customized, as desired for a given target application or end-use.
  • dielectric layer 224 may have a thickness (y-thickness in the y-direction), for example, in the range of about 1-20 nm (e.g., about 1-10 nm, about 10-20 nm, or any other sub-range in the range of . about 1-20 nm). In some instances, dielectric layer 224 may have a thickness (y-thickness), for example, in the range of about 2-8 nm. Other suitable materials, formation techniques, and configurations for dielectric layer 224 will depend on a given application and will be apparent in light of this disclosure.
  • exchange layer 226 may be customized, as desired for a given target application or end-use.
  • exchange layer 226 may be formed from any one, or combination, of highly reactive metals, such as, for example, titanium (Ti), hafnium (Hf), and tantalum (Ta).
  • Te titanium
  • Hf hafnium
  • Ta tantalum
  • exchange layer 226 may be formed from any suitable material(s) that provide for sufficient oxygen exchange in RRAM device 220, as desired for a given target application or end-use.
  • Exchange layer 226 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • the geometry and dimensions of exchange layer 226 may be customized, as desired for a given target application or end-use.
  • exchange layer 226 may have a thickness (y- thickness in the y-direction), for example, in the range of about 0.1-50 nm (e.g., about 0.1- 25 nm, about 25-50 nm, or any other sub-range in the range of about 0.1-50 nm). In some instances, exchange layer 226 may have a thickness (y-thickness), for example, in the range of about 5-15 nm. Other suitable configurations for exchange layer 226 will depend on a given application and will be apparent in light of this disclosure.
  • RRAM device 220 may be formed over (e.g., landed on) source contact 216, which may be a back-end-of-line (BEOL) metal layer 0 (generally referred to as a MetalO layer), in accordance with some embodiments.
  • BEOL back-end-of-line
  • RRAM device 220 may be formed over (e.g., landed on) any desired metal layer (e.g., Metal 1 , Metal2, Metal3, and beyond) of memory device 200. Numerous suitable configurations and variations will be apparent in light of this disclosure.
  • the process 100 may continue as in block 1 14 with further forming dielectric layer 212 over the resultant topography of memory device 200 (e.g., provided by RRAM device 220, earlier formed dielectric layer 212, and drain contact 218) and patterning one or more features (e.g., trenches; through-holes; single-damascene openings; double-damascene openings) therein.
  • the dimensions of dielectric layer 212 may be customized, as desired for a given target application or end-use, and in some cases dielectric layer 212 may be formed at this point in the process 100 up to a second thickness D2 over memory device 200, as generally shown by the second dashed line in Figures 2A-2B.
  • patterning of feature(s) within dielectric layer 212 may be provided via any of the example techniques discussed above, for instance, with respect to block 106 of process 100.
  • an anisotropic wet etch process may be employed in patterning the feature(s), and the etch chemistry may be customized based, at least in part, on the material composition of dielectric layer 212 and the underlying RRAM device 220 and drain contact 218. Patterning of a given feature may terminate, for example, upon reaching RRAM device 220 or drain portion 210 (or both).
  • the dimensions and geometry of a given feature may be customized, and in some cases, a given feature may have a profile of tapered sidewall, such as is generally shown in Figure 2A.
  • a given feature may have a profile of substantially straight sidewall (e.g., within about 2° of vertical). Numerous configurations and variations will be apparent in light of this disclosure. In a more general sense, and in accordance with some embodiments, a given feature formed in dielectric layer 212 can be of any uniform or non-uniform profile desired.
  • the process 100 may continue as in block 1 16 with forming: (1 ) an interconnect 230 in a feature within dielectric layer 212 over RRAM device 220; and (2) an interconnect 232 in a feature within dielectric layer 212 over drain contact 218.
  • the material composition of interconnects 230 and 232 may be customized, as desired for a given target application or end- use. In some cases, either or both of interconnects 230 and 232 may be formed from any one, or combination, of electrically conductive metals, such as, for example, copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta), among others.
  • Interconnects 230 and 232 can be formed via any one, or combination, of suitable standard, custom, or proprietary back-end-of-line (BEOL) metallization technique(s), as will be apparent in light of this disclosure.
  • BEOL back-end-of-line
  • either (or both) of interconnects 230 and 232 may be formed via any one, or combination, of an electroplating process, an electroless deposition process, and an ALD process.
  • the geometry and dimensions of interconnects 230 and 232 can be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the geometry of the features of dielectric layer 212 in which they reside.
  • a given interconnect 230 or 232 may be formed so as to fully land over an underlying structure (e.g., as can be seen generally of the interconnect 232 of Figure 2 A). In some other cases, however, a given interconnect 230 or 232 may be formed so as to only partially land over an underlying structure (e.g., as can be seen generally of the interconnect 232 of Figure 2B). Other suitable materials, formation techniques, and configurations for interconnects 230 and 232 will depend on a given application and will be apparent in light of this disclosure.
  • Figure 3 is a graph of a current- voltage (I-V) curve qualitatively showing performance of an example tunnel diode configured in accordance with an example embodiment of the present disclosure.
  • I-V current- voltage
  • This NDR region may be caused, for example, by quantum mechanical tunneling (e.g., a tunnel junction).
  • the NDR provided by the tunnel diode of memory device 200 may serve to clamp current, for example, during either (or both) FORMING and SET operations associated with RRAM device 220.
  • the tunnel diode may be configured, in accordance with some embodiments, to provide high conductance in an opposite polarity during a RESET operation of RRAM device 220.
  • RRAM device 220 is configured as an oxygen ion conduction RRAM
  • oxygen may be formed (e.g., from dielectric layer 224 and/or exchange layer 226) at the anode (e.g., one of the first and second electrode layers 222 and 228); and (2) an electrically conductive filament with oxygen vacancies may extend from the cathode (e.g., the other of the first and second electrode layers 222 and 228).
  • the filament of oxygen vacancies may provide electrical conduction, for instance, by electron hopping from one oxygen vacancy to another.
  • the filament may be broken (e.g., may retract from extending completely to the anode), changing the Schottky barrier height at the electrode/exchange layer interface, resulting in a change in resistance.
  • the filament may be reformed.
  • the distance to be bridged by the filament e.g., the distance from the tip of the filament to the anode
  • the distance to be bridged by the filament may be shorter than the full distance initially bridged during the FORMING operation, because a portion of the filament remains present upon RESET. This may lead to lower voltages in the SET-RESET cycle, in which filamentary switching with oxygen vacancies may be provided.
  • Figure 4 is a partial schematic view of a memory device 200 formed via the process 100 of Figure 1 , in accordance with an embodiment of the present disclosure.
  • Figure 5 illustrates an example embedded bi-directional memory circuit configured in accordance with an embodiment of the present disclosure.
  • the memory circuit of this example embodiment includes column select circuitry, row select circuitry, read/write (R/W) control circuitry, voltage supply circuitry (Voltage Supply 1 and 2), and an MxN array of memory cells 220 (M and N can be any integer values, as will be appreciated).
  • Each memory cell 220 includes a dielectric layer 224 and exchange layer 226 connected in series and sandwiched between first and second electrodes 222 and 228.
  • a diode portion 214 and source contact 216 may be disposed between the first electrode 222 of each memory cell 220 and an associated word line.
  • the actual array size will depend on the given application. Specific examples include a 32-row by 32-column organization, a 64-row by 64-column organization, a 128-row by 128-column organization, or a 32-row by 128-column organization. Further, note that the number of rows M need not match the number of columns N. As can be seen further, each column is associated with its own bit line (bl 0 , bli, . . . , bl n ), and each bit line is driven by a corresponding column select circuit included in the column select circuitry.
  • each row is associated with its own word line (wlo, wli, . . . , wl m ), and each word line is driven by a corresponding row select circuit included in the row select circuitry.
  • word line wlo, wli, . . . , wl m
  • the R/W control circuitry receives memory access requests (e.g., from a local processor or communication chip in which the memory is embedded), generates the requisite control signals based on that request (e.g., read, write 0, or write 1), and applies those control signals to the row and column selector circuitry.
  • the voltage supplies 1 and 2 are switched or otherwise commanded (e.g., by the RAV control, the respective selector circuitries, or both) to provide the voltage necessary to bias the array so as to facilitate the requested action.
  • the row and column selector circuitry then applies the appropriate voltages from voltage supplies 1 and 2 across the array so that only the selected memory cell(s) 202 are accessed.
  • each of the voltage supply 1 , voltage supply 2, row selector circuitry, column select circuitry, and R/W control can be implemented with standard, custom, or proprietary technology as desired, and the present disclosure is not intended to be limited to any particular configurations thereof. Rather, any suitable configurations can be used in an embodiment of the present disclosure, where the memory cells 220 are configured with a dielectric layer 224 and exchange layer 226 provided as described herein.
  • the example memory of Figure 5 is bi-directional in nature, in that the current flow through a given memory cell 220 will depend on the voltage values applied by supplies 1 and 2. In general, the current will flow from the greater supply to the lesser supply. For example, and in accordance with one example embodiment, if voltage supply 1 is 0.9 volts and voltage supply 2 is 0.0 volts, then current will flow from supply 1 through the corresponding row selector circuitry and corresponding memory cell 220 and through the corresponding column selector circuitry to voltage supply 2, assuming that the memory cell 220 is turned on (e.g., threshold VTH exceeded) so as to allow current to flow therethrough. The opposite current direction would apply if voltage supply 2 was 0.9 volts and voltage supply 1 was 0.0 volts.
  • the voltage supplies 1 and 2 can be configured to provide positive and negative voltage or current (or both) to the selected memory cells 220 within the array and may include components that are directed toward specific memory operations.
  • a voltage supply may include specific current sources, set at different levels, for reading from and writing to a given memory cell 220.
  • the row and column selector circuits operate to select among the different polarities of voltage supply provided by the respective voltage supplies 1 and 2, which in this example embodiment are controlled by the RAV control circuitry.
  • the memory may be unidirectional, in that bi- directionality is not required.
  • FIG. 6 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • the computing system 1000 houses a motherboard 1002.
  • the motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein.
  • the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.
  • computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1000 may include a plurality of communication chips 1006.
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein.
  • multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips).
  • processor 1004 may be a chip set having such wireless capability.
  • any number of processor 1004 and/or communication chips 1006 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • Example 1 is a non-volatile memory device including: a semiconductor substrate having a channel region; a gate stack disposed over the channel region; a source portion disposed adjacent one side of the gate stack; a diode portion disposed over the source portion, wherein the source portion and the diode portion together constitute at least a portion of a tunnel diode; a source contact disposed over and configured for electronic contact with the source portion through the diode portion; and a resistive random-access memory (RRAM) device disposed over and configured for electronic contact with the source contact.
  • RRAM resistive random-access memory
  • Example 2 includes the subject matter of any of Examples 1 and 4-23, wherein: at least one of the source portion and the diode portion includes at least one material selected from the group consisting of silicon (Si), germanium (Ge), and silicon germanium (SiGe); the source portion is n-doped; and the diode portion is p-doped.
  • Example 3 includes the subject matter of any of Examples 1 and 4-23, wherein: at least one of the source portion and the diode portion includes at least one material selected from the group consisting of silicon (Si), germanium (Ge), and silicon germanium (SiGe); the source portion is p-doped; and the diode portion is n-doped.
  • Example 4 includes the subject matter of any of Examples 1-3 and 5-23, wherein the tunnel diode is configured to clamp current during at least one of: a FORMING operation of the RRAM device, in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof; and a SET operation of the RRAM device, in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device to the anode thereof.
  • a FORMING operation of the RRAM device in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof
  • a SET operation of the RRAM device in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device to the anode thereof.
  • Example 5 includes the subject matter of any of Examples 1—4 and 6-23, wherein the tunnel diode is configured to provide conductance in an opposite polarity during a RESET operation of the RRAM device, in which an electrically conductive filament of oxygen vacancies extending from a cathode of the RRAM device to an anode of the RRAM device is broken.
  • Example 6 includes the subject matter of any of Examples 1-5 and 7-23, wherein the diode portion has an x-width in the range of about 20-30 nm.
  • Example 7 includes the subject matter of any of Examples 1-6 and 8-23, wherein the diode portion has a y-thickness in the range of about 20-50 nm.
  • Example 8 includes the subject matter of any of Examples 1-7 and 9-23, wherein the diode portion has a trapezoidal cross-sectional geometry.
  • Example 9 includes the subject matter of any of Examples 1-8 and 10-23, wherein the diode portion has at least one tapered sidewall.
  • Example 10 includes the subject matter of any of Examples 1-9 and 1 1-23, wherein the diode portion has a curvilinear top surface.
  • Example 1 1 includes the subject matter of any of Examples 1-10 and 12-23, wherein the diode portion has a first portion of a first y-thickness and a second portion of a second y- thickness different from the first portion.
  • Example 12 includes the subject matter of any of Examples 1-1 1 and 14-23, wherein the RRAM device is in direct physical contact with the source contact.
  • Example 13 includes the subject matter of any of Examples 1-1 1 and 14-23, wherein there is at least one intervening layer between the RRAM device and the source contact.
  • Example 14 includes the subject matter of any of Examples 1-13 and 15-23, wherein the source contact is disposed at a back-end-of-line (BEOL) metal layer 0 of the memory device.
  • BEOL back-end-of-line
  • Example 15 includes the subject matter of any of Examples 1-14 and 16-23 and further includes an interconnect disposed over and configured for electronic contact with the RRAM device, wherein the interconnect includes at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta).
  • the interconnect includes at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta).
  • Example 16 includes the subject matter of any of Examples 1-15 and 17-23 and further includes a drain portion disposed adjacent another side of the gate stack.
  • Example 17 includes the subject matter of Example 16 and further includes a drain contact disposed over and configured for electronic contact with the drain portion.
  • Example 18 includes the subject matter of Example 17 and further includes an interconnect disposed over and configured for electronic contact with the drain contact, wherein the interconnect includes at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta).
  • the interconnect includes at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), and tantalum (Ta).
  • Example 19 includes the subject matter of any of Examples 1-18 and 20-23, wherein the gate stack includes: a gate dielectric layer disposed over the channel of the semiconductor substrate; and a gate disposed over the gate dielectric layer.
  • Example 20 includes the subject matter of any of Examples 1-19 and 21—23, wherein the RRAM device includes: a first electrode layer; a dielectric layer disposed over the first electrode layer; an exchange layer disposed over the dielectric layer; and a second electrode layer disposed over the exchange layer.
  • Example 21 includes the subject matter of Example 20, wherein at least one of the first and second electrode layers: includes at least one material selected from the group consisting of tungsten (W), iridium (Ir),. ruthenium (Ru), titanium nitride (TiN), and tantalum nitride (TaN); and has a y-thickness in the range of about 5-500 nm.
  • Example 22 includes the subject matter of Example 20, wherein the dielectric layer: includes a sub-stoichiometric oxide of at least one material selected from the group consisting of hafnium oxide (HfO x ), titanium oxide (TiO x ), tantalum oxide (TaO x ), aluminum oxide (A10 x ), and tungsten oxide (WO x ), wherein x is in the range of about 1.7-1.9; and has a y-thickness in the range of about 1-20 nm.
  • HfO x hafnium oxide
  • TiO x titanium oxide
  • TaO x tantalum oxide
  • Al oxide A10 x
  • WO x tungsten oxide
  • Example 23 includes the subject matter of Example 20, wherein the exchange layer: includes at least one material selected from the group consisting of titanium (Ti), hafnium (Hf), and tantalum (Ta); and has a y-thickness in the range of about 0.1-50 nm.
  • the exchange layer includes at least one material selected from the group consisting of titanium (Ti), hafnium (Hf), and tantalum (Ta); and has a y-thickness in the range of about 0.1-50 nm.
  • Example 24 is a method of fabricating a non-volatile memory device, the method including: forming a gate stack over a channel region of a semiconductor substrate; forming a source portion adjacent one side of the gate stack, at least one of over and in the semiconductor substrate; forming a diode portion over the source portion, wherein the source portion and the diode portion together constitute at least a portion of a tunnel diode; forming a source contact over the diode portion, wherein the source contact is configured for electronic contact with the source portion through the diode portion; and forming a resistive random-access memory (RRAM) device over the source contact, wherein the RRAM device is configured for electronic contact with the source contact.
  • RRAM resistive random-access memory
  • Example 25 includes the subject matter of any of Examples 24 and 27-39, wherein: at least one of the source portion and the diode portion includes at least one material selected from the group consisting of silicon (Si), germanium (Ge), and silicon germanium (SiGe); the source portion is n-doped; and the diode portion is p-doped.
  • Example 26 includes the subject matter of any of Examples 24 and 27-39, wherein: at least one of the source portion and the diode portion includes at least one material selected from the group consisting of silicon (Si), germanium (Ge), and silicon germanium (SiGe); the source portion is p-doped; and the diode portion is n-doped.
  • Example 27 includes the subject matter of any of Examples 24-26 and 28-39 and further includes: doping either the source portion or the diode portion with at least one material selected from the group consisting of arsenic (As) and phosphorous (P), at a dopant concentration in the range of about 1E19-1 E21 cm “3 ; and doping the other of the source portion and the diode portion with boron (B), at a dopant concentration in the range of about 1 E19-1 E21 cm “3 .
  • As arsenic
  • P phosphorous
  • B boron
  • Example 28 includes the subject matter of any of Examples 24-27 and 29-39, wherein the tunnel diode is configured to clamp current during at least one of: a FORMING operation of the RRAM device, in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof; and a SET operation of the RRAM device, in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device to the anode thereof.
  • a FORMING operation of the RRAM device in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof
  • a SET operation of the RRAM device in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device to the anode thereof
  • Example 29 includes the subject matter of any of Examples 24-28 and 30-39, wherein the tunnel diode is configured to provide conductance in an opposite polarity during a RESET operation of the RRAM device, in which an electrically conductive filament of oxygen vacancies extending from a cathode of the RRAM device to an anode of the RRAM device is broken.
  • Example 30 includes the subject matter of any of Examples 24-29 and 32-39, wherein the RRAM device is in direct physical contact with the source contact.
  • Example 31 includes the subject matter of any of Examples 24-29 and 32-39, wherein there is at least one intervening layer between the RRAM device and the source contact.
  • Example 32 includes the subject matter of any of Examples 24-31 and 33-39, wherein forming the diode portion over the source portion includes: forming a dielectric layer over the semiconductor substrate; patterning a first feature within the dielectric layer, wherein the first feature lands over the source portion; and depositing the diode portion within the first feature, over the source portion.
  • Example 33 includes the subject matter of Example 32, wherein forming the diode portion over the source portion further includes: patterning a second feature within the dielectric layer; masking off the second feature such that the diode portion is prevented from being deposited therein; and unmasking the second feature.
  • Example 34 includes the subject matter of any of Examples 24-33 and 35-39 and further includes: forming an interconnect over the RRAM device, wherein the interconnect is configured for electronic contact with the RRAM device.
  • Example 35 includes the subject matter of any of Examples 24-34 and 36-39, wherein the gate stack includes: a gate dielectric layer disposed over the channel portion of the semiconductor substrate; and a gate disposed over the gate dielectric layer.
  • Example 36 includes the subject matter of any of Examples 24-35 and 37-39, wherein the RRAM device includes: a first electrode layer; a dielectric layer disposed over the first electrode layer; an exchange layer disposed over the dielectric layer; and a second electrode layer disposed over the exchange layer.
  • Example 37 includes the subject matter of Example 36, wherein at least one of the first and second electrode layers: includes at least one material selected from the group consisting of tungsten (W), iridium (Ir), ruthenium (Ru), titanium nitride (TiN), and tantalum nitride (TaN); and has a y-thickness in the range of about 5-500 nm.
  • Example 38 includes the subject matter of Example 36, wherein the dielectric layer: includes a sub-stoichiometric oxide of at least one material selected from the group consisting of hafnium oxide (HfO x ), titanium oxide (TiO x ), tantalum oxide (TaO x ), aluminum oxide (A10 x ), and tungsten oxide (WO x ), wherein x is in the range of about 1.7-1.9; and has a y-thickness in the range of about 1-20 nm.
  • HfO x hafnium oxide
  • TiO x titanium oxide
  • TaO x tantalum oxide
  • Al oxide A10 x
  • WO x tungsten oxide
  • Example 39 includes the subject matter of Example 36, wherein the exchange layer: includes at least one material selected from the group consisting of titanium (Ti), hafnium (Hf), and tantalum (Ta); and has a y-thickness in the range of about 0.1-50 nm.
  • the exchange layer includes at least one material selected from the group consisting of titanium (Ti), hafnium (Hf), and tantalum (Ta); and has a y-thickness in the range of about 0.1-50 nm.
  • Example 40 is a non-volatile memory device including: a transistor including a doped source region; a resistive random-access memory (RRAM) device disposed over the transistor; and a P+ N+ tunnel diode configured to operatively couple the RRAM device and the doped source region and including: at least a portion of the doped source region; and a doped diode layer disposed over the doped source region; wherein the doped diode layer and the at least a portion of the doped source region are oppositely doped.
  • RRAM resistive random-access memory
  • Example 41 includes the subject matter of any of Examples 40 and 42-46, wherein: one of the doped source region and the doped diode layer is doped with at least one material selected from the group consisting of arsenic (As) and phosphorous (P) and has a dopant concentration in the range of about 1E19-1 E21 cm “3 ; and the other of the doped source region and the doped diode layer is doped with boron (B) and has a dopant concentration in the range of about 1 E19- 1 E21 cm “3 .
  • As arsenic
  • P phosphorous
  • B boron
  • Example 42 includes the subject matter of any of Examples 40-41 and 43—46, wherein the doped diode layer has: an x-width in the range of about 20-30 nm; and a y-thickness in the range of about 20-50 nm.
  • Example 43 includes the subject matter of any of Examples 40-42 and 44—46, wherein the RRAM device includes: a first electrode layer; a sub-stoichiometric oxide layer disposed over the first electrode layer; an oxygen exchange layer disposed over the sub-stoichiometric oxide layer; and a second electrode layer disposed over the oxygen exchange layer.
  • Example 44 includes the subject matter of any of Examples 40—43 and 45 ⁇ 16, wherein the P+/N+ tunnel diode is configured to clamp current during at least one of: a FORMING operation of the RRAM device, in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof; and a SET operation of the RRAM device, in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device to the anode thereof.
  • a FORMING operation of the RRAM device in which oxygen is formed at an anode of the RRAM device and an electrically conductive filament of oxygen vacancies extends from a cathode of the RRAM device to the anode thereof
  • a SET operation of the RRAM device in which a broken electrically conductive filament of oxygen vacancies is reformed, extending from the cathode of the RRAM device
  • Example 45 includes the subject matter of any of Examples 40 ⁇ 14 and 46, wherein the P+ N+ tunnel diode is configured to provide conductance in an opposite polarity during a RESET operation of the RRAM device, in which an electrically conductive filament of oxygen vacancies extending from a cathode of the RRAM device to an anode of the RRAM device is broken.
  • Example 46 includes the subject matter of any of Examples 40—45, wherein the P+/N+ tunnel diode exhibits a negative differential resistance (NDR).
  • NDR negative differential resistance

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Abstract

L'invention concerne des techniques permettant d'intégrer une diode tunnel 1T -1 R dans une cellule de mémoire résistive non volatile 1T -1 R (RRAM). La diode tunnel peut être connectée en série à la cellule RRAM de façon à générer une commande du courant. La jonction p-n de la diode peut être formée, par exemple, à l'aide du matériau de source/drain et d'une couche de matériau de diode supplémentaire qui peut être, par exemple, un matériau de type p ou de type n épitaxial dopé à l'opposé du matériau de source/drain sous-jacent. Un contact de source et la partie de source peuvent être électroniquement mis en contact par la partie de diode. La diode tunnel P +/N + formée par la partie source et la partie diode peut fournir une résistance différentielle négative (NDR) qui sert à fixer un courant et à protéger contre le dépassement pendant les opérations de de formation et de mise à l'état initial des dispositifs RRAM, réduisant ainsi les dommages occasionnés aux filaments de RRAM. Dans certains cas, la diode tunnel peut être conçue pour fournir une conductance élevée dans une polarité opposée pendant l'opération de remise à l'état initial du dispositif RRAM.
PCT/US2015/000403 2015-12-24 2015-12-24 Dispositifs mémoires comprenant une diode tunnel intégrée en contact et leurs techniques de fabrication WO2017111844A1 (fr)

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WO2019132997A1 (fr) * 2017-12-29 2019-07-04 Intel Corporation Dispositif de mémoire à matériaux de résistance négative
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US11652454B2 (en) 2020-02-14 2023-05-16 Epinovatech Ab Monolithic microwave integrated circuit front-end module
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