WO2017111826A1

WO2017111826A1 - Deuterium anneal for non-planar iii-v field effect transistor

Info

Publication number: WO2017111826A1
Application number: PCT/US2015/000384
Authority: WO
Inventors: Srinivasa Aravind KILLAMPALLI; Jay Prakash GUPTA; Willy Rachmady; Joshua M. HOWARD
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2015-12-26
Filing date: 2015-12-26
Publication date: 2017-06-29
Anticipated expiration: 2018-06-26

Abstract

A high pressure, deuterium anneal is disclosed for passivating interfaces in non-planar group III-V field effect transistors. An exemplary non-planar field effect transistor (FET) includes a source region, a drain region, and a III-V semiconductor channel region disposed between the source region and the drain region. The non-planar FET further includes a gate stack disposed over the III-V semiconductor channel region, where the III-V semiconductor channel region includes deuterium proximal an interface between the gate stack and the III-V semiconductor channel region.

Description

DEUTERIUM ANNEAL FOR NON-PLANAR III-V FIELD EFFECT TRANSISTOR

TECHNICAL FIELD

[0001] This disclosure relates in general to the field of integrated circuit devices and, more particularly, to non-planar group ΠΙ-V field effect transistors.

BACKGROUND

[0002] New transistor architectures, such as non-planar field effect transistors (FETs), and new transistor materials, such as group III-V materials, have been introduced to improve transistor performance as transistor dimensions continue to shrink. Significant challenges exist in integrating group ΠΙ-V materials into non-planar FETs in a manner that meets transistor performance and reliability targets. For example, current manufacturing processes are failing to adequately passivate interfaces (such as III-V semiconductor channel/gate interfaces) and defects in gate dielectric materials in non-planar group III-V FETs, particularly for highly scaled non-planar group ΙΠ-V transistor architectures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, and can be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

[0004] FIG. 1A illustrates a schematic view of an integrated circuit device according to various aspects of the present disclosure;

[0005] FIG. IB illustrates a schematic cross-sectional view of the integrated circuit device of FIG. 1 A along line B-B according to various aspects of the present disclosure;

[0006] FIG. 2A illustrates a schematic cross-sectional view of the integrated circuit device of FIG. 1 A along line B-B during a high pressure, deuterium anneal process according to various aspects of the present disclosure;

[0007] FIG. 2B illustrate a schematic cross-sectional view of the integrated circuit device of FIG. 1A along line B-B after a high pressure, deuterium anneal process according to various aspects of the present disclosure;

[0008] FIG. 3 is a capacitance-voltage graph for a capacitor with III-V semiconductor channel material after a super-atmospheric (high pressure), deuterium anneal and a sub- atmospheric, hydrogen anneal according to various aspects of the present disclosure; [0009] FIG. 4A is a capacitance-voltage graph for a capacitor with ΓΠ-V semiconductor channel material both pre- and post- a high pressure, deuterium anneal according to various aspects of the present disclosure;

[0010] FIG. 4B is a capacitance-voltage graph for a capacitor with ΙΠ-V semiconductor channel material both pre- and post- a low pressure, deuterium anneal according to various aspects of the present disclosure;

[0011] FIG. 5 illustrates a flow chart of a method for passivating interfaces of an integrated circuit device according to various aspects of the present disclosure;

[0012] FIG. 6 illustrates a cross-sectional view of an exemplary interposer according to various aspects of the present disclosure; and

[0013] FIG. 7 illustrates a schematic block diagram of an exemplary computing device according to various aspects of the present disclosure.

DETAILED DESCRIPTION

[0014] Described herein are integrated circuit devices, such as non-planar group ΠΙ-V field effect transistors (FETs), having deuterium-passivated interfaces, surfaces, and/or films along with methods for passivation in integrated circuit devices. In various embodiments, a high pressure, deuterium anneal is disclosed for passivating interfaces (for example, III-V semiconductor channel/gate interfaces), surfaces, and/or films in non-planar group III-V FETs. While the deuterium-passivated interfaces, surfaces, and/or films described herein are included in non-planar group ΙΠ-V FETs, it should be appreciated that the embodiments described herein may be readily adapted to other capacitively-coupled device designs which employ a material layer (such as a dielectric layer) interfacing with a III-V semiconductor surface (for example, planar group III-V transistors (including metal-oxide-semiconductor FETs (MOSFETs)), MOS capacitors, etc.). Further, the present disclosure contemplates using the deuterium anneal disclosed herein for passivating interfaces (for example, group IV semiconductor channel/gate interfaces), surfaces, and/or films in non-planar group IV FETs and/or planar group IV FETs.

[0015] The present disclosure sets forth numerous specific details, however, it will be apparent to one skilled in the art, that aspects of the present disclosure may be practiced without these specific details. In some instances, well-known methods and devices are depicted in block diagram form, rather than in detail, to avoid obscuring aspects of the present disclosure. Reference throughout this specification to "an embodiment", "in one embodiment", "some embodiments", or "various embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, such references are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the two embodiments are not specified to be mutually exclusive. Further, though various operations may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0016] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other material layers or components. For example, one layer disposed over (above) or under (below) another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0017] FIG. 1A illustrates a schematic view of an integrated circuit device 100 according to various aspects of the present disclosure, and FIG. IB illustrates a schematic cross- sectional view of integrated circuit device 100 of FIG. 1A along line B-B according to various aspects of the present disclosure. In FIG. 1A and FIG. I B, integrated circuit device 100 includes a non-planar group III-V field effect transistor (FET) 102A and a non-planar group m-V FET 102B fabricated on a substrate 104. In alternate embodiments, integrated circuit device 100 includes one or more planar ΠΙ-V FETs. Substrate 104 includes any suitable semiconductor material, such as silicon, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium nitride, indium gallium arsenide, gallium antimonide, other group III-V materials, other group rv materials, other suitable semiconductor materials, or combinations thereof. In some embodiments, substrate 104 implements silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology. In some embodiments, substrate 104 includes various doped regions, including p-type doped regions (for example, areas doped with p-type dopants, such as boron) and/or n-type doped regions (for example, areas doped with n-type dopants, such as phosphorus). Isolation regions 106, such as shallow trench isolations (STIs) or deep trench isolations (DTIs), formed over and/or in substrate 104 isolate electronic components of integrated circuit device 100, such as non-planar group ΙΠ-V FET 102A and non-planar group III-V FET 102B. Isolation regions 106 include any suitable isolation material, such as a dielectric material. Though only non-planar group III-V FET 102A and non-planar group III-V FET 102B are depicted, integrated circuit device 100 includes any number of electronic components, including but not limited to, transistors, resistors, capacitors, diodes, power sources, inductors, sensors, transceivers, receivers, antennas, other electronic components, or a combination thereof in any geometry. Electronic components associated with integrated circuit device 100 may include those that are mounted on integrated circuit device 100 or those connected to integrated circuit device 100. Further, integrated circuit device 100 may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, and/or any other suitable application, depending on electronic components associated with integrated circuit device 100. In some implementations, integrated circuit device 100 may be employed as part of a chipset for executing one or more related functions in a computer.

[0018] Non-planar group III-V FET 102A and non-planar group III-V FET 102B may be configured as double-gate transistors, tri-gate transistors, wrap-around gate transistors, or all- around gate transistors (such as nanowire and nanoribbon-based transistors). In FIG. 1 A and FIG. IB, non-planar group ΠΙ-V FET 102A and non-planar group III-V FET 102B are fin- like FETs (FinFETs) that include a fin 1 10 protruding from substrate 104. Fin 1 10 is configured as a heterostructure that includes a stack of material layers, such as a barrier layer 1 12, a channel layer 1 14, and a barrier layer 1 16. Barrier layer 1 12 is disposed over substrate 104, channel layer 114 is disposed over barrier layer 112, and barrier layer 1 16 is disposed over channel layer 1 14. Barrier layer 1 12, channel layer 1 14, and barrier layer 1 16 include group III materials (for example, boron (B), aluminum (Al), gallium (Ga), indium (In), other group III element, or a combination thereof), group V materials (for example, phosphorous (P), arsenic (As), antimony (Sb), other group V element, or a combination thereof), or group ΠΙ-V materials. In some embodiments, barrier layer 1 12, channel layer 1 14, and/or barrier layer 116 are composed of binary compounds (for example, InP, InAs, InSb, GaAs, or other suitable binary compound), ternary compounds (for example, InAsSb, InGaAs, InAlAs, AlGaAs, or other suitable ternary compound), or quaternary compounds (for example, InGaAsSb, InAlAsSb, InAlGaAs, or other suitable quaternary compound). For example, in some embodiments, barrier layer 1 12 is an InAlAs layer or an InAlSb layer, channel layer 114 is an InAs layer or an InSb layer, and barrier layer 116 is an InGaAs layer. Barrier layer 1 12, channel layer 114, and/or barrier layer 1 16 can include different materials or same materials with varying constituent ratios to achieve desired band gaps and/or lattice spacing. For example, in some embodiments, to achieve carrier confinement and/or reduced device leakage, barrier layer 1 12 and/or barrier layer 1 16 include a material having a band gap that is wider than a bandgap of a material of channel layer 114. In some embodiments, materials of barrier layer 112, channel layer 1 14, and barrier layer 1 16 are lattice matched to ensure negligible dislocations therebetween. For example, in some embodiments, when fabricating heterostructure of fin 1 10, channel layer 1 14 may be lattice matched to barrier layer 1 12, and barrier layer 1 16 may be lattice matched to channel layer 1 14 (in other words, lattice constants of each layer are similar enough that dislocation formation is negligible). In yet other embodiments, barrier layer 112, channel layer 114, and barrier layer 116 are lattice mismatched (for example, to achieve strained epitaxial layers). The heterostructure of fin 1 10 can include other material layers, such as a compositional buffer layer (not shown) and/or other suitable layer. In some embodiments, a compositional buffer layer may be disposed between substrate 104 and barrier layer 1 12. In some embodiments, compositional buffer layer includes a material having a lattice structure onto which barrier layer 1 12 may be formed with negligible dislocations. In some embodiments, compositional buffer layer changes a lattice structure of the heterostructure of fin 1 10, by a gradient of lattice constants, from a lattice structure of substrate 104 to a lattice structure more compatible for epitaxially growing high quality, low defect layers thereon (such as barrier layer 1 12). In some embodiments, barrier layer 1 12, channel layer 1 14, and/or barrier layer 1 16 includes various doped regions, including p-type doped regions and/or n-type doped regions.

[0019] Non-planar group ΙΠ-V FET 102A and non-planar group III-V FET 102B each include a source region 120, a drain region 122, and a channel region 124 disposed between source region 120 and drain region 122. In FIG. 1A and FIG. IB, source region 120, drain region 122, and channel region 124 are portions of (and/or defined in) at least one material layer (such as group III, group V, and/or group ΠΙ-V material layers) included in the heterostructure of fin 1 10. In some embodiments, source region 120 and drain region 122 include barrier layer 1 16, and channel region 124 is a portion of channel layer 1 14 disposed between source region 120 and drain region 122. In some embodiments, source region 120 and drain region 122 are doped regions of the one or more material layers, such as lightly doped and or heavily doped regions formed in barrier layer 1 16 and/or channel layer 1 14. Source region 120 and drain region 122 are generally formed using an implantation diffusion process and/or an etching deposition process. In the implantation/diffusion process, an ion implantation process can implant dopants (such as boron, aluminum, antimony, phosphorous, arsenic, or other suitable dopant) into fin 1 10 to form source/drain regions. An annealing process may be performed to activate the dopants, causing the dopants to diffuse further into fin 1 10. In the etching/deposition process, fin 110 may be etched to form recesses at desired locations for source/drain regions, and then an epitaxial deposition process may be performed to fill the recesses with a suitable material for source region 120 and drain region 122. In some implementations, source region 120 and drain region 122 are formed by epitaxially growing a semiconductor material, such as a group III, a group V, or a group III-V material. In some embodiments, the epitaxially grown (deposited) semiconductor material may be doped in situ with any suitable dopants (such as boron, arsenic, or phosphorous). In some implementations, source region 120 and drain region 122 can be formed from a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, one or more layers of metal and/or metal alloys may be used to form source/drain regions.

[0020] A gate stack 130 is disposed over channel region 124 of fin 1 10. For example, gate stack 130 wraps around channel layer 1 14 to define channel region 124 of fin 1 10. Gate stack 130 includes at least two material layers, such as a gate dielectric layer 132 and a gate electrode layer 134. Gate dielectric layer 132 is disposed on channel layer 1 14, and gate electrode layer 134 is disposed on gate dielectric layer 132. Gate dielectric layer 132 includes a dielectric material, such as silicon oxide, silicon dioxide (S1O2), a high-k dielectric material, or a combination thereof. Exemplary high-k dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, other high-k dielectric material, or a combination thereof. In some embodiments, gate dielectric layer 132 includes more than one gate dielectric layer, such as an interface layer (for example, a S1O2 layer) formed on channel layer 1 14 and a high-k dielectric layer formed on the interface layer. Gate electrode layer 134 includes a conductive material, such as polysilicion, a P-type work function metal, an N-type work function metal, other suitable conductive material, or a combination thereof. For a p-type MOS (PMOS) transistor, gate electrode layer 134 includes a p-type work function metal, such as ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides thereof (for example, ruthenium oxide), metal alloys thereof, other p-type work function metal, or a combination thereof. In some embodiments, the PMOS transistor includes a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For an n-type MOS (NMOS) transistor, gate electrode layer 134 includes an n- type work function metal, such as hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, metal alloys thereof, other n-type work function metal, or a combination thereof. In some embodiments, the NMOS transistor includes a NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, gate electrode layer 134 includes at least two metal layers, for example, a work function metal layer and a metal fill layer. Gate electrode layer 134 can include other metal layers, such as barrier layers. In some embodiments, gate stack 130 includes additional layers, such as interface layers, barrier layers, gate silicide layers, and/or other suitable layers. A gate silicide layer includes any metal capable of reacting with silicon (such as titanium, tantalum, tungsten, cobalt, nickel, platinum, palladium, other suitable metal, metal alloys thereof, or a combination thereof) to form a metal silicide, which can enhance electrical contact to gate stack 130. In some embodiments, such as depicted in FIG. 1A and FIG. IB, gate spacers 136 are disposed on sidewalls of gate stack 130. Gate spacers 136 include any suitable material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or a combination thereof. In some embodiments, gate spacers 136 include silicon nitride doped with carbon. Gate spacers 136 can include any number of gate spacer pairs, for example, two pairs, three pairs, or four pairs of sidewall spacers formed on opposing sides of gate stack 130.

[0021] Various deposition, patterning, and/or etching processes are performed to form isolation regions 106, fin 110 (including barrier layer 112, channel layer 1 14, and barrier layer 116), source region 120, drain region 122, channel region 124, gate stack 130 (including gate dielectric layer 132 and gate electrode layer 134), and gate spacers 136. Deposition processes can include physical vapor deposition processes, chemical vapor deposition processes, atomic layer deposition processes, electrodeposition processes (such as electroplating and/or electroless plating), epitaxial processes, thermal oxidation processes, other suitable deposition processes, or a combination thereof. Patterning processes include any process used to pattern a material layer. Various patterning processes can include forming a photoresist (resist) layer and/or hard mask layer over substrate 104 (for example, by a spin coating process) and performing a lithography process to pattern the photoresist layer and or hard mask layer. The lithography process can include optical photolithography, immersion photolithography, deep ultraviolet (UV) lithography, extreme UV lithography, other suitable lithography process, or a combination thereof. Etching processes can include dry etching processes, wet etching processes, other suitable etching processes, or a combination thereof. Forming the various features of integrated circuit device 100 can further include performing annealing processes and/or any other suitable process.

[0022] Non-planar FETs based on III-V semiconductor materials, such as non-planar group III-V FET 102A and non-planar group III-V FET 102B, are promising for improving performance of highly scaled transistor architectures. III-V semiconductor channel regions (such as channel region 124) exhibit higher channel mobility and lower effective mass than conventional silicon channel regions, leading to higher carrier (injection) velocity for non- planar group III-V FETs. However, non-planar group ΙΠ-V FETs currently lack transistor architectures that can fully benefit from the high channel mobility and/or low effective mass in the ΠΙ-V semiconductor channel regions. For example, high density of interface states (Dit) existing at an III-V semiconductor channel/gate interface, such as an interface 138 between channel layer 1 14 (particularly, III-V semiconductor channel region 124) and overlying gate stack 130 (particularly, gate dielectric layer 132), can diminish gains in transistor performance achieved by higher channel mobility and/or lower effective mass. In FIG. 1A and FIG. I B, surface states at or near a surface of channel layer 1 14 can trap electrons and or holes, causing a high density of interface states at or near interface 138. Similarly, surface states of gate dielectric layer 132 at or near interface 138 can also trap electrons and/or holes, contributing to the high density of interface states at or near interface 138. Often, the surface states are caused by dangling III-V semiconductor bonds, dangling silicon bonds, and/or other crystal lattice defects associated with the surface of channel layer 1 14 and/or gate dielectric layer 132. Such surface states prevent interface 138 from being electrically neutral, reducing carrier mobility in channel layer 1 14 and degrading transistor performance. Passivating interface 138 is thus critical for maximizing performance and reliability of non-planar group ΠΙ-V FET 102A and/or non-planar group III-V FET 102B, particularly maximizing benefits achieved by ΠΙ-V semiconductor materials.

[0023] Current solutions for passivating interfaces and/or dielectric layers include subjecting integrated circuit device 100 to a sub-atmospheric pressure, hydrogen annealing process or an atmospheric pressure, hydrogen annealing process. Though the hydrogen annealing processes can eliminate surface states at interfaces in integrated circuit device 100, it has been observed that current hydrogen annealing processes fail to adequately passivate interfaces in non-planar group III-V FETs. The present disclosure thus proposes a method for passivating interfaces, surfaces, and/or any defects in dielectric material layers in non- planar group III-V FETs that overcomes the limitations of conventional passivation processes. In various embodiments, a high pressure, deuterium anneal is disclosed for passivating a non-planar group III-V FET's channel/gate interface (such as interface 138 of non-planar group III-V FET 102A and non-planar group ΠΙ-V FET 102B). The high pressure, deuterium anneal process described herein can provide a number of significant benefits that over conventional passivation processes, including current hydrogen annealing processes.

[0024] FIG. 2A illustrates a schematic cross-sectional view of integrated circuit device 100 of FIG. 1A along line B-B during a high pressure, deuterium anneal process according to various aspects of the present disclosure; and FIG. 2B illustrates a schematic cross-sectional view of integrated circuit device 100 of FIG. 1A along line B-B after the high pressure, deuterium anneal process according to various aspects of the present disclosure. In FIG. 2A, an interlayer dielectric (ILD) layer 140 is formed over integrated circuit device 100 (for example, over non-planar group III-V FET 102 A and non-planar group III-V FET 102B). ILD layer 140 includes any suitable dielectric material, such as a low-k dielectric material. Exemplary low-k dielectric materials include silicon dioxide, carbon doped oxide, silicon nitride, organic polymers (such as perfluorocyclobutane or polytetrafluoroethylene), fluorosilicate glass (FSG), organosilicates (such as silsesquioxane, siloxane, or organosilicate glass), other low-k dielectric material, or combinations thereof. ILD layer 140 can include pores or air gaps to reduce its dielectric constant. In some embodiments, integrated circuit device 100 further includes an interconnect structure (not shown) formed over substrate 104, which provides various interconnects for connecting various electronic components, such as non-planar group ΙΠ-V FET 102 A and non-planar group ΙΠ-V FET 102B, of integrated circuit device 100. The interconnect structure includes various ILD layers (such as ELD layer 140). The interconnect structure further includes various metallization layers formed in the ILD layers (such as in DLD layer 140) to form metal interconnects to electronic components of integrated circuit device 100 (for example, to gate stack 130, source region 120, and drain region 122 of non-planar group III-V FET 102A and/or non-planar group ΙΠ-V FET 102B). Metal interconnects can include various conductive layers, such as a barrier layer and a conductive interconnect layer. The barrier layer includes a material that can serve as both a diffusion barrier for a material of the conductive interconnect layer (such as acting as a diffusion barrier to copper or copper alloys forming the conductive interconnect layer), such as titanium, tantalum, titanium nitride, tantalum nitride, tungsten, molybdenum, ruthenium, paladium, rhodium, nickel, cobalt, platinum, other suitable material, metal alloys thereof, or a combination thereof. The conductive interconnect layer includes any suitable conductive material for forming interconnects in an interconnect structure, including copper, aluminum, tungsten, cobalt, ruthenium, nickel, iron, molybdenum, other suitable conductive material, metal alloys thereof, or a combination thereof.

[0025] In FIG. 2A, integrated circuit device 100 (particularly, non-planar group ΙΠ-V FET 102 A and/or non-planar group III-V FET 102B) is subjected to an annealing process 150, which is a high pressure, deuterium anneal. For example, non-planar group III-V FET 102 A and non-planar group ΠΙ-V FET 102B are annealed in a deuterium-containing ambient (D) at a pressure greater than one atmosphere. In some embodiments, annealing process 150 anneals integrated circuit device 100 at a pressure ranging from about 10 atmospheres to about 20 atmospheres. In some embodiments, integrated circuit device 100 is placed in a pressurized chamber (for example, under pressure greater than one atmosphere) and a deuterium-containing passivating gas, such as a deuterium (D₂) gas, is introduced into the pressurized chamber while the integrated circuit device 100 is heated for a time sufficient to allow deuterium to diffuse into fin 1 10 and passivate interface 138 (a III-V semiconductor channel/gate interface), other interface, and/or any defects present in dielectric layers of (such as gate dielectric layer 132) in integrated circuit device 100. For example, deuterium can diffuse into fin 1 10 proximal to a surface of barrier layer 112 and/or channel layer 114. Though not depicted, deuterium can diffuse into gate dielectric layer 132 and/or isolation region 106 proximal to a surface of barrier layer 1 12 and/or channel layer 1 14. In yet other embodiments, deuterium can diffuse into other layers of integrated circuit 100 proximal to an interface that needs passivated. As noted, annealing process 150 is performed for any suitable time. In some embodiments, annealing process 150 anneals integrated circuit device 100 for a time ranging from about 30 minutes to about two hours. In alternate embodiments, annealing process 150 anneals integrated circuit device 100 for a time less than 30 minutes or greater than two hours. In some embodiments, annealing process 150 anneals integrated circuit device 100 in a 100% deuterium ambient (although trace amounts of other passivating gases may be present). In some embodiments, annealing process 150 anneals integrated circuit device 100 in less than 100% deuterium ambient, such as a 75% deuterium ambient, a 50% deuterium ambient, or other deuterium ambient percentage that can sufficiently passivate interface 138, other interface, and/or any defects present in dielectric layers of (such as gate dielectric layer 132) in integrated circuit device 100. Since III-V semiconductor materials tend to exhibit lower melting points than silicon, annealing process 150 is performed at a temperature low enough to avoid damaging (for example, melting) III-V semiconductor materials of integrated circuit device 100. In some embodiments, annealing process 150 is performed at a temperature less than about 450°C. In some embodiments, annealing process 150 anneals integrated circuit device 100 at a temperature of about 350°C. Annealing process 150 can implement different pressures, times, and temperatures in various embodiments to enhance diffusion of deuterium into fin 1 10 and passivate interface 138 (the ΙΠ-V semiconductor channel/gate interface), other interface, and/or any defects present in dielectric layers of in integrated circuit device 100.

[0026] During annealing process 150, deuterium (D) penetrates integrated circuit device 100, diffusing into fin 1 10 and passivating ΙΠ-V semiconductor interfaces, such as the III-V semiconductor channel/gate dielectric interface (channel region 124), along with any defects present in dielectric layers (such as gate dielectric layer 132) of non-planar group III-V FET 102A and non-planar group ΠΙ-V FET 102B. High pressure implemented by annealing process 150 allows more deuterium species to diffuse into fin 1 10, other interface, and/or any defects present in dielectric layers of (such as gate dielectric layer 132) at lower temperatures required for annealing III-V semiconductor materials. In some embodiments, deuterium passivates surface states (electrons and/or holes) at or near the surface of channel layer 1 14 and/or barrier layer 1 12. For example, in some embodiments, deuterium attaches to dangling ΠΙ-V semiconductor bonds at or near the surface of channel layer 1 14 and/or barrier layer 1 12. In some embodiments, deuterium passivates surface states (electrons and/or holes) at or near a surface of gate dielectric layer 132 that is proximal interface 138. For example, in some embodiments, deuterium attaches to dangling silicon bonds at or near the surface of gate dielectric layer 132 that is proximal interface 138. Turning to FIG. 2B, fin 110 includes a deuterium-passivated surface 160 after annealing process 150. Deuterium passivates interface 138 between channel layer 114 and gate dielectric layer 132, such that channel region 124 (III-V semiconductor channel region) includes deuterium proximal interface 138 between gate dielectric layer 132 and channel region 124. Though not depicted, in some embodiments, gate dielectric layer 132 includes deuterium proximal interface 138. Other interfaces, surfaces, and/or dielectric layers in integrated circuit device 100 may be passivated during annealing process 150, which can further improve transistor performance. For example, in some embodiments, deuterium passivates an interface 162 between barrier layer 1 12 and isolation region 106 (referred to as an isolation interface). In some embodiments, deuterium passivates source-drain junctions, such as an interface between channel layer 1 14 and source region 120 and/or drain region 122. Passivating isolation interfaces and/or source-drain junctions can minimize off-state leakage exhibited by non-planar group III-V FET 102A and/or non-planar group III-V FET 102B, for example, by saturating dangling III- V semiconductor bonds and or dangling silicon bonds at these interfaces. To ensure that deuterium remains proximal interface 138, interface 162, and/or other interface in integrated circuit device 100 (such that such interfaces remain passivated), annealing process 150 is performed near an end of fabricating integrated circuit device 100, for example, after forming the interconnect structure. In various embodiments, no other thermal processes are performed on integrated circuit device 100 after annealing process 150.

[0027] Deuterium-passivated III-V semiconductor surfaces, such as deuterium-passivated surface 160, exhibit less surface states than conventional hydrogen-passivated III-V semiconductor surfaces, allowing non-planar group III-V FET 102A and/or non-planar group ΙΠ-V FET 102B to benefit from higher channel mobility and/or lower effective mass provided by their ΠΙ-V semiconductor channel regions (such as III-V semiconductor channel region 124). FIG. 3 is a capacitance-voltage (C-V) graph 180 that illustrates capacitance per unit area (C/A) (in F/cm²) as a function of a gate voltage (in V) for a capacitor with III-V semiconductor channel material after a super-atmospheric (high pressure), deuterium anneal and a sub-atmospheric, hydrogen anneal according to various aspects of the present disclosure. In some embodiments, the super-atmospheric pressure, deuterium anneal involved annealing the III-V semiconductor channel material in 100% deuterium ambient greater than or equal to about 10 atmospheres, and the sub-atmospheric pressure, hydrogen anneal involved annealing the ΠΙ-V semiconductor channel material in 100% hydrogen ambient less than or equal to about one atmosphere. In FIG. 3, C-V graph 180 includes post- deuterium anneal C-V curves 185 (such as a post-deuterium anneal C-V curve 185 A, a post- deuterium anneal C-V curve 185B, a post-deuterium anneal C-V curve 185C, a post- deuterium anneal C-V curve 185D, and a post-deuterium anneal C-V curve 185E) and post- hydrogen anneal C-V curves 190 (such as a post-hydrogen anneal C-V curve 190A, a post- hydrogen anneal C-V curve 190B, a post-hydrogen anneal C-V curve 190C, a post-hydrogen anneal C-V curve 190D, and a post-hydrogen anneal C-V curve 190E). As seen in FIG. 3, deuterium passivation species provide stronger passivation of ΠΙ-V semiconductor materials (significantly reducing and/or eliminating traps) than hydrogen passivation species. For example, post-deuterium anneal C-V curves 185 reveal that super-atmospheric, deuterium anneal substantially reduces (and even eliminates) frequency dispersion, particularly in inversion mode, which corresponds with substantially reduced (or eliminated) surface states (such as trapped electrons and/or holes) at a surface of the III-V semiconductor channel material. In contrast, post-hydrogen anneal C-V curves 190 reveal that sub-atmospheric, hydrogen anneal process minimally reduces frequency dispersion, which corresponds with hydrogen failing to adequately passivate surface states at the surface of the III-V semiconductor channel material. Accordingly, super-atmospheric, deuterium anneal can significantly improve passivation of interfaces (such as ΠΙ-V channel/gate interfaces), surfaces (such as III-V semiconductor channel layer surfaces), and/or any defects in dielectric materials (such as gate dielectric layers) in non-planar group III-V FETs, leading to non- planar group III-V FETs exhibiting improved performance and reliability.

[0028] High pressure, deuterium-passivated ΙΠ-V semiconductor surfaces, such as deuterium-passivated surface 160, exhibit less surface states than low pressure, deuterium- passivated III-V semiconductor surfaces, allowing non-planar group ΙΠ-V FET 102A and/or non-planar group III-V FET 102B to benefit from the higher channel mobility and/or lower effective mass provided by their III-V semiconductor channel regions (such as III-V semiconductor channel region 124). FIG. 4A is a capacitance-voltage (C-V) graph 200 that illustrates capacitance per unit area (C/A) (in F/cm²) as a function of a gate voltage (in V) for a capacitor with ΠΙ-V semiconductor channel material both pre- and post- a high pressure, deuterium anneal (such as anneal process 150) according to various aspects of the present disclosure. In some embodiments, the III-V semiconductor channel material was annealed in 100% deuterium ambient greater than or equal to about 10 atmospheres. In FIG. 4 A, C-V graph 200 includes a pre-anneal C-V curve 202A and a corresponding post-anneal C-V curve 202B, a pre-anneal C-V curve 204A and a corresponding post-anneal C-V curve 204B, a pre- anneal C-V curve 206A and a corresponding post-anneal C-V curve 206B, a pre-anneal C-V curve 208A and a corresponding post-anneal C-V curve 208B, and a pre-anneal C-V curve 21 OA and a corresponding post-anneal C-V curve 21 OB. FIG. 4B is a C-V graph 220 that illustrates capacitance per unit area (C/A) (in F/cm²) as a function of a gate voltage (in V) for a capacitor with III-V semiconductor channel material pre- and post- a lower pressure, deuterium anneal according to various aspects of the present disclosure. In some embodiments, the III-V semiconductor channel material was annealed in 100% deuterium ambient less than or equal to about 2 atmospheres. In FIG. 3B, C-V graph 220 includes a pre-anneal C-V curve 222A and a corresponding post-anneal C-V curve 222B, a pre-anneal C-V curve 224A and a corresponding post-anneal C-V curve 224B, a pre-anneal C-V curve 226A and a corresponding post-anneal C-V curve 226B, a pre-anneal C-V curve 228A and a corresponding post-anneal C-V curve 228B, and a pre-anneal C-V curve 23 OA and a corresponding post-anneal C-V curve 230B. As seen in FIG. 4A and FIG. 4B, deuterium passivation species provide stronger passivation of ΠΙ-V semiconductor materials (significantly reducing and/or eliminating traps) during a high pressure, deuterium anneal. For example, post-anneal C-V curves 202B, 204B, 206B, 208B, and 210B reveal that high- pressure, deuterium anneal substantially reduces (and even eliminates) frequency dispersion, particularly in inversion mode, which corresponds with substantially reduced (or eliminated) surface states (such as trapped electrons and/or holes) at a surface of the III-V semiconductor channel material. In contrast, post-anneal C-V curves 202B, 204B, 206B, 208B, and 210B reveal that low pressure, deuterium anneal process minimally reduces frequency dispersion, which corresponds with insufficient amounts of deuterium passivating surface states at the surface of the III-V semiconductor channel material. Because the high pressure, deuterium process increases molecular flux of deuterium (the passivating species) to appropriate interfaces, the high pressure, deuterium process enhances interface passivation compared to the low pressure, deuterium process. Accordingly, a high pressure, deuterium anneal can significantly improve passivation of interfaces (such as III-V channel/gate interfaces), surfaces (such as III-V semiconductor channel layer surfaces), and or any defects in dielectric materials (such as gate dielectric layers) in non-planar group ΙΠ-V FETs, leading to non- planar group III-V FETs exhibiting improved performance and reliability.

[0029] FIG. 5 illustrates a flow chart of an exemplary method 300 for passivating interfaces of an integrated circuit device, such as integrated circuit device 100, according to various aspects of the present disclosure. Method 300 begins at block 310, where a non- planar FET (such as non-planar group III-V FET 102 A) is formed that includes a III-V semiconductor channel region (such as channel region 124) and a gate stack (such as gate stack 130) disposed over the III-V semiconductor channel region. At block 320, an interface between the III-V semiconductor channel region and the gate stack (such as interface 138) is passivated by annealing the non-planar FET in a deuterium-containing ambient at a pressure greater than one atmosphere (such as by subjecting non-planar group III-V FET 102 A to annealing process 150). Subsequent processing may be performed to complete fabrication of the integrated circuit device 100. Although the various embodiments described herein are with respect to benefits for non-planar FETs, such benefits may also be achieved for planar devices, such as planar transistors (for example, MOSFETs). Furthermore, embodiments described herein may be effective for source-drain junction isolation.

[0030] FIG. 6 illustrates a schematic cross-sectional view of an exemplary interposer 400 according to various aspects of the present disclosure. Interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, a polymer material (such as polyimide), or any other suitable material. In some embodiments, interposer 400 is formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, group ΠΙ-V materials, group rv materials, or combinations thereof. Interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404. In some embodiments, first substrate 402 is an integrated circuit die (for example, an integrated circuit die that includes integrated circuit device 100 described above, which includes non-planar group III-V FET 102A and/or non-planar group ΠΙ-V FET 102B having passivated III-V semiconductor channel/gate interfaces and/or passivated dielectric layers), and second substrate 404 is another integrated circuit die, a memory module, or a computer motherboard. Generally, interposer 400 serves as an electrical interface routing between first substrate 402 and second substrate 404. For example, interposer 400 can spread a connection to a wider pitch or reroute a connection to a different connection. In some embodiments, interposer 400 couples first substrate 402 (for example, an integrated circuit die) to a ball grid array (BGA) 406, which is coupled to second substrate 404. In some embodiments, as depicted, first substrate 402 and second substrate 404 are attached to opposing sides of interposer 400. In some embodiments, first substrate 402 and second substrate 404 are attached to the same side of interposer 400. In further embodiments, three or more substrates may be interconnected by way of interposer 400. Interposer 400 can include an interconnect structure 408 that includes metal interconnects, including but not limited to, trenches 410, vias 412, and through-silicon vias (TSVs) 414. Interposer 400 can also include embedded devices 416, including both passive devices and active devices. Exemplary embedded devices include capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, other suitable embedded devices, or combinations thereof. In some embodiments, RF devices, power amplifiers, power management devices, antennas, arrays, sensors, microelectromechanical systems (MEMS) devices, other devices, or combinations thereof can be formed on and/or attached to interposer 400.

[0031] FIG. 7 illustrates a schematic block diagram of an exemplary computing device 500 according to various aspects of the present disclosure. Computing device 500 includes a number of components. In some implementations, these components are attached to one or more motherboards. In some implementations, some or all of these components are fabricated onto a system-on-a-chip (SoC) die. The various components of computing device 500 can implement integrated circuit device 100 described above, which includes non-planar group ni-V FET 102A and/or non-planar group ΠΙ-V FET 102B having deuterium- passivated interfaces and/or surfaces, such as passivated III-V semiconductor channel/gate interfaces. In FIG. 7, computing device 500 includes an integrated circuit die 502 (which can include a processor 504 and a memory 506 (such as an on-chip memory)) and a communications chip 508. In some embodiments, integrated circuit die 502 physically and electrically couples to a motherboard. In some embodiments communications chip 508 also physically and electrically couples to the motherboard. In some embodiments, communications chip 508 is part of integrated circuit die 502 and/or processor 504. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Memory 506, often used as cache memory, can be provided by any suitable memory technology, such as embedded DRAM (eDRAM) or spin- transfer torque memory (STTM). Communications chip 508 (also referred to as a communications logic unit) enables wireless communications for data transfer to and from computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communications chip 508 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 502.1 1 family), WiMAX (IEEE 502.16 family), IEEE 502.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 500 may include multiple communications chips 508. For example, a first communications chip may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and a second communications chip may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0032] Depending on its applications, computing device 500 may include other components that may or may not be physically and/or electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, a volatile memory 510 (for example, dynamic random access memory (DRAM)), a nonvolatile memory 512 (for example, read only memory (ROM) or flash memory), a graphics processing unit (GPU) 514, a digital signal processor (DSP) 516, a crypto processor 518 (a specialized processor that can execute cryptographic algorithms within hardware), a chipset 520, an antenna 522, a display 524 (such as a touchscreen display), a display controller 526 (such as a touchscreen display controller), a power source (for example, a battery 528), a power amplifier (not shown), a voltage regulator (not shown), a video codec (not shown), an audio codec (not shown), a global positioning system (GPS) device 530, motion sensor(s) 532 (which may include a motion processor, an accelerometer, a gyroscope, and/or a compass), a speaker 534, a camera 536, input devices 538 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 540 (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so forth). In various implementations, computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 500 may be any other electronic device that processes data.

[0033] OVERVIEW OF EXAMPLE EMBODIMENTS: Various embodiments of the present disclosure include integrated circuit devices, such as non-planar group ΠΙ-V field effect transistors, having deuterium-passivated interfaces and/or surfaces, along with methods for passivating interfaces in integrated circuit devices, as described below. While the deuterium-passivated interfaces, surfaces, and/or films described herein are included in non- planar group III-V FETs, it should be appreciated that the embodiments so described may be readily adapted to other capacitively-coupled device designs, which employ a material layer (such as a dielectric layer) interfacing with a III-V semiconductor surface (for example, planar transistors (including as metal-oxide-semiconductor FETs (MOSFETs), MOS capacitors, etc.). Furthermore, although the various embodiments described herein are with respect to benefits for non-planar FETs, such benefits may also be achieved for planar devices, such as planar transistors (for example, MOSFETs). Embodiments described herein may also be effective for source-drain junction isolation.

[0034] In some embodiments, an exemplary non-planar field effect transistor (FET) includes a source region, a drain region, and a III-V semiconductor channel region disposed between the source region and the drain region. The non-planar FET further includes a gate stack disposed over the III-V semiconductor channel region, where the ΙΠ-V semiconductor channel region includes deuterium proximal an interface between the gate stack and the III-V semiconductor channel region. In some embodiments, the gate stack includes a gate dielectric layer disposed on the ΙΠ-V semiconductor channel region, and a gate electrode layer disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer is a high-k dielectric layer. In some embodiments, the III-V channel region includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.

[0035] In some embodiments, the source region, the drain region, and the III-V semiconductor channel region are portions of a heterostructure disposed over a substrate. In some embodiments, the heterostructure includes a first barrier layer disposed over the substrate, a III-V channel layer disposed over the first barrier layer, wherein the gate stack is disposed over the ΠΙ-V channel layer, and a second barrier layer disposed over the III-V channel layer. In some embodiments, the III-V channel layer includes deuterium proximal an interface between the gate stack and the ΙΠ-V channel layer. In some embodiments, the first barrier layer includes deuterium proximal an interface between an isolation region and the first barrier layer. In some embodiments, the first barrier layer and the second barrier layer include a group III material, a group V material, or a group III-V material.

[0036] In some embodiments, an exemplary fin-like field effect transistor (FinFET) includes a substrate; a fin that includes a HI-V channel layer disposed over the substrate, wherein the III-V channel layer includes a ΠΙ-V channel layer surface, and a gate stack disposed over the III-V channel layer that defines a ΓΠ-V semiconductor channel region of the fin. Deuterium is proximal to the ΠΙ-V channel layer surface. In some embodiments, the gate stack includes a gate dielectric layer disposed over the III-V channel layer surface, and a gate electrode layer disposed over the gate dielectric layer. In some embodiments, the deuterium is in the III-V channel layer and/or the gate dielectric layer. In some embodiments, the III-V channel layer includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP. In some embodiments, an exemplary the gate dielectric layer is a high-k dielectric layer. In some embodiments, the fin further includes a first barrier layer disposed between the substrate and the ΠΙ-V channel layer, and a second barrier layer disposed over the III-V channel layer. In some embodiments, the first barrier layer includes a first barrier layer surface, wherein deuterium is proximal the first barrier layer surface. In some embodiments, the deuterium is in the first barrier layer and/or other material layer adjacent the first barrier layer (such as in an isolation feature formed adjacent the first barrier layer). In some embodiments, the first barrier layer and the second barrier layer include a group III material, a group V material, or a group ΠΙ-V material.

[0037] In some embodiments, an exemplary method for passivating an interface includes forming a non-planar field effect transistor (FET) that includes a III-V semiconductor channel region and a gate stack disposed over the ΠΙ-V semiconductor channel region, passivating an interface between the III-V semiconductor channel region and the gate stack by annealing the non-planar FET in a deuterium-containing ambient at a pressure greater than one atmosphere. In some embodiments, the deuterium-containing ambient is 100% deuterium. In some embodiments, the pressure ranges from about 10 atmospheres to about 20 atmospheres. In some embodiments, the non-planar FET is annealed at a temperature less than about 450°C. In some embodiments, the annealing is performed for a time ranging from about thirty minutes to about two hours. In some embodiments, no other thermal processes are performed on the non-planar FET after the annealing.

[0038] In some embodiments, forming the non-planar FET includes forming a fin that includes a ΙΠ-V channel layer over a substrate, and forming the gate stack over the III-V channel layer to define the III-V semiconductor channel region of the fin. In some embodiments, passivating the interface between the III-V semiconductor channel region and the gate stack includes diffusing deuterium proximal to a surface of the III-V channel layer, wherein the gate stack is disposed over the surface of the III-V channel layer. In some embodiments, the deuterium is diffused into the III-V channel layer and/or gate stack (such as a gate dielectric layer) proximal to the surface of III-V channel layer. In some embodiments, forming the gate stack includes forming a gate dielectric layer on the III-V channel layer, and forming a gate electrode layer on the gate dielectric layer. In some embodiments, forming the fin includes forming a first barrier layer between the substrate and the III-V channel layer and a second barrier layer over the ΠΙ-V channel layer. In some embodiments, annealing the non-planar FET further includes diffusing deuterium proximal to a surface of the first barrier layer. In some embodiments, the deuterium is diffused into the first barrier layer, the ΙΠ-V channel layer, and/or other material layer adjacent the first barrier layer (such as in an isolation feature) proximal to the surface of first barrier layer.

[0039] In some embodiments, an exemplary transistor includes a ΙΠ-V semiconductor channel layer disposed over a substrate, wherein deuterium is proximal to an interface associated with the III-V semiconductor channel layer, and a gate stack disposed over the III- V semiconductor channel layer. In some embodiments, the interface is between the gate stack and the III-V semiconductor channel layer. In some embodiments, the III-V semiconductor channel layer includes the deuterium proximal to the interface. In some embodiments, the gate stack includes a gate dielectric layer disposed on the III-V semiconductor channel layer, wherein the gate dielectric layer includes the deuterium proximal to the interface, and a gate electrode layer disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer is a high-k gate dielectric layer.

[0040] In some embodiments, a first barrier layer disposed between the substrate and the III-V semiconductor channel layer, and a second barrier layer disposed over the III-V semiconductor channel layer. In some embodiments, the first barrier layer includes deuterium proximal an interface between an isolation region and the first barrier layer. In some embodiments, the interface is between the III-V semiconductor channel layer and the second barrier layer, and the III-V semiconductor channel layer includes the deuterium proximal to the interface. In some embodiments, the ΠΙ-V channel layer includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.

[0041] In some embodiments, an exemplary a method for passivating an interface associated with a transistor includes forming a transistor that includes a III-V semiconductor channel layer and a gate stack disposed over the ΠΙ-V semiconductor channel layer, and passivating an interface associated with the III-V semiconductor channel layer by annealing the transistor in a deuterium-containing ambient at a pressure greater than one atmosphere. In some embodiments, an interface between the III-V semiconductor channel layer and the gate stack is passivated by the annealing. In some embodiments, the deuterium-containing ambient is 100% deuterium. In some embodiments, the pressure ranges from about 10 atmospheres to about 20 atmospheres. In some embodiments, the non-planar FET is annealed at a temperature less than about 450°C. In some embodiments, the annealing is performed for a time ranging from about thirty minutes to about two hours. In some embodiments, no other thermal processes are performed on the transistor after the annealing.

[0042] Although the present disclosure describes and references various embodiments, the present disclosure is not intended to be limited to the described embodiments, but instead the various aspects of the present disclosure can be practiced with modification and alteration within the spirit and scope of the appended claims. The scope of the present disclosure should be, therefore, determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS:

1. A non-planar field effect transistor (FET) comprising:

a source region, a drain region, and a III-V semiconductor channel region disposed between the source region and the drain region; and

a gate stack disposed over the III-V semiconductor channel region, wherein the III-V semiconductor region includes deuterium proximal an interface between the gate stack and the III-V semiconductor channel region.

2. The non-planar FET of claim 1, wherein the gate stack includes:

a gate dielectric layer disposed on the III-V semiconductor channel region; and a gate electrode layer disposed on the gate dielectric layer.

3. The non-planar FET of claim 2, wherein the gate dielectric layer is a high-k dielectric layer.

4. The non-planar FET of claims 1 or 2, wherein the III-V channel region includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.

5. The non-planar FET of claims 1 or 2, wherein the source region, the drain region, and the III-V semiconductor channel region are portions of a heterostructure disposed over a substrate, wherein the heterostructure includes:

a first barrier layer disposed over the substrate;

a III-V channel layer disposed over the first barrier layer, wherein the gate stack is disposed over the III-V channel layer; and

a second barrier layer disposed over the ΠΙ-V channel layer.

6. The non-planar FET of claim 5, wherein the III-V channel layer includes deuterium proximal an interface between the gate stack and the III-V channel layer.

7. The non-planar FET of claim 5, wherein the first barrier layer includes deuterium proximal an interface between an isolation region and the first barrier layer.

8. The non-planar FET of claim 5, wherein the first barrier layer and the second barrier layer include a group III material, a group V material, or a group III-V material.

9. A fin-like field effect transistor (FinFET) comprising:

a substrate;

a fin that includes a III-V channel layer disposed over the substrate, wherein the III-V channel layer includes a III-V channel layer surface, wherein deuterium is proximal to the III- V channel layer surface; and

a gate stack disposed over the III-V channel layer that defines a III-V semiconductor channel region of the fin, wherein the gate stack includes a gate dielectric layer disposed over the III-V channel layer surface and a gate electrode layer disposed over the gate dielectric layer.

10. The FinFET of claim 9, wherein the HI-V channel layer includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.

1 1. The FinFET of claims 9 or 10, wherein the gate dielectric layer is a high-k dielectric layer.

12. The FinFET of claims 9 or 10, wherein the fin further includes:

a first barrier layer disposed between the substrate and the III-V channel layer; and a second barrier layer disposed over the III-V channel layer.

13. The FinFET of claim 12, wherein the first barrier layer includes a first barrier layer surface, wherein deuterium is proximal to the first barrier layer surface.

14. The FinFET of claim 12, wherein the first barrier layer and the second barrier layer include a group III material, a group V material, or a group ΙΠ-V material.

15. A method for passivating an interface, the method comprising: forming a non-planar field effect transistor (FET) that includes a ΙΠ-V semiconductor channel region and a gate stack disposed over the III-V semiconductor channel region; and passivating an interface between the ΙΠ-V semiconductor channel region and the gate stack by annealing the non-planar FET in a deuterium-containing ambient at a pressure greater than one atmosphere.

16. The method of claim 15, wherein the deuterium-containing ambient is 100% deuterium.

17. The method of claim 15, wherein the pressure ranges from about 10 atmospheres to about 20 atmospheres.

18. The method of claim 15, wherein the non-planar FET is annealed at a temperature less than about 450°C.

19. The method of claim 15, wherein the annealing is performed for a time ranging from about thirty minutes to about two hours.

20. The method of claim 15, wherein no other thermal processes are performed on the non-planar FET after the annealing.

21. The method any of claims 15-20, wherein forming the non-planar FET includes:

forming a fin that includes a III-V channel layer over a substrate, wherein the gate stack is formed over the III-V channel layer to define the III-V semiconductor channel region.

22. The method of claim 21, wherein passivating the interface between the III-V semiconductor channel region and the gate stack includes:

diffusing deuterium proximal to a surface of the III-V channel layer, wherein the gate stack is disposed over the surface of the III-V channel layer.

23. The method of claim 21 , wherein forming the gate stack includes: forming a gate dielectric layer on the III-V channel layer; and

forming a gate electrode layer on the gate dielectric layer.

24. The method of claim 21, wherein forming the fin includes:

forming a first barrier layer between the substrate and the ΠΙ-V channel layer; and forming a second barrier layer over the III-V channel layer.

25. The method of claim 24, wherein annealing the non-planar FET further includes diffusing deuterium proximal to a surface of the first barrier layer.