WO2017111771A1

WO2017111771A1 - Thin film polysilicon resistor by gate-to-gate isolation

Info

Publication number: WO2017111771A1
Application number: PCT/US2015/000179
Authority: WO
Inventors: Chen-Guan LEE; Chia-Hong Jan; Joodong Park; En-Shao LIU
Original assignee: Intel Corporation
Priority date: 2015-12-23
Filing date: 2015-12-23
Publication date: 2017-06-29

Abstract

Techniques are disclosed for forming polysilicon resistors. The polysilicon resistors are not constrained in the orthogonal-to-gate direction (or parallel-to-fin direction). Specifically, the resistors are not constrained by the gate pitch or gate critical dimension. In addition, the resistors may exhibit better variation control with respect to their vertical thickness (z- direction). For example, according to some embodiments, a thin film polysilicon resistor is provided, wherein the z-direction of the resistor is controlled by a polysilicon thin film deposition process, such that no or minimal recess etching or polishing is needed. Thus, better thickness control is achieved. In addition, the x-y dimension of the thin film polysilicon resistor is flexible and can be set based on a number of fins removed in advance of the polysilicon thin film deposition process. The resistor can thus sit between fins in a location that is wider than the normal fin pitch, according to some embodiments.

Description

THIN FILM POLYSILICON RESISTOR BY GATE-TO-GATE ISOLATION BACKGROUND

[0001] Polysilicon resistors are widely used in system-on-chip (SoC) applications due to benefit of having a near-zero temperature coefficient of resistance. A near-zero temperature coefficient of resistance means that the resistance value of the resistor varies only a small amount with variations in temperature in a given range. In contrast, a positive temperature coefficient of resistance means that the resistance value of the resistor will tend to increase with increasing temperature, and a negative temperature coefficient of resistance means that the resistance value of the resistor will tend to decrease with decreasing temperature. The resistance of a polysilicon resistor layer depends on the resistor layer geometry and specific polysilicon material used.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure la illustrates a top down view of a polysilicon resistor configured in accordance with an embodiment of the present disclosure.

[0003] Figure lb illustrates a cross-section view of the polysilicon resistor shown in Figure l a, taken at A-A', according to an embodiment.

[0004] Figure lb' illustrates a cross-section view of the polysilicon resistor shown in Figure la, taken at A-A', according to another embodiment.

[0005] Figure lc illustrates a cross-section view of the polysilicon resistor shown in Figure la, taken at B-B', according to an embodiment.

[0006] Figure lc' illustrates a cross-section view of the polysilicon resistor shown in Figure la, taken at B-B', according to another embodiment.

[0007] Figures 2a-i collectively illustrate a methodology for forming a polysilicon resistor in accordance with an embodiment of the present disclosure.

[0008] Figure 3a illustrates a top down view of a polysilicon resistor constrained by gate pitch- and gate critical dimension.

[0009] Figure 3b illustrates a cross-section view of the polysilicon resistor shown in Figure 3a, taken at A-A'.

[0010] Figure 3c illustrates a cross-section view of the polysilicon resistor shown in Figure 3a, taken at B-B'.

[0011] Figure 4 illustrates a computing system implemented with one or more integrated circuit structures configured in accordance with an embodiment of the present disclosure. [0012] As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the disclosure to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

[0013] Techniques are disclosed for forming polysilicon resistors. The polysilicon resistors are not constrained in the orthogonal-to-gate direction. Specifically, the resistors are not constrained by the gate pitch or gate critical dimension (CD). In addition, the resistors may exhibit better variation control with respect to their vertical thickness (z-direction). For example, according to some embodiments, a thin film polysilicon resistor is provided, wherein the z- direction of the resistor is controlled by a polysilicon thin film deposition process, such that no or minimal recess etching or polishing is needed. Thus, better thickness control is achieved. In addition, the x-y dimension of the thin film polysilicon resistor is flexible and can be set based on the number of fins removed in advance of the polysilicon thin film deposition process. As will be appreciated in light of this disclosure, the polysilicon resistor can sit between fins, in a location where any number of fins have been removed or a location where fins were not formed. To this end, the polysilicon resistor can sit between fins in a location that is wider than the normal fin pitch, according to some embodiments. Hence, the polysilicon resistor can effectively have any desired geometry and is not constrained by the gate pitch or gate CD.

General Overview

[0014] One possible approach to fabricate polysilicon resistors is to start from a standard polysilicon dummy gate process. In an example dummy gate process, a gate stack is formed by blanket depositing a gate dielectric layer (e.g., silicon dioxide) and a dummy gate electrode layer (e.g., polysilicon). A patterning and etch process is then employed to remove portions of the gate electrode layer and gate dielectric layer to form a dummy gate stack. The dummy gate process typically further includes forming spacers on the side of the gate stack. Further note that the gate dielectric may also be dummy material as well. As is known, such dummy gate stack materials are essentially place holders that can be later removed and replaced during a metal replacement gate (RMG) process. For instance, a dummy gate stack including a dummy gate dielectric of silicon dioxide and a dummy gate electrode of polysilicon can be removed and replaced with a high-k gate dielectric and elemental metal gate electrode. In such dummy gate forming processes where it is also desirable to form a polysilicon resistor, rather than removing all non-gate polysilicon when forming the dummy gate stack, the process can be modified to completely remove the polysilicon in some areas but to only recess the polysilicon in select areas where resistors are desired. In this way, the recessed polysilicon remaining, which would be in addition to the polysilicon left for the dummy gate stack, can be used as a resistor. Silicide contact terminals can then be added to the resistor using a trench-based contact forming process. Masking can be used to protect the recessed polysilicon when removing the non-gate and non- resistor polysilicon material and any other materials targeted for removal. Thus, polysilicon resistors can be formed within a standard polysilicon dummy gate process. However, such polysilicon resistors are subject to unresolved issues.

[0015] For instance, polysilicon resistors are prone to geometric variation caused by the polysilicon recess and polish etch. In particular, the vertical thickness (z-dimension) of the resistor is difficult to control (during selective recess process noted above), which in turn affects the resistance value of the resistor. Furthermore, the lateral dimension of such a polysilicon resistor in the orthogonal-to-gate direction is constrained by the polysilicon gate critical dimension (CD) and gate pitch. This dimensional constraint effectively limits the resistivity of each polysilicon resistor template and has a density penalty (the resistance is based on area). Figures 3a-c illustrate such issues for polysilicon resistors having a width constrained in the orthogonal-to-gate direction (or A-A' direction). Figure 3a shows a top-down view of the polysilicon resistors. As can be seen, a plurality of typical gates stacks are shown, and two polysilicon resistors are formed among them. Resistor contacts are provided as well. Figure 3b and Figure 3c are cross-section views taken along the A-A' and B-B' lines, respectively, of Figure 3a. As can be further seen, the resistors and gate stacks are formed on an interlayer isolation layer that is provided on a substrate. Each gate stack includes a gate electrode (and a gate dielectric, not shown, directly between the interlayer isolation and the gate electrode), and gate spacers on the sides of the gate electrode. A hardmask is provided on top of the gate stack, which protects the gate stack during the recess etch used to form the resistors. Note, however, that it is difficult to gauge the vertical thickness of the resistors during this etch, and within- wafer or within-die variation due to this etch can be a concern. Further note that the width of each resistor in the orthogonal-to-gate direction is determined by the gate pitch and the gate CD. Further note that the length of each resistor is adjustable, but that length must be in the parallel- to-gate direction. In summary, polysilicon resistors are prone to variance in z-direction thickness (due to recess etch and polish process) and are constrained in the orthogonal-to-gate direction (due to gate pitch and CD). [0016] Thus, and according to an embodiment of the present disclosure, techniques are disclosed for providing polysilicon resistors that are not constrained in the orthogonal-to-gate direction. In addition, the resistors may exhibit better variation control with respect to their vertical thickness (z-direction). According to some embodiments, a thin film resistor is provided that uses a polysilicon film deposited for gate-to-gate isolation as the resistor body. By intentionally blocking removal of the polysilicon in between fins, this polysilicon thin film can be preserved and used as a resistor. The thickness (or z-dimension) of the resistor is determined by the polysilicon film thickness deposited. Thus, variance in thickness due to recess etching or polishing is avoided. As will be appreciated, recess etching and polishing are major contributors to thickness variation. In addition, the x-y dimensions of the thin film polysilicon resistor are flexible and are determined by the drawn plug size for gate-to-gate isolation. In more detail, the polysilicon thin film resistor sits between fins. In some embodiments, this space between fins can be controlled by a fin cut etch. Alternatively, this space between fins can be controlled by the fin formation process, where fins are not formed in that location. As will be appreciated in light of this disclosure, any number of fins can be removed (or not formed, as the case may be) to make room for a polysilicon resistor of any desired dimension. This gives the freedom for controlling the resistor width/length (x-y dimensions), and a wide resistance range for one resist template. In contrast, a typical polysilicon resistor is constrained by the gate pitch and CD, as previously explained and shown in Figure 3a.

Integrated Circuit Architecture

[0017] Figure la illustrates a top down view of a polysilicon resistor configured in accordance with an embodiment of the present disclosure. As can be seen, a plurality of gates stacks is formed over a plurality of fins. The fins are substantially orthogonal to the dummy gate stacks, as normally done. Note, however, that a number of fins have been removed from the central area. In particular, about three or four rows of fins have been removed, or at least the depicted portion of those rows. As can be further seen, a relatively wide and long polysilicon resistor is formed in the space previously occupied by the removed fins. In other embodiments, rather than relying on a fin removal process, the fins can be more selectively formed such that no fins are formed in the central area as shown. Note that the polysilicon resistor has a width in the orthogonal-to-gate direction that is much larger than the gate CD as well as the gate pitch, in this example embodiment. Resistor contacts are formed on the polysilicon resistor. [0018] Figures lb-b' and Figures lc-lc' are cross-section views taken along the A- A' and B-B' lines, respectively, of Figure la. As can be further seen, the polysilicon resistors and dummy gate stacks are formed on an interlayer isolation layer that is provided on a substrate. The substrate can be any suitable substrate configuration. For instance, in some embodiments, the substrate may be a bulk substrate of one or more group IV semiconductor materials, such as a bulk silicon, germanium, silicon germanium, or silicon carbide substrate. Alternatively, the substrate may be a bulk substrate of a ΙΠ-V semiconductor material, which may include at least one group ΠΙ element (e.g., aluminum, gallium, indium, boron, thallium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth). Alternatively, the substrate may be a sapphire substrate. In still other example embodiments, the substrate need not be a bulk configuration and may instead be, for example, a multilayer structure or an X-on-insulator (XOI) structure where X comprises, for instance, a column IV material, a III-V material, or sapphire, and the insulator material can be an oxide material or dielectric material or some other electrically insulating material. In a more general sense, the substrate may include any material and structural configuration suitable for building a semiconductor circuit thereon.

[0019] The interlayer isolation can be any suitable isolation or insulator material. In some embodiments, for example, the interlayer isolation is an oxide native to the substrate (e.g., a silicon substrate with an interlayer isolation of silicon dioxide). Alternatively, the interlayer isolation need not be native to the substrate (e.g., a silicon substrate with an interlayer isolation of silicon nitride). The dielectric constant of the interlayer isolation material can vary as well, depending on factors such as conductor density within the interlayer isolation material and desired electrical isolation. In some embodiments, the interlayer isolation has a low-k dielectric constant, such as porous silicon dioxide, carbon doped silicon dioxide, or polymeric dielectrics. Such low-k dielectrics are particularly helpful to reduce undesired capacitive coupling between conductors within the given low-k dielectric. In a more general sense, the interlayer isolation can be any isolation material capable of providing sufficient dielectric constant and insulating qualities.

[0020] As can be further seen in Figures lb-b', each dummy gate stack includes a dummy gate electrode and gate spacers on the sides of the gate electrode. The dummy gate stack may further include a dummy gate dielectric, not shown, directly between the interlayer isolation and the dummy gate electrode. A hardmask is provided on top of the dummy gate stack, which can be used to protect the dummy gate stack during subsequent processing (such as during source and drain formation). Note that the cross-section of the dummy gate stack shown in Figures lb-b' is taken parallel to the fins but through a location where the fins were either removed or not provided (i.e., A-A'). As such, the portion of the gate stack shown in the cross-section is directly over the interlayer isolation. Thus, no channel is shown; rather, the channel is in the fin, which would be a different cross-section. The dummy gate stack can be implemented with any suitable materials. For instance, in one example embodiment, the dummy gate electrode is polysilicon, the dummy gate dielectric is silicon dioxide, and the gate spacer is silicon nitride. Numerous other materials can be used for the gate spacer and dummy gate dielectric materials, in conjunction with a dummy polysilicon gate electrode. As will be appreciated in light of this disclosure, the dummy polysilicon gate electrode can be at least partially provisioned in the same polysilicon film deposition process that is used to form the polysilicon resistor. However, in other embodiments, the polysilicon resistor is deposited at a different time than the polysilicon dummy gate electrode. Further note that the polysilicon used for the resistor may be the same as the polysilicon used for the dummy gate electrode in some embodiments, but in other embodiments may be a different polysilicon. For instance, the dummy gate electrode may be undoped polysilicon and the resistor can be doped polysilicon.

[0021] As can be seen in Figure lb, the polysilicon resistor is deposited between the gates where there are no fins. The metal contacts can be formed on the resistor using a trench based contact process, as normally done. In one such case, the structure is first filled with a dielectric material (such as more interlayer dielectric material) and then planarized to the top of the hard mask on the dummy gate stack. Then, a contact trench is etched down to each end of the resistor. A metal contact can then be deposited into the trench onto the resistor, followed by an annealing process to form a silicide contact. The contact may include, for example, a single plug metal, while in other embodiment may include multiple layers such as resistance reducing metal, plug metal, and capping metal. Any number of suitable contact structures can be used to form a contact on the polysilicon resistor. Figure lb shows the contacts landed squarely on the resistor. Figure lb' illustrates an alternative embodiment where the resistor has less than perfect right angle edges and flatness, and the contacts are landed closer to the edge of the resistor. In still other embodiments, the resistor contacts may be partially landed, with at least one portion of the contact on the underlying interlayer isolation.

[0022] Figure lc illustrates a cross-section taken perpendicular to the fins and at a location between dummy gate stacks (i.e., Β-Β')· As can be seen, the dummy gate dielectric is provided on the fins, which covers the entirety of the fins in this example embodiment. In other embodiments, the fins may not include the dummy gate dielectric outside the dummy gate stack region. In one specific example embodiment, the substrate is a bulk silicon substrate and the fins are native silicon fins extending therefrom. The interlayer isolation is porous silicon dioxide, and the dummy gate dielectric is silicon dioxide. Figure lc' shows an alternative embodiment where the polysilicon resistor has a different morphology, including slightly rounded (or otherwise less square corners) and a less than perfectly flat top surface. As will be appreciated in light of this surface, relatively tight control of the resistor's vertical thickness can be achieved with the polysilicon film deposition process so as to provide a relatively flat top resistor surface and uniform thickness. However, Figure l c' demonstrates that perfect or relatively high thickness uniformity is not necessarily needed in all embodiments. In some embodiments, for instance, the vertical thickness of the polysilicon resistor can vary by up to 2%, or 5%, or 10%, or higher, assuming the corresponding variation in resistance is tolerable to the given integrated circuit being fabricated. Variable thickness can be measured, for instance, with respect to the difference between high and low points of the resistor top surface. So, for example, the vertical thickness of the polysilicon resistor at a high point of the top surface may be 10 nm and the vertical thickness of the polysilicon resistor at a low point of the top surface may be 9 nm. This example scenario represents an example case where the vertical thickness of the polysilicon resistor varies by 10%.

[0023] Further details of techniques for forming polysilicon resistors according to an embodiment will now be provided with respect to Figures 2a-i.

[0024] Figures 2a-i collectively illustrate a methodology for forming a polysilicon resistor in accordance with an embodiment of the present disclosure.' As will be appreciated in light of this disclosure, the methodology includes a gate-to-gate isolation process, which generally includes creating the fin cut or otherwise fin free region upfront (before polysilicon formation). In more detail, Figure 2a is the top-down view that illustrates the gate-to-gate isolation regions and a polysilicon resistor placement in one of those regions, according to an embodiment. As can be seen, the outer two gate lines are continuous across all the fins shown, while the inner two gate lines are broken into a series of smaller segments along the same gate line. Further note that about three or four rows of fins are removed (or not formed) between gate segments Gi and G₂, and another three or four rows of fins are removed (or not formed) between gate segments G₂ and G₃. In addition, further note another three or four rows of fins are removed (or not formed) along gate segment G₃ in the middle portion of the run, and another three or four rows of fins are removed (or not formed) at the end of the G₃ run. In a fin cut based methodology, the fins can be removed prior to dummy gate formation, according to some embodiments. In still other such embodiments, the fins can be removed post-gate formation, such as during a polysilicon dummy gate removal process that is further tuned or otherwise configured to also remove the fins in the target area. In some such embodiments, masking can be used to isolate the targeted fins for removal, and to protect the fins not targeted for removal. Alternatively, a selective directional etching process can be used to selectively remove to the targeted fins post-gate formation. As previously explained, other embodiments may employ a methodology free of fin cutting/removal, where fins are selectively not formed in the target areas. As will be appreciated, note that any fins removed from the gate-to-gate isolation region(s) can be removed because there are no active devices planned in those regions (so no fins are needed).

[0025] Once the fin free target areas are provided (whether by fin cut or selective fin formation), and with further reference to the example embodiment of Figure 2a, neighboring segments Gi and G₂ are separated by a certain distance (based on the fin free area), and G₃ is a longer segment of the gate line. As will be appreciated, transistor channels are located (or will be) in the regions where a given gate line (or gate line segment, as the case may be) passes over a given fin. In addition, and as will be explained in turn, the fins may be configured with fin-based channels or wire-based channels. In any such cases, by defining the gate-to-gate isolation upfront in the fin free regions (by patterning the fin free isolation region or regions before the formation of dummy gate) according to some embodiments, the risk of gate-to-gate and gate-to- TCN shorting can be reduced. In contrast, if gate-to-gate isolation is formed later (post-gate formation) by cutting polysilicon lines, there is a greater risk for polysilicon remaining in the gate-to-gate isolation space, which in turn may result in shorting. TCN refers to a source or drain trench-based contact. Such gate-to-gate and gate-to-TCN shorting are common yield limiters for typical transistor processes. Thus, the techniques provided herein according to some embodiments may be used to avoid or reduce the occurrence of gate-to-gate and gate-to-TCN shorting, which may in turn increase production yield.

[0026] Figure 2a shows a substrate with fins already formed thereon and patterned. The fins are patterned, in that a number of fins have been removed to form regions where the gate-to-gate isolation can be formed, according to some embodiments. In other embodiments, the fins are patterned, in that a number of fins are not formed or otherwise provided so as to form regions where the gate-to-gate isolation can be formed. Note, however, that such a selective fin formation process deviates from standard fin forming processes, which are typically come with an expectation that the fins being produced will have a common fin pitch, rather than multiple fin pitches. As can be further seen, note that the dimension of the polysilicon resistor in the gate-to- gate isolation direction is only limited by the distance between adjacent fins, which in turn can be controlled by the number of fins removed. Figures 2b-2e define the upfront gate-to-gate isolation process, according to an embodiment. The cross-section in these figures is taken parallel to, and through, gate stack, at the location designated by the dashed line A-A' of Figure 2a. Said differently, the cross-section taken at line A-A' is perpendicular to the fins. Note that the gate stacks shown in Figure 2a are not yet formed in Figures 2b-2e. Rather, in this example embodiment, the gate stacks are formed after the gate-to-gate isolation is formed (the gate stack formation is discussed with reference to Figure 2f). [0027] Note that the fins can be original or "native" to the substrate, wherein the fins and substrate form a unitary mass. Alternatively, the fins can be replacement fins that are formed on the substrate through a recess-and-replace process, such as described in U.S. Patent Application Publication No. 2014/0027860. That application provides techniques for customization of fin- based transistor devices to provide a diverse range of channel and/or source-drain configurations. In general, native sacrificial fins can be removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In some such embodiments, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer material. The p-type layer material can be completely independent of the process for the n-type layer material, and vice-versa. Another embodiment may include a combination of original (native) fins and replacement fins. Another embodiment may include replacement fins all of the same configuration. In still other embodiments, the fins can be configured with nanowires through a recess-and-replace process, such as described in U.S. Patent No. 9,012,284. That patent provides techniques for customization of nanowire transistor devices to provide a diverse range of channel and/or source- drain configurations. In general, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application (at least one layer in a given stack is used to form a wire or ribbon). In some such embodiments, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. Note that a nanowire that is relatively thin (in the vertical direction) is sometimes referred to as a ribbon, which is intended to be included in the term nanowire or wire, as used herein. The p-type layer stack can be completely independent of the process for the n- type layer stack, and vice-versa. Another embodiment may include any combination of original (native) fins, replacement fins, and nanowires. Another embodiment may include fins all having the same nanowire configuration. Any of these and numerous other fin-based configurations can be used in conjunction with the polysilicon resistor techniques provided herein. To this end, and for purposes of simplicity, reference to a given fin herein is intended to refer to any such configurations, regardless of whether that fin is implemented with an original (native), replacement, or nanowire type configuration. As will be appreciated in light of this disclosure, in embodiments that employ a recess-and-replace process to provide replacement fins (or nanowires or ribbons, as the case may be), sacrificial fins removed from areas where a polysilicon resistor is targeted for population need not be replaced with custom semiconductor materials or stacks. [0028] In any such cases, once the substrate with the fins patterned as desired is provided, the methodology continues in this example embodiment as shown in Figure 2b, with depositing an interlayer isolation, which can be provisioned to the top of the fins, planarized, and then recessed to a desired level to expose the upper portion of the fins, as shown. Alternatively, the interlayer isolation can be selectively deposited to the desired thickness (so as to avoid the planarization and recess processing). In any case, the depth of the interlayer isolation recess can vary from one embodiment of the next, depending on factors such as desired fin height (or active channel portion of fin). As further shown in Figure 2b, a dummy oxide (or other suitable dummy gate dielectric) is deposited on top of the exposed fins. The dummy oxide may be a native oxide but need not be. In one example embodiment, the fins are implemented with silicon, and the dummy oxide is silicon dioxide. Other embodiments can include any suitable dummy gate dielectric suitable for a given fin composition. The interlayer isolation can be deposited using any number of deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). The dummy oxide (gate dielectric) can be deposited using similar deposition techniques (CVD, ALD, PVD) or thermally grown. The dummy oxide layer thickness can also vary from one embodiment to the next, but is typically thinner than the interlayer isolation thickness and in some embodiments is in the range of 5 nm to 30 nm. In some cases, the dummy oxide (gate dielectric) can be the same as the interlayer isolation material. In other embodiments, however, the dummy oxide (gate dielectric) is different than the interlayer isolation material. As further shown in Figure 2b, a film of polysilicon is deposited over the dummy oxide (gate dielectric), using any suitable deposition technique, such as CVD, ALD, or PVD. In this embodiment, note that the deposited polysilicon film is conformal in nature and is thick enough to fill the space in between fins and leaves some overburden on top of the fins. Further note that this polysilicon deposition is to form the polysilicon resistor in the gate-to-gate isolation area (fin cut or fin free region). Thus, the thickness of the polysilicon layer can be set based on the desired resistor thickness, according to an embodiment.

[0029] As can be seen in Figure 2c, the method of this example embodiment continues with depositing a thick oxide layer or other suitable gate-to-gate (GTG) isolation material. This GTG isolation material can be, for example, the same as the dummy oxide (gate dielectric) material shown in Figure 2b, but need not be the same. Example GTG isolation materials include, for instance, silicon dioxide, porous silicon dioxide, and carbon-doped silicon dioxide, to name a few example materials. The method further includes planarizing the GTG isolation material and patterning for gate-to-gate isolation, to provide the resulting structure in Figure 2c. Any number of etch schemes can be used, including wet and/or dry etch processes, as will be appreciated in light of this disclosure. In some embodiments, the GTG isolation material is patterned along with the underlying polysilicon layer with a directional dry etch process. After such a directional dry etch of the GTG isolation and polysilicon, only the gate-to-gate isolation and resistor regions have the thick oxide (or other GTG isolation material) remaining, as shown in Figure 2c. As can be further seen, polysilicon is left close to fins and underneath the GTG isolation material.

[0030] As shown in Figure 2d, the method of this example embodiment continues with depositing a robust conformal passivation layer, using any suitable deposition technique (e.g., CVD, ALD, PVD). The passivation layer thickness can vary from one embodiment to the next, but in some embodiments is in the range of 30 nm to 50 nm. The conformal passivation layer is then subjected to anisotropic/directional dry etch to provide the resulting structure shown in Figure 2e, according to an embodiment. The passivation layer can be implemented, for example, with any material having suitable dry-etch selectivity with respect to the exposed other materials (i.e., dummy oxide/gate dielectric, GTG isolation material, and the polysilicon). Specifically, the dry-etch will anisotropically remove the lateral (horizontal) portions of the passivation layer and mostly not remove the longitudinal (vertical) portions of the passivation layer and the underlying or otherwise exposed other materials. In some embodiments having silicon dioxide for the GTG isolation layer and the dummy oxide (gate dielectric), the passivation layer can be, for example, a film of silicon carbide, silicon nitride, or silicon oxynitride. Given the directional and selective nature of an anisotropic dry etch process, only passivation material on the sidewall remains, as shown in Figure 2e. Further note that the sidewalls of the remaining passivation material need not be perfectly orthogonal to the fins; rather, the sidewalls of the remaining passivation material can be somewhat slanted or otherwise flared outward toward the top of the fins. Further note that the polysilicon resistor remains below the GTG isolation.

[0031] As shown in Figure 2f, the methodology of this example embodiment continues with depositing polysilicon for the dummy gate over the structure, and then planarizing and patterning the polysilicon to form the gate polysilicon lines. As shown in Figure 2a, the polysilicon lines generally span across the fins in an orthogonal manner, with the gates being formed on at least the sides and possibly the top of a given fin to provide multi-gate devices such as double-gate and tri-gate FinFETs. In still other embodiments having a wire-based channel (nanowire or ribbon-based channel), the gate may be on all sides of the wire to provide a so-called gate-all- around configuration. Note that the GTG isolation and passivation combination effectively forms the gate-to-gate isolation between gate regions Gi and G₂ and between G₂ and G₃. With the dummy gate stack now fully formed, the source/drain regions can be formed as normally done. For instance, fin material in the source/drain regions adjacent the gates can be removed and replaced with epitaxial deposition of desired source/drain material (e.g., germanium or silicon germanium) and any doping (e.g., in situ doping or subsequent implantation/anneal based doping). Alternatively, the source/drain material can be native to the fins (no epi-deposition of source/drain materials needed). In such cases, an implantation doping/annealing scheme can be used to dope the source/drain regions as desired. The source/drain regions are generally depicted in Figure 2i. Once the source/drain regions are formed, the methodology further continues with a deposition and planarization of an interlayer dielectric material such as an oxide or other suitable fill material (e.g., silicon dioxide, porous silicon dioxide, or carbon-doped silicon dioxide, to name a few example interlayer dielectric materials). Such a interlayer dielectric material would effectively fill in the structure in between the gate lines shown in Figure 2i, and could be planarized down to the top of the gate stacks, as typically done.

[0032] As shown in Figure 2g, the methodology of this example embodiment continues with performing a remove metal gate (RMG) process, which replaces the dummy gate materials with the desired gate materials. So, for example, the polysilicon gate electrode is replaced by a desired metal stack. In some embodiments, the gate dielectric is also removed and replaced (before the gate electrode is provided), such as further shown in Figure 2g (in cross-hatch). For instance, a dummy gate dielectric of silicon dioxide (deposited in Figure 2b) can be removed (standard etch removal) and replaced with a high-k gate dielectric material. Example high-k dielectric gate dielectrics include, for example, hafnium oxide (or hafnia), hafnium silicate, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicate, tantalum oxide, tantalum silicate, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, aluminum silicate, lead scandium tantalum oxide, and lead zinc niobate, to name some examples. Typical metal deposition processes may be used to form the metal gate electrode, such as CVD, ALD, PVD, electroless plating, or electroplating. The metal gate electrode layer may include, for example, a p-type workfunction metal, such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. In some example configurations, two or more metal gate electrode layers may be deposited. For instance, a workfunction metal may be deposited in the gate trench followed by a suitable metal gate electrode fill metal such as aluminum or silver. In a more general sense, any suitable gate materials can be used to form the gate in the RMG process, as will be appreciated.

[0033] As shown in Figure 2h, the methodology of this example embodiment continues with defining and etching the contact regions for the various transistor(s) and polysilicon resistor(s). Once the contact trenches are formed, a contact metal deposition can be carried out as normally done to form a metal plug or contact structure within the trench. The contact structure may include just the metal plug, but other embodiments may include additional layers, such as one or more of an adhesion layer, a resistance-reducing metal layer, a workfunction metal layer, and a capping layer. Typical contact metal materials include aluminum, silver, gold, nickel, platinum, or titanium, although any suitably conductive contact metal or alloy can be provisioned using conventional deposition processes. An annealing process can then be carried out to form a silicide (or germanide, or other suitable anneal-based contact interface between a given metal contact and the underlying semiconductor). Any suitable contact metal fill, planarization, and polishing processes can be carried out as needed. Figure 2h further illustrates the vertical thickness of the various features, including the polysilicon resistors, according to an example embodiment. As previously explained, the vertical thickness of the resistors can be well controlled during the polysilicon deposition process shown in Figure 2b. The example embodiment shown in Figure 2i illustrates a top down view that shows two contact terminals for the given thin film polysilicon resistor. Further note the GTG isolation including the oxide/passivation structure in the fin free location to the left of the polysilicon resistor. A standard interconnect process can be followed to finish the routing.

Example System

[0034] Figure 4 illustrates a computing system implemented with one or more integrated circuit structures configured in accordance with an embodiment of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006 (two are shown in this example), each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board or a daughterboard mounted on a main board or the only board of system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures configured with polysilicon resistors as provided herein. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

[0035] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some such example embodiments of the present disclosure, the integrated circuit die of the processor 1004 may include transistor circuitry having one or more polysilicon resistors as provided herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0036] The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip 1006 includes one or more polysilicon resistors as provided herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

[0037] In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the system 1000 may be any other electronic device that processes data or employs integrated circuitry configured with polysilicon resistors as variously described herein. As will be appreciated in light of this disclosure, various embodiments of the present disclosure can be used to improve performance on products fabricated at any process node (e.g., in the micron range, or sub-micron and beyond) by allowing for the use of polysilicon resistors.

Further Example Embodiments

[0038] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0039] Example 1 is an integrated circuit device, comprising: a substrate having a plurality of semiconductor fins extending therefrom; a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction; and a polysilicon resistor between two of the fins and having a thickness in the parallel-to-fin direction that is greater than the gate line thickness.

[0040] Example 2 includes the subject matter of Example 1, wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch, and the resistor thickness is greater than the gate pitch.

[0041] Example 3 includes the subject matter of Example 1, wherein spacing between neighboring fins defines a fin pitch, and spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

[0042] Example 4 includes the subject matter of Example 3, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin cut region from which fins were removed.

[0043] Example 5 includes the subject matter of Example 3, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin free region where no fins were formed. Note that still other embodiments may include example 4 and 5 on a common substrate.

[0044] Example 6 includes the subject matter of any of Examples 1 through 5, wherein the polysilicon resistor has a vertical thickness that varies less than 10%.

[0045] Example 7 includes the subject matter of Example 6, wherein the vertical thickness varies less than 5%.

[0046] Example 8 includes the subject matter of Example 6 or 7, wherein the vertical thickness varies less than 2%. [0047] Example 9 includes the subject matter of any of Examples 1 through 8, wherein at least one of the fins includes a channel region under a corresponding one of the gate lines, the at least one fin further including source and drain regions adjacent the channel region.

[0048] Example 10 includes the subject matter of Example 6, further including source and drain contacts operatively coupled to the source and drain regions.

[0049] Example 1 1 includes the subject matter of any of Examples 1 through 10, further including first and second contacts operatively coupled to the polysilicon resistor.

[0050] Example 12 includes the subject matter of any of Examples 1 through 1 1 , wherein the polysilicon resistor is between at least two transistor gates, the device further comprising gate-to- gate isolation over the resistor and between the two transistor gates.

[0051] Example 13 includes the subject matter of Example 12, wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon.

[0052] Example 14 includes the subject matter of any of Examples 1 through 13, wherein at least some of the fins are native to the substrate.

[0053] Example 15 includes the subject matter of any of Examples 1 through 14, wherein at least some of the fins are replacement fins distinct from the substrate.

[0054] Example 16 includes the subject matter of any of Examples 1 through 15, wherein at least some of the fins comprise one or more nanowires.

[0055] Example 17 is an integrated circuit device, comprising: a substrate having a plurality of semiconductor fins extending therefrom, wherein spacing between neighboring fins defines a fin pitch; a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction, wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch; and a polysilicon resistor between two of the fins and having a thickness in the parallel-to-fin direction that is greater than the gate line thickness, wherein spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

[0056] Example 18 includes the subject matter of Example 17, wherein the resistor thickness is greater than the gate pitch.

[0057] Example 19 includes the subject matter of Example 17 or 18, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin cut region from which fins were removed. [0058] Example 20 includes the subject matter of Example 17 or 18, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin free region where no fins were formed. Note that still other embodiments may include example 19 and 20 on a common substrate.

[0059] Example 21 includes the subject matter of any of Examples 17 through 20, wherein the polysilicon resistor has a vertical thickness that varies less than 10%.

[0060] Example 22 includes the subject matter of Example 21, wherein the vertical thickness varies less than 5%.

[0061] Example 23 includes the subject matter of Example 21, wherein the vertical thickness varies less than 2%.

[0062] Example 24 includes the subject matter of any of Examples 17 through 23, wherein each fin includes at least one channel region under a corresponding one of the gate lines, each fin further including source and drain regions adjacent each channel region.

[0063] Example 25 includes the subject matter of Example 24, further comprising source and drain contacts operatively coupled to the source and drain regions.

[0064] Example 26 includes the subject matter of Example 24 or 25, further comprising first and second contacts operatively coupled to the polysilicon resistor.

[0065] Example 27 includes the subject matter of any of Examples 17 through 26, wherein the polysilicon resistor is between at least two transistor gates, the device further comprising gate-to- gate isolation over the resistor and between the two transistor gates.

[0066] Example 28 includes the subject matter of Example 27, wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon.

[0067] Example 29 includes the subject matter of any of Examples 17 through 28, wherein at least some of the fins are native to the substrate.

[0068] Example 30 includes the subject matter of any of Examples 17 through 29, wherein at least some of the fins are replacement fins distinct from the substrate.

[0069] Example 31 includes the subject matter of any of Examples 17 through 30, wherein at least some of the fins comprise one or more nanowires.

[0070] Example 32 is a method forming an integrated circuit device, the method comprising: providing a substrate having a plurality of semiconductor fins extending therefrom; providing a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction; and providing a polysilicon resistor between two of the fins, the resistor having a thickness in the parallel-to-fin direction that is greater than the gate line thickness.

[0071] Example 33 includes the subject matter of Example 32, wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch, and the resistor thickness is greater than the gate pitch.

[0072] Example 34 includes the subject matter of Example 32 or 33, wherein spacing between neighboring fins defines a fin pitch, and spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

[0073] Example 35 includes the subject matter of Example 34, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin cut region from which fins were removed.

[0074] Example 36 includes the subject matter of Example 34, wherein the spacing between the two fins having the polysilicon resistor therebetween is a fin free region where no fins were formed. Note that still other embodiments may include example 35 and 36 on a common substrate.

[0075] Example 37 includes the subject matter of any of Examples 32 through 36, wherein providing the polysilicon resistor between two of the fins is carried out prior to providing the plurality of gate lines over, and perpendicular to, the fins.

[0076] Example 38 includes the subject matter of Example 37, wherein the polysilicon resistor has a vertical thickness that varies less than 2%.

[0077] Example 39 includes the subject matter of any of Examples 32 through 38, wherein at least one of the fins includes a channel region under a corresponding one of the gate lines, the at least one fin further including source and drain regions adjacent the channel region, the method further comprising at least one of: providing source and drain contacts operatively coupled to the source and drain regions; and providing first and second contacts operatively coupled to the polysilicon resistor.

[0078] Example 40 includes the subject matter of any of Examples 32 through 39, wherein the polysilicon resistor is between at least two transistor gates, the method further comprising providing gate-to-gate isolation over the resistor and between the two transistor gates.

[0079] Example 41 includes the subject matter of Example 40, wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon, and wherein the etch scheme comprises a directional dry etch. [0080] Example 42 includes the subject matter of any of Examples 32 through 41 , wherein providing a substrate having the plurality of semiconductor fins comprises removing at least some fins to make room for the polysilicon resistor.

[0081] Example 43 includes the subject matter of any of Examples 32 through 42, wherein at least some of the fins are native to the substrate.

[0082] Example 44 includes the subject matter of any of Examples 32 through 43, wherein at least some of the fins are replacement fins distinct from the substrate.

[0083] Example 45 includes the subject matter of any of Examples 32 through 44, wherein at least some of the fins comprise one or more nanowires.

[0084] Example 46 includes the subject matter of any of Examples 1 through 45, wherein the integrated circuit device is part of a processor or a communication chip or chip set.

[0085] Example 47 includes the subject matter of any of Examples 1 through 46, wherein the integrated circuit device is part of a computing system, such as a laptop, desktop, smartphone, tablet, or other computing system.

[0086] The foregoing description of example embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.

Claims

CLAIMS What is claimed is:

1. An integrated circuit device, comprising:

a substrate having a plurality of semiconductor fins extending therefrom;

a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction; and

a polysilicon resistor between two of the fins and having a thickness in the parallel-to-fin direction that is greater than the gate line thickness.

2. The device of claim 1 wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch, and the resistor thickness is greater than the gate pitch.

3. The device of claim 1 wherein spacing between neighboring fins defines a fin pitch, and spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

4. The device of claim 1 wherein at least one of the fins includes a channel region under a corresponding one of the gate lines, the at least one fin further including source and drain regions adjacent the channel region, the device further comprising source and drain contacts operatively coupled to the source and drain regions.

5. The device of claim 1 , further comprising first and second contacts operatively coupled to the polysilicon resistor.

6. The device of any of claims 1 through 5 wherein the polysilicon resistor is between at least two transistor gates, the device further comprising gate-to-gate isolation over the resistor and between the two transistor gates.

7. The device of claim 6 wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon.

8. The device of claim 1 wherein at least some of the fins are replacement fins distinct from the substrate.

9. The device of claim 1 wherein at least some of the fins comprise one or more nanowires.

10. An integrated circuit device, comprising:

a substrate having a plurality of semiconductor fins extending therefrom, wherein spacing between neighboring fins defines a fin pitch;

a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction, wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch; and a polysilicon resistor between two of the fins and having a thickness in the parallel-to-fin direction that is greater than the gate line thickness, wherein spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

1 1. The device of claim 10 wherein the resistor thickness is greater than the gate pitch.

12. The device of claim 10 wherein each fin includes at least one channel region under a corresponding one of the gate lines, each fin further including source and drain regions adjacent each channel region, the device further comprising source and drain contacts operatively coupled to the source and drain regions.

13. The device of claim 12, further comprising first and second contacts operatively coupled to the polysilicon resistor.

14. The device of any of claims 10 through 13 wherein the polysilicon resistor is between at least two transistor gates, the device further comprising gate-to- gate isolation over the resistor and between the two transistor gates.

15. The device of claim 14 wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon.

16. The device of claim 10 wherein at least some of the fins are replacement fins distinct from the substrate.

17. The device of claim 10 wherein at least some of the fins comprise one or more nanowires.

18. A method forming an integrated circuit device, the method comprising: providing a substrate having a plurality of semiconductor fins extending therefrom;

providing a plurality of gate lines over, and perpendicular to, the fins, each gate line having a thickness in a parallel-to-fin direction; and

providing a polysilicon resistor between two of the fins, the resistor having a thickness in the parallel-to-fin direction that is greater than the gate line thickness.

19. The method of claim 18 wherein the gate line thickness defines a critical dimension of each gate line, and the gate lines are spaced from one another based on a gate pitch, and the resistor thickness is greater than the gate pitch.

20. The method of claim 18 wherein spacing between neighboring fins defines a fin pitch, and spacing between the two fins having the polysilicon resistor therebetween is at least two times greater than the fin pitch.

21. The method of claim 18 wherein providing the polysilicon resistor between two of the fins is carried out prior to providing the plurality of gate lines over, and perpendicular to, the fins.

22. The method of claim 18 wherein at least one of the fins includes a channel region under a corresponding one of the gate lines, the at least one fin further including source and drain regions adjacent the channel region, the method further comprising at least one of:

providing source and drain contacts operatively coupled to the source and drain regions; and

22

\ providing first and second contacts operatively coupled to the polysilicon resistor.

23. The method of any of claims 18 through 22 wherein the polysilicon resistor is between at least two transistor gates, the method further comprising providing gate-to-gate isolation over the resistor and between the two transistor gates.

24. The method of claim 23 wherein the gate-to-gate isolation comprises a material that is etch selective with respect to polysilicon, such that the material is removable by a given etch scheme at a rate faster than that etch scheme can remove polysilicon, and wherein the etch scheme comprises a directional dry etch.

25. The method of claim 23 wherein providing a substrate having the plurality of semiconductor fins comprises removing at least some fins to make room for the polysilicon resistor.