WO2017105029A1 - Method for manufacturing superconductive wire material having superconductive strips self-aligned by metal substrate defect - Google Patents

Method for manufacturing superconductive wire material having superconductive strips self-aligned by metal substrate defect Download PDF

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WO2017105029A1
WO2017105029A1 PCT/KR2016/014301 KR2016014301W WO2017105029A1 WO 2017105029 A1 WO2017105029 A1 WO 2017105029A1 KR 2016014301 W KR2016014301 W KR 2016014301W WO 2017105029 A1 WO2017105029 A1 WO 2017105029A1
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region
superconducting
metal substrate
layer
surface roughness
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PCT/KR2016/014301
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French (fr)
Korean (ko)
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고락길
김석환
조영식
하동우
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한국전기연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H01B12/02—Superconductive or hyperconductive conductors, cables, or transmission lines characterised by their form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment

Definitions

  • the present invention relates to a superconducting wire, and more particularly to a high temperature superconducting wire consisting of a plurality of superconducting strips.
  • Superconductors have zero resistance at DC current, but in an alternating current environment AC losses inversely proportional to the width of the filaments occur. In particular, the ratio of the thickness to the width of the HTS shows a very high hysteresis loss in the high state.
  • the tape-shaped superconducting wire is composed of a plurality of superconducting layer strips (or filaments) therein, for example, Korean Patent Laid-Open No. 10-2013-29801 has a superconducting strip extending in the longitudinal direction therebetween.
  • a superconductor having a structure separated by an insulating strip is disclosed. The above patent discloses that a plurality of superconducting strips uses a photolithography process such as a mask to implement a superconducting strip stripping structure, and cannot be a suitable method for manufacturing a continuous wire.
  • an object of the present invention is to provide a method for producing a superconducting wire to minimize the damage of the material constituting the wire for the stripping of the superconducting layer.
  • the present invention includes the steps of introducing a plurality of defect regions having a second roughness larger than the first surface roughness on a metal substrate having a first surface roughness; Forming a buffer layer on the metal substrate on which the defect region is formed; And providing a superconducting layer on the substrate on which the buffer layer is formed.
  • the present invention includes the steps of introducing a plurality of defect regions having a second roughness greater than the first surface roughness in the buffer layer having a first surface roughness on the metal substrate; And forming a superconducting layer on the buffer layer in which the defect region is formed.
  • the defect area may include a groove or a scratch.
  • at least two rows of defect regions may be formed in the longitudinal direction of the superconducting wire.
  • the defect region may extend intermittently or continuously in the longitudinal direction of the metal substrate.
  • the defect area may be laser machined or machined.
  • the lattice structure of the superconducting material layer is self-aligned in a direction perpendicular to the defect area.
  • the introducing of the plurality of defect regions may include providing a metal substrate polished to have a first surface roughness; And forming a defective area of a second surface roughness on the substrate.
  • the second surface roughness is preferably an average roughness of 2nm or more within 5 ⁇ m x 5 ⁇ m.
  • a superconducting wire in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are stacked, wherein at least a portion of the metal substrate has a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod, and the buffer layer is formed to cover the first region and the second region.
  • the buffer layer on the first region and the second region provides a superconducting wire, characterized in that they have different orientations.
  • the present invention also provides a superconducting wire in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are stacked, wherein at least a portion of the metal substrate includes: a first region having a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod, and below a critical temperature, the layer of superconducting material on the first region has superconductivity, The material layer on the second region provides a superconducting wire, characterized in that it does not have superconductivity.
  • a superconducting wire rod composed of a superconducting strip self-aligned to the defect and artificially forming a defect relating to surface roughness on the metal substrate. Accordingly, it is possible to provide a superconducting wire composed of a plurality of superconducting strips in a simple manufacturing process.
  • the damage of the buffer layer does not occur. Therefore, the buffer layer existing under each superconducting layer strip serves as a diffusion barrier layer.
  • the superconducting wire produced according to the method of the present invention is composed of a plurality of superconducting layer strips to provide a self-protection function for the quench.
  • FIG. 1 is a view schematically showing a cross section of a metal substrate of a superconducting wire according to an embodiment of the present invention.
  • FIG. 2 is a plan view of the metal substrate of FIG. 1.
  • FIG 3 is a schematic cross-sectional view of a metal substrate according to another embodiment of the present invention.
  • FIG. 4 is a plan view of a metal substrate according to another embodiment of the present invention.
  • 5 to 7 are cross-sectional views schematically showing the cross-section of the superconducting wire step by step according to the manufacturing example of the superconducting wire of the present invention.
  • FIG. 8 is a procedure diagram schematically showing a manufacturing procedure of the superconducting wire of the present invention.
  • FIG. 9 is a view schematically showing a cross-sectional structure of the base material according to another embodiment of the present invention.
  • Figure 1 is a view schematically showing a cross section of a metal substrate of a superconducting wire according to an embodiment of the present invention
  • Figure 2 is a plan view.
  • Metal substrates for the formation of superconducting layers should be surface polished with very high precision.
  • the surface roughness of the superconducting substrate directly affects the texturing of the buffer layer.
  • the superconducting material formed on the untextured buffer layer is difficult to have a crystal structure of the required biaxial orientation, and does not function as a superconducting layer.
  • the production process of the second generation high temperature superconducting thin film such as YBCO can be largely divided into a template process consisting of a biaxially oriented oxide film on a metal substrate and a process of coating a YBCO layer, which is a superconductor.
  • the template process is biaxially oriented oxide film by PVD method such as IBAD (Ion-Beam Assisted Deposition) or ISD (Inclined Substrate Deposition) on a stainless steel or Hastelloy alloy substrate with disordered crystal orientation. It is carried out by the method of orienting and depositing.
  • PVD method such as IBAD (Ion-Beam Assisted Deposition) or ISD (Inclined Substrate Deposition) on a stainless steel or Hastelloy alloy substrate with disordered crystal orientation. It is carried out by the method of orienting and depositing.
  • a template in which a buffer layer of several layers is additionally added is used, and the YBCO superconductor layer is formed on the template by PLD, MOD, MOCVD, Is deposited.
  • the substrate is, for example, a substrate such as Ni alloy, Hastelloy, stainless steel is polished to have a first surface roughness.
  • the substrate is electropolished to obtain the first surface roughness.
  • the first surface roughness preferably maintains an average surface roughness Ra in a 5 ⁇ m ⁇ 5 ⁇ m region at 2.0 nm.
  • the particle size of the particles constituting the substrate can be appropriately controlled.
  • a defect region having a higher surface roughness is introduced into the upper surface of the metal substrate surface-treated with the first surface roughness.
  • the defect area 112 on the metal substrate 110 may be provided in the form of a groove or a scratch having a predetermined depth with respect to a surface thereof.
  • the defect area 112 extends in the longitudinal direction of the superconducting wire.
  • the width and depth of the groove can be designed so that the defect area has an appropriate surface roughness.
  • the depth of the groove is preferably in the range of 1nm ⁇ 500nm and the width of the groove is 10 ⁇ m ⁇ 200 ⁇ m It is preferable to be in a range.
  • the defect area may be implemented by one or more grooves.
  • the defect area 112 may be formed by optical means such as a laser or mechanical means such as a knife or a blade.
  • optical means such as a laser or mechanical means such as a knife or a blade.
  • mechanical means such as a knife or a blade.
  • Various other methods of forming grooves or scratches that are not mentioned may be introduced in this embodiment.
  • the artificially introduced defect region 112 such as a scratch form, has a higher surface roughness than other regions of the metal substrate surface. Accordingly, the buffer layer on the metal substrate polished with high precision forms an epitaxial structure having a high degree of orientation, whereas the buffer layer formed on the defect area cannot have a biaxially oriented structure and is formed on the buffer layer. The superconducting layer to be obtained also cannot have a biaxially oriented structure.
  • FIG. 4 is a plan view of a metal substrate of a superconducting wire according to another embodiment of the present invention.
  • the defective region 112 is intermittently formed in the length direction of the metal substrate.
  • the defect area 112 may be designed in various shapes such as a rectangle or a circle.
  • FIG. 5 to 7 are cross-sectional views schematically showing a process of implementing a superconducting wire on a metal substrate shown in FIG. 1 as an example of manufacturing a superconducting wire according to an embodiment of the present invention.
  • a buffer layer 120 is formed on the metal substrate.
  • the buffer layer 120A formed at the portion corresponding to the defect area does not have a biaxially oriented texture unlike the buffer layer material formed on the smooth surface.
  • the buffer layers 120 and 120A are continuously formed in a plane on the metal substrate. Accordingly, the buffer layers 120 and 120A may function as a diffusion barrier for the superconducting material layer in addition to determining the lattice structure of the superconducting material layers 130 and 130A.
  • the buffer layer 120A may include a plurality of layer structures.
  • the buffer layer may include a barrier layer, a seed layer, an IBAD template, a homogeneous epibuffer layer, and a lattice alignment buffer layer.
  • the buffer layer may have a laminated structure of yttrium oxide (Y 2 O 3 ) / magnesia (MgO) / lanthanum manganate (LaMnO 3 ) or ceria (CeO 2 ), or alumina (Al 2 O 3 ) / yttrium oxide (Y 2).
  • the buffer layer may be formed by a known thin film deposition method such as electron beam deposition or sputtering.
  • the thickness of the buffer layer may vary, and for example, the buffer layer may have a thickness of 100 nm.
  • a superconducting layer 130 is formed on the metal substrate on which the buffer layer 120 is formed.
  • the superconducting layer 130 may be a ReBCO (ReBa 2 Cu 3 O 7 , wherein Re is at least one of metallic elements consisting of Nd, Sm, Eu, Gd, Dy, Ho, and Y) high temperature superconducting material. have.
  • a layer of superconducting material is also laminated on the portion corresponding to the defect area.
  • the superconducting material layer 130 formed on the smooth portion has a crystal structure that matches the buffer layer and functions as a superconducting layer below the critical temperature
  • the superconducting material layer 130A formed on the portion corresponding to the defect region is biaxially oriented. And therefore do not function as a superconducting layer below the critical temperature.
  • the superconducting material layer having superconductivity and the superconducting material layer having different lattice structures derived from defects of the metal substrate can be arranged in parallel in the longitudinal direction of the wire rod on the same plane. Also, in the present invention, whether the superconducting material layer functions as a superconducting layer is determined according to the lattice orientation of the buffer layer due to the substrate defects and the substrate defects. That is, in the present invention, the superconducting layer may be self-aligned with respect to the defect area of the metal substrate.
  • the superconducting wire of the present invention can exhibit the same electromagnetic characteristics as a plurality of superconducting strips are connected in parallel.
  • the stabilization layer 140 is formed on the metal substrate 110 on which the superconducting layer 130 is formed, thereby completing the manufacture of the superconducting wire.
  • the stabilization layer 140 may be formed of a precious metal material such as gold or silver or a material having high electrical conductivity.
  • the stabilization layer may be formed by a conventional method such as electroplating, electroless plating.
  • FIG. 8 is a procedure diagram schematically showing an example of a manufacturing procedure of the superconducting wire of the present invention.
  • the metal substrate is polished to an average roughness of a required level (S110). Subsequently, a defect region is formed on the metal substrate in parallel in the longitudinal direction of the wire rod (S120).
  • the defect area may extend continuously or intermittently along the longitudinal direction of the wire rod. As described above, the defect area may be implemented by a groove or a scratch.
  • a buffer layer is formed on the metal substrate (S120).
  • the buffer layer may be formed of multiple layers of various materials in consideration of diffusion barriers, lattice matching, and the like.
  • a superconducting material layer is formed on the buffer layer (S130).
  • the formed superconducting material layer has a different lattice structure corresponding to the defect area of the lower metal substrate.
  • the superconducting material layer formed on the defect region does not have a biaxially oriented crystal structure, and thus does not have superconductivity in the superconducting environment under the critical temperature, the critical magnetic field, and the critical current.
  • the superconducting wire is manufactured by forming a stabilization layer on the superconducting material layer S130 (S140).
  • a stabilization layer may be additionally formed or another laminate structure may be added.
  • FIG. 9 is a schematic cross-sectional view of a superconducting wire in another embodiment of the present invention.
  • a buffer layer 120 is formed on the metal substrate 110.
  • the metal substrate 110 is surface-treated with a first surface roughness.
  • a defect region is introduced into the buffer layer 120 above the metal substrate.
  • the defect area 122 on the buffer layer 120 may be provided in the form of a groove or a scratch having a predetermined depth with respect to the surface.
  • the defect area 122 may extend in the longitudinal direction of the superconducting wire.
  • the superconducting layer is formed on the base material having the cross-sectional structure of FIG. 9, a layer of the superconducting material is also laminated on the portion corresponding to the defect area.
  • the superconducting material layer formed on the smooth portion has a crystal structure that matches the buffer layer and functions as a superconducting layer below the critical temperature
  • the superconducting material layer formed on the portion corresponding to the defect area does not have a biaxial orientation and thus is critical It will not function as a superconducting layer below the temperature.
  • the present invention is applicable to superconducting wire application parts such as superconducting wire and superconducting coil.

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Abstract

Provided is a method for manufacturing a superconductive wire material having superconductive strips self-aligned by a metal substrate defect. The present invention provides a method for manufacturing a superconductive wire material, comprising the steps of: introducing a plurality of defect areas on a metal substrate having a first surface roughness, the defect areas having a second surface roughness that is larger than the first surface roughness; forming a buffer layer on the metal substrate on which the defect areas are formed; and forming a superconductive layer on the substrate on which the buffer layer is formed. According to the present invention, it is possible to provide a superconductive wire material comprising a plurality of superconductive strips through a simple manufacturing process.

Description

금속기판 결함에 의해 자기 정렬된 초전도 스트립을 구비하는 초전도 선재의 제조 방법Manufacturing method of superconducting wire having superconducting strip self-aligned by metal substrate defect
본 발명은 초전도 선재에 관한 것으로, 보다 상세하게는 복수의 초전도 스트립으로 구성되는 고온 초전도 선재에 관한 것이다.The present invention relates to a superconducting wire, and more particularly to a high temperature superconducting wire consisting of a plurality of superconducting strips.
초전도체는 DC 전류에서 저항 값이 영(zero)이지만, 교류 전류 환경에서는 필라멘트의 폭에 반비례하는 AC 손실이 발생한다. 특히, HTS의 폭에 대하여 두께의 비율은 높은 상태에서는 매우 높은 히스테리시스 손실을 나타난다. Superconductors have zero resistance at DC current, but in an alternating current environment AC losses inversely proportional to the width of the filaments occur. In particular, the ratio of the thickness to the width of the HTS shows a very high hysteresis loss in the high state.
초전도 선재가 다수의 필라멘트형 초전도 구조로 이루어지는 경우 AC 손실을 감소하는 구조를 이룰 수 있다는 것이 알려져 있다. 이러한 테이프 형태의 초전도 선재는 내부에 복수의 초전도층 스트립(또는 필라멘트)으로 구성되는데, 예를 들어, 한국공개특허 10-2013-29801호는 길이 방향으로 연장되는 서로 인접하는 초전도 스트립이 그 사이의 절연 스트립에 의하여 분리된 구조의 초전도체를 개시하고 있다. 상기 공개특허는 복수의 초전도 스트립은 초전도층 스트립 분리 구조를 구현하기 위하여 마스크와 같은 포토 리소그래피 공정을 이용하며, 실제 연속적인 선재를 제조하는 데에 적합한 방식이 될 수 없다.It is known that if the superconducting wire is made of a plurality of filamentary superconducting structures, the structure can reduce the AC loss. The tape-shaped superconducting wire is composed of a plurality of superconducting layer strips (or filaments) therein, for example, Korean Patent Laid-Open No. 10-2013-29801 has a superconducting strip extending in the longitudinal direction therebetween. A superconductor having a structure separated by an insulating strip is disclosed. The above patent discloses that a plurality of superconducting strips uses a photolithography process such as a mask to implement a superconducting strip stripping structure, and cannot be a suitable method for manufacturing a continuous wire.
그 밖에 종래 초전도층 스트립을 세분화하기 위하여 초전도층을 물리적이나 화학적으로 분리하는 방식이 적용되기도 하는데, 이러한 방식들 또한 초전도층이나 버퍼층의 손상이 초래된다는 문제점을 갖는다.In addition, in order to subdivide the conventional superconducting layer strip, a method of physically or chemically separating the superconducting layer may be applied. Such methods also have a problem that damage to the superconducting layer or the buffer layer is caused.
상기 종래 기술의 문제점을 해결하기 위하여, 본 발명은 복수의 초전도 스트립으로 구성되는 초전도 선재의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the problems of the prior art, it is an object of the present invention to provide a method for manufacturing a superconducting wire consisting of a plurality of superconducting strips.
또한, 본 발명은 초전도층의 스트립화를 위하여 선재를 구성하는 물질의 손상을 최소화하는 초전도 선재의 제조 방법을 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide a method for producing a superconducting wire to minimize the damage of the material constituting the wire for the stripping of the superconducting layer.
또한 본 발명은 퀀치 현상으로부터 자기 보호 가능한 초전도 선재를 제공하는 것을 목적으로 한다.It is another object of the present invention to provide a superconducting wire which can be self-protected from a quench phenomenon.
상기 기술적 과제를 달성하기 위하여 본 발명은, 제1 표면 거칠기를 갖는 금속기판 상에 상기 제1 표면 거칠기보다 큰 제2 거칠기를 갖는 복수의 결함 영역을 도입하는 단계; 상기 결함 영역이 형성된 금속기판 상에 버퍼층을 형성하는 단계; 및 상기 버퍼층이 형성된 기판 상에 초전도층을 형성하는 단계를 포함하는 초전도 선재의 제조 방법을 제공한다. In order to achieve the above technical problem, the present invention includes the steps of introducing a plurality of defect regions having a second roughness larger than the first surface roughness on a metal substrate having a first surface roughness; Forming a buffer layer on the metal substrate on which the defect region is formed; And providing a superconducting layer on the substrate on which the buffer layer is formed.
또한 본 발명은 금속기판 상의 제1 표면 거칠기를 갖는 버퍼층에 상기 제1 표면 거칠기보다 큰 제2 거칠기를 갖는 복수의 결함 영역을 도입하는 단계; 및 상기 결함 영역이 형성된 버퍼층 상에 초전도층을 형성하는 단계를 포함하는 초전도 선재의 제조 방법을 제공한다. In addition, the present invention includes the steps of introducing a plurality of defect regions having a second roughness greater than the first surface roughness in the buffer layer having a first surface roughness on the metal substrate; And forming a superconducting layer on the buffer layer in which the defect region is formed.
본 발명에서 상기 결함 영역은, 홈 또는 스크래치를 포함할 수 있다. 또한, 상기 초전도 선재의 길이 방향으로 최소한 2열 이상의 결함 영역이 형성될 수도 있다.In the present invention, the defect area may include a groove or a scratch. In addition, at least two rows of defect regions may be formed in the longitudinal direction of the superconducting wire.
본 발명에서 상기 결함 영역은 상기 금속기판의 길이 방향으로 단속적 또는 연속적으로 연장될 수 있다. In the present invention, the defect region may extend intermittently or continuously in the longitudinal direction of the metal substrate.
본 발명에서 상기 결함 영역은 레이저 가공되거나 기계 가공될 수 있다. In the present invention, the defect area may be laser machined or machined.
또한, 본 발명에서 상기 초전도 물질층의 격자 구조는 상기 결함 영역에 대하여 수직 방향으로 자기 정렬된다. Further, in the present invention, the lattice structure of the superconducting material layer is self-aligned in a direction perpendicular to the defect area.
본 발명에서 상기 복수의 결함 영역 도입 단계는, 제1 표면 거칠기를 갖도록 연마된 금속기판을 제공하는 단계; 및 상기 기판에 제2 표면 거칠기의 결함 영역을 형성하는 단계를 포함할 수 있다. In the present invention, the introducing of the plurality of defect regions may include providing a metal substrate polished to have a first surface roughness; And forming a defective area of a second surface roughness on the substrate.
또한, 본 발명에서 상기 제2 표면 거칠기는 평균 거칠기가 5㎛ x 5㎛ 내에서 2nm 이상인 것이 바람직하다. Further, in the present invention, the second surface roughness is preferably an average roughness of 2nm or more within 5㎛ x 5㎛.
상기 다른 기술적 과제를 달성하기 위하여 본 발명은 금속기판, 버퍼층, 초전도 물질층 및 안정화층이 적층된 초전도 선재에 있어서, 상기 금속기판의 최소한 일부는 제1 표면 거칠기를 갖는 제1 영역; 및 제2 표면 거칠기를 갖는 제2 영역을 구비하고, 상기 제1 영역 및 제2 영역은 선재의 길이 방향으로 연장되며, 상기 버퍼층은 상기 제1 영역 및 제2 영역을 덮도록 형성되며, 상기 제1 영역 및 제2 영역 상의 버퍼층은 서로 다른 배향을 갖는 것을 특징으로 하는 초전도 선재를 제공한다. According to an aspect of the present invention, there is provided a superconducting wire in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are stacked, wherein at least a portion of the metal substrate has a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod, and the buffer layer is formed to cover the first region and the second region. The buffer layer on the first region and the second region provides a superconducting wire, characterized in that they have different orientations.
또한, 본 발명은 금속기판, 버퍼층, 초전도 물질층 및 안정화층이 적층된 초전도 선재에 있어서, 상기 금속기판의 최소한 일부는 제1 표면 거칠기를 갖는 제1 영역; 및 제2 표면 거칠기를 갖는 제2 영역을 구비하고, 상기 제1 영역 및 제2 영역은 선재의 길이 방향으로 연장되며, 임계 온도 이하에서 상기 제1 영역 상의 초전도 물질층은 초전도성을 구비하는 반면, 상기 제2 영역 상의 물질층은 초전도성을 구비하지 않는 것을 특징으로 하는 초전도 선재를 제공한다.The present invention also provides a superconducting wire in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are stacked, wherein at least a portion of the metal substrate includes: a first region having a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod, and below a critical temperature, the layer of superconducting material on the first region has superconductivity, The material layer on the second region provides a superconducting wire, characterized in that it does not have superconductivity.
본 발명에 따르면, 금속기판에 인위적으로 표면 거칠기에 관한 결함을 형성하고, 상기 결함에 대하여 자기 정렬된 초전도 스트립으로 구성되는 초전도 선재를 제공할 수 있게 된다. 이에 따라, 간단한 제조 공정으로 복수의 초전도 스트립으로 구성되는 초전도 선재의 제공이 가능하다. According to the present invention, it is possible to provide a superconducting wire rod composed of a superconducting strip self-aligned to the defect and artificially forming a defect relating to surface roughness on the metal substrate. Accordingly, it is possible to provide a superconducting wire composed of a plurality of superconducting strips in a simple manufacturing process.
또한 본 발명의 초전도 선재의 제조 방법에 따르면 버퍼층의 손상이 발생하지 않는다. 따라서, 각 초전도층 스트립의 하부에 존재하는 버퍼층은 확산 장벽층(Diffusion Barrier)로서 기능하게 된다.In addition, according to the manufacturing method of the superconducting wire of the present invention, the damage of the buffer layer does not occur. Therefore, the buffer layer existing under each superconducting layer strip serves as a diffusion barrier layer.
또한, 본 발명의 방법에 따라 제조된 초전도 선재는 복수의 초전도층 스트립으로 구성되어 있어 퀀치 등에 대해 자기 보호 기능을 구비하게 된다.In addition, the superconducting wire produced according to the method of the present invention is composed of a plurality of superconducting layer strips to provide a self-protection function for the quench.
도 1은 본 발명의 일실시예에 따른 초전도 선재의 금속기판의 단면을 개략적으로 도시한 도면이다.1 is a view schematically showing a cross section of a metal substrate of a superconducting wire according to an embodiment of the present invention.
도 2는 도 1의 금속기판의 평면도이다. FIG. 2 is a plan view of the metal substrate of FIG. 1.
도 3은 본 발명의 다른 실시예에 따른 금속기판의 단면을 개략적으로 도시한 도면이다. 3 is a schematic cross-sectional view of a metal substrate according to another embodiment of the present invention.
도 4는 본 발명의 다른 실시예에 따른 금속기판의 평면도이다. 4 is a plan view of a metal substrate according to another embodiment of the present invention.
도 5 내지 도 7은 본 발명의 초전도 선재의 제조예에 따라 단계별로 초전도 선재의 단면을 모식적으로 도시한 단면도이다. 5 to 7 are cross-sectional views schematically showing the cross-section of the superconducting wire step by step according to the manufacturing example of the superconducting wire of the present invention.
도 8은 본 발명의 초전도 선재의 제조 절차를 모식적으로 도시한 절차도이다.8 is a procedure diagram schematically showing a manufacturing procedure of the superconducting wire of the present invention.
도 9는 본 발명의 다른 실시예에 따른 모재의 단면 구조를 개략적으로 도시한 도면이다.9 is a view schematically showing a cross-sectional structure of the base material according to another embodiment of the present invention.
이하 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 일실시예에 따른 초전도 선재의 금속기판의 단면을 개략적으로 도시한 도면이고, 도 2는 평면도이다. 1 is a view schematically showing a cross section of a metal substrate of a superconducting wire according to an embodiment of the present invention, Figure 2 is a plan view.
초전도층의 형성을 위한 금속기판은 매우 높은 정밀도로 표면 연마되어야 한다. 상기 초전도 기판은 표면 거칠기는 버퍼층의 텍스쳐링에 직접적으로 영향을 미친다. 또한, 텍스쳐되지 않는 버퍼층 상에 형성되는 초전도 물질은 요구되는 2축 배향의 결정구조를 구비하기 어려우며, 초전도층으로 기능하지 않게 된다.Metal substrates for the formation of superconducting layers should be surface polished with very high precision. The surface roughness of the superconducting substrate directly affects the texturing of the buffer layer. In addition, the superconducting material formed on the untextured buffer layer is difficult to have a crystal structure of the required biaxial orientation, and does not function as a superconducting layer.
2세대 고온 초전도 박막 예컨대 YBCO의 제조공정은 크게 금속기판 상에 2축 배향된 산화물막으로 이루어지는 템플릿 공정과 초전도체인 YBCO층을 입히는 공정으로 나눌 수 있다. The production process of the second generation high temperature superconducting thin film such as YBCO can be largely divided into a template process consisting of a biaxially oriented oxide film on a metal substrate and a process of coating a YBCO layer, which is a superconductor.
여기서, 템플릿 공정은 결정 배향이 무질서한 스테인레스 스틸이나 하스텔로이 합금 기판 위에 주로 IBAD(Ion-Beam Assisted Deposition, 이온빔 보조증착법)나 ISD(Inclined Substrate Deposition, 기판경사 증착법)와 같은 PVD 법으로 산화물막을 2축으로 배향시켜서 증착하는 방법으로 수행된다. 이 때, 초전도체층과의 확산 방지나 격자 불일치(lattice mismatch)를 해소하기 위하여 여러 층의 완충층을 추가로 입인 템플릿이 사용되며, 상기 템플릿 상에 YBCO 초전도층은 PLD, MOD, MOCVD 등의 방법으로 증착된다. Here, the template process is biaxially oriented oxide film by PVD method such as IBAD (Ion-Beam Assisted Deposition) or ISD (Inclined Substrate Deposition) on a stainless steel or Hastelloy alloy substrate with disordered crystal orientation. It is carried out by the method of orienting and depositing. In this case, in order to prevent diffusion with the superconductor layer or to solve lattice mismatch, a template in which a buffer layer of several layers is additionally added is used, and the YBCO superconductor layer is formed on the template by PLD, MOD, MOCVD, Is deposited.
본 발명에서 상기 기판은 예컨대, Ni 합금, 하스텔로이, 스테인레스 스틸 등의 기판은 제1 표면 거칠기를 갖도록 연마된다. 예시적으로 상기 제1 표면 거칠기를 얻기 위해 상기 기판은 전해 연마된다. 본 발명에서 상기 제1 표면 거칠기는 5㎛ x 5㎛ 영역 안에서의 평균 표면 거칠기(Ra)가 2.0nm로 유지되는 것이 바람직하다. 이를 위하여 부가적으로 상기 기판을 구성하는 입자의 입도가 적절히 제어될 수 있다. In the present invention, the substrate is, for example, a substrate such as Ni alloy, Hastelloy, stainless steel is polished to have a first surface roughness. By way of example, the substrate is electropolished to obtain the first surface roughness. In the present invention, the first surface roughness preferably maintains an average surface roughness Ra in a 5 μm × 5 μm region at 2.0 nm. To this end, additionally, the particle size of the particles constituting the substrate can be appropriately controlled.
본 발명의 일실시예에 따르면, 제1 표면 거칠기로 표면 가공된 상기 금속기판의 상부 표면에 이보다 높은 표면 거칠기를 갖는 결함 영역이 도입된다. 도 1 및 도 2에 도시된 바와 같이, 상기 금속기판(110) 상의 상기 결함 영역(112)은 표면에 대하여 소정 깊이를 갖는 홈 또는 스크래치 형태로 제공될 수 있다. 도시된 바와 같이 상기 결함 영역(112)은 초전도 선재의 길이 방향으로 연장된다. 본 발명에서 결함 영역이 적절한 표면 거칠기를 갖도록 홈의 폭 및 깊이가 설계될 수 있다. 예컨대, 상기 홈의 깊이는 1nm ~ 500nm 범위에 있는 것이 바람직하고 상기 홈의 폭은 10㎛ ~ 200 ㎛ 범위에 있는 것이 바람직하다. According to one embodiment of the present invention, a defect region having a higher surface roughness is introduced into the upper surface of the metal substrate surface-treated with the first surface roughness. As shown in FIGS. 1 and 2, the defect area 112 on the metal substrate 110 may be provided in the form of a groove or a scratch having a predetermined depth with respect to a surface thereof. As shown, the defect area 112 extends in the longitudinal direction of the superconducting wire. In the present invention, the width and depth of the groove can be designed so that the defect area has an appropriate surface roughness. For example, the depth of the groove is preferably in the range of 1nm ~ 500nm and the width of the groove is 10㎛ ~ 200㎛ It is preferable to be in a range.
한편, 도 3에 도시된 바와 같이, 본 발명에서 상기 결함 영역은 하나 이상의 홈에 의해 구현될 수도 있다. On the other hand, as shown in Figure 3, in the present invention, the defect area may be implemented by one or more grooves.
본 발명에서 상기 결함 영역(112)은 레이저와 같은 광학적 수단 또는 나이프나 블레이드와 같은 기계적 수단에 의해 형성될 수 있다. 기타 언급되지 않은 다양한 방식의 홈 또는 스크래치 형성 방법이 본 실시예에서 도입될 수 있다. In the present invention, the defect area 112 may be formed by optical means such as a laser or mechanical means such as a knife or a blade. Various other methods of forming grooves or scratches that are not mentioned may be introduced in this embodiment.
홈 또는 스크래치 형태 같이 인위적으로 도입된 결함 영역(112)은 금속기판 표면의 다른 영역에 비해 높은 표면 거칠기를 갖는다. 이에 따라, 높은 정밀도로 연마된 금속기판 상의 버퍼층은 높은 배향도를 갖는 에피택셜 구조를 형성하는 반면, 상기 결함 영역 상에 형성되는 버퍼층은 2축 배향된 구조를 가질 수 없게 되고, 상기 버퍼층 상에 형성되는 초전도층 또한 2축 배향 구조를 가질 수 없게 된다. home Alternatively, the artificially introduced defect region 112, such as a scratch form, has a higher surface roughness than other regions of the metal substrate surface. Accordingly, the buffer layer on the metal substrate polished with high precision forms an epitaxial structure having a high degree of orientation, whereas the buffer layer formed on the defect area cannot have a biaxially oriented structure and is formed on the buffer layer. The superconducting layer to be obtained also cannot have a biaxially oriented structure.
도 4는 본 발명의 다른 실시예에 따른 초전도 선재의 금속기판에 대한 평면도이다. 4 is a plan view of a metal substrate of a superconducting wire according to another embodiment of the present invention.
도 4의 (a) 및 (b)를 참조하면, 도 1과는 달리 결함 영역(112)은 금속기판의 길이 방향으로 단속적으로 형성되어 있다. 또한 도시된 바와 같이, 상기 결함 영역(112)은 사각형 또는 원형 등 다양한 형상으로 설계될 수 있다. Referring to FIGS. 4A and 4B, unlike FIG. 1, the defective region 112 is intermittently formed in the length direction of the metal substrate. In addition, as illustrated, the defect area 112 may be designed in various shapes such as a rectangle or a circle.
도 5 내지 도 7은 본 발명의 일실시예에 따른 초전도 선재의 제조예로서 도 1에 도시된 금속기판 상에서 초전도 선재의 구현 과정을 모식적으로 도시한 단면도이다. 5 to 7 are cross-sectional views schematically showing a process of implementing a superconducting wire on a metal substrate shown in FIG. 1 as an example of manufacturing a superconducting wire according to an embodiment of the present invention.
도 5를 참조하면, 상기 금속기판 상에 버퍼층(120)이 형성된다. 상기 결함 영역에 대응하는 부위에 형성된 버퍼층(120A)은 매끈한 표면 상에 형성된 버퍼층 물질과는 달리 2축 배향된 텍스쳐를 갖지 않는다. 본 발명의 실시예에서 상기 버퍼층(120, 120A)은 상기 금속기판 상에 평면적으로 연속적으로 형성된다. 이에 따라 버퍼층(120, 120A)은 초전도 물질층(130, 130A)의 격자 구조를 결정하는 역할을 하는 이외에도 초전도 물질층에 대한 확산 장벽으로서 온전히 기능할 수 있게 된다. Referring to FIG. 5, a buffer layer 120 is formed on the metal substrate. The buffer layer 120A formed at the portion corresponding to the defect area does not have a biaxially oriented texture unlike the buffer layer material formed on the smooth surface. In the exemplary embodiment of the present invention, the buffer layers 120 and 120A are continuously formed in a plane on the metal substrate. Accordingly, the buffer layers 120 and 120A may function as a diffusion barrier for the superconducting material layer in addition to determining the lattice structure of the superconducting material layers 130 and 130A.
본 발명에서 상기 버퍼층(120A)은 복수의 층 구조를 포함할 수 있다. 예컨대, 상기 버퍼층은 장벽층(barrier layer), 시드층(seed layer), IBAD 템플릿, 균질에피버퍼층 및 격자맞춤버퍼층을 포함하여 구성될 수 있다. 예컨대, 상기 버퍼층은 산화이트륨(Y2O3) / 마그네시아(MgO) / 란타늄망가네이트(LaMnO3) 또는 세리아(CeO2)의 적층 구조나, 알루미나(Al2O3) / 산화이트륨(Y2O3) / 마그네시아(MgO) / 란타늄망가네이트(LaMnO3) 또는 세리아(CeO2)의 적층 구조를 가질 수 있다. 본 발명에서 상기 버퍼층은 공지의 박막 증착 방법 예컨대 전자빔 증착이나 스퍼터링에 의하여 형성될 수 있다. 또한, 본 발명에서 상기 버퍼층의 두께는 다양할 수 있으며, 예시적으로 상기 버퍼층은 100nm 두께를 가질 수 있다. In the present invention, the buffer layer 120A may include a plurality of layer structures. For example, the buffer layer may include a barrier layer, a seed layer, an IBAD template, a homogeneous epibuffer layer, and a lattice alignment buffer layer. For example, the buffer layer may have a laminated structure of yttrium oxide (Y 2 O 3 ) / magnesia (MgO) / lanthanum manganate (LaMnO 3 ) or ceria (CeO 2 ), or alumina (Al 2 O 3 ) / yttrium oxide (Y 2). O 3 ) / magnesia (MgO) / lanthanum manganate (LaMnO 3 ) or It may have a laminated structure of ceria (CeO 2 ). In the present invention, the buffer layer may be formed by a known thin film deposition method such as electron beam deposition or sputtering. In addition, in the present invention, the thickness of the buffer layer may vary, and for example, the buffer layer may have a thickness of 100 nm.
이어서, 도 6에 도시된 바와 같이, 상기 버퍼층(120)이 형성된 금속기판 상에 초전도층(130)이 형성된다. Subsequently, as shown in FIG. 6, a superconducting layer 130 is formed on the metal substrate on which the buffer layer 120 is formed.
본 발명에서 상기 초전도층(130)은 ReBCO(ReBa2Cu3O7, 여기서 Re는 Nd, Sm, Eu, Gd, Dy, Ho 및 Y로 이루어지는 금속 원소 중 최소한 하나)계 고온 초전도 물질이 사용될 수 있다. In the present invention, the superconducting layer 130 may be a ReBCO (ReBa 2 Cu 3 O 7 , wherein Re is at least one of metallic elements consisting of Nd, Sm, Eu, Gd, Dy, Ho, and Y) high temperature superconducting material. have.
본 발명에서 상기 결함 영역에 대응하는 부위에도 초전도 물질의 층이 적층된다. 그러나, 매끈한 부위에 형성된 초전도 물질층(130)은 버퍼층과 정합하는 결정 구조를 가지며 임계 온도 이하에서 초전도층으로서 기능하지만, 상기 결함 영역에 대응하는 부위에 형성된 초전도 물질층(130A)은 2축 배향을 가지지 않으며 이에 따라 임계 온도 이하에서 초전도층으로서 기능하지 않는다. In the present invention, a layer of superconducting material is also laminated on the portion corresponding to the defect area. However, although the superconducting material layer 130 formed on the smooth portion has a crystal structure that matches the buffer layer and functions as a superconducting layer below the critical temperature, the superconducting material layer 130A formed on the portion corresponding to the defect region is biaxially oriented. And therefore do not function as a superconducting layer below the critical temperature.
이와 같이 본 발명에서는, 초전도성을 구비한 초전도 물질층과 금속기판의 결함으로부터 유래되어 다른 격자 구조를 갖는 초전도 물질층을 동일 평면 상에서 선재의 길이 방향으로 평행하게 배열할 수 있다. 또한, 본 발명에서 상기 초전도 물질층이 초전도층으로 기능하는가 여부는 하부의 기판 결함, 그리고 기판 결함에 따른 버퍼층의 격자 배향에 따라 결정된다. 즉 본 발명에서 초전도층은 금속기판의 결함 영역에 대하여 자기 정렬될 수 있다. As described above, in the present invention, the superconducting material layer having superconductivity and the superconducting material layer having different lattice structures derived from defects of the metal substrate can be arranged in parallel in the longitudinal direction of the wire rod on the same plane. Also, in the present invention, whether the superconducting material layer functions as a superconducting layer is determined according to the lattice orientation of the buffer layer due to the substrate defects and the substrate defects. That is, in the present invention, the superconducting layer may be self-aligned with respect to the defect area of the metal substrate.
이에 따라, 본 발명의 초전도 선재는 복수의 초전도 스트립이 병렬로 연결되는 것과 마찬가지의 전자기적 특성을 나타낼 수 있게 된다. Accordingly, the superconducting wire of the present invention can exhibit the same electromagnetic characteristics as a plurality of superconducting strips are connected in parallel.
도 7을 참조하면, 상기 초전도층(130)이 형성된 금속기판(11O) 상에 안정화층(140)이 형성을 형성함으로써 초전도 선재의 제조가 완료된다. Referring to FIG. 7, the stabilization layer 140 is formed on the metal substrate 110 on which the superconducting layer 130 is formed, thereby completing the manufacture of the superconducting wire.
상기 안정화층(140)은 금, 은과 같은 귀금속 물질 또는 높은 전기 전도성의 물질로 형성될 수 있다. 상기 안정화층은 전기 도금, 무전해 도금 등의 통상의 방법에 의해 형성될 수 있다. The stabilization layer 140 may be formed of a precious metal material such as gold or silver or a material having high electrical conductivity. The stabilization layer may be formed by a conventional method such as electroplating, electroless plating.
도 8은 본 발명의 초전도 선재의 제조 절차의 일례를 모식적으로 도시한 절차도이다.8 is a procedure diagram schematically showing an example of a manufacturing procedure of the superconducting wire of the present invention.
도 8을 참조하면, 금속기판이 요구되는 정도의 평균 거칠기로 연마된다(S110). 이어서, 상기 금속기판 상에 선재의 길이 방향으로 평행하게 결함 영역이 형성된다(S120). 상기 결함 영역은 선재의 길이 방향을 따라 연속되거나 단속적으로 연장될 수 있다. 전술한 바와 같이 상기 결함 영역은 홈 또는 스크래치에 의해 구현될 수 있다. Referring to FIG. 8, the metal substrate is polished to an average roughness of a required level (S110). Subsequently, a defect region is formed on the metal substrate in parallel in the longitudinal direction of the wire rod (S120). The defect area may extend continuously or intermittently along the longitudinal direction of the wire rod. As described above, the defect area may be implemented by a groove or a scratch.
다음으로, 상기 금속기판 상에 버퍼층이 형성된다(S120). 상기 버퍼층은 확산 장벽, 격자 정합 등을 고려하여 다양한 물질로 된 다중층으로 형성될 수 있다. 이어서, 상기 버퍼층 상에 초전도 물질층을 형성한다(S130). 형성된 초전도 물질층은 하부의 금속기판의 결함 영역에 대응하여 다른 격자 구조를 갖는다. 상기 결함 영역 상에 형성된 초전도 물질층은 2축 배향된 결정 구조를 갖지 않으며, 따라서 임계 온도, 임계 자장 및 임계 전류 하의 초전도 환경에서 초전도성을 갖지 않는다. Next, a buffer layer is formed on the metal substrate (S120). The buffer layer may be formed of multiple layers of various materials in consideration of diffusion barriers, lattice matching, and the like. Subsequently, a superconducting material layer is formed on the buffer layer (S130). The formed superconducting material layer has a different lattice structure corresponding to the defect area of the lower metal substrate. The superconducting material layer formed on the defect region does not have a biaxially oriented crystal structure, and thus does not have superconductivity in the superconducting environment under the critical temperature, the critical magnetic field, and the critical current.
이어서, 상기 초전도 물질층(S130) 상에 안정화층을 형성함으로써(S140) 초전도 선재의 제조가 완료된다. 물론, 상기 안정화층의 형성 이후 부가적인 물질층이 추가로 형성이나 또 다른 적층 구조가 부가될 수도 있을 것이다.Subsequently, the superconducting wire is manufactured by forming a stabilization layer on the superconducting material layer S130 (S140). Of course, after the stabilization layer is formed, an additional material layer may be additionally formed or another laminate structure may be added.
도 9는 본 발명의 다른 실시예에 초전도 선재의 단면을 개략적으로 도시한 도면이다.9 is a schematic cross-sectional view of a superconducting wire in another embodiment of the present invention.
도 9를 참조하면, 금속기판(110) 상에 버퍼층(120)이 형성되어 있다. 9, a buffer layer 120 is formed on the metal substrate 110.
전술한 바와 같이 상기 금속기판(110)은 제1 표면 거칠기로 표면 가공된 것이다. 또한, 상기 금속기판 상부의 버퍼층(120)에는 결함 영역이 도입되어 있다. 상기 버퍼층(120) 상의 상기 결함 영역(122)은 표면에 대하여 소정 깊이를 갖는 홈 또는 스크래치 형태로 제공될 수 있다. 또한, 상기 결함 영역(122)은 초전도 선재의 길이 방향으로 연장될 수 있다. As described above, the metal substrate 110 is surface-treated with a first surface roughness. In addition, a defect region is introduced into the buffer layer 120 above the metal substrate. The defect area 122 on the buffer layer 120 may be provided in the form of a groove or a scratch having a predetermined depth with respect to the surface. In addition, the defect area 122 may extend in the longitudinal direction of the superconducting wire.
도 9의 단면 구조를 갖는 모재에 초전도층을 형성하는 경우, 상기 결함 영역에 대응하는 부위에도 초전도 물질의 층이 적층된다. 그러나, 매끈한 부위에 형성된 초전도 물질층은 버퍼층과 정합하는 결정 구조를 가지며 임계 온도 이하에서 초전도층으로서 기능하지만, 상기 결함 영역에 대응하는 부위에 형성된 초전도 물질층은 2축 배향을 가지지 않으며 이에 따라 임계 온도 이하에서 초전도층으로서 기능하지 않게 된다. In the case where the superconducting layer is formed on the base material having the cross-sectional structure of FIG. 9, a layer of the superconducting material is also laminated on the portion corresponding to the defect area. However, although the superconducting material layer formed on the smooth portion has a crystal structure that matches the buffer layer and functions as a superconducting layer below the critical temperature, the superconducting material layer formed on the portion corresponding to the defect area does not have a biaxial orientation and thus is critical It will not function as a superconducting layer below the temperature.
본 발명은 초전도 선재 및 초전도 코일 등의 초전도 선재 응용 부품에 적용 가능하다.The present invention is applicable to superconducting wire application parts such as superconducting wire and superconducting coil.

Claims (11)

  1. 제1 표면 거칠기를 갖는 금속기판 상에 상기 제1 표면 거칠기보다 큰 제2 거칠기를 갖는 복수의 결함 영역을 도입하는 단계;Introducing a plurality of defect regions having a second roughness greater than the first surface roughness on a metal substrate having a first surface roughness;
    상기 결함 영역이 형성된 금속기판 상에 버퍼층을 형성하는 단계; 및Forming a buffer layer on the metal substrate on which the defect region is formed; And
    상기 버퍼층이 형성된 기판 상에 초전도층을 형성하는 단계를 포함하는 초전도 선재의 제조 방법.Forming a superconducting layer on the substrate on which the buffer layer is formed.
  2. 금속기판 상의 제1 표면 거칠기를 갖는 버퍼층에 상기 제1 표면 거칠기보다 큰 제2 거칠기를 갖는 복수의 결함 영역을 도입하는 단계; 및Introducing a plurality of defect regions having a second roughness greater than the first surface roughness into a buffer layer having a first surface roughness on a metal substrate; And
    상기 결함 영역이 형성된 버퍼층 상에 초전도층을 형성하는 단계를 포함하는 초전도 선재의 제조 방법.Forming a superconducting layer on the buffer layer in which the defect region is formed.
  3. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 결함 영역은, The defect area is,
    홈 또는 스크래치를 포함하고 상기 초전도 선재의 길이 방향으로 최소한 2열 이상의 결함 영역이 형성된 것을 특징으로 하는 초전도 선재의 제조 방법.At least two rows of defect regions are formed in the longitudinal direction of the superconducting wire including grooves or scratches.
  4. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 결함 영역은 상기 금속기판의 길이 방향으로 단속적 또는 연속적으로 연장되는 것을 특징으로 하는 초전도 선재의 제조 방법.And wherein the defect region extends intermittently or continuously in the longitudinal direction of the metal substrate.
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 결함 영역은 레이저 가공되는 것을 특징으로 하는 초전도 선재의 제조 방법.The defect region is a laser processing method of producing a superconducting wire.
  6. 제4항에 있어서,The method of claim 4, wherein
    상기 결함 영역은 기계 가공되는 것을 특징으로 하는 초전도 선재의 제조 방법.And said defect area is machined.
  7. 제1항 또는 제2항에 있어서.The method according to claim 1 or 2.
    상기 초전도 물질층의 격자 구조는 상기 결함 영역에 대하여 수직 방향으로 자기 정렬되는 것을 특징으로 하는 초전도 선재의 제조 방법.The lattice structure of the superconducting material layer is self-aligned in a direction perpendicular to the defect region.
  8. 제1항에 있어서.The method of claim 1.
    상기 복수의 결함 영역 도입 단계는,In the introducing of the plurality of defective areas,
    제1 표면 거칠기를 갖도록 연마된 금속기판을 제공하는 단계;Providing a metal substrate polished to have a first surface roughness;
    상기 금속기판에 제2 표면 거칠기의 결함 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 초전도 선재의 제조 방법.And forming a defect region of a second surface roughness on the metal substrate.
  9. 제8항에 있어서.The method of claim 8.
    상기 제2 표면 거칠기는 평균 거칠기가 5㎛ x 5㎛ 내에서 2nm 이상인 것을 특징으로 하는 초전도 선재의 제조 방법.The second surface roughness is a method of manufacturing a superconducting wire, characterized in that the average roughness is 2nm or more within 5㎛ 5㎛.
  10. 금속기판, 버퍼층, 초전도 물질층 및 안정화층이 적층된 초전도 선재에 있어서,In a superconducting wire material in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are laminated,
    상기 금속기판의 최소한 일부는 제1 표면 거칠기를 갖는 제1 영역; 및 제2 표면 거칠기를 갖는 제2 영역을 구비하고, 상기 제1 영역 및 제2 영역은 선재의 길이 방향으로 연장되며,At least a portion of the metal substrate may include a first region having a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod,
    상기 버퍼층은 상기 제1 영역 및 제2 영역을 덮도록 형성되며, The buffer layer is formed to cover the first region and the second region,
    상기 제1 영역 및 제2 영역 상의 버퍼층은 서로 다른 배향을 갖는 것을 특징으로 하는 초전도 선재.The superconducting wire rod, characterized in that the buffer layer on the first region and the second region have a different orientation.
  11. 금속기판, 버퍼층, 초전도 물질층 및 안정화층이 적층된 초전도 선재에 있어서,In a superconducting wire material in which a metal substrate, a buffer layer, a superconducting material layer, and a stabilization layer are laminated,
    상기 금속기판의 최소한 일부는 제1 표면 거칠기를 갖는 제1 영역; 및 제2 표면 거칠기를 갖는 제2 영역을 구비하고, 상기 제1 영역 및 제2 영역은 선재의 길이 방향으로 연장되며,At least a portion of the metal substrate may include a first region having a first surface roughness; And a second region having a second surface roughness, wherein the first region and the second region extend in the longitudinal direction of the wire rod,
    임계 온도 이하에서 상기 제1 영역 상의 초전도 물질층은 초전도성을 구비하는 반면, 상기 제2 영역 상의 물질층은 초전도성을 구비하지 않는 것을 특징으로 하는 초전도 선재.Below the critical temperature, the superconducting material layer on the first region has superconductivity, while the layer of material on the second region does not have superconductivity.
PCT/KR2016/014301 2015-12-14 2016-12-07 Method for manufacturing superconductive wire material having superconductive strips self-aligned by metal substrate defect WO2017105029A1 (en)

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KR20100102271A (en) * 2009-03-11 2010-09-24 한국기계연구원 Superconducting tape having a flux pinning sites and method for forming the same
EP2592632A1 (en) * 2011-06-30 2013-05-15 Furukawa Electric Co., Ltd. Superconducting thin film substrate and superconducting thin film, and superconducting thin film substrate manufacturing method
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JP2005056754A (en) * 2003-08-06 2005-03-03 Sumitomo Electric Ind Ltd Superconductive wire and its manufacturing method
KR20100102271A (en) * 2009-03-11 2010-09-24 한국기계연구원 Superconducting tape having a flux pinning sites and method for forming the same
EP2592632A1 (en) * 2011-06-30 2013-05-15 Furukawa Electric Co., Ltd. Superconducting thin film substrate and superconducting thin film, and superconducting thin film substrate manufacturing method
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