WO2017099736A1

WO2017099736A1 - Dielectric buffer layer

Info

Publication number: WO2017099736A1
Application number: PCT/US2015/064620
Authority: WO
Inventors: Adwait TELANG; John-Gerard MUIRHEAD; Kevin J. Lee; Sriram PATTABHIRAMAN; James Jeong
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2015-12-09
Filing date: 2015-12-09
Publication date: 2017-06-15
Anticipated expiration: 2018-06-09
Also published as: TWI714657B; TW201731056A

Abstract

Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.

Description

DIELECTRIC BUFFER LAYER

TECHNICAL FIELD

[0001] The present disclosure pertains to semiconductor processing, and more particularly to protecting against plating through a passivation layer seam using a spin-on dielectric added as a buffer layer for logic memory interface plating.

BACKGROUND

[0002] After a redistribution layer (RDL) plating process, a passivation layer is deposited at the logic memory interface (LMI) layer as a dielectric to prevent RDL line to line leakage and shorting. This passivation layer has seam due to high topography of the RDL line, which opens up during LMI plating, and causes plate-out in the seam that leads line to line shorting. Furthermore, the weak region in the seam post fab processing causes copper extrusion in the seam during thermal cycling and will lead to early failure of the device. FIG. 1 is a schematic diagram of a silicon wafer that includes plated-out metal from a passivation layer seam.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 is a schematic diagram of a silicon wafer that includes plated-out metal from a passivation layer seam.

[0004] FIG. 2A is a schematic diagram of a cross-section of a silicon wafer that includes a redistribution layer and a passivation layer in accordance with embodiments of the present disclosure.

[0005] FIG. 2B is a schematic diagram of a cross-section of a silicon wafer with a patternable dielectric material in accordance with embodiments of the present disclosure.

[0006] FIG. 2C is a schematic diagram of a cross-section of a silicon wafer with a processed patternable dielectric material in accordance with embodiments of the present disclosure.

[0007] FIG. 2D is a schematic diagram of a cross-section of a silicon wafer with a cured and patternable dielectric material in accordance with embodiments of the present disclosure. [0008] FIG. 2E is a schematic diagram of a cross-section of a silicon wafer with a processed passivation layer and exposed redistribution layer in accordance with embodiments of the present disclosure.

[0009] FIG. 2F is a schematic diagram of a cross-section of a silicon wafer having undergone a cleaning process in accordance with embodiments of the present disclosure.

[0010] FIG. 2G is a schematic diagram of a cross-section of a silicon wafer with a patternable dielectric material in accordance with embodiments of the present disclosure.

[0011] FIG. 3 is a process flow diagram of forming a passivation layer seam barrier on a silicon wafer using a patternable dielectric material in accordance with embodiments of the present disclosure.

[0012] FIG. 4 is a schematic block diagram of an interposer implementing one or more embodiments of the disclosure.

[0013] FIG. 5 is a schematic block diagram of a computing device built in accordance with an embodiment of the disclosure.

[0014] FIG. 6 is a schematic diagram of a silicon wafer backside attached to a silicon carrier wafer.

DETAILED DESCRIPTION

[0015] Described herein are methods of forming a guard layer over a passivation layer to protect against seam attack and plate out during electroless deposition of, e.g., logic/memory interface landing pads.

[0016] This disclosure describes fabricating a patternable buffer layer after LMI passivation layer deposition. The patternable buffer layer will prevent the LMI plating solution from contacting the LMI passivation layer seam and hence protect the seam from LMI plating chemical solution attack.

[0017] FIG. 2A is a schematic diagram of a cross-section of a silicon wafer 200 that includes a redistribution layer and a passivation layer in accordance with embodiments of the present disclosure. In some embodiments, FIG. 2A-2G illustrates a silicon wafer front-side; in some embodiments, FIG. 2A-2G illustrates a silicon wafer backside. A silicon wafer backside is described in more detail in FIG. 6. Silicon wafer 200 includes a substrate 202. The substrate can be silicon, silicon oxide, or other material. The silicon wafer 200 is shown to have undergone a metal plating process to form discrete metal lines 204. For example, the discrete metal lines may be metal lines used in a redistribution layer (RDL). The discrete metal lines can include a top portion 209 and a sidewall 211 (or two sidewalls 211). Adjacent discrete metal lines 204 are separated by a gap that defines a trench 210. Prior to forming the passivation layer 206, the substrate 202 between the discrete metal lines 204 is exposed at the bottom of the trench 210. In some embodiments, the discrete metal lines are formed using a metal plating process. The discrete metal lines can include copper, aluminum, or other conductive metal.

[0018] The silicon wafer 200 also includes a passivation layer 206 that covers the top portion 209, the sidewalls 211, and the exposed substrate 202 within the trench 210. The passivation layer 206 can include silicon nitride, silicon carbide, carbon doped silicon nitride, silicon oxynitride, and carbon-doped silicon oxynitride. The passivation layer 206 can act to protect copper or other metals from diffusion across the trench 210 that would cause line leakage or short circuit in the RDL.

[0019] The passivation layer 206 can be formed in a known manner. Often, seams 208 will form between passivation layer surfaces due to the relatively high topography of the discrete metal lines 204. The seams 208 make the RDL vulnerable to short circuits across discrete metal lines 204 by exposing the discrete metal lines to electroless deposition of metal introduced to create the logic/memory interface (LMI) landing pads.

[0020] To address the vulnerability of the seams to cause a short, a patternable dielectric material 212 can be introduced to the trenches that prevents electroless plating bath solutions from attacking the seam and plating through the seam. FIG. 2B is a schematic diagram of a cross-section of a silicon wafer 240 with a patternable dielectric material in accordance with embodiments of the present disclosure. The patternable dielectric material 212 can be a photodefineable, photoimageable or photopatternable dielectric material or other dielectric that can be patterned using lithographic techniques or other known techniques. In some embodiments, the patternable dielectric material 212 can be a positive photoimageable dielectric material. In some embodiments, the patternable dielectric material can be a spin expose develop (SED) patternable material. In some embodiments, the patternable dielectric material 212 can be processed to form a permanent film (e.g., the patternable dielectric material 212 can be cured to form a permanent film).

[0021] Example photodefinable dielectric materials include but are not limited to: InterVia™ 8000-series photodefinable dielectric materials from Dow Chemical; Cyclotene™ 4000-series photodefinable dielectric materials from Dow Chemical; SU-8 photodefinable epoxy materials from Microchem; WL-5000 series photodefinable silicone dielectric materials from Dow Corning; Avatrel® photodefinable dielectric materials from Promerus; SINR-series photodefinable dielectric materials from ShinEtsuMicroSi;

SUMIRESIN EXCEL® CRC-8600 series photodefinable dielectric materials from Sumitomo Bakelite Co, Ltd.; Photodefinable polyimide and PBO materials from FujiFilm;

Photoneece™ photodefinable polyimide materials from Toray; Pimel™ photodefinable polyimide and PBO materials from Asahi Kasei E-materials Corp.; Photodefinable polyimide materials from HD Microsystems; WPR-series photodefinable dielectric materials from JSR Micro, Inc., and PerMX™ 3000 -series photodi electric dry film adhesives from Dupont.

[0022] The patternable dielectric material 212 can be introduced to the silicon wafer 240 by spin coating, dry film lamination, extrusion coating, or by other known techniques. The patternable dielectric material 212 forms a patternable dielectric material layer over the passivation layer 206, including the passivation layer 206 in the trenches 210. Specifically, the patternable dielectric material 212 covers the seams 208 formed by the passivation layer in the trenches and other locations 208. The patternable dielectric material 212 can resist degradation by chemicals in electroless plating solutions to protect the passivation layer seams 208 from being compromised by the electroless plating solution.

[0023] The patternable dielectric material can include one or more of the following characteristics:

[0024] The patternable dielectric material is compatible with the plating solution and allows plating without impacting the composition of the plated film.

[0025] The patternable dielectric material prevents the LMI plating solution from contacting the LMI passivation layer seam, hence the seam is protected from LMI plating chemical solution attack.

[0026] The patternable dielectric material applied is patternable and compatible with existing toolsets.

[0027] A curing process is used for the patternable dielectric material, which is done at low temperature required for through silicon via processing steps.

[0028] The patternable dielectric material does not react with the plating solution and does not alter the plating chemistry or composition of the plated film. [0029] The patternable dielectric material has low stress which prevents excessive wafer bow during processing and prevents additional stress in the wafer at end of line.

[0030] The patternable dielectric material has good dielectric properties and itself acts as a dielectric barrier preventing line to line shorting.

[0031] The patternable dielectric material is able to survive downstream assembly processes.

[0032] FIG. 2C is a schematic diagram of a cross-section of a silicon wafer 250 with a processed patternable dielectric material in accordance with embodiments of the present disclosure. In FIG. 2C, the patternable dielectric material 212 can be processed to form a pattern on the passivation layer 206. For a patternable dielectric material 212 that includes a positive photoimageable or photo patternable dielectric material, a mask can be used to expose to UV light those regions on the top of the discrete metal lines 204 and on top of the passivation layer 206 but not over the trenches 201 where LMI Openings 214 are desired, and the positive photoimageable or photo patternable dielectric material in these exposed regions is removed during a develop process, as is well-known in the art. This exposed portion of the passivation layer 206 is shown in FIG. 2C as the LMI opening 214 created during the patternable dielectric patterning. Noteworthy is that the patternable dielectric material 212 still covers the seams 208 after the patternable dielectric material is developed.

[0033] FIG. 2D is a schematic diagram of a cross-section of a silicon wafer 260 with a cured and patternable dielectric material in accordance with embodiments of the present disclosure. In some embodiments, the silicon wafer 260 can be heated to cure the patternable dielectric material 212 to form a permanent film (shown in FIG. 2D as cured patternable dielectric material 216). The cured patternable dielectric material 216 can withstand etching techniques that are used to remove the passivation layer 206 so that the seams 208 are still covered by the cured patternable dielectric material 216. The temperature and duration of the cure is dependent on the type of patternable dielectric material used.

[0034] FIG. 2E is a schematic diagram of a cross-section of a silicon wafer 270 with a processed passivation layer and exposed redistribution layer in accordance with embodiments of the present disclosure. The discrete metal lines 204 that make up the RDL are exposed so that metal can be deposited onto the discrete metal lines 204 to form electrical contacts (i.e., the LMI landing pads). The passivation layer 206 that was exposed from the patternable dielectric material 212 development can be etched using known techniques, such as dry or wet etching techniques. The result of the etching is an opening in the passivation layer 218 that exposes the discrete metal lines 204 (e.g., the top portion of the discrete metal lines) without exposing the trenches 210 or, more particularly, the seams 208.

[0035] FIG. 2F is a schematic diagram of a cross-section of a silicon wafer 280 having undergone a post-passivation layer etch cleaning process in accordance with embodiments of the present disclosure. During the cleaning process etch polymer or other contaminants are removed from the wafer surface.

[0036] FIG. 2G is a schematic diagram of a cross-section of a silicon wafer 290 with a patternable dielectric material in accordance with embodiments of the present disclosure. The logic/memory interface (LMI) landing pad can be deposited onto the exposed discrete metal lines 204 via electroless plating (eless plating). The landing pad is shown as an eless plated surface finish 220 in FIG. 2G. The eless plated surface finish 220 includes metals that are, after depositing, in electrical contact with the exposed discrete metal line 204. Suitable eless plated surface finishes include but are not limited to: electroless CoP/immersion Au, electroless CoWP/immersion Au, electroless NiP/immersion Au, electroless NiP/electroless Pd/immersion Au, electoless Sn, electroless NiP/electroless Sn, electroless CoP/immersion Au, electroless CoWP/electroless Sn, electoless Cu/electroless CoP/immersion Au, electroless Cu/electroless CoWP/immersion Au, electroless Cu/electroless NiP/immersion Au, electroless Cu/electroless NiP/electroless Pd/immersion Au, electroless Cu/electroless Sn, electroless Cu/electroless NiP/electroless Sn, electroless Cu/electroless CoP/immersion Au, electroless Cu/electroless CoWP/electroless Sn. Other surface finishes may also be suitable depending on the chip-to-chip solder material(s) and/or chip-to-chip attachment methods that are employed. The passivation layer 206 and the cured patternable dielectric material 216 prevent electroless plating solution from contacting the discrete metal lines 204 within the trenches 210 (i.e., by plating out through the seams 208). Thus, the cured patternable dielectric material isolates the electroless metal deposition to the top exposed portion of each discrete metal lines 204. Put differently, each discrete metal line 204 includes a LMI landing pad and is electrically isolated from the other discrete metal lines 204.

[0037] In an alternate embodiment a C4 or flip-chip bump is fabricated on top of the landing pad opening instead of a surface finish. The C4 or flip-chip bumps are made using techniques that are known in the art, and can include materials such as PbSn, Sn, SnAg, Cu, In, SnAgCu, SnCu, Au, etc. [0038] FIG. 3 is a process flow diagram 300 of forming a passivation layer seam barrier on a silicon wafer using a patternable dielectric material in accordance with embodiments of the present disclosure. In some embodiments, the passivation layer seam barrier can be formed on a silicon front-side; and in some embodiments, the passivation layer seam barrier can be formed on a silicon backside. On a silicon wafer, a redistribution layer can be formed (302). The redistribution layer can include a plurality of discrete (e.g., isolated from each other) metal lines formed by plating, such as electrolytic or electroless deposition or other known techniques. The discrete metal lines can be copper, aluminum, or other metal.

[0039] A passivation layer can be formed over the RDL (304). The passivation layer can cover the sidewalls and the top of each discrete metal line and the exposed silicon substrate between each metal line. The passivation layer can form seams at joints or other places where the passivation layer meets from the deposition process (e.g., chemical vapor deposition techniques). For example, seams can be formed in the trenches between discrete metal lines. The seams that are formed are vulnerable to attack from chemicals in the electroless deposition process that is used to form logic/memory interface landing pads. The result of such an attack can result in the electroless deposition solution contacting the metal of the discrete metal lines and causing electroless plating through the seams. The plating out of the metal through the seams in the trenches can cause shorts between adjacent discrete metal lines.

[0040] A patternable dielectric material layer can be formed over the passivation layer (306). Specifically, a patternable dielectric material layer can be formed to cover the passivation layer including the seams. The patternable dielectric material layer can be formed by spin coating, dry film lamination, extrusion coating, or by other known techniques. The patternable dielectric material layer can include a patternable dielectric material, such as a positive photoimageable or photopatternable dielectric material, or spin expose develop (SED) patternable dielectric.

[0041] The patternable dielectric material can be processed to expose the top portion of the passivation layer (308). The patternable dielectric material can be processed by photolithography to remove a portion of the patternable dielectric material covering the passivation layer (e.g., the passivation layer over a top portion of the discrete metal lines. The processing of the patternable dielectric should not remove the patternable dielectric material that covers the passivation layer seams. As part of the processing of the pattemable dielectric material, the pattemable dielectric material can be cured (310). Curing the pattemable dielectric material can form a permanent film that can withstand the etching of the passivation layer, the cleaning of the substrate and other layers, and the electroless plating of the LMI landing pads.

[0042] The passivation layer that covers the discrete metal lines can be processed to expose a portion of the discrete metal lines (312). The passivation layer can be etched, such as by a dry etch, a wet etch, or by other known techniques. The etching process should not affect the pattemable dielectric material.

[0043] A cleaning process can be used to remove etch polymer or other contaminates or to otherwise prepare the exposed metal surface for subsequent processing.

[0044] The LMI landing pads can be formed on the exposed discrete metal lines (316). The LMI landing pads can be formed using electroless deposition. The electroless deposition can deposit metals onto the metal lines, such as metals described above. The electroless deposition chemicals are prevented from attacking the seams because the seams are covered by the cured pattemable dielectric material. By preventing the electroless deposition chemicals from attacking the seams, the electroless deposition chemicals.

[0045] In this description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0046] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0047] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0048] Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0049] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

[0050] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0051] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0052] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0053] In some implementations, when viewed as a cross-section of the transistor along the source-channel -drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. [0054] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0055] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0056] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0₂), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as

silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant. [0057] FIG. 4 is a schematic block diagram of an interposer 1000 in accordance with embodiments of the present disclosure. The interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404. The first substrate 402 may be, for instance, an integrated circuit die. The second substrate 404 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 400 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 400 may couple an integrated circuit die to a ball grid array (BGA) 406 that can subsequently be coupled to the second substrate 404. In some embodiments, the first and second substrates 402/404 are attached to opposing sides of the interposer 400. In other embodiments, the first and second substrates 402/404 are attached to the same side of the interposer 400. And in further embodiments, three or more substrates are interconnected by way of the interposer 400.

[0058] The interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0059] The interposer may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 412. The interposer 400 may further include embedded devices 414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 400.

[0060] In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 400.

[0061] FIG. 5 is a computing device 500 in accordance with embodiments of the present disclosure. The computing device 500 may include a front side 501 and a backside 550. The computing device 500 a number of components, some of which reside on the front side 501. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. The components in the computing device 500 include, but are not limited to, an integrated circuit die 502 and at least one communications logic unit 508. In some implementations the communications logic unit 508 is fabricated within the integrated circuit die 502 while in other implementations the communications logic unit 508 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 502. The integrated circuit die 502 may include a CPU 504 as well as on-die memory 506, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).

[0062] Computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 510 (e.g., DRAM), non-volatile memory 512 (e.g., ROM or flash memory), a graphics processing unit 514 (GPU), a digital signal processor 516, a crypto processor 542 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 520, an antenna 522, a display or a touchscreen display 524, a touchscreen controller 526, a battery 530 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 528, a motion coprocessor or sensors 532 (that may include an accelerometer, a gyroscope, and a compass), a speaker 534, a camera 536, user input devices 538 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 540 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0063] The communications logic unit 508 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 508 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communications logic units 508. For instance, a first communications logic unit 508 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communications logic unit 508 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0064] The processor 504 of the computing device 500 includes one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0065] The communications logic unit 508 may also include one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments of the disclosure.

[0066] In further embodiments, another component housed within the computing device 500 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the disclosure.

[0067] In various embodiments, the computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

[0068] The backside 550 can include a redistribution layer (RDL) 552. One or more of the above recited components can be interconnected using metal lines forming the redistribution layer 552. Each metal line can be accessed through a via or logic/memory interface landing pad, which can be formed on the computing device backside 550 in accordance with embodiments of the present disclosure. For example, the backside 550 can include a redistribution layer metal line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and a metal interface covering the top portion of and in electrical contact with the redistribution line. In some embodiments, the front-side 501 can also include an RDL 503 and a passivation layer seam buffer in accordance with

embodiments of the present disclosure. [0069] FIG. 6 is a schematic diagram 600 of a silicon device wafer backside attached to a silicon carrier wafer. FIG. 6 shows similar components as shown in FIGS. 2A-2G. The silicon device wafer 602 includes a backside 601 that has features, such as the discrete metal lines 604, the passivation layer 606 (which can be a silicon nitride layer), the patternable dielectric material layer 616 that protects the seams 608 in the passivation layer 606, and the logic/memory interface (LMI) landing pads 620, in accordance with embodiments of the present disclosure.

[0070] The silicon device wafer 602 also includes a device side 603. Features on the backside 601 can be electrically linked to features on the device side by through-silicon vias (TSV) 662. On the device side, the silicon device wafer 602 can include Frontend and Backend layers (FE/BE layers) 656, a hard passivation layer 658, and one or more bumps 662. The bumps 662 are electrically connected to the backend metal wiring layers 656 on the device side 603 of the silicon device wafer 602. After the backside 601 processing is finished, the thinned silicon device wafer 602 is detached from the temporary silicon carrier wafer 652 and the thinned silicon device wafer 602 is cut up into individual chips. The bumps 662 on each individual chip is then electrically connected to, e.g., by way of a soldering process, to a chip package.

[0071] The schematic diagram 600 shows how a silicon wafer 602 can be carried on a silicon carrier wafer 652. The silicon device wafer 602 can be affixed to the silicon carrier wafer by a layer of glue or other adhesive 654.

[0072] The following paragraphs provide examples of various ones of the

embodiments disclosed herein.

[0073] Example 1 is a device that includes a substrate, a redistribution line having a top portion and a sidewall portion, a passivation layer at least partially covering the sidewall portion, a dielectric layer at least partially covering the passivation layer; and a metal interface covering the top portion of and in electrical contact with the redistribution line.

[0074] Example 2 may include the subject matter of example 1, wherein the passivation layer comprises one or a combination of silicon nitride, silicon carbide, carbon doped silicon nitride, silicon oxynitride, or carbon-doped silicon oxynitride.

[0075] Example 3 may include the subject matter of example 1, wherein the dielectric layer comprises a patternable dielectric material. [0076] Example 4 may include the subject matter of any of example 1 or 2 or 3, wherein the dielectric layer comprises a spin expose develop dielectric.

[0077] Example 5 may include the subject matter of any of examples 1 or 2 or 3 or 4, wherein the dielectric layer comprises a permanent film.

[0078] Example 6 may include the subject matter of any of examples 1 or 2 or 3 or 4 or 5, wherein the metal interface comprises a logic/memory interface (LMI).

[0079] Example 7 may include the subject matter of any of examples 1 or 2 or 3 or 4 or 5 or 6, wherein the redistribution line comprises copper or aluminum.

[0080] Example 8 may include the subject matter of any of examples 1 or 2 or 3 or 4 or 5 or 6 or 7, wherein the redistribution line, the passivation layer, the dielectric layer, and the metal interface reside on a silicon wafer backside.

[0081] Example 9 is a method for forming a logic/memory interface (LMI) landing pad on a silicon wafer, the method including forming, on a substrate, a redistribution layer; forming, on the redistribution layer and the substrate, a passivation layer covering the substrate and the redistribution layer; forming, on the passivation layer, a pattemable dielectric material layer; processing the pattemable dielectric material layer to expose a portion of the passivation layer covering the redistribution layer; processing the portion of the passivation layer covering the redistribution layer to expose a portion of the redistribution layer; and forming, on the exposed portion of the redistribution layer, an LMI landing pad in electrical contact with the redistribution layer.

[0082] Example 10 may include the subject matter of example 9, wherein forming the pattemable dielectric material layer comprises spinning on the pattemable dielectric material layer.

[0083] Example 11 may include the subject matter of any of examples 9 or 10, wherein the pattemable dielectric material layer comprises a positive photoimageable dielectric material.

[0084] Example 12 may include the subject matter of any of examples 9 or 10 or 11, wherein the pattemable dielectric material layer comprises a spin expose develop (SED) material.

[0085] Example 13 may include the subject matter of any of examples 9 or 10 or 11 or 12, wherein processing the pattemable dielectric material layer includes masking a first portion of the pattemable dielectric material layer and exposing a second portion of the patternable dielectric to a light source to remove the second portion from the passivation layer to expose the portion of the passivation layer.

[0086] Example 14 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13, wherein processing the patternable dielectric material layer further comprises curing the patternable dielectric material layer to form a permanent film.

[0087] Example 15 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14, wherein forming the redistribution layer comprises electrolytic or electroless plating of copper.

[0088] Example 16 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15, wherein forming the LMI landing pad comprises depositing the LMI landing pad by electroless deposition.

[0089] Example 17 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16, wherein processing the portion of the passivation layer comprises etching the portion of the passivation layer.

[0090] Example 18 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16 or 17, wherein forming the patternable dielectric material layer on the passivation layer comprises covering one or more seams formed in the passivation layer with the patternable dielectric material layer; and wherein processing the portion of the passivation layer covering the redistribution layer comprises maintaining the patternable dielectric material layer covering one or more seams formed in the passivation layer.

[0091] Example 19 is a computing device that includes a substrate comprising a device side and a backside. The device side can include a processor; a communications logic unit within the processor; a memory within the processor; a graphics processing unit within the computing device; an antenna within the computing device; a power amplifier within the processor; and a voltage regulator within the processor. The backside can include the backside can include a redistribution line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and a metal interface covering the top portion of and in electrical contact with the redistribution line.

[0092] Example 20 may include the subject matter of example 19, wherein the passivation layer comprises silicon nitride. [0093] Example 21 may include the subject matter of any of examples 19 or 20, wherein the dielectric layer comprises a patternable dielectric material.

[0094] Example 22 may include the subject matter of any of examples 19 or 20 or 21, wherein the dielectric layer comprises a permanent film.

[0095] Example 23 may include the subject matter of any of examples 19 or 20 or 21 or 22, wherein the metal interface comprises a logic/memory interface (LMI).

[0096] Example 24 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16 or 17 or 18, wherein the LMI landing pad is formed on a silicon wafer backside.

[0097] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Claims

CLAIMS:

1. A device comprising:

a substrate;

a redistribution line having a top portion and a sidewall portion;

a passivation layer at least partially covering the sidewall portion;

a dielectric layer at least partially covering the passivation layer; and

a metal interface covering the top portion of and in electrical contact with the redistribution line.

2. The device of claim 1, wherein the passivation layer comprises one or a combination of silicon nitride, silicon carbide, carbon doped silicon nitride, silicon oxynitride, or carbon-doped silicon oxynitride.

3. The device of claim 1, wherein the dielectric layer comprises a patternable dielectric material.

4. The device of claim 1 or 3, wherein the dielectric layer comprises a spin expose develop dielectric.

5. The device of claim 1 or 3, wherein the dielectric layer comprises a permanent film.

6. The device of claim 1, wherein the metal interface comprises a logic/memory interface (LMI).

7. The device of claim 1, wherein the redistribution line comprises copper or aluminum.

8. The device of claim 1, wherein the redistribution line, the passivation layer, the dielectric layer, and the metal interface reside on a silicon wafer backside.

9. A method for forming a logic/memory interface (LMI) landing pad on a silicon wafer, the method comprising:

forming, on a substrate, a redistribution layer;

forming, on the redistribution layer and the substrate, a passivation layer covering the substrate and the redistribution layer;

forming, on the passivation layer, a patternable dielectric material layer;

processing the patternable dielectric material layer to expose a portion of the passivation layer covering the redistribution layer;

processing the portion of the passivation layer covering the redistribution layer to expose a portion of the redistribution layer; and

forming, on the exposed portion of the redistribution layer, an LMI landing pad in electrical contact with the redistribution layer.

10. The method of claim 9, wherein forming the patternable dielectric material layer comprises spinning on the patternable dielectric material layer.

11. The method of claim 9 or 10, wherein the patternable dielectric material layer comprises a positive photoimageable dielectric material.

12. The method of claim 9, wherein the patternable dielectric material layer comprises a spin expose develop (SED) material.

13. The method of claim 9, wherein processing the patternable dielectric material layer comprises:

masking a first portion of the patternable dielectric material layer;

exposing a second portion of the patternable dielectric to a light source to remove the second portion from the passivation layer to expose the portion of the passivation layer.

14. The method of claim 9, wherein processing the patternable dielectric material layer further comprises curing the patternable dielectric material layer to form a permanent film.

15. The method of claim 9, wherein forming the redistribution layer comprises electrolytic or electroless plating of copper.

16. The method of claim 9, wherein forming the LMI landing pad comprises depositing the LMI landing pad by electroless deposition.

17. The method of claim 9, wherein processing the portion of the passivation layer comprises etching the portion of the passivation layer.

18. The method of claim 9, wherein forming the pattemable dielectric material layer on the passivation layer comprises covering one or more seams formed in the passivation layer; and

wherein processing the portion of the passivation layer covering the redistribution layer comprises maintaining the pattemable dielectric material layer covering one or more seams formed in the passivation layer.

19. A computing device comprising:

a substrate comprising a device side and a backside;

the device side comprising:

a processor;

a communications logic unit within the processor;

a memory within the processor;

a graphics processing unit within the computing device;

an antenna within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor;

the backside comprising:

a redistribution line having a top portion and a sidewall portion;

a passivation layer at least partially covering the sidewall portion;

a dielectric layer at least partially covering the passivation layer; and

20. The device of claim 19, wherein the passivation layer comprises one or a combination of silicon nitride, silicon carbide, carbon doped silicon nitride, silicon oxynitride, or carbon-doped silicon oxynitride.

21. The device of claim 19, wherein the dielectric layer comprises a patternable dielectric material.

22. The device of claim 19, wherein the dielectric layer comprises a permanent film.

23. The device of claim 19, wherein the metal interface comprises a logic/memory interface (LMI).