WO2017096750A1

WO2017096750A1 - Hierarchical power domain organization

Info

Publication number: WO2017096750A1
Application number: PCT/CN2016/080705
Authority: WO
Inventors: Xiaoqiang WU; Yanfei CAI; Jonathan Zhang
Original assignee: Qualcomm Incorporated
Priority date: 2015-12-08
Filing date: 2016-04-29
Publication date: 2017-06-15
Also published as: WO2017096520A1

Abstract

An integrated circuit (IC) is disclosed herein for hierarchical power domain organization. In an example aspect, an IC includes a power distribution path, first and second power domains, and first and second banks of block switches. The power distribution path provides a distribution voltage. The first power domain receives power from a first power distribution network. The first bank of block switches is coupled to the power distribution path and to the first power domain via the first power distribution network. The first bank of block switches uses the distribution voltage to switchably provide a first-level voltage to the first power domain via the first power distribution network. The second bank of block switches is coupled to the first power distribution network and to the second power domain. The second bank of block switches uses the first-level voltage to switchably provide a second-level voltage to the second power domain.

Description

HIERARCHICAL POWER DOMAIN ORGANIZATION

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of PCT International Application Serial No. PCT/CN2015/096640, entitled “HIERARCHICAL POWER DOMAIN ORGANIZATION” filed on December 8, 2015, which is expressly incorporated by reference herein in its entirety.

BACKGROUND

Field of the Disclosure

This disclosure relates generally to power management of integrated circuits (ICs) that are used in electronic devices and, more specifically, to organizing power domains in a hierarchy to reduce leakage current and thereby lower power consumption.

Description of Related Art

Power consumption is an increasingly important concern in the design and use of electronic devices. From a global perspective, a multitude of electronic devices that are used by consumers and businesses consume significant amounts of power. Accordingly, efforts are made to lower the power consumption of electronic devices to help conserve the earth’s resources and lower costs for both consumers and businesses. From an individual perspective, the prevalence of portable electronic devices that are powered by batteries continues to increase. The less energy that is consumed by, for instance, a portable battery-powered personal computing device, the longer the battery-powered computing device can operate without recharging the battery. Lower energy consumption also enables the use of smaller batteries and therefore the adoption of smaller and thinner form factors for portable electronic devices. Consequently, the popularity of portable electronic devices also provides a strong motivation to lower the power consumption of electronic devices.

Electronic devices include integrated circuits (ICs) that consume power while enabling the devices to perform functions for a user, such as aural or textual communicating, game playing, photo editing, or video streaming. Generally, integrated circuits include multiple circuit blocks, such as memory storage units, mathematical processing units, graphical processing units, buffers, and so forth. These circuit blocks are built using one or more transistors. The transistors consume power in order to perform operations using voltages and currents. With portable electronic devices in particular, power usage by transistors can significantly impact battery life.

SUMMARY

In an example aspect, an integrated circuit is disclosed. The integrated circuit includes a power distribution path, a first power domain, a first bank of block switches, a second power domain, and a second bank of block switches. The power distribution path is configured to provide a distribution voltage. The first power domain is configured to receive power from a first power distribution network. The first bank of block switches is coupled to the power distribution path and to the first power domain via the first power distribution network. The first bank of block switches is configured to use the distribution voltage to switchably provide a first-level voltage to the first power domain via the first power distribution network. The second bank of block switches is coupled to the first power distribution network and to the second power domain. The second bank of block switches is configured to use the first-level voltage to switchably provide a second-level voltage to the second power domain.

In an example aspect, an integrated circuit is disclosed. The integrated circuit includes a power distribution path, a first power domain, a second power domain, and a first power distribution network. The power distribution path is configured to provide a distribution voltage. The first power domain includes multiple circuit devices. The first power distribution network is configured to supply power to the multiple circuit devices of the first power domain. The integrated circuit also includes first switching means for providing power to the first power domain, with the first switching means configured to use the distribution voltage to provide a first-level voltage to the first power domain by holding the first power distribution network at the first-level voltage. The integrated circuit further includes second switching means for providing power to the second power domain, with the second switching means configured to obtain the first-level voltage via the first power distribution network and to use the first-level voltage to provide a second-level voltage to the second power domain.

In an example aspect, a method for implementing a hierarchical power domain organization in an integrated circuit is disclosed. The method includes asserting a first enable power signal and switching on multiple first block switches based on the assertion of the first enable power signal. The method also includes energizing a first power distribution network associated with a first power domain responsive to the switching on of the multiple first block switches. The method additionally includes asserting a second enable power signal and switching on multiple second block switches based on the assertion of the second enable power signal. The method further includes providing power to a second power domain by routing the power through the multiple first block switches, the first power distribution network, and the multiple second block switches based on the first enable power signal and the second enable power signal.

In an example aspect, an apparatus is disclosed. The apparatus includes a power distribution path, a first power distribution network, a second power distribution network, a first bank of block switches, and a second bank of block switches. The power distribution path is configured to provide a distribution voltage at a power distribution node. The first power distribution network corresponds to a first power node and is configured to provide power to a first power domain. The second power distribution network corresponds to a second power node and is configured to provide power to a second power domain. The first bank of block switches is coupled between the power distribution node and the first power node. The first bank of block switches is configured to use the distribution voltage to switchably provide a first-level voltage to the first power distribution network. The second bank of block switches is coupled between the first power node and the second power node. The second bank of block switches is configured to use the first-level voltage to switchably provide a second-level voltage to the second power distribution network.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 depicts a power source and an integrated circuit (IC) that illustrates an example of a hierarchical arrangement for power domain organization.

FIG. 2 depicts a portion of an integrated circuit that illustrates multiple power domains, along with multiple power distribution networks, and multiple banks of block switches that are organized in accordance with an example hierarchical scheme.

FIG. 3 depicts a portion of an integrated circuit that illustrates an example component layout for multiple circuit blocks of multiple power domains, multiple power distribution networks, and multiple block switches for hierarchical power domain organization.

FIG. 4 depicts a portion of an integrated circuit that illustrates another example component layout for multiple circuit blocks of multiple power domains, multiple power distribution networks, and multiple block switches for hierarchical power domain organization.

FIG. 5 depicts multiple circuit devices that illustrate an example of a serial coupling for multiple block switches in relation to multiple power distribution networks, along with associated ones of multiple circuit blocks.

FIG. 6 depicts a multi-layer, top-down view of an example layout for a power distribution network that supplies power to circuit devices of a circuit block.

FIG. 7 depicts a multi-layer, cut-away side view of an example layout for power distribution in which multiple block switches are implemented in series for a hierarchical power domain organization.

FIG. 8 is a flow diagram illustrating an example process for implementing a hierarchical power domain organization.

FIG. 9 depicts an example electronic device that includes an integrated circuit having multiple blocks.

DETAILED DESCRIPTION

Transistors of integrated circuits (ICs) enable the computing capabilities of electronic devices. To operate, transistors use voltages and currents. If a voltage potential is applied across a transistor and the transistor is active (e.g., turned on) , the transistor consumes a relatively significant amount of power as current flows through the transistor. Unfortunately, even if a transistor is inactive (e.g., turned off) and not performing operations for an integrated circuit, the transistor can still consume power due to leakage current. If an integrated circuit includes numerous inactive transistors, the total amount of power consumed due to the total leakage current can be appreciable, even though the inactive transistors are not performing operations. Power consumption due to leakage currents can be lowered, however, if a voltage potential across the inactive transistors is reduced or removed.

Controlling or reducing an amount of power that an integrated circuit consumes over time or on an instantaneous basis is an example of power management. Energy consumption can be reduced to zero or near zero during times of nonuse if an integrated circuit is powered down completely. At times of lower utilization, an integrated circuit may be partially powered down to reduce power consumption by lowering, if not removing, the voltage potential across inactive transistors. For example, if an integrated circuit cannot be powered down as a whole, one or more blocks, or cores, may be powered down separately from one or more other blocks by reducing or removing the voltage available to the blocks being powered down. If an integrated circuit chip having a graphics processing unit (GPU) , for instance, is waiting for additional data or user input before changing a display on a screen, a block of the integrated circuit that includes the GPU may be powered down. A block containing a modem that is idle may be powered down between incoming or outgoing communications. Also, if a memory is divided into two blocks and half of the memory is unused, the block with the unused memory half may be powered down while the other block of memory remains powered.

One or more blocks, which may be related by function or physical proximity for instance, can be grouped into a power domain. With a conventional power management approach to organizing power domains, each respective block of multiple respective power domains is provided at least one corresponding block switch so that blocks can be powered down independently. If a given block is to be currently powered up, the corresponding block switch is switched on to provide power. If the given block is to be currently powered down, on the other hand, the corresponding block switch is switched off to save power.

For integrated circuit chips in a package, a chip-level power path is extended from an external power source, or at least one pad designated for the external power source, to each separate block switch that respectively corresponds to each block of multiple blocks. Each pad may be located along one or more edges of a die of the integrated circuit. Thus, although an integrated circuit may have multiple pads that provide access to an external power source, each of the multiple pads typically lie along an edge of the package. Consequently, blocks that are disposed toward a center of the die are located relatively far from pads that provide access to external power.

This conventional approach to power domain organization creates a number of problems. With respect to a first problem, some blocks are placed in internal areas of an integrated circuit chip that are relatively far from a pad for the external power source. Consequently, the chip-level power path extends a great distance over the chip from the pad to the internal blocks. The long chip-level power path induces a higher current-resistance (IR) drop that impacts a voltage supply level for the distantly-placed blocks. Furthermore, the long chip-level power path consumes a greater proportion of the limited area of the integrated circuit chip. For this first problem, the increased IR drop can be partially mitigated by increasing a width of a metal forming the chip-level power path. This widening of the metal strip can indeed reduce the IR drop. Unfortunately, the consumption of the limited area of the integrated circuit chip also increases along with the width of the chip-level power path.

With respect to a second problem created by conventional approaches to power domain organization, if multiple blocks are to be powered down to save energy, the respective sets of corresponding block switches for each respective block of the multiple blocks continue to consume power from the external power source due to leakage current, even while the block switches are switched off. For this second problem, the leakage current can be decreased with two approaches. With a first conventional approach, the channels of the transistors forming the block switches are lengthened. Although longer transistor channels do result in lower leakage currents, longer transistor channels unfortunately also result in decreased current levels when the transistors are turned on because longer channels create greater resistances. Thus, lowering leakage currents with this first approach causes a corresponding block to receive less current when the block is powered up.

With a second conventional approach to decreasing leakage currents, fewer block switches in a set of block switches are utilized for each corresponding block. Although fewer block switches does result in less leakage current when the transistors are turned off, the fewer block switches unfortunately also provide less current when the transistors are turned on. Thus, lowering leakage current with this second conventional approach reduces the on current linearly along with any reduction of the off leakage current. Furthermore, with fewer pathways for current to flow into a given block, IR performance suffers, especially with high-frequency scenarios.

To at least partially address these problems, a hierarchical power domain organization as described herein can be implemented with an integrated circuit. In one or more embodiments, multiple banks of block switches are connected in series and coupled to a power distribution path for the integrated circuit. Multiple power domains are tied into the multiple banks of block switches at different nodes along the series to obtain power that is provided by the power distribution path if one or more upstream, or higher level, banks of block switches are switched on.

In these manners, the power distribution path may be disposed on the integrated circuit from a power source or pad to a first bank of block switches. Area consumption of the integrated circuit may be reduced by avoiding extension of the power distribution path to a second bank of block switches that is connected in series with the first bank of block switches. Moreover, if the first bank of block switches is switched off, any leakage current from the second bank of block switches, or one or more other downstream, or lower level, banks of block switches, occurs at a relatively negligible current level.

In one or more embodiments, an integrated circuit includes a power distribution path, a first bank of block switches, a first power domain, a second bank of block switches, and a second power domain. The power distribution path is implemented to provide a distribution voltage for multiple power domains. The first bank of block switches is coupled to the power distribution path and to the first power domain, which is associated with a first power distribution network. The first bank of block switches is coupled to the second bank of block switches via the first power distribution network for the first power domain. The first bank of block switches is implemented to use the distribution voltage to switchably provide a first-level voltage to the first power domain and the second bank of block switches via the first power distribution network. The second bank of block switches is coupled to the second power domain and to the first bank of block switches via the first power distribution network. The second bank of block switches is implemented to use the first-level voltage to switchably provide a second-level voltage to the second power domain. In addition to the first power distribution network, the integrated circuit may also include a second power distribution network that is associated with the second power domain. Each power distribution network for a respective power domain may be implemented using multiple parallel metal paths that offer a multiplicity of power nodes and that can form a mesh across multiple metal layers so as to supply power to a circuit block of the respective power domain.

In these manners, the second bank of block switches can obtain power from the power distribution path via the first power distribution network as well as the first bank of block switches, which can reduce a length of the power distribution path that is disposed on an integrated circuit as compared to prior approaches. Also, the second bank of block switches does not permit an appreciable leakage current if the first bank of block switches is switched off. Moreover, the overall IR drop to reach the second bank of block switches can be lower because the overall power path to the second bank of block switches is partially formed from the multiple parallel metal paths of the first power distribution network, which can lower the resistance of the overall power path.

FIG. 1 depicts generally at 100 a power source 108 and an integrated circuit 106 that illustrates an example of a hierarchical arrangement for power domain organization. The power source 108 is shown to include a power management integrated circuit 118 (PMIC) . As illustrated, the integrated circuit 106 includes a first power domain 102, a second power domain 104, a power distribution path 110, a first bank of block switches 112, and a second bank of block switches 114. The first bank of block switches 112 and the second bank of block switches 114 are connected in series and coupled to the power distribution path 110. The first power domain 102 and the second power domain 104 obtain power by being connected at different nodes along the series connection of the two banks of block switches.

The first bank of block switches 112 is coupled to the power distribution path 110 at a power distribution node 130. The first bank of block switches 112 is coupled to the second bank of block switches 114 at a first power node 132. A second power node 134 is indicated below the second bank of block switches 114 on the other side from the first bank of block switches 112. The first power domain 102 is coupled between the first power node 132 and ground. The second power domain 104 is coupled between the second power node 134 and ground.

In an example operation, the power management integrated circuit 118 of the power source 108 provides power to the power distribution path 110. Although the power source 108 is shown as being external to the integrated circuit 106, the power source 108 may alternatively be part of the integrated circuit 106. The power source 108 holds the power distribution path 110, and thus the power distribution node 130, at a distribution voltage 120 (VD) . If the first bank of block switches 112 is switched on, the first bank of block switches 112 uses the distribution voltage 120 to produce a first-level voltage 122 (V1L) at the first power node 132. A value of the first-level voltage 122 is close to that of the distribution voltage 120, but the first-level voltage 122 is lower due to the IR drop of intervening circuitry between the power distribution node 130 and the first power node 132. If the second bank of block switches 114 is switched on, as well as the first bank of block switches 112 being switched on, the second bank of block switches 114 produces a second-level voltage 124 (V2L) at the second power node 134 using the first-level voltage 122. A value of the second-level voltage 124 is close to that of the first-level voltage 122, but the second-level voltage 124 is lower due to the IR drop of intervening circuitry between the first power node 132 and the second power node 134. Thus, the first-level voltage 122 is lower than the distribution voltage 120, and the second-level voltage 124 is lower than the first-level voltage 122.

If the first bank of block switches 112 is holding the first power node 132 at the first-level voltage 122, the first power domain 102 receives power at the first-level voltage 122. If the first bank of block switches 112 is holding the first power node 132 at the first-level voltage 122, and if the second bank of block switches 114 is holding the second power node 134 at the second-level voltage 124, the second power domain 104 receives power at the second-level voltage 124. On one hand, if the first bank of block switches 112 is not switched on, the second bank of block switches 114 cannot produce the second-level voltage 124. On the other hand, if the first bank of block switches 112 is not switched on and the second bank of block switches 114 is not switched on, the second bank of block switches 114 does not generate an appreciable leakage current because the second bank of block switches 114 receives just a leakage level of current from the switched-off first bank of block switches 112.

In example implementations, the integrated circuit 106 is configured such that the second power domain 104 cannot receive power at an operational level from the power distribution path 110 unless both the first bank of block switches 112 and the second bank of block switches 114 are switched on. Although two levels of switches and power domains are shown for an example hierarchical power domain arrangement, three or more levels may alternatively be implemented by an integrated circuit 106. Implementations in which the first power node 132 and the second power node 134 are realized using respective power distribution networks for the first power domain 102 and the second power domain 104 are described below with reference to FIG. 2.

FIG. 2 depicts a portion 200 of an integrated circuit that illustrates multiple power domains, along with multiple power distribution networks, and multiple banks of block switches that are organized in accordance with an example hierarchical scheme. As shown, the portion 200 includes the power distribution path 110, the first bank of block switches 112, the first power domain 102, the second bank of block switches 114, and the second power domain 104. The integrated circuit portion 200 further includes a switch control block 206, a first power distribution network 222, and a second power distribution network 224. The first bank of block switches 112 includes a first block switch 212 (FBS) , and the second bank of block switches 114 includes a second block switch 214 (SBS) . The first power domain 102 includes a first circuit block 202, and the second power domain 104 includes a second circuit block 204. The first power distribution network 222 and the second power distribution network 224 each include metal lines 302 and metal lines 304. Metal lines 302 and metal lines 304 together form a metal mesh to distribute power across each power distribution network.

Metal lines

302 and 304 are described below with reference to FIGS. 3, 6, and 7.

The first circuit block 202 and the second circuit block 204 are capable of performing functional operations for the integrated circuit, such as storing bytes, manipulating graphical data, encoding or decoding data communication, making a mathematical calculation for a game, reformatting text of a document, and so forth. In contrast, the switch control block 206 performs control operations of the switches of the first bank of block switches 112 and the second bank of block switches 114 by turning the switches on and off in accordance with desired power management states for respective ones of the different power domains. Although one block switch and one circuit block are shown for each of the banks of block switches and the power domains respectively, there may alternatively be multiple block switches or circuit blocks per block switch bank or power domain respectively.

The first bank of block switches 112 is coupled to the power distribution path 110. The first bank of block switches 112 is also coupled to the first power domain 102 and the second bank of block switches 114 via the first power distribution network 222. The second bank of block switches 114 is coupled to the second power domain 104 in addition to the first bank of block switches 112. The first power distribution network 222 is associated with the first power domain 102 and supplies power to the first circuit block 202. The second power distribution network 224 is associated with the second power domain 104 and supplies power to the second circuit block 204. Each of the first block switch 212 and the second block switch 214 may be implemented using, for example, one or more transistors that are arranged in parallel.

In an example operation, the first block switch 212 receives the distribution voltage 120 from the power distribution path 110. The first block switch 212, if switched on, produces the first-level voltage 122 from the supplied distribution voltage 120. The first block switch 212 provides the first-level voltage 122 to the first circuit block 202 and the second block switch 214 via the first power distribution network 222. If the first block switch 212 is providing the first-level voltage 122, the second block switch 214, if switched on, produces the second-level voltage 124 from the received first-level voltage 122. The second block switch 214 provides the second-level voltage 124 to the second circuit block 204 via the second power distribution network 224.

In a power management scenario, each power domain can enter a sleep state or a wake state. For the sleep state, a circuit block that is to sleep can be powered down by the switch control block 206 switching off the corresponding block switch. Thus, if the switch control block 206 switches off the second block switch 214, the power is switched off to the second circuit block 204. With a hierarchical arrangement of block switches, however, if the switch control block 206 switches off the first block switch 212, the power, besides leakage power, is switched off to both the first circuit block 202 and the second block switch 214. With power not being provided to the second block switch 214 because the first block switch 212 is switched off by the switch control block 206, the second block switch 214 cannot power the second circuit block 204 at an operational level, regardless of whether the second block switch 214 is switched on or off by the switch control block 206. In other words, the second block switch 214 cannot power the second circuit block 204 at a level that is sufficient for the second circuit block 204 to perform designated processing functionality, such as manipulating graphical information in a GPU or storing data in a volatile memory. Hence, the second circuit block 204 cannot receive power at an operational level from the power distribution path unless both the first block switch 212 and the second block switch 214 are switched on. However, with the power to the second block switch 214 switched off by the first block switch 212, any leakage current generated by the second block switch 214 is substantially less than that generated by the first block switch 212. The first block switch 212 creates more leakage current because the first block switch 212 is coupled to the power distribution path 110 without any intervening block switch or switches in this example.

FIG. 3 depicts a portion of an integrated circuit that illustrates an example component layout 300 for multiple circuit blocks of multiple power domains (which are not explicitly shown in FIG. 3) , multiple power distribution networks, and multiple block switches for hierarchical power domain organization. As illustrated, the component layout 300 includes the switch control block 206, the power distribution path 110, the first circuit block 202, and the second circuit block 204. Example implementations for banks of block switches are shown as multiple first block switches 212-1 to 212-8 and multiple second block switches 214-1 to 214-8. The component layout 300 further includes the first power distribution network 222 and the second power distribution network 224.

In one or more embodiments, the power distribution path 110 may be formed from at least a portion of a layer of metal, such as a top metal layer or a redistribution layer (RDL) . The power distribution path 110 is indicated by a dotted fill pattern. The first power distribution network 222 and the second power distribution network 224 may be formed using one or more different layers of metal, such as two lower metal layers. The multiple first block switches 212-1 to 212-8 are shown to be adjacent to and distributed along at least a portion of the first circuit block 202. The multiple second block switches 214-1 to 214-8 are shown to be adjacent to and distributed along the first circuit block 202. The multiple second block switches 214-1 to 214-8 may alternatively or additionally be adjacent to or distributed along the second circuit block 204.

The multiple first block switches 212-1 to 212-8 are coupled to a power source (e.g., the power source 108 of FIG. 1) via the power distribution path 110. The multiple first block switches 212-1 to 212-8 are also coupled to the first circuit block 202 and to the multiple second block switches 214-1 to 214-8 via the first power distribution network 222. The multiple second block switches 214-1 to 214-8 are further coupled to the second circuit block 204 via the second power distribution network 224.

The multiple second block switches 214-1 to 214-8 are shown being disposed at a location relatively physically closer to the first circuit block 202 of the first power domain 102 than to the second circuit block 204 of the second power domain 104. This facilitates tying the multiple second block switches 214-1 to 214-8 to the first power distribution network 222 without extending the first power distribution network 222 beyond the physical layout of the first circuit block 202. This also serves to reduce the size or length of the first power distribution network 222 relative to the size or length of the second power distribution network 224, which can save power if the multiple second block switches 214-1 to 214-8 are switched off. However, the multiple second block switches 214-1 to 214-8 may be disposed relatively physically closer to the second circuit block 204 than to the first circuit block 202, or approximately equidistant between the two circuit blocks.

For a hierarchical arrangement, the multiple second block switches 214-1 to 214-8 are coupled between the multiple first block switches 212-1 to 212-8 and the second circuit block 204 via the first power distribution network 222 and the second power distribution network 224. The multiple first block switches 212-1 to 212-8 provide power to the first circuit block 202 and to the multiple second block switches 214-1 to 214-8 via the first power distribution network 222. The multiple second block switches 214-1 to 214-8 provide power to the second circuit block 204 via the second power distribution network 224.

In example implementations, the first power distribution network 222 or the second power distribution network 224 is realized using multiple metal lines. As shown, one or more metal lines 302 or metal lines 304 form each

power distribution network

222 or 224. The metal lines 302 are illustrated running north-south and are represented by a cross-hatched fill pattern. The metal lines 304 are illustrated running east-west and are represented by a lined fill pattern. The metal lines 302 for a first set of metal lines are disposed in one metal layer, and the metal lines 304 for a second set of metal lines are disposed in another metal layer. As shown, the metal lines 302 and the metal lines 304 are laid out substantially parallel to each other, but the metal lines may be laid out in an alternative manner. Two metal lines are substantially parallel to each other if the two metal lines are disposed in a same metal layer and extend across an intended distance, such as a width of a circuit block, of the same metal layer without touching one another. The metal lines 304 are shown to cross over the metal lines 302 in different metal layers such that a power distribution network mesh is formed. Circuit devices (not shown) of the first circuit block 202 tap into the first power distribution network 222 to obtain power, which is described further with reference to FIGS. 6 and 7.

The first power distribution network 222, such as a metal mesh, increases the overall capability for enabling current flow throughout the first circuit block 202 as well as to the multiple second block switches 214-1 to 214-8. The overall increase in current distribution pathways or the parallel nature of the current distribution paths effectively lowers the resistance of the first power distribution network 222 and the second power distribution network 224. The IR drop attributable to these power distribution networks having multiple current distribution paths is reduced accordingly. Consequently, the first-level voltage 122, and thus the distribution voltage 120, can be reduced as compared to prior approaches while still achieving a desired minimum threshold for the second-level voltage 124. With lower voltage levels, power provided by a power source can be lowered, and total power consumption is thereby reduced.

The multiple first block switches 212-1 to 212-8 may be implemented as multiple first block header switches, and the multiple second block switches 214-1 to 214-8 may be implemented as multiple second block header switches. Thus, certain examples of block switches, such as the first block switch 212 and the second block switch 214, are described herein or illustrated in the accompanying drawings as block header switches. However, hierarchical power domain organization is nevertheless applicable to implementations in which block switches are realized as block footer switches.

FIG. 4 depicts a portion of an integrated circuit that illustrates another example component layout 400 for multiple circuit blocks of multiple power domains (which are not explicitly shown in FIG. 3) , multiple power distribution networks, and multiple block switches for hierarchical power domain organization. In FIG. 4, the multiple first block switches (FBS) and the multiple second block switches (SBS) are shown over the metal layers of the power distribution path 110, the first power distribution network 222, and the second power distribution network 224 to improve clarity by enabling the reference lettering and numbering to be discernable.

With component layout 400, multiple rows of block switches are implemented. For example, two rows of first block switches 212-1, 212-2, … 212-7, and 212-8 plus 212-9, 212-10, …212-15, and 212-16 and two rows of second block switches 214-1, 214-2, …214-7, 214-8 plus 214-9, 214-10, …214-15, and 214-16 are shown. Adding a second row to the block switches increases (e.g., doubles) the number of current pathways that are implemented in parallel between the power distribution path 110 and the first power distribution network 222 and between the first power distribution network 222 and the second power distribution network 224 to thereby decrease resistance and lower power usage. On the other hand, the extensive metal pathways offered by the first power distribution network 222 results in a lower resistance between the multiple first block switches and the multiple second block switches. This lower resistance translates into a decreased IR drop； consequently, fewer second block switches may be implemented to thereby reduce the current leakage produced by the second bank of block switches.

Although two rows of block switches are described above and illustrated in FIG. 4, three or more rows may alternatively be implemented. Although the number of first block switches and the number of second block switches are shown as being equal to each other for the component layout 300 (of FIG. 3) and the component layout 400, these numbers may alternatively differ from each other. For example, 16 first block switches 212-1 to 212-16 and eight second block switches 214-1 to 214-8 may be implemented. Also, any given row may have a different number of block switches than eight.

FIG. 5 depicts generally at 500 multiple circuit devices that illustrate an example of a serial coupling for multiple block switches in relation to multiple power distribution networks, along with associated ones of multiple circuit blocks. As shown, the power distribution path 110 corresponds to the power distribution node 130. The first power distribution network 222 corresponds to the first power node 132, and the second power distribution network 224 corresponds to the second power node 134. A first block switch 212 (FBS) is coupled between the power distribution node 130 and the first power node 132. A second block switch 214 (SBS) is coupled between the first power node 132 and the second power node 134. The first circuit block 202, which is associated with the first power distribution network 222, is coupled between the first power node 132 and ground. The second circuit block 204, which is associated with the second power distribution network 224, is coupled between the second power node 134 and ground.

In one or more embodiments, the first block switch 212 is implemented with at least one first transistor 512, and the second block switch 214 is implemented with at least one second transistor 514. The first transistor 512 and the second transistor 514 are shown as p-type metal-oxide-semiconductor (PMOS) transistors. However, the first transistor 512 or the second transistor 514 may be implemented using an alternative transistor type, such as an n-type metal-oxide-semiconductor (NMOS) field effect transistor (FET) (e.g., for block footer switches) , a bipolar junction transistor (BJT) , and so forth. The first transistor 512 and the second transistor 514 each have a source, a drain, a gate, and a substrate terminal or node.

The source and substrate of the first transistor 512 are coupled to the power distribution node 130. The drain of the first transistor 512 is coupled to the first power node 132. The gate of the first transistor 512 serves as a first control input 532. The source and substrate of the second transistor 514 are coupled to the first power node 132. The drain of the second transistor 514 is coupled to the second power node 134. The gate of the second transistor 514 serves as a second control input 534. If the first transistor 512 is turned off, no appreciable current beyond leakage current flows from the power distribution node 130 to the first power node 132. However, if the first transistor 512 is turned on, current flows and the first transistor 512 produces the first-level voltage 122 at the first power node 132 using the distribution voltage 120 of the power distribution node 130. Thus, if turned on, the first transistor 512 provides the first-level voltage 122 to the first circuit block 202 via the first power distribution network 222.

If the second transistor 514 is turned off, no appreciable current beyond leakage current flows from the first power node 132 to the second power node 134. However, if the second transistor 514 is turned on, current flows and the second transistor 514 produces the second-level voltage 124 at the second power node 134 using the first-level voltage 122 of the first power node 132. Thus, if the first transistor 512 and the second transistor 514 are both turned on, the second transistor 514 provides the second-level voltage 124 to the second circuit block 204 via the second power distribution network 224. The first block switch 212 provides first switching means for providing power to the first circuit block 202 of the first power domain 102 (e.g., of FIGS. 1 and 2) , with the first switching means configured to use the distribution voltage 120 to provide a first-level voltage 122 to the first circuit block 202 by holding the first power distribution network 222 at the first-level voltage 122. The second block switch 214 provides second switching means for providing power to the second circuit block 204 of the second power domain 104 (e.g., of FIGS. 1 and 2) , with the second switching means configured to obtain the first-level voltage 122 via the first power distribution network 222 and to use the first-level voltage 122 to provide a second-level voltage 124 to the second circuit block 204.

In an example operation, the first control input 532 receives a first enable power signal 502 via a buffer 522. The second control input 534 receives a second enable power signal 504 via a buffer 524. If the switch control block 206 drives the first enable power signal 502 low, the first transistor 512 is turned on. On the other hand, if the switch control block 206 drives the first enable power signal 502 high, the first transistor 512 is turned off. Similarly, if the switch control block 206 drives the second enable power signal 504 low, the second transistor 514 is turned on. Conversely, if the switch control block 206 drives the second enable power signal 504 high, the second transistor 514 is turned off. Although not shown in FIG. 5, the first enable power signal 502 may be forwarded (e.g., after the buffer 522) to at least one other first transistor 512 (not shown) of another first block switch 212 to switch on multiple first block switches of a first bank of block switches. Analogously, the second enable power signal 504 may be forwarded to at least one other second transistor 514 (not shown) of another second block switch 214.

Switch control block 206 may be implemented to include power management mode circuitry 506. Power management mode circuitry 506 is configured to implement power management commands, such as one or more commands for entering wake or sleep states for different power domains, which are represented by first and second circuit blocks in FIG. 5. Power management mode circuitry 506 may receive separate or joint commands for the power states of the first circuit block 202 and the second circuit block 204. For example, separate first and second commands may respectively indicate that the first circuit block 202 is to enter a wake state and that the second circuit block 204 is to enter a sleep state. Alternatively, a single joint command may indicate that the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a sleep state. Regardless, the power management mode circuitry 506 drives the first enable power signal 502 and the second enable power signal 504 to implement the indicated wake or sleep states.

If implementing at least one command for a power management mode in which the first circuit block 202 is to enter a sleep state and the second circuit block 204 is to enter a sleep state, the power management mode circuitry 506 de-asserts the first enable power signal 502 and de-asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a high voltage (e.g., a logical one) to the first control input 532 and to the second control input 534 to turn off the first transistor 512 and the second transistor 514, respectively. While the power management mode circuitry 506 is de-asserting the first enable power signal 502 and the second enable power signal 504, an operational level of current cannot flow to the first power distribution network 222 or to the second power distribution network 224.

If implementing at least one command for a power management mode in which the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a sleep state, the power management mode circuitry 506 asserts the first enable power signal 502 and de-asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage (e.g., a logical zero) to the first control input 532 to turn on the first transistor 512 and a high voltage to the second control input 534 to turn off the second transistor 514.

If implementing at least one command for a power management mode in which the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a wake state, the power management mode circuitry 506 asserts the first enable power signal 502 and asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage to the first control input 532 and to the second control input 534 to turn on the first transistor 512 and the second transistor 514, respectively.

If implementing at least one command for a power management mode in which the first circuit block 202 is to enter a sleep state and the second circuit block 204 is to enter a wake state, the power management mode circuitry 506 asserts the first enable power signal 502 and asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage to the second control input 534 to turn on the second transistor 514. Because the power domains as represented by the first and second circuit blocks are coupled in series, the power management mode circuitry 506 also provides a low voltage to the first control input 532 to turn on the first transistor 512 so that the first block switch 212 is producing the first-level voltage 122 at the first power node 132. In this power management mode, the first circuit block 202 does receive power, but the first circuit block 202 can be in a sleep state because the block is not being used functionally. Accordingly, some power may be saved by gating a clock signal (not shown) to the first circuit block 202.

In some implementations, switching transistors that provide power are divided into the “few” and the “rest. ” The “few” transistors are turned on first in an orderly fashion to handle potential voltage droops and current losses. The “rest” of the transistors, which can be 5-20 times more numerous than the “few” transistors, are then turned on. To accommodate a “few” versus the “rest” scenario, a first block switch 212 may include two first transistors 512 that are respectively controlled by two first enable power signals 502, one for the “few” transistors and another for the “rest” of the transistors. Analogously, the contents and operation of a second block switch 214 may likewise be adapted to handle two or more different groupings of circuitry.

FIG. 6 depicts a multi-layer, top-down view 600 of an example layout for a first power distribution network 222 that supplies power to circuit devices of the first circuit block 202. As illustrated, the multi-layer, top-down view 600 includes a first block switch 212 (FBS) and a second block switch 214 (SBS) in addition to the first circuit block 202. The first circuit block 202 includes multiple circuit devices, with a circuit device 602 being explicitly shown. Examples for the circuit device 602 include an inverter, a flip-flop, a buffer, or a logical gate.

In example implementations, the first block switch 212 is coupled to the second block switch 214 via the first power distribution network 222. The first power distribution network 222 includes the metal lines 302 in a first metal layer and the metal lines 304 in a second metal layer. Both the first metal layer and the second metal layer include metal power lines and metal ground lines. For the first metal layer having lines with a cross-hatched pattern fill, metal ground lines are explicitly shown, but metal ground lines are omitted from the second metal layer for the sake of clarity. Thus, the metal lines 302 are shown to include metal ground lines 302-0 and metal power lines 302-1. To visually differentiate the two, the metal power lines 302-1 are illustrated as being wider than the metal ground lines 302-0.

The circuit device 602 ties into the first power distribution network 222 through at least one via 604. One via 604 couples the circuit device 602 to a metal ground line 302-0, and another via 604 couples the circuit device 602 to a metal power line 302-1. The metal lines for power of the first layer, which are represented by 302-1, and the metal lines for power of the second layer, which are represented generally by 304, are interconnected by multiple vias 604 to form a metal mesh for power, or metal power mesh. The metal lines for ground of the first layer, which are represented by 302-0, and the metal lines for ground of the second layer, which are represented generally by 304, are interconnected by multiple vias 604 to form a metal mesh for a ground potential, or metal ground mesh. An example of an interconnection between metal layers using multiple vias 604 to form a metal power mesh is shown in FIG. 7.

FIG. 7 depicts a multi-layer, cut-away side view 700 of an example layout for power distribution in which multiple block switches are implemented in series for a hierarchical power domain organization. Multiple layers are shown, including a layer at the bottom having circuit devices and multiple metal layers having metal lines. As illustrated, the multi-layer, cut-away side view 700 includes the first block switch 212, the circuit device 602, and the second block switch 214, each of which is disposed on a substrate 702 of an integrated circuit. The view further includes the power distribution path 110, the first power distribution network 222, the second power distribution network 224, a metal power line 302-1 for the first power distribution network 222, a metal power line 302-1 for the second power distribution network 224, multiple metal lines 304 for the first power distribution network 222 and for the second power distribution network 224, and multiple instances of vias 604. Generally, a first set of metal lines 302 are connected to a second set of metal lines 304 through multiple vias 604 to form a metal mesh for each power distribution network.

The vias 604 as shown in FIGS. 6 and 7 are illustrated conceptually. Vias 604 may be implemented in any manner to create an electrical connection between two different layers. Two different layers can be connected by one or by multiple vias 604. A via 604 creates an electrical connection between two adjacent layers or between two non-adjacent layers that are separated by one or more other layers. Because the power distribution path 110 is on a metal layer that is higher than both the first metal layer of the metal lines 302 and the second metal layer of the metal lines 304, the via 604 coupling the first block switch 212 to the power distribution path 110 extends through multiple metal layers, which is indicated by the dashed lines.

In example implementations, the first block switch 212 switchably bridges the power distribution path 110 and the first power distribution network 222. The first block switch 212 is coupled to the power distribution path 110, which is disposed in an upper metal layer, and to the metal power line 302-1 of the first power distribution network 222 with multiple different instances of a via 604, two of which are explicitly shown. The circuit device 602 is coupled to the metal power line 302-1 of the first power distribution network 222. Although not explicitly shown in FIG. 7, the circuit device 602 is also coupled to the metal ground line 302-0 (of FIG. 6) of the first power distribution network 222. The second block switch 214 switchably bridges the first power distribution network 222 and the second power distribution network 224. The second block switch 214 is coupled to the metal power line 302-1 of the first power distribution network 222 and to the metal power line 302-1 of the second power distribution network 224 with multiple different instances of a via 604, two of which are explicitly shown.

In example implementations, an integrated circuit includes at least one upper metal layer and multiple lower metal layers that are lower than the upper metal layer (e.g., that have an elevation that is closer to the substrate 702) . The power distribution path 110 is disposed at the upper metal layer that is higher than the multiple lower metal layers. Circuitry that is downstream from the first bank of block switches 112 obtains power via the multiple lower metal layers. This downstream circuitry can include circuitry of the first power domain 102, circuitry of the second bank of block switches 114, or circuitry of the second power domain 104. The multiple lower metal layers can include a first metal layer and a second metal layer. For instance, the first metal layer can include metal lines 302, and the second metal layer can include metal lines 304. Further, the first power distribution network 222 includes a first metal mesh disposed across the first metal layer and the second metal layer, with the first power distribution network 222 capable of providing power to the first power domain 102 via the first metal mesh. The second power distribution network 224 includes a second metal mesh disposed across the first metal layer and the second metal layer, with the second power distribution network 224 capable of providing power to the second power domain 104 via the second metal mesh. The circuitry that is downstream from the first bank of block switches 112 therefore obtains power from the first and second lower metal layers and not from the upper metal layer in these example implementations.

FIG. 8 is a flow diagram illustrating an example process 800 for implementing a hierarchical power domain organization. Process 800 is described in the form of a set of blocks 802-812 that specify operations that may be performed. However, operations are not necessarily limited to the order shown in FIG. 8 or described herein, for the operations may be implemented in alternative orders or in fully or partially overlapping manners. Operations represented by the illustrated blocks of process 800 may be performed by an integrated circuit, such as an integrated circuit 106 of FIG. 1 or an integrated circuit 910 as is described below with reference to FIG. 9. Thus, the operations of process 800 may be performed by an integrated circuit, or a portion thereof, having a hierarchical power domain organization.

At block 802, a first enable power signal is asserted. For example, a switch control block 206 of an integrated circuit 106 may assert a first enable power signal 502. To do so, power management mode circuitry 506 may drive the first enable power signal 502 high or low such that a first transistor 512 coupled thereto is made active. At block 804, multiple first block switches are switched on based on the asserting of the first enable power signal. For example, the power management mode circuitry 506 may switch on multiple first block switches 212-1 to 212-8 based on the assertion of the first enable power signal 502. A voltage level at a gate of a PMOS transistor, such as a first control input 532 of the first transistor 512, may be brought low to turn on the PMOS transistor.

At block 806, a first power distribution network associated with a first power domain is energized responsive to the switching on of the multiple first block switches. For example, a voltage potential of a first power distribution network 222, which is associated with a first power domain 102, may increase to a targeted voltage level responsive to the multiple first block switches 212-1 to 212-8 being switched on. To effectuate the increased voltage potential, current from a power distribution path 110 may be enabled to flow into the first power distribution network 222.

At block 808, a second enable power signal is asserted. For example, the switch control block 206 of the integrated circuit 106 may assert a second enable power signal 504. To do so, the power management mode circuitry 506 may drive the second enable power signal 504 high or low such that a second transistor 514 coupled thereto is made active. At block 810, multiple second block switches are switched on based on the asserting of the second enable power signal. For example, the power management mode circuitry 506 may switch on multiple second block switches 214-1 to 214-8 based on the assertion of the second enable power signal 504. The integrated circuit 106 may route the second enable power signal 504 to multiple instances of a second buffer 524, which buffers provide the signal to the gate terminals of multiple respective instances of the second transistor 514 of the second block switch 214.

At block 812, power is provided to a second power domain by routing the power through the multiple first block switches, the first power distribution network, and the multiple second block switches based on the first enable power signal and the second enable power signal. For example, circuitry of an integrated circuit 106 may provide power to a second power domain 104 by routing the power through the multiple first block switches 212-1 to 212-8, the first power distribution network 222, and the multiple second block switches 214-1 to 214-8 based on the first enable power signal 502 and the second enable power signal 504. The power routing may be at least partially effectuated by routing power from a power distribution node 130 to a first power node 132 that corresponds to the first power distribution network 222 and from the first power node 132 to a second power node 134 that corresponds to a second power distribution network 224, which is associated with the second power domain 104. An operational level of current is permitted to flow or is prevented from flowing between the power nodes by block switches that are positioned between the power nodes, with the on or off states of the block switches controlled by the first enable power signal 502 and the second enable power signal 504.

FIG. 9 depicts an example electronic device 902 that includes an integrated circuit (IC) 910 having multiple blocks. As shown, the electronic device 902 includes an antenna 904, a transceiver 906, and a user input/output (I/O) interface 908 in addition to the IC 910. Illustrated examples of an IC 910 include a microprocessor 912, a graphics processing unit (GPU) 914, a memory array 916, and a modem 918.

The electronic device 902 may be a mobile or battery-powered device or a fixed device that is designed to be powered by an electrical grid. Examples of an electronic device 902 include a server computer, a network switch or router, a blade of a data center, a personal computer, a desktop computer, a notebook computer, a tablet computer, a smart phone, an entertainment appliance, or a wearable computing device such as a smartwatch, intelligent glasses, or an article of clothing. An electronic device 902 may also be a device, or a portion thereof, having embedded electronics. Examples of an electronic device 902 with embedded electronics include a passenger vehicle, industrial equipment, a refrigerator or other home appliance, a drone or other unmanned aerial vehicle (UAV) , or a power tool.

For an electronic device with a wireless capability, the electronic device 902 includes an antenna 904 that is coupled to a transceiver 906 to enable reception or transmission of one or more wireless signals. The IC 910 may be coupled to the transceiver 906 to enable the IC 910 to have access to received wireless signals or to provide wireless signals for transmission via the antenna 904. The electronic device 902 as shown also includes at least one user I/O interface 908. Examples of an I/O interface 908 include a keyboard, a mouse, a microphone, a touch-sensitive screen, a camera, an accelerometer, a haptic mechanism, a speaker, a display screen, or a projector.

The IC 910 may comprise, for example, one or more instances of a microprocessor 912, a GPU 914, a memory array 916, a modem 918, and so forth. The microprocessor 912 may function as a central processing unit (CPU) or other general-purpose processor. Some microprocessors include different parts, such as multiple processing cores, that may be individually powered on or off. The GPU 914 may be especially adapted to process visual-related data for display. If visual-related data is not being rendered or otherwise processed, the GPU 914 may be powered down. The memory array 916 stores data for the microprocessor 912 or the GPU 914. Example types of memory for the memory array 916 include random access memory (RAM) , such as dynamic RAM (DRAM) or static RAM (SRAM) , flash memory, and so forth. If programs are not accessing data stored in memory, the memory array 916 may be powered down. The modem 918 modulates a signal to encode information into the signal or demodulates a signal to extract encoded information. If there is no information to encode or decode for outbound or inbound communications, the modem 918 may be idled to reduce power consumption. The IC 910 may include additional or alternative parts than those that are shown, such as an I/O interface, a sensor such as an accelerometer, a transceiver or another part of a receiver chain, a customized or hard-coded processor such as an application-specific integrated circuit (ASIC) , and so forth.

The IC 910 may also comprise a system on a chip (SOC) . An SOC may integrate a sufficient number or type of components to enable the SOC to provide computational functionality as a notebook, a mobile phone, or another electronic apparatus using one chip at least primarily. Components of an SOC, or an IC 910 generally, may be termed blocks or cores. Examples of cores or circuit blocks (e.g., a first circuit block 202 or a second circuit block 204 of FIG. 2) , in addition to those that are illustrated, include a voltage regulator, a memory array, a memory controller, a general-purpose processor, a cryptographic processor, a modem, a vector processor, an interface or communication controller, a wireless controller, or a GPU. Any of these cores or circuit blocks, such as a processing or GPU circuit block, may further include multiple internal circuit blocks. A circuit block of an SOC may be powered down if not in use according to the techniques described in this document.

Unless context dictates otherwise, use herein of the word “or” may be considered use of an “inclusive or, ” or a term that permits inclusion or application of one or more items that are linked by the word “or” (e.g., a phrase “A or B” may be interpreted as permitting just “A, ” as permitting just “B, ” or as permitting both “A” and “B” ) . Although subject matter has been described in language specific to structural features or methodological operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, including not necessarily being limited to the organizations in which features are arranged or the orders in which operations are performed.

Claims

An integrated circuit comprising:

a power distribution path configured to provide a distribution voltage；

a first power domain configured to receive power from a first power distribution network；

a first bank of block switches coupled to the power distribution path and to the first power domain via the first power distribution network, the first bank of block switches configured to use the distribution voltage to switchably provide a first-level voltage to the first power domain via the first power distribution network；

a second power domain； and

a second bank of block switches coupled to the first power distribution network and to the second power domain, the second bank of block switches configured to use the first-level voltage to switchably provide a second-level voltage to the second power domain.
The integrated circuit of claim 1, further comprising:

the first power distribution network, the first power distribution network configured to couple the first bank of block switches to the second bank of block switches.
The integrated circuit of claim 2, wherein the first power distribution network comprises at least part of a first metal layer that includes a first set of metal lines that are substantially parallel to each other.
The integrated circuit of claim 3, wherein:

the first power distribution network comprises at least part of a second metal layer that includes a second set of metal lines that cross over the first set of metal lines； and

the first set of metal lines are connected to the second set of metal lines through multiple vias to form a metal mesh.
The integrated circuit of claim 1, further comprising:

an upper metal layer； and

multiple lower metal layers that are lower than the upper metal layer,

wherein:

the power distribution path is disposed at the upper metal layer that is higher than the multiple lower metal layers； and

circuitry that is downstream from the first bank of block switches is configured to obtain power via the multiple lower metal layers.
The integrated circuit of claim 5, wherein the multiple lower metal layers include a first metal layer and a second metal layer； and further comprising:

the first power distribution network, the first power distribution network including a first metal mesh disposed across the first metal layer and the second metal layer, the first power distribution network configured to provide power to the first power domain via the first metal mesh； and

a second power distribution network coupled to the second bank of block switches, the second power distribution network including a second metal mesh disposed across the first metal layer and the second metal layer, the second power distribution network configured to provide power to the second power domain via the second metal mesh, wherein:

the circuitry that is downstream from the first bank of block switches is configured to not obtain power from the upper metal layer except for indirectly via the first bank of block switches； and

the circuitry that is downstream from the first bank of block switches comprises circuitry of the first power domain, circuitry of the second bank of block switches, and circuitry of the second power domain.
The integrated circuit of claim 1, wherein:

the first power domain includes a first circuit block；

the second power domain includes a second circuit block；

the first bank of block switches includes multiple first block switches that are distributed along at least a portion of the first circuit block； and

the second bank of block switches includes multiple second block switches that are distributed along at least a portion of the first circuit block.
The integrated circuit of claim 7, wherein:

the multiple first block switches comprise multiple first block header switches for at least the first circuit block； and

the multiple second block switches comprise multiple second block header switches for at least the second circuit block.
The integrated circuit of claim 1, wherein:

the first bank of block switches is configured to be switched on for a wake state of the first power domain and to be switched off for a sleep state of the first power domain； and

the second bank of block switches is configured to be switched on for a wake state of the second power domain and to be switched off for a sleep state of the second power domain.
The integrated circuit of claim 9, wherein the integrated circuit is configured such that the second power domain cannot receive power at an operational level from the power distribution path unless both the first bank of block switches and the second bank of block switches are switched on.
The integrated circuit of claim 9, wherein the integrated circuit is configured such that at least the first bank of block switches is switched on to enable the second power domain to enter the wake state irrespective of the wake state or the sleep state of the first power domain.
An integrated circuit comprising:

a power distribution path configured to provide a distribution voltage；

a first power domain including multiple circuit devices；

a first power distribution network configured to supply power to the multiple circuit devices of the first power domain；

first switching means for providing power to the first power domain, the first switching means configured to use the distribution voltage to provide a first-level voltage to the first power domain by holding the first power distribution network at the first-level voltage；

a second power domain； and

second switching means for providing power to the second power domain, the second switching means configured to obtain the first-level voltage via the first power distribution network and to use the first-level voltage to provide a second-level voltage to the second power domain.
The integrated circuit of claim 12, wherein the first switching means is further configured to provide the first-level voltage to the first power domain responsive to assertion of a first enable power signal that corresponds to the first power domain.
The integrated circuit of claim 13, wherein the second switching means is further configured to provide the second-level voltage to the second power domain responsive to assertion of a second enable power signal that corresponds to the second power domain.
The integrated circuit of claim 14, wherein the integrated circuit is configured such that the first enable power signal and the second enable power signal are both asserted to enable the second switching means to provide the second-level voltage to the second power domain.
The integrated circuit of claim 12, wherein:

the first switching means includes a first transistor that is coupled between a power distribution node and a first power node corresponding to the first power distribution network, the first transistor having a first control input configured to receive a first enable power signal；

the power distribution path is configured to hold the power distribution node at the distribution voltage of the power distribution path； and

the first transistor is configured to hold the first power node at the first-level voltage based on the first enable power signal.
The integrated circuit of claim 16, wherein:

the second switching means includes a second transistor that is coupled between the first power node and a second power node corresponding to a second power distribution network, the second transistor having a second control input configured to receive a second enable power signal； and

the second transistor is configured to hold the second power node at the second-level voltage based on the second enable power signal.
The integrated circuit of claim 17, wherein:

the second transistor is further configured to hold the second power node at the second-level voltage based on the first enable power signal and the second enable power signal； and

the second-level voltage comprises a voltage level that is sufficient to enable circuitry of the second power domain to perform designated processing functionality.
The integrated circuit of claim 17, wherein:

the first power domain is coupled to the first power node and configured to receive power at the first-level voltage via the first power node；

the second power domain is coupled to the second power node and configured to receive power at the second-level voltage via the second power node； and

the first-level voltage is lower than the distribution voltage, and the second-level voltage is lower than the first-level voltage.
A method for implementing a hierarchical power domain organization in an integrated circuit, the method comprising:

asserting a first enable power signal；

switching on multiple first block switches based on the asserting of the first enable power signal；

energizing a first power distribution network associated with a first power domain responsive to the switching on of the multiple first block switches；

asserting a second enable power signal；

switching on multiple second block switches based on the asserting of the second enable power signal； and

providing power to a second power domain by routing the power through the multiple first block switches, the first power distribution network, and the multiple second block switches based on the first enable power signal and the second enable power signal.
The method of claim 20, further comprising:

providing the power to the first power domain by routing the power through the multiple first block switches based on the first enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first power domain to enter a sleep state and for the second power domain to enter a sleep state by:

de-asserting the first enable power signal； and

de-asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first power domain to enter a wake state and for the second power domain to enter a sleep state by:

asserting the first enable power signal； and

de-asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first power domain to enter a wake state and for the second power domain to enter a wake state by:

asserting the first enable power signal； and

asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first power domain to enter a sleep state and for the second power domain to enter a wake state by:

asserting the first enable power signal； and

asserting the second enable power signal.
The method of claim 20, wherein:

the first power distribution network comprises multiple layers having metal lines that form a power distribution network mesh, each layer of the multiple layers including multiple metal lines that are disposed substantially parallel to each other within a given layer of the multiple layers； and

the providing the power comprises routing the power to the second power domain via the power distribution network mesh.
The method of claim 20, wherein:

the method further comprises energizing a second power distribution network associated with the second power domain responsive to the switching on of the multiple second block switches； and

the providing the power comprises routing the power through the multiple first block switches, the first power distribution network, the multiple second block switches, and the second power distribution network.
An apparatus comprising:

a power distribution path configured to provide a distribution voltage at a power distribution node；

a first power distribution network corresponding to a first power node and configured to provide power to a first power domain；

a second power distribution network corresponding to a second power node and configured to provide power to a second power domain；

a first bank of block switches coupled between the power distribution node and the first power node, the first bank of block switches configured to use the distribution voltage to switchably provide a first-level voltage to the first power distribution network； and

a second bank of block switches coupled between the first power node and the second power node, the second bank of block switches configured to use the first-level voltage to switchably provide a second-level voltage to the second power distribution network.
The apparatus of claim 28, further comprising:

a switch control block configured to implement a control operation for the first bank of block switches and the second bank of block switches, the switch control block further configured to switch on the first bank of block switches and the second bank of block switches to enable the second power distribution network to provide power to the second power domain.
The apparatus of claim 29, further comprising:

the first power domain including a first circuit block configured to provide a functional operation, the first circuit block including a circuit device that obtains power via the first power distribution network.