WO2017095408A1

WO2017095408A1 - Clamp circuit for a power converter

Info

Publication number: WO2017095408A1
Application number: PCT/US2015/063523
Authority: WO
Inventors: Arthur B. Odell
Original assignee: Power Integrations Inc
Current assignee: Power Integrations Inc
Priority date: 2015-12-02
Filing date: 2015-12-02
Publication date: 2017-06-08
Anticipated expiration: 2018-06-02

Abstract

A controller includes a regulation control circuit coupled to generate a drive signal in response to a feedback signal to control switching of a power switch to control a transfer of energy from an input to an output of a power converter. The regulation circuit includes an enable circuit coupled to generate an enable signal that is representative of a determination to turn on the power switch. A clamp control circuit is coupled to generate a clamp drive signal in response to the enable signal to turn on a clamp switch coupled to an energy transfer element for a first duration near an end of an off time of the power switch to inject charge stored in the clamp circuit into the energy transfer element to discharge a parasitic capacitance of the power switch into the energy transfer element before the power switch is turned on.

Description

CLAMP CIRCUIT FOR A POWER CONVERTER

BACKGROUND OF THE INVENTION

Field of the Invention

[0001] The present invention relates generally to switched mode power converters, and more specifically to power converters coupled in a flyback topology.

Discussion of the Related Art

[0002] Electronic devices use power to operate. Switched mode power converters are commonly used due to their high efficiency, small size and low weight to power many of today's electronics. Conventional wall sockets provide a high voltage alternating current. In a switching power converter, a high voltage alternating current (ac) input is converted to provide a well- regulated direct current (dc) output through an energy transfer element. The switched mode power converter control circuit usually provides output regulation by sensing one or more inputs representative of one or more output quantities and controlling the output in a closed loop. In operation, a switch is utilized to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of pulses per unit time of the switch in a switched mode power converter.

[0003] Switched mode power converters may include a clamp circuit coupled across a primary winding to prevent damage to the switch. Generally the clamp circuit includes passive components, such as diodes, resistors or capacitors. In general, a passive component may store or maintain energy in the form of voltage or current. An active component may produce energy in the form of a voltage or current. One example of an active component may be a transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0005] FIG. 1A is a functional block diagram of an example power converter and controller for controlling an active clamp circuit, in accordance with an embodiment of the disclosure.

[0006] FIG. IB is a diagram illustrating example waveforms of a current through a power switch, in accordance with an embodiment of the disclosure.

[0007] FIG. 2 is a timing diagram illustrating example waveforms of various voltages, currents, and control signals of FIG. 1A, in accordance with an embodiment of the disclosure. [0008] FIG. 3 is a functional block diagram of an example controller of FIG. 1 A for controlling an active clamp circuit, in accordance with an embodiment of the disclosure.

[0009] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

[0010] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

[0011] Reference throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment", "in an embodiment", "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0012] As mentioned above, clamp circuits may be used to prevent damage to components of the power converter. Clamp circuits are typically coupled across the primary winding of a power converter and may limit the amount of voltage across the primary winding when the power switch of the power converter is OFF. In general the clamp circuit includes passive components but may also include active components, such as a transistor, to control when the clamp circuit is enabled. A clamp circuit that uses an active component, such as a transistor, may be referred to as an active clamp circuit.

[0013] Active clamp circuits may also be used to reduce losses experienced by the power converter. Typical losses experienced in a power converter are conduction losses and switching losses. Conduction losses and switching losses occur due to the electrical resistance in the circuit and the parasitic capacitance that is switched by the power converter, particularly when the power switch is a transistor. When the power switch conducts current, the resistance of the circuit along with the current passing in the circuit generates conduction loss. Switching losses are generally associated with the losses, which occur while the power switch of the power converter is transitioning between an ON state and an OFF state or vice versa. In one example, a switch that is ON (or closed) may conduct current while a switch that is OFF (or open) cannot conduct current. When the power switch is open, voltage across the switch stores energy in the parasitic capacitance. The parasitic capacitance discharges when the power switch closes, dissipating the energy stored in the parasitic capacitance in the resistance of the power switch to produce switching loss. Further, switching losses may result from having a non-zero voltage across the power switch at the moment the power switch turns ON or from having a non-zero current through the power switch when the power switch turns OFF. An active clamp circuit may be used to reduce the switching losses through the use of zero voltage switching techniques. Similar to a passive clamp circuit, an active clamp circuit is coupled across the primary winding of a power converter and includes a switch (such as a transistor) to enable current flow through the active clamp circuit. Typical active clamp circuits enable current flow through the active clamp for the entirety of the OFF time of the power switch. The active clamp circuit facilitates the discharge of the parasitic capacitance associated with the power switch and the voltage across the power switch falls to substantially zero prior to the power switch turning ON and as such switching losses may be reduced.

[0014] One topology for a switched mode power converter is known as a flyback converter. The flyback converter can provide low output currents at low component cost and is relatively simple in comparison to other converter topologies. The flyback converter may also utilize an active clamp circuit to prevent excess voltage from damaging components within the flyback converter. However, flyback converters may be limited at higher output power ranges and use at higher switching frequencies due to leakage inductance related losses and switching losses. An active clamp circuit may also be used with a flyback converter, however, typical active clamp circuits (where the clamp switch is ON when the power switch of the power converter is OFF) could result in current ringing and an increase in the RMS current. The current ringing and increased RMS current generally translates to a larger output capacitor used for the flyback converter, which would increase cost for the power converter. As such, previous active clamp circuits may not work well with flyback converters.

[0015] Examples in accordance with teachings of the present invention includes a clamp control circuit that controls an active clamp circuit such that current flows through the active clamp circuit during portions of the OFF time of the power switch. In addition, the current through the active clamp circuit is substantially equal to zero for a portion of the OFF time of the power switch. Further, the clamp switch is not turned ON until near the end of the OFF time of the power switch. In one example, the active clamp circuit includes a capacitance and a clamp switch. The clamp switch may be exemplified as a transistor that has an associated anti-parallel diode. At or near the beginning of the OFF time of the power switch, the anti-parallel diode of the clamp switch conducts a charge associated with the leakage inductance of the power converter is transferred to the clamp capacitance and stored. The anti-parallel diode stops conducting substantially when the net charge associated with leakage inductance of the power converter has been transferred. The clamp switch remains OFF until near the end of the OFF time of the power switch. Once it is determined that the power switch should turn ON, the clamp switch is turned on for a first duration of time. The transistor of the clamp switch is turned on such that the net charge previously transferred to the clamp capacitance associated with the leakage inductance is transferred to the primary winding.

[0016] There are several considerations in selecting the length of the first duration (time which the transistor of the clamp switch is ON). As mentioned above, the net charge to be transferred (and ergo current) is substantially the same as the net charge previously transferred to the clamp capacitance associated with the leakage inductance through the anti-parallel diode. As such, a shorter first duration corresponds to a larger voltage on the power switch. Too large of a voltage may damage the power switch. However, the longer the first duration, the higher the root-mean- square (RMS) current experienced by the power converter. In one example, the first duration of time may be substantially equal to the duration of time that the anti-parallel diode conducts the net charge previously transferred to the clamp capacitance associated with the leakage inductance.

[0017] Examples in accordance with teachings of the present invention include a clamp control circuit coupled to receive an enable signal that indicates when the power switch is going to be turned ON. In response to the enable signal, the clamp control circuit turns ON the clamp switch for a first duration. Once the clamp switch turns OFF, the power switch turns ON after a second duration delay has elapsed. For instance, a power converter in accordance with the teachings of the present invention includes an energy transfer element coupled between an input of the power converter and an output of the power converter. A power switch is coupled to the energy transfer element, and an active clamp circuit is coupled to the energy transfer element and the power switch. A controller is coupled to the active clamp circuit and the power switch to control switching a clamp switch in the active clamp circuit, as well as the power switch. In one example, the controller includes a regulation control circuit coupled to generate a drive signal in response to a feedback signal representative of the output of the power converter to control switching of the power switch. The switching of the power switch controls a transfer of energy from the input of the power converter through the energy transfer element to the output of power converter. The regulation circuit includes an enable circuit that is coupled to generate the enable signal in response to the feedback signal. A clamp control circuit is coupled to generate a clamp drive signal in response to the enable signal from the regulation control circuit to control switching of the clamp switch included in the active clamp circuit, wherein the clamp drive signal is coupled to turn on the clamp switch for a first duration near an end of an off time of the power switch to inject charge stored in the active clamp circuit into the energy transfer element to discharge a parasitic capacitance of the power switch into the energy transfer element before the power switch is turned on in response to the drive signal.

[0018] To illustrate, FIG. 1A shows a functional block diagram of an example power converter 100 is including an example active clamp circuit 104 and controller 122 in accordance with the teachings of the present invention. The illustrated example of the power converter 100 includes an energy transfer element 106, a primary winding 108 of the energy transfer element 106, a secondary winding 110 of the energy transfer element 106, a power switch SI 112, an input return 111, an active clamp circuit 104, an output rectifier Dl 114 (also referred to as an output diode Dl), an output capacitor C2 116, an output return 117, a sense circuit 120, a controller 122, and a driver circuit 166. The active clamp circuit 104 is shown including a clamp capacitance CI 128 and a clamp switch 130 (represented as a transistor with an associated anti- parallel diode). Controller 122 is shown as including a regulation control circuit 124 and a clamp control circuit 126. Further illustrated is an uncoupled inductor L_LK 132, which may represent the leakage inductance associated with the energy transfer element 106 or a discrete inductor. In dashed lines, a capacitance Cp 133 is shown to represent all the capacitance that couples to the power switch SI 112 and may include natural capacitance internal to the energy transfer element 106, the natural internal capacitance of power switch SI 112 and/or discrete capacitors. Also shown in FIG. 1A are an input voltage Vnsr 102, an output voltage Vo 134, an output current Io 135, an output quantity Uo 136, a feedback signal U_FB 137, a current sense signal 136, a switch current ID 138, a drive signal UDR 140, an enable signal UEN 141 , a clamp drive signal UCD 142, a power switch voltage VDS 143, a primary voltage Vp 144, a leakage voltage VL 145, a clamp voltage Vci 146, clamp current ICL 147, and a secondary current Is 168. In the illustrated example, the power converter 100 is shown as having a flyback topology. It is appreciated that other known topologies and configurations of power converters may also benefit from the teachings of the present disclosure.

[0019] The power converter 100 provides output power to a load 1 18 from an

unregulated input Vnsr 102. In one embodiment, the input Vnsr 102 is a rectified and filtered ac line voltage. In another embodiment, the input voltage Vnsr 102 is a dc input voltage. The input Vnsr 102 is coupled to the energy transfer element 106. In some embodiments, the energy transfer element 106 may be a coupled inductor, transformer, or an inductor. The example energy transfer element 106 is shown as including two windings, a primary winding 108 (with Np number of turns) and secondary winding 1 10 (with Ns number of turns). However, the energy transfer element 106 may have more than two windings. The voltage across the primary winding 108 is illustrated as the primary voltage Vp 144 with the positive polarity at the dot end of the primary winding 108. When the power switch S I 1 12 is ON, the primary voltage Vp 144 is substantially equal to the negative sum of the input voltage Vnsr 102 and the leakage voltage VL 145, or mathematically: V_p = -(V_IN + V_L) . When the power switch S I 1 12 is OFF, the primary voltage Vp 144 is substantially equal to the reflected output voltage of the secondary winding 1 10. The primary winding 108 of the energy transfer element is further coupled to the power switch S 1 1 12 and the power switch S I 1 12 is further coupled to input return 1 1 1. The voltage across the power switched S I 1 12 is denoted as power switch voltage VDS 143 (which is also the voltage across the parasitic capacitance Cp 133). As shown, the uncoupled inductance LLK 132 may be coupled between the power switch S I 1 12 and the primary winding 108. The uncoupled inductance LLK 132 which may represent the leakage inductance associated with the energy transfer element 106 or a discrete inductor. The voltage across the uncoupled inductance LLK 132 may be denoted as the leakage voltage VL 145.

[0020] Coupled across the primary winding 108 and the uncoupled inductance LLK 132 is the active clamp circuit 104. The active clamp circuit 104 is shown as including clamp capacitance CI 128 and clamp switch 130 coupled in series. The voltage across the clamp capacitance CI 128 is denoted as the clamp voltage Vci 128 while the current in the clamp circuit is denoted as clamp current ICL 147. The active clamp circuit 104 limits the maximum voltage on the power switch S I 1 12 and control of the clamp switch 130 of the active clamp circuit 104 facilitates zero voltage switching of the power switch S I 1 12. In addition, the active clamp circuit 104 may reduce RMS current in the power converter 100. As will be further discussed, the active clamp circuit 104 is coupled to receive the clamp control signal UC_D 142 from the controller 122. Specifically, the clamp control signal UC_D 142 is received at a driver circuit 166 which drives the clamp switch 130 (illustrated as a transistor). The transistor of the clamp switch 130 is controlled to turn ON to inject current into the primary winding 108. The clamp switch 130 is turned ON for a first duration prior to the power switch SI 112 turning ON. In other words, the clamp switch 130 is not turned ON for the entire duration that the power switch SI 112 is turned off. At or near the beginning of the OFF time of the power switch SI 112, the anti-parallel diode of the clamp switch 130 conducts the charge associated with the uncoupled inductance L_LK 132 of the power converter 100. This charge from the uncoupled inductance L_LK 132 is transferred to the clamp capacitance CI 128 through the anti-parallel diode of clamp switch 130 and is stored. The anti-parallel diode stops conducting substantially after the net charge associated with uncoupled inductance L_LK 132 of the power converter 100 has been transferred. The clamp switch 130 remains OFF until near the end of the OFF time of the power switch SI 112. Once it is determined that the power switch should turn ON, the clamp switch 130 is turned on for a first duration of time. The transistor of the clamp switch 130 is turned on such that the net charge previously transferred to the clamp capacitance CI 128 associated with the uncoupled inductance L_LK 132 is transferred to the primary winding 108. As such, the energy associated with the uncoupled inductance L_LK 132 is returned to the system rather than being dissipated. In one example, the uncoupled inductance L_LK 132 represents the leakage inductance of the energy transfer element 106. The clamp switch 130 is controlled such that the leakage energy is reset and returned to the power converter rather than being dissipated.

[0021] Secondary winding 110 is coupled to the output rectifier Dl 114, which is exemplified as a diode. However, the output rectifier Dl 114 may be a transistor used as a synchronous rectifier. The current outputted from the secondary winding 110 is illustrated as secondary current Is 168. Output capacitor C2 116 is shown as being coupled to the output rectifier Dl 114 and the output return 117. The power converter 100 further includes circuitry to regulate the output, which is exemplified as output quantity Uo 136. In general, the output quantity Uo 136 is an output voltage Vo 134, and output current Io 135, or a combination of the two. A sense circuit 120 is coupled to sense the output quantity Uo 136 and to provide the feedback signal U_FB 137, which is representative of the output quantity Uo 136.

[0022] As shown, the controller 122 is coupled to receive the feedback signal U_FB 137. The controller 122 is also coupled to receive the current sense signal 139 and provides the drive signal U_DR 140 and the clamp drive signal UC_D 142. The current sense signal 139 may be representative of the drain current I_D 138 which is received by the power switch SI 112 and may be a voltage signal or a current signal. In addition, the controller 122 provides drive signal U_DR 140 to the power switch SI 112 to control various switching parameters to control the transfer of energy from the input of power converter 100 through the energy transfer element 106 to the output of power converter 100. Examples of such parameters may include switching frequency (or period), duty cycle, ON and OFF times of the power switch SI 112, or varying the number of pulses per unit time of the power switch SI 112. In addition, the power switch SI 112 may be controlled such that it has a fixed switching frequency or a variable switching frequency. In one example of variable switching frequency control, the switching frequency may be reduced for light-load or no-load conditions. Previously, it was difficult to achieve zero voltage switching (ZVS) for flyback converters at lower switching frequencies with conventional active clamp techniques where the clamp circuit is turned on for the entire off-time of the power switch. In addition, the clamp current would resonate and the RMS current would increase. However, embodiments of the present invention may be used in a converter operating with a variable switching frequency control. As will be further illustrated, this may be possible in part due to the clamping of the power switch voltage V_DS 143 during the off-time of the power switch SI 112 and the clamp current IC_L 147 being substantially equal to zero for a portion of the off-time of the power switch S 1 112.

[0023] Switch SI 112 is opened and closed in response to the drive signal U_DR 140. In operation, the switching of the switch SI 112 produces a pulsating secondary current Is 168 at the output rectifier Dl 114. The secondary current Is 168 is filtered by the output capacitor C2 116 to produce a substantially constant output voltage Vo 134, output current Io 135, or a combination of the two. In one example, the switch SI 112 may be a transistor such as a metal- oxide-semiconductor field-effect transistor (MOSFET). In another example, controller 122 may be implemented as a monolithic integrated circuit or may be implemented with discrete electrical components or a combination of discrete and integrated components. Controller 122 and switch SI 112 could form part of an integrated circuit that is manufactured as either a hybrid or monolithic integrated circuit.

[0024] Controller 122 includes the regulation control circuit 124 and the clamp control circuit 126. As shown, the regulation control circuit 124 is coupled to receive the current sense signal 139 and the feedback signal U_FB 137. The regulation control circuit 124 also outputs the drive signal U_DR 140, which controls the switching of the power switch SI 112, and the enable signal U_EN 141. In one example, the enable signal U_EN 141 may be representative of when the power switch SI 1 12 is going to be enabled (or turned ON). Or in other words, the enable signal U_EN 141 may be representative of a determination to turn ON the power switch SI 1 12.

[0025] Clamp control circuit 126 is coupled to receive the enable signal U_EN 141 and outputs the clamp drive signal UC_D 142. The clamp drive signal UC_D 142 controls various switching parameters of the clamp switch 130, such as the ON or OFF times of the clamp switch 130. In one example, the clamp drive signal UC_D 142 controls the amount of current provided to the primary winding 108 such that the net charge associated with the uncoupled inductor L_LK 132 is transferred to the primary winding 108. In one example, in response to the enable signal U_EN 141 , the clamp control circuit 126 outputs the clamp drive signal UC_D 142 to turn ON the clamp switch 130 for the first duration T_A. The regulation control circuit 124 is further coupled to receive the clamp drive signal UC_D 142. In operation, the regulation control circuit 124 does not turn ON the power switch SI 1 12 until the second duration T_B has passed after the clamp switch 130 has turned OFF.

[0026] The first duration T_A may be selected such that sufficient charge is provided from clamp circuit 104 to the primary winding 108, which will be used to discharge the parasitic capacitance Cp 133. As mentioned above, the net charge to be transferred to the primary winding 108 (and ergo current) is substantially the same as the amount of charge that was transferred from the uncoupled inductor L_LK 132 to the clamp capacitance CI 128. As such, a shorter first duration T_A corresponds to a larger switch voltage V_DS 143 on the power switch SI 1 12. Too large of a voltage V_DS 143 may damage the power switch. However, the longer the first duration T_A, the higher the root-mean-square (RMS) current experienced by the power converter. In one example, the first duration T_A of time that the clamp switch 130 is turned on may be selected to be substantially equal to the duration of time during which the anti-parallel diode of the clamp switch 130 conducts. The second duration T_B of time that power switch SI 1 12 is delayed to be turned on may be selected to provide sufficient time for the power switch voltage V_DS 143 to fall to substantially zero (or in other words, to provide sufficient time for the parasitic capacitance Cp 133 to discharge completely to the primary winding 108) before power switch SI 1 12 is turned on.

[0027] Both the drive signal U_DR 140 and the clamp drive signal UC_D 142 are rectangular pulse waveforms with varying lengths of logic high and logic low sections. In one example, logic high may correspond to an ON switch while logic low may correspond to an OFF switch. The clamp control circuit 126 may output a logic high value for the clamp drive signal UC_D 142 for the first duration T_A in response to the enable signal U_EN 141 (indicating that the power switch SI 1 12 should be turned ON). Once the clamp drive signal UC_D 142 falls to a logic low value, the regulation control circuit 124 transitions the drive signal U_DR 140 from a logic low to a logic high value a second duration T_B after the clamp drive signal UC_D 142 has transitioned to a logic low value.

[0028] Although a single controller is illustrated in FIG. 1A, it should be appreciated that multiple controllers may be utilized by the power converter 100. In addition, the regulation control circuit 124 and the clamp control circuit 126 need not be within a single controller.

Further, portions of the regulation control circuit 124 need not be within a single controller. For example, the power converter 100 may have a primary controller coupled to the input side of the power converter 100 and a secondary controller coupled to the output side of the power converter 100. In one example, the circuit within the regulation control circuit 124 which receives the feedback signal and generates the enable signal may be in the secondary controller.

[0029] FIG. IB illustrates a diagram 100 of current through the power switch SI 112 for various modes of control including a switching period Ts 148, a switch on-time toN 149, a switch off-time toEF 150, trapezoidal shape 151, and triangular shape 152. FIG. IB illustrates the general waveforms of the current through the power switch SI 112 over time in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

[0030] During any switching period Ts 148, switch SI 112 may conduct in response to the drive signal U_DR 140 from the controller 122 to regulate the output Uo 136. The switching period Ts 148 may be separated into two sections of time: switch on-time toN 149 and switch off- time toFF 150. Switch on-time toN 149 denotes the portion of the switching period Ts 148 which the switch SI 112 is conducting. Switch off-time toFF 150 denotes the remaining portion of the switching period Ts 148 when the switch SI 110 is not conducting. The current waveform of FIG. IB shows two fundamental modes of operation. The trapezoidal shape 151 is characteristic of continuous conduction mode (CCM), whereas the triangular shape 152 is characteristic of discontinuous conduction mode (DCM). During CCM, the current through the power switch SI 112 is substantially non-zero immediately after the start of the switch on-time toN 149 and steadily increases throughout the switch on-time toN 149. During DCM, the current through the power switch SI 112 is substantially zero at the beginning of the switch on-time toN 149, and steadily increases from zero throughout the switch on-time toN 149. In the examples, the active clamp circuit 104 may be used with a controller that operates in both CCM and DCM.

[0031] FIG. 2 illustrates a timing diagram 200 of example waveforms of the switch current ID 238, drive signal UDR 240, enable signal UEN 241, clamp drive signal UCD 242, power switch voltage VDS 243, drain current ID 238, clamp current ICL 247, and secondary current Is 268, which correspond to the similarly named and numbered elements also shown in FIG. 1A. [0032] The drive signal UDR 240, enable signal UEN 241 , and clamp drive signal UCD 242 are rectangular pulse waveforms of varying lengths of logic high and logic low sections. Logic high and logic low values for the drive signal U_DR 240, and the clamp drive signal UC_D 242 denote when the power switch SI 1 12 and clamp switch 130 are ON or OFF, respectively. As shown, the duration of time that drive signal U_DR 240 is logic high is denoted as the on-time TON 249 of the power switch, and the duration of time that the drive signal U_DR 240 is logic low is denoted as the off-time TOFF 250.

[0033] At time to 253, the drive signal U_DR 240 transitions to a logic high value and the power switch SI 1 12 is turned ON. As shown, the switch current I_D 238 begins to increase from a non-zero value (indicating that the controller and power switch SI 1 12 are operating in CCM). The rate which the switch current I_D 238 increases is partially determined by the input voltage Vnsr 102 and the inductance of the primary winding 108. For the example shown, the switch current I_D 238 increases until the current limit I_LF 267 is reached at time ti 254, which will cause the drive signal U_DR 240 to turn off the power switch SI 1 12. Thus, at time ti 254, the drive signal U_DR 240 transitions to a logic low value and the power switch SI 1 12 is turned OFF. During the on-time TON 249, the enable signal UEN 241 and clamp drive signal UCD 242 are substantially logic low, while the power switch voltage V_DS 243, clamp current IC_L 247, and a secondary current Is 268 are substantially equal to zero.

[0034] When the power switch SI 1 12 turns OFF, current is induced in the secondary winding 1 10 and the voltage on the secondary winding 1 10 is high enough that output rectifier Dl 1 14 begins to conduct and the secondary current Is 268 increases from substantially zero. In addition, when the power switch SI 1 12 is off, the output voltage across the secondary winding 1 10 is reflected to the primary winding 108, and the switch voltage V_DS 243 therefore also increases due to the charging of the parasitic capacitance Cp 133. The switch current I_D 238 (which is the current at the drain of the power switch when the power switch is a transistor), the switch current I_D 238 decreases to substantially zero.

[0035] At time t₂ 255, the switch voltage V_DS 243 increases to a high enough voltage that forward biases the anti-parallel diode of the clamp switch 130. The clamp current IC_L 247 is substantially non-zero (due to current which charged the parasitic capacitance Cp 133) and flows through the clamp switch 130 to the clamp capacitance CI 128. The direction of the clamp current IC_L 247 is indicated by the positive value of the clamp current IC_L 247 shown in FIG. 2. As illustrated, the peak value of the clamp current IC_L 247 is denoted as the peak reset current I_RS_T 268. The magnitude of the clamp current IC_L 247 decreases as charge is transferred from the uncoupled inductance L_LK 132 through the clamp switch 130 to the clamp capacitance CI 128. In one example, the anti-parallel diode conducts the clamp current IC_L 247 to the clamp capacitance C I 128 for a duration of time that is substantially equal to a reset duration T_RS_T 269, as shown in FIG. 2. In one example, the length of time T_RS_T 269 is substantially equal to the first duration TA 259.

[0036] The switch voltage V_DS 243 is substantially equal to the sum of the clamp voltage Vci 146 and the input voltage Vnsr 102, or mathematically: V_DS = V_cl + V_IN . In addition, the peak clamp voltage Vci 146 is substantially equal to the sum of the primary voltage Vp 144 and the leakage voltage V_L 145, or mathematically: V_cl = V_P +V_L . The duration between time t₃ 256 and time t₂ 255 is referred to the reset duration TRST 269. In one example, the reset duration TRST 269 is substantially the conduction time of the anti-parallel diode of the clamp switch 130 when the anti-parallel diode conducts the clamp current IC_L 247 to the clamp capacitance CI 128. During the reset duration T_RS_T 269, the net charge associated with the uncoupled inductance L_LK 132 is transferred to and stored by clamp capacitance CI 128. As such, during the reset duration T_RS_T 269, the clamp voltage Vci 146 (and ergo the switch voltage V_DS 243) increases as the leakage voltage VL 145 decreases.

[0037] At time t₃ 256 at the end of the T_RS_T 269 duration, the net charge from the uncoupled inductance L_LK 132 is transferred to and stored by clamp capacitance C I 128 and the anti-parallel diode ceases conduction. As illustrated, just prior to time t₃ 256, the switch voltage V_DS 243 has reached the peak value as the charge from the uncoupled inductance L_LK 132 has transferred to the clamp capacitance C I 128. Further, the clamp current IC_L 247 is substantially equal to zero and the leakage voltage V_L 145 is substantially zero. During the off-time TO_FF 250 of the power switch S I 112, the primary voltage Vp 144 is substantially equal to the reflected output voltage of the power converter. The reflected output voltage is determined by the turns ratio between the primary winding 108 and the secondary winding 110 (Np and Ns) and the output voltage Vo 134. At time t₃ 256, the clamp voltage Vci 146 is high enough such that the anti-parallel diode of the clamp switch 130 is reverse biased and does not conduct. As such, the switch voltage V_DS 243 decreases and is substantially clamped to the sum of the primary voltage Vp 144 and the input voltage Vnsr 102 (since the leakage voltage V_L 145 is substantially equal to zero at this time), or mathematically: V_DS = V_p +V_IN . The difference between the peak value of the switch voltage V_DS 243 during the reset duration T_RS_T 269 and the clamped value of the switch voltage V_DS 243 after time t₃ 256 is substantially the value of the leakage voltage V_L 245 at time t₂ 255 (which, in some examples is the maximum value of the leakage voltage V_L 245). [0038] Typical active clamp circuits would turn on the clamp switch 130 (turn on the transistor shown in FIG. 1A) after the anti-parallel diode of the clamp switch 130 has stopped conducting (for this example, at time t₃ 256). Previously, turning on the clamp switch after the anti-parallel diode has stopped conducting could lead the clamp current IC_L to resonate and increase the RMS current which made zero voltage switching difficult to achieve for flyback converters operating at a low switching frequency. However, in accordance with examples of the present invention, the clamp switch 130 is not turned on until near the end of the off-time TO_FF 250. As such, zero voltage switching can be achieved for a variable frequency converter and the RMS currents may be reduced.

[0039] At time U 251, the regulation control circuit 124 has determined that the power switch S I 112 should turn on. As such, the enable signal U_EN 241 transitions to the logic high value, and the clamp control circuit 126 outputs a logic high value for the clamp drive signal UC_D 242. The clamp drive signal UC_D 242 remains logic high for the first duration T_A 259, which may also be referred to as a charge duration and illustrated in FIG. 2 as the duration of time between time t₄ 257 and t₅ 258. The magnitude of the clamp current IC_L 247 begins to increase as the clamp current IC_L 247 flows from the clamp capacitance CI 128 through the clamp switch 130. The direction of the clamp current IC_L 247 is indicated by the negative value of the clamp current IC_L 247 as shown in FIG. 2. The switch voltage V_DS 243 also increases to the sum of the clamp voltage Vci and the input voltage V_M.

[0040] The duration between time t₄ 257 and time t₅ 258 is illustrated as the first duration T_A 259. During the first duration T_A 259, charge is transferred from the clamp capacitance CI 128 to the primary winding 108. The first duration T_A 259 may be selected such that the net charge associated with the uncoupled inductance L_LK 132 that was previously transferred to and stored by clamp capacitance C I 128 during the reset duration T_RS_T 269 is transferred to the primary winding 108 during first duration T_A 259. As shown, at the beginning of the first duration T_A 259, the switch voltage V_DS 243 is substantially equal to the sum of the clamp voltage Vci 146 and the input voltage Ym and decreases as the charge on the clamp capacitance CI 128 is transferred to the primary winding 108. The peak magnitude of the clamp current IC_L 247 during the first duration T_A 259 is substantially the peak charge current IC_HG 270. In addition, during the first duration T_A 259, a spike may be present on the secondary current Is 268. In one example, if the first duration T_A 259 is less than the conduction time of the anti- parallel diode of the clamp switch 130, the switch voltage V_DS 243 would increase to a value higher than the sum of the clamp voltage Vci 146 and the input voltage V_IN 102. If the first duration T_A 259 is greater than the conduction time of the anti-parallel diode of the clamp switch 130, the switch voltage VDS 243 would increase to a lower value than the sum of the clamp voltage Vci 146 and the input voltage Vnsr 102.

[0041] To illustrate, the net charge during the reset duration TRST 269 is substantially equal to the product of the peak reset current IRST 268 and the reset duration TRST 269. The net charge during the first duration TA 259 is substantially equal to the product of the peak charge current ICHG 270 and the first duration TA 259. In a steady condition, the amount of net charge transferred to the clamp capacitance CI 128 during the reset duration TRST 269 should equal to the amount of charge transferred from the CI 128 during the first duration TA 259, or mathematically: I_RST xT_RST = I_CHG xT_A . As mentioned above, during the off-time the primary voltage Vp is substantially constant value equal to the reflected output voltage of the power converter. Further, the clamp voltage Vci is also a substantially constant value once the charge has been transferred. As such, the voltage applied to the uncoupled inductance LLK 132 is substantially the leakage voltage VL 245 and the difference between the peak value of the switch voltage VDS 243 and the clamped value of the switch voltage VDS 243 is substantially the leakage voltage VL 245. Since the amount of charge is the same during the reset duration and the first

V T V T

duration, ^{L RST} = ^{L A} . As such, in one example the first duration TA 259 is substantially

2L_LK 2L_LK

equal to the reset duration TRST 269. Further, if the first duration TA 259 is and the reset duration TRST 269 are substantially equal, the peak reset current IRST 268 and the peak charge current ICHG 270 are also substantially equal. In addition, the leakage voltage VL 245 is a function of the peak reset current IRST 268, uncoupled inductance LLK 132, and the first duration TA 259, or mathematically: V_L = L_LK χ^- .

[0042] At time t₅ 258 (end of the first duration T_A 259), the clamp drive signal UCD 242 transitions to a logic low value and the clamp switch 130 is turned off. The second duration TB 260 delay begins and the switch voltage VDS 243 decreases as the parasitic capacitance Cp 133 is discharged. The discharging of the parasitic capacitance Cp 133 is also illustrated by the negative value of the drain current ID 238. Second duration TB 260 may be selected such that there is sufficient time for the parasitic capacitance Cp 133 to completely discharge and the power switch voltage VDS 243 to fall to substantially zero before the power switch S I 1 12 is turned on. Further, the secondary current Is 268 begins to decrease.

[0043] At time t₆ 270 (end of the second duration TB 260), the drive signal UDR 240 transitions to a logic high value and the power switch S I 1 12 is turned on. The primary current Ip 238 is substantially non-zero while the secondary current Is 268 is substantially equal to zero. As such, the energy associated with the uncoupled inductance (i.e. leakage inductance) is returned to the system rather than being dissipated.

[0044] FIG. 3 illustrates a functional block diagram of an example controller 322, which is one example of the controller 122 of FIG. 1 A, including the regulation control circuit 324 and the clamp control circuit 326. As shown, the regulation control circuit 324 includes an enable circuit 361 , a latch 362, a comparator 363, and a delay circuit 364. The clamp control circuit 326 is shown as including a monostable multivibrator 365, which is also referred to as a one-shot.

[0045] Although a single controller is illustrated, it should be appreciated that multiple controllers may be utilized by the power converter. In addition, the regulation control circuit 324 and the clamp control circuit 326 need not be within a single controller. Further, portions of the regulation control circuit 324 need not be within a single controller. For example, the power converter may have a primary controller coupled to the input side of the power converter and a secondary controller coupled to the output side of the power converter. In one example, the enable circuit 361 may be in the secondary controller and the feedback signal U_FB 337 may be received by the enable circuit 361 in the secondary controller. The enable circuit 361 may send the enable signal U_EN 341 via a communication link to the primary controller.

[0046] As shown in FIG. 3, the enable circuit 361 may be coupled to receive the feedback signal U_FB 337 and output the enable signal U_EN 341. In one example, the enable signal U_EN 341 may be representative of a determination to turn on (i.e., "enable") the power switch. The enable circuit 361 may determine to turn on the power switch S I 1 12 in response to the feedback signal U_FB 337. For example, the enable circuit 361 may include a comparator which is coupled to receive the feedback signal U_FB 337 and a reference. When the feedback signal U_FB 337 falls below the reference, the enable circuit 361 may determine to turn on the power switch S I 1 12 and the enable circuit may output a pulse in the enable signal U_EN 341.

[0047] The monostable multivibrator 365 is coupled to receive the enable signal U_EN 341 and output the clamp drive signal UC_D 342. In response to a leading edge in the enable signal U_EN 341 , the monostable multivibrator 365 outputs a pulse for the first duration T_A of time. As such, the clamp switch 130 is turned on for the first duration T_A, at which time the net charge associated with the uncoupled inductance L_LK 132 that was previously transferred to and stored by clamp capacitance C I 128 during a previous reset duration T_RS_T 269 is transferred to the primary winding 108, as discussed in detail above. At the end of the first duration T_A, the clamp drive signal UC_D 342 transitions to a logic low value and the clamp switch 130 is turned off.

[0048] The latch 362 is coupled to receive the clamp drive signal UC_D 342 at the set- input. The small circle at the set-input of the latch 362 represents an inverter and indicates that the latch 362 is set at the falling edge of the clamp drive signal UC_D 342. Or in other words, the Q-output of the latch 362 transitions to a logic high value when the clamp drive signal UC_D 342 transitions to a logic low value. The output of the latch 362 is further coupled to be received by the delay circuit 364. The output of the delay circuit 364 is the drive signal U_DR 340. As shown, the delay circuit 364 delays the output of the latch 362 for second duration, T_B, of time.

[0049] The latch 362 is also coupled to receive the output of comparator 363 at the reset- input. As shown, the comparator 363 is coupled to receive the current limit I_LIM 367 (at the inverting input) and the current sense signal 339 (representative of the switch current I_D at the non-inverting input). When the current sense signal 339 (and as such the switch current I_D) reaches the current limit I_LIM 367, the output of the comparator 363 is logic high and the latch 362 is reset. As such, the drive signal U_DR 340 transitions to a logic low value and turns off the power switch S I 1 12.

[0050] The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.

Claims

CLAIMS What is claimed is:

1. A controller for use in a power converter, comprising:

a regulation control circuit coupled to generate a drive signal in response to a feedback signal representative of an output of the power converter to control switching of a power switch coupled to an energy transfer element to control a transfer of energy from an input of the power converter to the output of power converter, wherein the regulation circuit includes an enable circuit coupled to generate an enable signal in response to the feedback signal, wherein the enable signal is representative of a determination to turn on the power switch; and

a clamp control circuit coupled to generate a clamp drive signal in response to the enable signal from the regulation control circuit to control switching of a clamp switch included in a clamp circuit coupled to the energy transfer element and the power switch, wherein the clamp drive signal is coupled to turn on the clamp switch for a first duration near an end of an off time of the power switch to in response to the determination to turn on the power switch.

2. The controller of claim 1, wherein the clamp control circuit is further coupled to control the clamp switch to inject charge stored in the clamp circuit into the energy transfer element to discharge a parasitic capacitance of the power switch into the energy transfer element before the power switch is turned on.

3. The controller of claim 1, wherein the regulation control circuit is further coupled to receive the clamp drive signal from the clamp control circuit, wherein the regulation circuit further includes a delay circuit coupled to output the drive signal in response to the clamp drive signal, wherein the delay circuit is coupled to delay turning on the power switch a second duration after the first duration to provide sufficient time for the parasitic capacitance of the power switch to be discharged into the energy transfer element before the power switch is turned on.

4. The controller of claim 3, wherein the regulation circuit further includes a latch coupled between the clamp control circuit and the delay circuit, wherein the latch is coupled to be set in response to the clamp drive signal from the clamp circuit to generate the drive signal received by the delay circuit.

5. The controller of claim 4, wherein the regulation control circuit is further coupled to receive a current sense signal representative of a switch current through the power switch, wherein the latch is coupled to be reset in response to the current sense signal indicating that the switch current reaches a current limit to cause the drive signal to turn off the power switch.

6. The controller of claim 5, wherein the regulation control circuit further includes a comparator coupled to receive the current sense signal and a current limit signal, wherein an output of the comparator is coupled to reset the latch.

7. The controller of claim 1, wherein the clamp control circuit includes a monostable multivibrator coupled to generate the clamp drive signal in response to the enable signal, wherein the monostable multivibrator is coupled to output a pulse for the first duration in response to a leading edge in the enable signal.

8. The controller of claim 1 wherein the clamp drive signal is coupled to turn on the clamp switch for the first duration near the end of the off time of the power switch to inject the charge stored in a clamp capacitance of the clamp circuit to a primary winding of the energy transfer element, wherein the charge stored in the clamp capacitance is previously transferred at or near a beginning of the off time of the power switch through an anti-parallel diode associated with the clamp switch from a leakage inductance of the power converter, wherein the clamp switch and the anti-parallel diode of the clamp switch are coupled between the clamp

capacitance, and the primary winding and the power switch.

9. The controller of claim 8, wherein the anti-parallel diode associated with the clamp switch is coupled to conduct a clamp current to transfer the charge from the leakage inductance to the clamp capacitance while the anti-parallel diode is forward biased at or near the beginning of the off time of the power switch for a duration substantially equal to the first duration.

10. The controller of claim 8 wherein no current is conducted through the clamp switch or the anti-parallel diode associated with the clamp switch during the off time of the power switch after the charge from the leakage inductance has been transferred to the clamp

capacitance through the anti-parallel diode at or near the beginning of the off time of the power switch, and before the clamp switch is turned on near the end of the off time of the power switch to inject the charge stored in the clamp capacitance into the primary winding.

11. A power converter, comprising:

an energy transfer element coupled between an input of the power converter and an output of the power converter;

a power switch coupled to the energy transfer element;

an active clamp circuit coupled to the energy transfer element and the power switch; and a controller coupled to the active clamp circuit and the power switch, wherein the controller wherein the controller includes:

a regulation control circuit coupled to generate a drive signal in response to a feedback signal representative of the output of the power converter to control switching of the power switch to control a transfer of energy from the input of the power converter to the output of power converter, wherein the regulation circuit includes an enable circuit coupled to generate an enable signal in response to the feedback signal, wherein the enable signal is representative of a determination to turn on the power switch; and

a clamp control circuit coupled to generate a clamp drive signal in response to the enable signal from the regulation control circuit to control switching of a clamp switch included in the active clamp circuit, wherein the clamp drive signal is coupled to turn on the clamp switch for a first duration near an end of an off time of the power switch in response to the

determination to turn on the power switch.

12. The power converter of claim 11, wherein the regulation control circuit is further coupled to receive the clamp drive signal from the clamp control circuit, wherein the regulation circuit further includes a delay circuit coupled to output the drive signal in response to the clamp drive signal, wherein the delay circuit is coupled to delay turning on the power switch a second duration after the first duration to provide sufficient time for a parasitic capacitance of the power switch to be discharged into the energy transfer element before the power switch is turned on.

13. The power converter of claim 12, wherein the regulation circuit further includes a latch coupled between the clamp control circuit and the delay circuit, wherein the latch is coupled to be set in response to the clamp drive signal from the active clamp circuit to generate the drive signal received by the delay circuit.

14. The power converter of claim 13, wherein the regulation control circuit is further coupled to receive a current sense signal representative of a switch current through the power switch, wherein the latch is coupled to be reset in response to the current sense signal indicating that the switch current reaches a current limit to cause the drive signal to turn off the power switch.

15. The power converter of claim 14, wherein the regulation control circuit further includes a comparator coupled to receive the current sense signal and a current limit signal, wherein an output of the comparator is coupled to reset the latch.

16. The power converter of claim 11, wherein the clamp control circuit includes a monostable multivibrator coupled to generate the clamp drive signal in response to the enable signal, wherein the monostable multivibrator is coupled to output a pulse for the first duration in response to a leading edge in the enable signal.

17. The power converter of claim 11, wherein the active clamp circuit further includes: a clamp capacitance coupled to the clamp switch, wherein the clamp capacitance is coupled to store the charge that is injected into a primary winding of the energy transfer element through the clamp switch in response to the clamp drive signal; and

an anti-parallel diode associated with the clamp switch, wherein the clamp switch and the anti-parallel diode associated with the claim switch are coupled between the clamp capacitance, and the energy transfer element and the power switch.

18. The power converter of claim 17, wherein the charge stored in the clamp capacitance of the active clamp circuit that is injected into the primary winding is previously transferred at or near a beginning of the off time of the power switch through the anti-parallel diode associated with the clamp switch from a leakage inductance of the power converter.

19. The power converter of claim 18, wherein the anti-parallel diode associated with the clamp switch is coupled to conduct a clamp current to transfer the charge from the leakage inductance to the clamp capacitance while the anti-parallel diode is forward biased at or near the beginning of the off time of the power switch for a duration substantially equal to the first duration.

20. The power converter of claim 18 wherein no current is conducted through the clamp switch or the anti-parallel diode associated with the clamp switch during the off time of the power switch after the charge from the leakage inductance has been transferred to the clamp capacitance through the anti-parallel diode at or near the beginning of the off time of the power switch, and before the clamp switch is turned on near the end of the off time of the power switch to inject the charge stored in the clamp capacitance into the primary winding.

21. The power converter of claim 18, wherein the energy transfer element further includes an uncoupled inductance coupled between the active clamp circuit and the primary winding.

22. The power converter of claim 21, wherein the uncoupled inductance is representative of the leakage inductance of the power converter.

23. A controller for use in a power converter, comprising:

a clamp control circuit coupled to generate a clamp drive signal in response to the enable signal, wherein the clamp control circuit is coupled to control switching of a clamp switch included in a clamp circuit coupled to an energy transfer element and the power switch, wherein the clamp drive signal controls the clamp switch such that the clamp switch stores a leakage energy of the energy transfer element to the clamp circuit and returns the leakage energy to the energy transfer element.

24. The clamp control circuit of claim 23, wherein the clamp control circuit is coupled to turn on the clamp switch for a first duration near an end of an off time of the power switch in response to the determination to turn on the power switch, wherein during the first duration the leakage energy is returned to the energy transfer element.

25. The clamp control circuit of claim 23, circuit wherein the clamp control circuit is coupled to turn on the clamp switch for a first duration near an end of an off time of the power switch to in response to the determination to turn on the power switch, wherein during the first duration the leakage energy is returned the energy transfer element, wherein the leakage energy was previously stored in a clamp capacitance at near or beginning of the off time of the power switch through an anti-parallel diode associated with the clamp switch.

26. The clamp control circuit of claim 25, wherein the anti-parallel diode associated with the clamp switch is coupled to conduct a clamp current to transfer the charge from the leakage inductance to the clamp capacitance while the anti-parallel diode is forward biased at or near the beginning of the off time of the power switch.

27. The clamp control circuit of claim 23, wherein the regulation control circuit controls the power switch in a variable switching frequency mode.