WO2017092449A1 - Module de puissance intelligent et climatiseur - Google Patents

Module de puissance intelligent et climatiseur Download PDF

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Publication number
WO2017092449A1
WO2017092449A1 PCT/CN2016/097738 CN2016097738W WO2017092449A1 WO 2017092449 A1 WO2017092449 A1 WO 2017092449A1 CN 2016097738 W CN2016097738 W CN 2016097738W WO 2017092449 A1 WO2017092449 A1 WO 2017092449A1
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WIPO (PCT)
Prior art keywords
gate
input
input end
output
power module
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PCT/CN2016/097738
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English (en)
Chinese (zh)
Inventor
冯宇翔
Original Assignee
广东美的制冷设备有限公司
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Publication date
Priority claimed from CN201510863297.9A external-priority patent/CN105356786B/zh
Priority claimed from CN201520978827.XU external-priority patent/CN205123615U/zh
Priority claimed from CN201610126190.0A external-priority patent/CN105577017B/zh
Priority claimed from CN201620169940.8U external-priority patent/CN205453539U/zh
Application filed by 广东美的制冷设备有限公司 filed Critical 广东美的制冷设备有限公司
Publication of WO2017092449A1 publication Critical patent/WO2017092449A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Definitions

  • the present invention relates to the field of intelligent power module technologies, and in particular, to an intelligent power module and an air conditioner.
  • Intelligent Power Module is a power driver that integrates power electronic discrete devices and integrated circuit technology.
  • the intelligent power module includes power switching devices and high voltage driving circuits with overvoltage and overcurrent. And fault detection circuits such as overheating.
  • the logic input of the intelligent power module receives the control signal of the main controller, and the output drives the compressor or the subsequent circuit to work, and sends the detected system status signal back to the main controller.
  • the intelligent power module has the advantages of high integration, high reliability, self-test and protection circuit, especially suitable for driving the inverter of the motor and various inverter power sources. It is frequency conversion speed regulation, metallurgical machinery and electric power. Ideal power electronics for traction, servo drive, and variable frequency home appliances.
  • the structure diagram of the existing intelligent power module circuit is shown in Figure 1, and the MTRIP port is used.
  • the current detecting terminal is configured to protect the smart power module 100 according to the detected current magnitude.
  • the PFCIN port serves as the PFC (Power Factor Correction) control input of the intelligent power module.
  • the PFCINP terminal frequently switches between high and low levels according to a certain frequency, so that the IGBT tube 127 is continuously in the switching state and the FRD tube 131 is continuously in the freewheeling state, and the frequency is generally LIN1 to LIN3, HIN1 ⁇ HIN3 switching frequency is 2 to 4 times, and is not directly related to the switching frequency of LIN1 ⁇ LIN3, HIN1 ⁇ HIN3.
  • ITRIP is a current detecting terminal. It is generally grounded through a milliohm resistor. The current is measured by detecting the voltage drop of the milliohm resistor. When the current is too large, the intelligent power module 100 stops working to avoid overheating due to overcurrent. 100 produces permanent damage.
  • the voltage noise at the time of switching of the IGBT tube 121 to the IGBT tube 127 and the current noise when the FRD tube 111 to the FRD tube 116 and the FRD tube 131 are freewheeling are coupled to each other, and affect the input pins of the respective low voltage regions.
  • the thresholds of HIN1 to HIN3, LIN1 to LIN3, and PFCINP are generally around 2.3V, and the threshold voltage of ITRIP is generally only 0.5V or less. Therefore, ITRIP is the most susceptible pin.
  • the intelligent power module 100 When the ITRIP is triggered, the intelligent power module 100 will stop working, and since the overcurrent does not really occur at this time, the trigger of the ITRIIP at this time is a false trigger.
  • the voltage noise of the FRD transistors 111-116 and the FRD tube 141 when the reverse recovery current spike is coupled to the ground line during reverse recovery is most likely to cause such false triggering.
  • the FRD tubes 114 to 116, the FRD tubes 111 to 113, and the FRD tube 141 respectively generate reverse recovery current spikes, and the MTRIP terminal is generated.
  • Voltage noise in general, the longer the duration of the spike and the longer the reverse recovery time, the longer the noise duration of the MTRIP, the larger the peak value of the spike, that is, the larger the reverse recovery current, the more the noise amplitude of the MTRIP Big. Also, because the reverse recovery time and reverse recovery current of the FRD tube increase with respect to temperature.
  • MTRIP trigger the condition: voltage>Vth, and duration>Tth; in Figure 2, if Ta ⁇ Tth ⁇ Tb, then the reverse recovery current of FRD tube is not enough to cause MTRIP to false trigger at 25°C. High voltage duration of the first three cycles of the FRD tube at 75 ° C Too short is not enough to cause MTRIP to trigger falsely. By the fourth cycle, MTRIP will generate false triggers.
  • the length of the reverse recovery time of the FRD tube is related to the temperature. The higher the temperature, the longer the reverse recovery time. When the temperature is higher, the inverter part of the intelligent power module and the power correction part switch are more frequent. Therefore, as the system continues to work, the temperature of the intelligent power module 100 continues to rise, and the probability of the MTRIP being triggered is increasing. In some severe applications, the false trigger will eventually occur, and the system will stop working.
  • the present invention aims to solve at least one of the technical problems existing in the prior art or related art.
  • an object of the present invention is to provide a new intelligent power module, which can effectively reduce the probability of the intelligent power module being falsely triggered at a high temperature and improve the intelligent power module under normal operating conditions. The reliability of the intelligent power module.
  • Another object of the present invention is to provide an air conditioner having the intelligent power module.
  • an intelligent power module comprising: a three-phase upper arm signal input end, a three-phase lower arm signal input end, and a three-phase low voltage reference end.
  • HVIC High Voltage Integrated Circuit
  • the HVIC tube is provided with a signal input end connected to the three-phase upper arm and a three-phase lower bridge respectively a terminal of the arm signal input end, and a first port corresponding to the current detecting end and a second port corresponding to the PFC control input end, the first port is connected to the current detecting end through a connecting line, the first The two ports are connected to the PFC control input through a connection line; the sampling resistor, the three-phase low voltage reference And the current detecting end is connected to the first end of the sampling resistor, the second end of the sampling resistor is connected to the low voltage power supply negative end of the intelligent power module; an adaptive circuit, the adaptive The positive and negative poles of the power supply of the circuit are respectively connected to the positive end and the negative end of the low voltage power supply of the intelligent power module, and the first input end, the second input end and the third input end of the adaptive circuit are respectively connected to
  • the working mode of the adaptive circuit is any one of the following ways:
  • the adaptive circuit outputs the magnitude relationship between the value of the input signal of the eighth input end and the first set value when the input signals of the first input end to the seventh input end are all low level Corresponding level signal; when the input signal of the at least one input end of the first input end to the seventh input end is a high level, according to the temperature of the smart power module, the eighth A magnitude relationship between the value of the input signal at the input end and the second set value outputs a corresponding level signal, the second set value being greater than the first set value.
  • the adaptive circuit when the input signals of the adaptive circuit are low at the first input end to the seventh input end (ie, the three-phase upper arm signal input end, the three-phase lower arm signal input end, and the PFC control input end), Outputting a corresponding level signal according to a magnitude relationship between a value of the input signal of the eighth input terminal (ie, the current detecting terminal) and the first set value, so that the first input end to the seventh input end of the adaptive circuit
  • both are low level (that is, when the noise signal is not easy to generate)
  • the adaptive circuit can make a real-time response according to the signal value detected by the current detecting end, that is, when the signal value detected by the current detecting end is large, the output HVIC is output in time.
  • the enable signal for stopping the operation of the tube when the signal value detected by the current detecting end is small, outputting an enable signal for controlling the operation of the HVIC tube to ensure that the intelligent power module can work normally at normal temperature (ie, below a predetermined temperature value). And overcurrent protection.
  • the adaptive circuit is when the input signal of the at least one input end of the first input end to the seventh input end is a high level, if the temperature of the smart power module is higher than a predetermined temperature value, and the eighth When the value of the input signal at the input end is greater than or equal to the second set value, the enable signal of the first level is output; otherwise, the enable signal of the second level is output.
  • the first level enable signal may be a low level signal
  • the second level enable signal may be a high level signal
  • the adaptive circuit includes:
  • a first OR gate wherein the three inputs of the first OR gate respectively serve as a first input, a second input, and a third input of the adaptive circuit
  • a third OR gate the output of the first OR gate being coupled to the first input of the third OR gate, the output of the second OR gate being coupled to the second input of the third OR gate a third input end of the third OR gate as a seventh input end of the adaptive circuit, and an output end of the third OR gate is connected to an input end of the first NAND gate;
  • a first resistor a first end of the first resistor is connected to a positive pole of a power supply of the adaptive circuit, a second end of the first resistor is connected to a cathode of a Zener diode, and an anode of the Zener diode is connected a negative power supply to the adaptive circuit;
  • the first end of the second resistor is connected to the second end of the first resistor, The second end of the second resistor is connected to the positive input end of the first voltage comparator;
  • a thermistor a first end of the thermistor is connected to a second end of the second resistor, and a second end of the thermistor is connected to an anode of the Zener diode;
  • a cathode of the first voltage source is coupled to an anode of the Zener diode, a cathode of the first voltage source is coupled to a negative input terminal of the first voltage comparator, the first voltage
  • An output of the comparator is coupled to the second input of the first NAND gate, an output of the first NAND gate is coupled to an input of the first NOT gate, and an output of the first NOT gate is coupled To the control end of the analog switch;
  • a second voltage comparator a positive input terminal of the second voltage comparator serving as an eighth input terminal of the adaptive circuit, and a negative input terminal of the second voltage comparator being coupled to a positive terminal of the second voltage source a cathode of the second voltage source is connected to a negative power supply of the adaptive circuit, and an output of the second voltage comparator is connected to a first selection of the analog switch and a first input of a second NAND gate end;
  • a third voltage comparator a positive input terminal of the third voltage comparator is coupled to a positive input terminal of the second voltage comparator, and a negative input terminal of the third voltage comparator is coupled to a positive terminal of a third voltage source a negative electrode of the third voltage source is connected to a negative power supply of the adaptive circuit, and an output of the third voltage comparator is connected to a second input of the second NAND gate, the second The output of the NAND gate is connected to the input end of the second NOT gate, the output end of the second NOT gate is connected to the second selection end of the analog switch, and the fixed end of the analog switch is connected to the third NOT gate
  • the input of the third NOT gate serves as an output of the adaptive circuit.
  • the adaptive circuit is positively correlated with the temperature of the input signal of the eighth input terminal when the input signal from the first input terminal to the seventh input terminal is at a rising edge; the adaptive circuit is When the input signal from the first input end to the seventh input end is not at the rising edge, the filtering time of the input signal of the eighth input end is a fixed value;
  • the adaptive circuit outputs an enable signal of the first level to prevent the HVIC tube from operating when the voltage value of the input signal of the eighth input terminal is higher than a predetermined value and the duration exceeds the filtering time; otherwise And outputting a second level enable signal to allow the HVIC tube to operate.
  • the input signal to the current detecting end is made when the input signal of the adaptive circuit is at the rising edge of the three-phase upper arm signal input end, the three-phase lower arm signal input end, and the PFC control input end.
  • the filtering time is positively correlated with the temperature; so that the filtering time of the input signal of the current detecting end can be adjusted at the time when the temperature of the intelligent power module is most likely to cause the false triggering, thereby greatly reducing the current detecting end at a high temperature.
  • the filtering time of the input signal to the current detecting terminal is fixed.
  • the value is such that the sensitivity of the temperature detecting end can be ensured at other time points where the false triggering is not easy to occur, that is, when the voltage value of the input signal at the current detecting end is higher than a predetermined value and the duration exceeds the filtering time, the output prohibits the operation of the HVIC tube. a level of enable signal; otherwise, the output allows the second level of operation of the HVIC tube Signal, the intelligent power module to achieve reliable operation over the whole temperature range.
  • the first level enable signal may be a low level signal
  • the second level enable signal may be a high level signal
  • the adaptive circuit includes:
  • Seven pulse generating circuits wherein the input ends of the seven pulse generating circuits respectively serve as first input to seventh input of the adaptive circuit, and three pulses connected to the signal input end of the three-phase upper arm occur
  • the output ends of the circuit are respectively connected to the three input ends of the first OR gate, and the output ends of the three pulse generating circuits connected to the signal input end of the three-phase lower arm are respectively connected to the three input ends of the second OR gate;
  • a third OR gate an output of the first OR gate, an output of the second OR gate, and an output of a pulse generating circuit connected to the second port are respectively connected to the third OR gate
  • Three inputs, the output of the third OR gate is connected to the control end of the analog switch
  • a voltage comparator a positive input terminal of the voltage comparator serving as an eighth input terminal of the adaptive circuit, a negative input terminal of the voltage comparator being coupled to a positive pole of the first voltage source, the first voltage source a negative pole is used as a negative power supply of the adaptive circuit, and an output end of the voltage comparator is connected to a fixed end of the analog switch;
  • a first NOT gate wherein the input of the first NOT gate is connected to the first selection of the analog switch End, the output end of the first NOT gate is connected to the gate of the first NMOS transistor, and the substrate of the first NMOS transistor is connected to the source and then connected to the negative pole of the power supply of the adaptive circuit, An anode of the NMOS transistor is connected to the anode of the second voltage source, and a cathode of the second voltage source is connected to the anode of the power supply of the adaptive circuit;
  • the input end of the second NOT gate is connected to the anode of the second voltage source, and the output end of the second NOT gate is connected to the input end of the third NOT gate through the first thermistor,
  • the output end of the third NOT gate is connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is connected to the first input end of the first NOR gate;
  • a fifth NOT gate an input end of the fifth NOT gate is connected to an output end of the first NOT gate, an output end of the fifth NOT gate is connected to a gate of a second NMOS transistor, the second NMOS
  • the substrate of the tube is connected to the source and is connected to the negative pole of the power supply of the adaptive circuit, the drain of the second NMOS transistor is connected to the anode of the third voltage source, and the cathode of the third voltage source is connected to the cathode The positive pole of the power supply of the adaptive circuit;
  • a sixth NOT gate an input end of the sixth NOT gate is connected to a positive pole of the third voltage source, and an output end of the sixth NOT gate is connected to an input end of a seventh NOT gate through a second thermistor, The output end of the seventh NOT gate is connected to the input end of the eighth NOT gate, and the output end of the eighth NOT gate is connected to the first input end of the second NOR gate;
  • NOR gate the first input end of the third NOR gate is connected to the second input end of the first NOR gate and the output end of the second NOR gate, the first NOR An output of the gate is coupled to a second input of the second NOR gate, an output of the third NOR gate is coupled to an input of a ninth NOT gate, and an output of the ninth NOT gate is The output of the adaptive circuit;
  • any of the pulse generating circuits includes:
  • a sixth capacitor connected between the input end of the seventeenth gate and the negative pole of the power supply of the adaptive circuit
  • the HVIC tube is further provided with a signal output end of the PFC driving circuit
  • the smart power module further includes: a first power switch tube and a first diode, the first diode An anode of the tube is connected to an emitter of the first power switch tube, a cathode of the first diode is connected to a collector of the first power switch tube, and a collector of the first power switch tube is connected to An anode of the second diode, a cathode of the second diode is connected to a high voltage input of the smart power module, and a base of the first power switch is connected to a signal output of the PFC drive circuit
  • the emitter of the first power switch is used as the PFC low voltage reference end of the smart power module
  • the collector of the first power switch is used as the PFC end of the smart power module.
  • the first power switch tube can be an IGBT (Insulated Gate Bipolar) Transistor, insulated gate bipolar transistor).
  • IGBT Insulated Gate Bipolar
  • the smart power module further includes: a bootstrap circuit, the bootstrap circuit includes: a first bootstrap diode, an anode of the first bootstrap diode is connected to the smart power module a low voltage region power supply positive terminal, a cathode of the first bootstrap diode is connected to a positive phase of a U phase high voltage region power supply of the intelligent power module; a second bootstrap diode, an anode connection of the second bootstrap diode To the positive end of the low voltage power supply of the smart power module, the cathode of the second bootstrap diode is connected to the positive end of the V phase high voltage power supply of the intelligent power module; the third bootstrap diode, the third The anode of the bootstrap diode is connected to the positive end of the low voltage area power supply of the intelligent power module, and the cathode of the third bootstrap diode is connected to the positive end of the W phase high voltage power supply of the intelligent power module.
  • a bootstrap circuit includes: a first bootstrap di
  • the intelligent power module further includes: a three-phase upper arm circuit, wherein an input end of each phase upper arm circuit of the three-phase upper arm circuit is connected to the HVIC tube a signal output end of the corresponding phase in the three-phase high voltage region; a three-phase lower arm circuit, wherein the input end of each phase lower arm circuit of the three-phase lower arm circuit is connected to the three-phase low voltage of the HVIC tube The signal output of the corresponding phase in the zone.
  • the three-phase upper arm circuit includes: a U-phase upper arm circuit, a V-phase upper arm circuit, and a W-phase upper arm circuit;
  • the three-phase lower arm circuit includes: a U-phase lower arm circuit, and a V-phase lower bridge Arm circuit, W phase lower arm circuit.
  • each of the upper bridge arm circuits includes: a second power switch tube and a third diode, an anode of the third diode being connected to the second power switch tube An emitter, a cathode of the third diode is connected to a collector of the second power switch tube, and a collector of the second power switch tube is connected to a high voltage input end of the smart power module,
  • the base of the second power switch tube is used as an input end of the bridge circuit of each phase, and the emitter of the second power switch tube is connected to the negative end of the high voltage area power supply of the corresponding phase of the smart power module.
  • the second power switch tube can be an IGBT.
  • each phase lower arm circuit includes: a third power switch tube and a fourth diode, an anode of the fourth diode is connected to an emitter of the third power switch tube, a cathode of the fourth diode is connected to a collector of the third power switch tube, and a collector of the third power switch tube is connected to an anode of the third diode in the corresponding upper arm circuit,
  • the first The base of the three-power switch tube serves as an input end of the lower-side bridge arm circuit, and the emitter of the third power switch tube serves as a low-voltage reference terminal of a corresponding phase of the smart power module.
  • the third power switch tube may be an IGBT.
  • the voltage of the high voltage input of the intelligent power module is 300V.
  • a filter capacitor is connected between a positive end and a negative end of each phase high voltage power supply of the smart power module.
  • an air conditioner comprising: the intelligent power module as described in any of the above embodiments.
  • FIG. 1 is a schematic structural diagram of an intelligent power module in the related art
  • FIG. 2 is a waveform diagram showing noise generated by an intelligent power module in the related art
  • FIG. 3 is a schematic structural diagram of an intelligent power module according to an embodiment of the present invention.
  • FIG. 4 shows an external circuit schematic of an intelligent power module in accordance with an embodiment of the present invention
  • FIG. 5 is a block diagram showing the internal structure of an adaptive circuit according to a first embodiment of the present invention.
  • FIG. 6 is a block diagram showing the internal structure of an adaptive circuit according to a second embodiment of the present invention.
  • Fig. 7 is a view showing the internal structure of the pulse generating circuit shown in Fig. 6.
  • FIG. 3 shows a schematic structural diagram of an intelligent power module according to an embodiment of the present invention.
  • an intelligent power module includes: a HVIC tube 1101 and an adaptive circuit 1105.
  • VCC end of the HVIC tube 1101 is used as the low-voltage area power supply positive terminal VDD of the smart power module 1100, and VDD is generally 15V;
  • the HIN1 terminal is connected to the first input end of the adaptive circuit 1105; the HIN2 terminal is connected to the second input end of the adaptive circuit 1105; the HIN3 terminal is connected to the third input terminal of the adaptive circuit 1105; and the LIN1 terminal is connected to the fourth input of the adaptive circuit 1105.
  • the LIN2 terminal is connected to the fifth input end of the adaptive circuit 1105; the LIN3 terminal is connected to the sixth input end of the adaptive circuit 1105; the PFCINP terminal is connected to the seventh input end of the adaptive circuit 1105; and the ITRIP terminal is connected to the adaptive circuit 1105.
  • the seventh input terminal; the VCC terminal is connected to the positive end of the power supply of the adaptive circuit 1105; the GND terminal is connected to the negative terminal of the power supply of the adaptive circuit 1105; the output of the adaptive circuit 1105 is denoted as ICON for controlling the HIN1 to HIN3, LIN1 ⁇ The validity of the LIN3, PFCINP signal.
  • the bootstrap circuit structure inside the HVIC tube 1101 is as follows:
  • the VCC terminal is connected to the bootstrap diode 1102, the bootstrap diode 1103, and the anode of the bootstrap diode 1104; the cathode of the bootstrap diode 1102 is connected to the VB1 of the HVIC tube 1101; the cathode of the bootstrap diode 1103 is connected to the VB2 of the HVIC tube 1101; The cathode of the diode 1104 is connected to VB3 of the HVIC tube 1101.
  • the HIN1 end of the HVIC tube 1101 is the U-phase upper arm signal input end UHIN of the intelligent power module 1100; the HIN2 end of the HVIC tube 1101 is the V-phase upper arm signal input end VHIN of the intelligent power module 1100; the HIN3 end of the HVIC tube 1101
  • the W-phase upper arm signal input terminal WHIN of the intelligent power module 1100; the LIN1 end of the HVIC tube 1101 is the U-phase lower arm signal input terminal ULIN of the intelligent power module 1100; the LIN2 end of the HVIC tube 1101 is the intelligent power module 1100.
  • the V-phase lower arm signal input terminal VLIN; the LIN3 end of the HVIC tube 1101 is the W-phase lower arm signal input terminal WLIN of the intelligent power module 1100; the ITRIP end of the HVIC tube 1101 is the MTRIP end of the intelligent power module 1100; the HVIC tube 1101 PFCINP end As the PFC control input terminal PFCIN of the intelligent power module 1100; the GND end of the HVIC tube 1101 serves as the low-voltage area power supply negative terminal COM of the smart power module 1100.
  • the intelligent power module 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six input and PFCIN terminal receive 0V or 5V input signal.
  • the VB1 end of the HVIC tube 1101 is connected to one end of the capacitor 1131 and serves as the U-phase high voltage region power supply positive terminal UVB of the intelligent power module 1100; the HO1 end of the HVIC tube 1101 is connected to the gate of the U-phase upper arm IGBT tube 1121; HVIC The VS1 end of the tube 1101 is connected to the emitter of the IGBT tube 1121, the anode of the FRD tube 1111, the collector of the U-phase lower arm IGBT tube 1124, the cathode of the FRD tube 1114, and the other end of the capacitor 1131, and serves as the intelligent power module 1100.
  • the VB2 end of the HVIC tube 1101 is connected to one end of the capacitor 1132, and serves as the V-phase high voltage area power supply positive terminal VVB of the intelligent power module 1100; the HO2 end of the HVIC tube 1101 is connected to the gate of the V-phase upper arm IGBT tube 1123; HVIC The VS2 end of the tube 1101 is connected to the emitter of the IGBT tube 1122, the anode of the FRD tube 1112, the collector of the V-phase lower arm IGBT tube 1125, the cathode of the FRD tube 1115, and the other end of the capacitor 1132, and serves as the intelligent power module 1100.
  • the VB3 end of the HVIC tube 1101 is connected to one end of the capacitor 1133 as the W-phase high-voltage area power supply positive terminal WVB of the intelligent power module 1100; the HO3 end of the HVIC tube 1101 is connected to the gate of the W-phase upper arm IGBT tube 1123; the HVIC tube The VS3 end of 1101 is connected to the emitter of the IGBT tube 1123, the anode of the FRD tube 1113, the collector of the W-phase lower arm IGBT tube 1126, the cathode of the FRD tube 1116, and the other end of the capacitor 1133, and serves as the smart power module 1100.
  • the LO1 end of the HVIC tube 1101 is connected to the gate of the IGBT tube 1124; the LO2 end of the HVIC tube 1101 is connected to the gate of the IGBT tube 1125; the LO3 end of the HVIC tube 1101 is connected to the gate of the IGBT tube 1126; and the IGBT tube 1124 is fired.
  • the pole is connected to the anode of the FRD tube 1114 and serves as the U-phase low voltage reference terminal UN of the intelligent power module 1100; the emitter of the IGBT tube 1125 is connected to the anode of the FRD tube 1115 and serves as a V-phase low voltage reference of the intelligent power module 1100.
  • the terminal VN; the emitter of the IGBT transistor 1126 is connected to the anode of the FRD tube 1116 and serves as the W-phase low voltage reference terminal WN of the smart power module 1100.
  • VDD is the positive terminal of the HVIC tube 1101 power supply
  • GND is the power supply of the HVIC tube 1101.
  • Negative power supply; VDD-GND voltage is generally 15V; VB1 and VS1 are the positive and negative poles of the U-phase high-voltage region, HO1 is the output of the U-phase high-voltage region; VB2 and VS2 are the V-phase high-voltage region respectively.
  • the positive and negative electrodes, HO2 is the output end of the V-phase high-voltage zone; VB3 and VS3 are the positive and negative poles of the U-phase high-voltage zone, and HO3 is the output of the W-phase high-voltage zone; LO1, LO2, and LO3 are respectively U-phase, The output of the V-phase, W-phase low-voltage zone.
  • the PFCO end of the HVIC tube 1101 is connected to the gate of the IGBT tube 1127; the emitter of the IGBT tube 1127 is connected to the anode of the FRD tube 1117, and serves as the PFC low voltage reference terminal of the smart power module 1100 - VP; the collector of the IGBT tube 1127 Connected to the cathode of the FRD tube 1117, the anode of the FRD tube 1141, and as the PFC end of the smart power module 1100;
  • the collector of the IGBT tube 1121, the cathode of the FRD tube 1111, the collector of the IGBT tube 1122, the cathode of the FRD tube 1112, the collector of the IGBT tube 1123, the cathode of the FRD tube 1113, and the cathode of the FRD tube 1141 are connected as smart power.
  • the high voltage input terminal P, P of the module 1100 is generally connected to 300V.
  • the UN U phase low voltage reference terminal
  • VN V phase low voltage reference terminal
  • WN W phase low voltage reference terminal
  • HVIC tube 1101 The role of HVIC tube 1101 is:
  • the 0 or 5V logic input signals of the input terminals HIN1, HIN2, and HIN3 are respectively transmitted to the output terminals HO1, HO2, and HO3, and the signals of LIN1, LIN2, and LIN3 are respectively transmitted to the output terminals LO1 and LO2.
  • the signal of PFCINP is transmitted to the output terminal PFCO, where HO1 is the logic output signal of VS1 or VS1+15V, HO2 is the logic output signal of VS2 or VS2+15V, and HO3 is the logic output signal of VS3 or VS3+15V, LO1, LO2, LO3, PFCO are 0 or 15V logic output signals;
  • the present invention respectively proposes two specific embodiments as follows:
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the role of the adaptive circuit 1105 is:
  • the voltage value of ITRIP is compared with a voltage V2, which is A voltage greater than V1, when ITRIP>V2, ICON immediately outputs a low level, otherwise ICON remains at a high level.
  • FIG. 5 a specific circuit structure diagram of the adaptive circuit 1105 is shown in FIG. 5, specifically:
  • HIN1 is connected to one of the inputs of the OR gate 2001;
  • HIN2 is connected to one of the inputs of the OR gate 2001;
  • HIN3 is connected to one of the inputs of the OR gate 2001;
  • LIN1 is connected to one of the inputs of the OR gate 2002;
  • LIN2 is connected to one of the inputs of the OR gate 2002;
  • LIN3 is connected to one of the inputs of the OR gate 2002;
  • PFCINP is connected to one of the inputs of the OR gate 2003; the output of the OR gate 2001, the output of the OR gate 2002 or the other two inputs of the gate 2003; the output of the OR gate 2003 is connected to one of the inputs of the NAND gate 2014 end;
  • One end of the resistor 2004 is connected to VCC; the other end of the resistor 2004 is connected to one end of the resistor 2007 and the cathode of the Zener diode 2005; the anode of the Zener diode 2005 is connected to the GND;
  • the other end of the resistor 2007 is connected to the positive input terminal of the voltage comparator 2009 and one end of a PTC (Positive Temperature Coefficient) resistor 2006; the other end of the PTC resistor 2006 is connected to GND;
  • PTC Positive Temperature Coefficient
  • the negative input terminal of the voltage comparator 2009 is connected to the positive terminal of the voltage source 2008; the negative terminal of the voltage source 2008 is connected to the GND; the output terminal of the voltage comparator 2009 is connected to the other input terminal of the NAND gate 2014; the output terminal of the NAND gate 2014 The input end of the non-gate 2015; the output end of the non-gate 2015 is connected to the control end of the analog switch 2018;
  • the ITRIP is connected to the positive input terminal of the voltage comparator 2010 and the positive input terminal of the voltage comparator 2013; the positive terminal of the voltage source 2011 is connected to the negative input terminal of the voltage comparator 2010; the negative terminal of the voltage source 2011 is connected to the GND; Terminating the negative input terminal of the voltage comparator 2013; the negative terminal of the voltage source 2012 is connected to the GND; the output terminal of the voltage comparator 2010 is connected to the 0 selection terminal of the analog switch 2018 and one of the input terminals of the NAND gate 2016;
  • the output of the voltage comparator 2013 is connected to the other input of the NAND gate 2016; the output of the NAND gate 2016 is connected to the input of the NOT gate 2017; the output of the NOT gate 2017 is connected to the 1 selection of the analog switch 2018; the analog switch The fixed end of 2018 is connected to the input of NOT gate 2019; the output of NOT gate 2019 is used as ICON.
  • HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 and PFCINP are all low level, point A outputs high level; when point D voltage is greater than voltage of voltage source 2008, C outputs high level, otherwise C point output Low level
  • the Zener diode 2005 has a clamp voltage of 6.4V and the resistor 2004 is designed to be 20k ⁇ . At point B, it produces a stable 6.4V voltage that does not affect VCC voltage fluctuations.
  • the PTC resistor 2006 is designed to be 10k ⁇ at 25°C, at 100°C. 20k ⁇ ; resistor 2007 is designed to be 44k ⁇ , voltage source 2008 is designed to be 2V, then below 100°C, voltage comparator 2009 outputs low level, above 100°C, voltage comparator 2009 outputs high level; according to actual application needs,
  • the temperature of the output of the trigger voltage comparator 2009 can be controlled by adjusting the value of the resistor 2007;
  • the control end of the analog switch 2018 is a high level, otherwise the control end of the analog switch 2018 is a low level;
  • the voltage source 2011 is designed to be 0.5V
  • the voltage source 2012 is designed to be 0.7V, and can also be designed to be higher than 0.5V, such as 0.6V;
  • NAND gate 2016 and non-door 2017 dimensions can be designed to allow the process to allow 3 to 5 times the minimum size for adjusting the delay.
  • the threshold voltage of the ITRIP is increased during a period in which an error occurs, thereby greatly reducing the threshold voltage.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the role of the adaptive circuit 1105 is:
  • the filtering time of ITRIP of adaptive circuit 1105 is related to temperature: the lower the temperature, the shorter the filtering time; the higher the temperature, the longer the filtering time.
  • the filter time of the adaptive circuit 1105 for ITRIP is independent of temperature.
  • ICON When the voltage of ITRIP exceeds the threshold voltage set internally by the adaptive circuit 1105, and the time exceeding the threshold voltage exceeds the filter time, ICON is low; otherwise, ICON remains at a high level.
  • ICON is used as an enable signal for 7 inputs of HIN1 ⁇ HIN3, LIN1 ⁇ LIN3, and PFCINP.
  • ICON When ICON is high, 7 input signals can be transmitted normally.
  • ICON When ICON is low, 7 input signals are blocked and input. The signal is not transmitted to the output.
  • FIG. 6 a specific circuit structure diagram of the adaptive circuit 1105 is shown in FIG. 6, specifically:
  • HIN1 is connected to the input end of the pulse generating circuit 2034', the output end of the pulse generating circuit 2034' is connected to one of the input terminals of the OR gate 2001';
  • HIN2 is connected to the input end of the pulse generating circuit 2035', and the output end of the pulse generating circuit 2035' is connected.
  • HIN3 is connected to the input of the pulse generating circuit 2036', and the output of the pulse generating circuit 2036' is connected to one of the inputs of the OR gate 2001';
  • the input terminal of the pulse generating circuit 2037' is connected to the output terminal of the pulse generating circuit 2037'.
  • One of the input terminals of the OR gate 2002' is connected to the input terminal of the pulse generating circuit 2038'.
  • the output terminal of the pulse generating circuit 2038' is connected.
  • the input end of the PFCINP pulse generating circuit 2040', the output end of the pulse generating circuit 2040', the output end of the OR gate 2001', or the output end of the OR gate 2002' is connected to the three inputs of the OR gate 2003'; OR gate 2003' The output terminal is connected to the control end of the analog switch 2004';
  • ITRIP is connected to the positive input terminal of voltage comparator 2033'; the positive terminal of voltage source 2032' is connected to the negative input terminal of voltage comparator 2033'; the negative terminal of voltage source 2032' is connected to GND; the output terminal of voltage comparator 2033' is connected to analog a fixed end of the switch 2004';
  • the 1 selection terminal of the analog switch 2004' is connected to the input terminal of the NOT gate 2005'; the 0 selection terminal of the analog switch 2004' is connected to the input terminal of the NOT gate 2025';
  • the output of the non-gate 2005' is respectively connected to the gate of the NMOS transistor 2007' and the input terminal of the non-gate 2008'; the substrate of the NMOS transistor 2007' is connected to the source and connected to the GND; the drain and current source of the NMOS transistor 2007'
  • the input of the positive end of 2006' is connected to the input of the non-gate 2011'; the negative terminal of the current source 2006' is connected to VCC; the output of the non-gate 2011' is connected to one end of the PTC resistor 2013'; the other end of the PTC resistor 2013' is connected to the capacitor 2015 'The end of the 'non-gate 2017'; the other end of the capacitor 2015' is connected to GND; the output of the non-gate 2017' is connected to the input of the non-gate 2019'; the output of the non-gate 2019' is connected to the NOR 2021' One of the inputs;
  • the output of the non-gate 2008' is connected to the gate of the NMOS transistor 2010'; the substrate of the NMOS transistor 2010' is connected to the source and connected to the GND; the drain of the NMOS transistor 2010' and the positive terminal of the current source 2009', the non-gate 2012 'The input terminal is connected; the negative terminal of current source 2009' is connected to VCC; the output terminal of non-gate 2012' is connected to one end of PTC resistor 2014'; the other end of PTC resistor 2014' is connected to one end of capacitor 2016' and the non-gate 2018' Input end; the other end of the capacitor 2016' is connected to the GND; the output end of the NOT gate 2018' is connected to the input end of the NOT gate 2020'; the output end of the NOT gate 2020' is connected to one of the input terminals of the NOR gate 2022';
  • the output of the NOR gate 2021' is connected to the other input of the NOR gate 2020'; the output of the NOR gate 2020' is connected to the other input of the NOR gate 2021' and one of the inputs of the NOR gate 2023' ;
  • the output terminal of the NOT gate 2025' is connected to one end of the capacitor 2026' and the input terminal of the NOT gate 2027'; the other end of the capacitor 2026' is connected to the GND; the output terminal of the NOT gate 2027' is connected to one end of the capacitor 2030' and the non-gate 2028'.
  • the other end of the capacitor 2030' is connected to the GND; the output end of the non-gate 2028' is connected to one end of the capacitor 2031' and the input end of the NOT gate 2029'; the other end of the capacitor 2031' is connected to the GND; the output of the NOT gate 2029' Another input end of the NOR gate 2023';
  • the output of the NOR gate 2023' is coupled to the input of the NOT gate 2024'; the output of the NOT gate 2024' serves as the ICON terminal.
  • the structure and function of the pulse generating circuit 2034' to the pulse generating circuit 2040' are completely the same.
  • the internal circuit structure is described below by taking the pulse generating circuit 2034' as an example in conjunction with FIG. 7:
  • the input end of the pulse generating circuit 2034' is connected to the input terminal of the NOT gate 3001' and the NOT gate 3003';
  • the output end of the gate 3001' is connected to the input end of the NOT gate 3002';
  • the output end of the NOT gate 3002' is connected to one of the input terminals of the NAND gate 3006';
  • the output terminal of the NOT gate 3003' is connected to one end of the capacitor 3008' and the input terminal of the NOT gate 3004'; the other end of the capacitor 3008' is connected to the GND; the output terminal of the NOT gate 3004' is connected to one end of the capacitor 3009' and the non-gate 3005'. Input end; the other end of the capacitor 3009' is connected to the GND; the output end of the non-gate 3005' is connected to the other input end of the NAND gate 3006';
  • NAND gate 3006' is coupled to the input of NOT gate 3007'; the output of NOT gate 3007' serves as the output of pulse generation circuit 2034'.
  • the function of the pulse generating circuit 2034' is to generate a pulse on the rising edge of the input signal.
  • the width of the pulse is determined by the size of the capacitor and the size of the non-gate. This time needs to be larger than the FRD tube 1111 to FRD tube 1116, FRD shown in FIG. Reverse recovery time of tube 1131.
  • the non-gate 3001' to the non-gate 3005' take the minimum size allowed by the process, and the capacitor 3008' and the capacitor 3009' are designed to be 10-15 pF, and the pulse width is about 400 ns.
  • the voltage source 2032' is set as needed, and the voltage value of the voltage source is the threshold of ITRIP. For an intelligent power module application of 15A to 30A, it is generally set to 0.5V:
  • a pulse of about 400 ns is generated at the rising edges of HIN1 to HIN3, LIN1 to LIN3, and PFCINP. These pulses are output at the output of OR gate 2003' after the superposition of OR gates 2001' to OR gates 2003'. The pulse is the moment when the bus noise is the largest. At these moments, the analog switch 2004' is selected as the 1 selection terminal, and at other times, the analog switch is selected as the 0 selection terminal.
  • the size of the non-door 2011' NAND gate 2012' is exactly the same;
  • the size of the non-door 2017' is 1.5 times the size of the non-door 2011', and the size of the non-door 2019' is twice the size of the non-door 2011', so that the driving capacity can be amplified;
  • the current source 2006' and the current source 2009' have the same value, and can be set to the ⁇ A level in order to reduce the dynamic power consumption, and can be set to the 10 ⁇ A level in order to increase the reaction speed;
  • the PTC resistor 2013' and the PFC resistor 2014' are exactly the same. As the temperature rises, the tissue increases, and the time for charging the capacitor 2015' and the capacitor 2016' respectively increases, and the values of the capacitor 2015' and the capacitor 2016' are exactly the same. 3 to 5 pF level;
  • the NOR gate 2021' and the NOR gate 2022' constitute an RS flip-flop to ensure the stability of the level output at a moment of high noise;
  • the signal delay from A' to B' increases with increasing temperature, and if this delay is the filtering time from A' to B'; taking the above design parameters, the filtering time is between 25 °C and 125 When °C changes, the filtering time varies from 250ns to 400ns.
  • Another filter circuit is composed from C' to D', which is used at a time when the circuit noise is small.
  • the circuit has no temperature-dependent components, and the temperature stability is good.
  • the non-gate 2025' and the non-gate 2027' are allowed by the process.
  • the minimum size, the non-gate 2028' takes 1.5 times the size of the non-gate 2025'
  • the non-gate 2029' takes 2 times the size of the non-gate 2025'
  • the capacitance takes 1 ⁇ 2pF
  • the filter time from C' to D' is stable at 250ns ⁇ 270ns.
  • the filtering time of the ITRIP is adjusted by automatically determining the temperature of the intelligent power module at the time when the false trigger is most likely to occur, thereby greatly reducing the probability that the ITRIP is falsely triggered at a high temperature, and The sensitivity of ITRIP at other time points is ensured, so that the intelligent power module of the invention can work reliably in the whole temperature range.
  • the present invention proposes a new intelligent power module, which can effectively reduce the intelligent power module at high temperature under the premise of ensuring that the intelligent power module can work normally at normal temperature.
  • the probability of false triggering increases the reliability of the intelligent power module.

Abstract

L'invention concerne un module de puissance intelligent (1100) et un climatiseur. Un premier port connecté à une borne de détection de courant et un second port connecté à une borne d'entrée de commande PFC sont agencés sur un circuit intégré haute tension (HVIC) (1101) à l'intérieur du module de puissance intelligent (1100) ; une électrode positive et une électrode négative d'alimentation d'un circuit adaptatif (1105) sont connectées respectivement à une borne positive et à une borne négative d'alimentation de zone basse tension du module de puissance intelligent (1100) ; une première borne d'entrée, une deuxième borne d'entrée et une troisième borne d'entrée du circuit adaptatif (1105) sont connectées respectivement à des bornes correspondantes parmi des bornes d'entrée de signal de branche supérieure de pont triphasé ; une quatrième borne d'entrée, une cinquième borne d'entrée et une sixième borne d'entrée du circuit adaptatif (1105) sont connectées respectivement à des bornes correspondantes parmi des bornes d'entrée de signal de branche inférieure de pont triphasé ; une septième borne d'entrée du circuit adaptatif (1105) est connectée au second port, une huitième borne d'entrée du circuit adaptatif (1105) est connectée au premier port, et une borne de sortie du circuit adaptatif (1105) sert de borne de validation du HVIC (1101). Par différents moyens, le circuit adaptatif (1105) réduit la probabilité que le module de puissance intelligent (1100) sera déclenché par erreur à des températures élevées, ce qui permet d'augmenter la fiabilité du module de puissance intelligent (1100).
PCT/CN2016/097738 2015-11-30 2016-08-31 Module de puissance intelligent et climatiseur WO2017092449A1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
CN201510863297.9A CN105356786B (zh) 2015-11-30 2015-11-30 智能功率模块和空调器
CN201520978827.XU CN205123615U (zh) 2015-11-30 2015-11-30 智能功率模块和空调器
CN201510863297.9 2015-11-30
CN201520978827.X 2015-11-30
CN201610126190.0A CN105577017B (zh) 2016-03-04 2016-03-04 智能功率模块和空调器
CN201620169940.8 2016-03-04
CN201610126190.0 2016-03-04
CN201620169940.8U CN205453539U (zh) 2016-03-04 2016-03-04 智能功率模块和空调器

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