WO2017088507A1 - Procédé et dispositif de mise à jour de code de détection et de correction d'erreurs - Google Patents

Procédé et dispositif de mise à jour de code de détection et de correction d'erreurs Download PDF

Info

Publication number
WO2017088507A1
WO2017088507A1 PCT/CN2016/091840 CN2016091840W WO2017088507A1 WO 2017088507 A1 WO2017088507 A1 WO 2017088507A1 CN 2016091840 W CN2016091840 W CN 2016091840W WO 2017088507 A1 WO2017088507 A1 WO 2017088507A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
code
ecc
written
storage space
Prior art date
Application number
PCT/CN2016/091840
Other languages
English (en)
Chinese (zh)
Inventor
黄生儒
廉肖洁
薛军
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2017088507A1 publication Critical patent/WO2017088507A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a method and apparatus for updating an error detection and correcting an ECC code.
  • NAND Flash internal memory unit with NAND gate connected flash memory
  • NOR Flash internal memory unit with NAND gate connected flash memory
  • ECC check refers to calculating the ECC code by means of a data block (such as 256 bytes or 512 bytes of data as one data block) when reading and writing data, by comparing the ECC code of the written data with the read data. Whether the ECC codes are consistent or not, and whether the data is bit-reversed is determined. Since NAND Flash itself reads and writes data in the form of data blocks, ECC verification is perfectly suitable for NAND Flash.
  • NOR Flash is also more and more prone to bit inversion problems.
  • ECC verification is introduced to NOR Flash.
  • NOR Flash is a random read/write method, that is, the size of read and write data is random. If ECC is directly introduced into NOR Flash, it will be limited to reading in blocks. Writing data destroys the random read and write of NOR Flash.
  • Embodiments of the present invention provide a method and apparatus for updating an error detection and correcting an ECC code, which can achieve random read and write performance of a storage medium when performing ECC verification.
  • a first aspect of the embodiments of the present invention provides a method for updating an ECC code, where the method is applied to a data writing process of a storage medium, where the storage medium includes a plurality of storage blocks, and the method includes:
  • ECC code of total data in each of the storage blocks, where the ECC code includes a column check code and a row check code;
  • the written data, the location of the storage space where the data is written, and the original data stored by the storage space before the data is written are acquired.
  • the location of the storage space is used to determine a storage block to which the storage space belongs;
  • the column check code of the ECC code of the written data, the column check code of the ECC code of the original data, and the storage space belong to The column check code of the ECC code of the total data in the storage block is logically operated, and the column check code of the ECC code of the total data in the storage block to which the storage space belongs after the one-byte data is written is obtained, including:
  • the root And modifying the row check code of the ECC code of the total data in the storage block to which the storage space belongs according to the data to be written and the original data including:
  • Determining a parity of the written data and a parity of the original data determining whether a parity of the written data is the same as a parity of the original data; if yes, modifying the total data a row check code of the ECC code; if not, determining a bit associated with the data in the written storage space in the row check code of the ECC code of the total data, and reversing the bit Turning, wherein the inversion refers to changing data 0 to data 1, or changing data 1 to data 0.
  • the memory block is 256 bytes of storage space.
  • the smaller the number of bytes of the storage block the more the number of storage blocks in the storage medium, the more ECC codes to be recorded.
  • the more bytes of the storage block the total in the storage block. The larger the data, the more complex the ECC code to be recorded, and the combination of the above two factors, the most appropriate setting of 256 bytes.
  • a second aspect of the embodiments of the present invention provides a method for verifying an ECC code, where the method is applied to a data writing process of a storage medium, where the storage medium includes a plurality of storage blocks, and the method includes:
  • the performing parity check on the data in the storage space where the read data is located includes:
  • Calculating a parity code of the read data querying a parity code stored in a storage space of the read data when writing data; determining whether the calculated parity code is related to the saved parity The parity is the same; if not, the parity is erroneous; if so, the parity is not erroneous. With this technical solution, it is possible to first determine whether the read data is in error.
  • the performing the ECC code check on the total data in the storage block to which the storage space of the read data belongs includes:
  • the memory block is 256 bytes of storage space.
  • the smaller the number of bytes of the storage block the more the number of storage blocks in the storage medium, the more ECC codes to be recorded.
  • the more bytes of the storage block the total in the storage block. The larger the data, the more complex the ECC code to be recorded, and the combination of the above two factors, the most appropriate setting of 256 bytes.
  • a third aspect of the embodiments of the present invention provides an apparatus for updating an ECC code, where the apparatus has a behavior function for implementing the method provided by the foregoing first aspect, and the function may be implemented by using hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • a fourth aspect of the embodiments of the present invention provides an apparatus for verifying an ECC code, where the apparatus has a behavior function for implementing the method provided by the foregoing second aspect, and the function may be implemented by hardware, or may be implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • a fifth aspect of the embodiments of the present invention provides a storage device including a processor, a communication bus, a storage medium, a memory, and an input/output interface.
  • the communication bus is configured to implement connection communication between the components;
  • the storage medium includes a plurality of virtual storage blocks for storing data written by the external device, or sending data read by the external data;
  • the input and output The interface is used to provide an interface to an external device for reading and writing data; the program code is stored in the memory.
  • the processor when the storage device is in the data writing process, the processor is configured to call the program code stored in the memory, and performs the following operations:
  • ECC code of total data in each of the storage blocks, the ECC code including a column check code and a row check code; when randomly writing one byte of data to the storage medium, acquiring the written data The location of the storage space in which the data is written and the storage space is stored before the data is written Raw data, wherein the location of the storage space is used to determine a storage block to which the storage space belongs; a column check code of an ECC code for the written data, and a column of an ECC code of the original data The check code and the column check code of the ECC code of the total data in the storage block to which the storage space belongs are logically operated, and the ECC of the total data in the storage block to which the storage space belongs after the one-byte data is written is obtained.
  • the processor passes the column check code of the ECC code of the written data, the column check code of the ECC code of the original data, and the ECC code of the total data in the storage block to which the storage space belongs.
  • the column check code performs a logical operation, and the specific operation of the column check code of the ECC code of the total data in the storage block to which the storage space belongs after the one-byte data is written is: calculating the written data Column check code of the ECC code, and column check code of the ECC code of the original data; according to the formula Calculating a column check code of an ECC code of total data in a storage block to which the storage space belongs after writing one-byte data, wherein a column check code indicating an ECC code of the calculated total data, the ECC_CP indicating a column check code of an ECC code of the total data before calculation, and the Data_ECC_CP indicating an ECC code of the written data Column check code, the Buf_ECC_CP represents a column check code of the ECC code of the
  • the specific operation of the processor to modify the row check code of the ECC code of the total data in the storage block to which the storage space belongs according to the written data and the original data is: determining the write The parity of the data, and the parity of the original data; determining whether the parity of the written data is the same as the parity of the original data; if so, the row of the ECC code of the total data is not modified a check code; if not, determining a bit associated with the data in the written storage space in the row check code of the ECC code of the total data, and inverting it, wherein The inversion refers to changing data 0 to data 1, or changing data 1 to data 0.
  • the processor when the storage device is in the data reading process, the processor is used to call the program code stored in the memory, and performs the following operations:
  • the specific operation of the processor to perform parity check on the data of the storage space where the read data is located is: calculating a parity code of the read data; querying a storage space where the read data is written a parity code saved when data is entered; determining whether the calculated parity code is the same as the saved parity code; if not, the parity error occurs; if yes, the parity is not errored .
  • the specific operation of performing ECC code verification on the total data in the storage block to which the read data belongs is: calculating a total of the storage blocks to which the read data belongs. An ECC code of the data; querying a parity code saved when the storage block to which the read data belongs is written in the data; determining the calculated ECC code by comparing the calculated ECC code with the saved ECC code A bit inverted bit occurs in the read data, and is inverted, wherein the inversion refers to changing data 0 to data 1, or changing data 1 to data 0.
  • the ECC code of the total data in the storage block can be modified only according to the written data and the original data before the writing, which can be solved in the prior art.
  • the data of one storage block must be completely written before the problem of the ECC code can be calculated, so that the random writeability of the storage medium is not damaged.
  • the read data is first performed. Parity check, only when the parity error occurs, the ECC check is performed, which can solve the problem that the ECC check can be performed after the data of one memory block is completely read every time the data is read in the prior art, thereby reducing the problem. Destruction of random readability of storage media.
  • FIG. 1 is a schematic flowchart of a method for updating an ECC code according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for verifying an ECC code according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an apparatus for updating an ECC code according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a row and column code modification module according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an apparatus for verifying an ECC code according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a parity check module according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an ECC code verification module according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
  • the ECC code includes a column check code and a row check code, and the calculation object is a data block.
  • the following is an example of 256 bytes of data as a data block:
  • CP0 represents the column polarity of the 0th column, the 2nd column, the 4th column, and the 6th column;
  • CP1 indicates the column polarity of the first column, the third column, the fifth column, and the seventh column;
  • CP2 indicates the column polarity of the 0th column, the 1st column, the 4th column, and the 5th column;
  • CP3 indicates the column polarity of the second column, the third column, the sixth column, and the seventh column;
  • CP4 indicates the column polarity of the 0th column, the 1st column, the 2nd column, and the 3rd column;
  • CP5 indicates the column polarities of the fourth column, the fifth column, the sixth column, and the seventh column.
  • ⁇ represents a bitwise XOR operation
  • [Bit0] represents the result of 256 Bit0 XORs of column 0
  • [Bit2] indicates the first The result of 256 Bit2 XOR of 2 columns
  • [Bit4] represents the result of 256 Bit4 XOR of the 4th column
  • [Bit6] represents the result of 256 Bit6 XOR of the 6th column.
  • CP1 to CP5 can be obtained.
  • ECC_CP indicates the column check code of the ECC code
  • ECC_CP ⁇ CP5, CP4, CP3, CP2, CP1, CP0 ⁇ .
  • RP0 is the row polarity of rows 0, 2, 4, 6, ... 252, 254;
  • RP1 is the row polarity of the first, third, fifth, seventh, ..., 253, and 255 lines;
  • RP2 is the row polarity of lines 0, 1, 4, 5, ... 252, 254 (processing two lines, skipping two lines);
  • RP3 is the row polarity of the 2nd, 3rd, 6th, 7th, ..., 254th, and 255th lines (skip two lines, processing two lines);
  • RP4 is the row polarity of the line (processing four lines, skipping four lines);
  • RP5 is the row polarity of the line (skip four lines, handle four lines);
  • RP6 is the row polarity of the line (processing eight lines, skipping eight lines);
  • RP7 is the row polarity of the line (skip eight lines, handle eight lines);
  • RP8 is the row polarity of the line (processing sixteen lines, skipping sixteen lines);
  • RP9 is the row polarity of the line (skip six lines, handle sixteen lines);
  • RP10 is the row polarity of the line (processing thirty-two lines, skipping thirty-two lines);
  • RP11 is the row polarity of the line (skip thirty-two lines, processing thirty-two lines);
  • RP12 is the row polarity of the line (processing sixty-four lines, skipping sixty-four lines);
  • RP13 is the row polarity of the line (skip sixty-four lines, processing sixty-four lines);
  • RP14 is the row polarity of the line (handling one hundred and twenty-eight lines, skipping one hundred and twenty-eight lines);
  • RP15 is the line polarity of the line (skip one hundred and twenty-eight lines, handle one hundred and twenty-eight lines);
  • the ECC code includes a column check code ECC_CP and a row check code ECC_RP.
  • ECC_CP column check code
  • ECC_RP row check code
  • FIG. 1 is a schematic flowchart of a method for updating an ECC code according to an embodiment of the present invention.
  • the method is applied to a data writing process of a storage medium, where the storage medium includes a plurality of storage blocks, optionally, in the embodiment of the present invention. Set the storage block to 256 bytes of storage space.
  • the flow of the method for updating the ECC code in this embodiment as shown in the figure may include:
  • the ECC code corresponding to the 256-byte data in each memory block can be calculated by the calculation method of the ECC code introduced above.
  • the ECC code calculated after the last data write is recorded locally, or the newly calculated ECC code in other cases, the ECC code is directly found, and does not need to be calculated again.
  • the purpose of obtaining the ECC code of the total data in each memory block is to obtain a new ECC code by modifying the ECC code when the data is randomly written to the storage medium.
  • the written data, the location of the storage space where the data is written, and the original data stored by the storage space before the data is written are acquired.
  • the location of the storage space is used to determine a storage block to which the storage space belongs.
  • the location of the storage space may be a storage address or a serial number of a byte. Take the serial number of the storage space as an example: assume that the data randomly written to the storage medium is 0xF0, and the byte corresponding to the storage space to which the data is written is Byte9, and the storage space is before the data is written. If the stored original data is 0x31, the obtained information is 0xF0, Byte9, and 0x31.
  • a column check code of an ECC code of the written data a column check code of an ECC code of the original data, and a column check of an ECC code of a total data in a storage block to which the storage space belongs
  • the code performs a logical operation to obtain a column check code of the ECC code of the total data in the storage block to which the storage space belongs after writing the one-byte data, and is modified according to the written data and the original data.
  • the ECC code includes a column check code and a row check code, so it is necessary to separately modify the ECC code of the total data in the storage block to which the written byte belongs according to the written data and the original data.
  • the row check code of the column check code and the ECC code is necessary to separately modify the ECC code of the total data in the storage block to which the written byte belongs according to the written data and the original data.
  • the method of modifying the column check code of the ECC code may be: a column check code of the ECC code of the written data, a column check code of the ECC code of the original data, and a total data in the storage block to which the storage space belongs.
  • the column check code of the ECC code performs a logical operation to obtain a column check code of the ECC code of the total data in the memory block to which the storage space to which the one-byte data is written.
  • Step 1 Calculate the column check code of the ECC code of the written data, and the column check code of the ECC code of the original data.
  • the written data is 0xF0
  • the original data is 0x31
  • Data_ECC_CP indicates the column check code of the ECC code of the written data
  • Buf_ECC_CP indicates the column check code of the ECC code of the original data
  • Step 2 according to the formula A column check code of an ECC code of total data in a memory block to which the storage space to which the one-byte data is written is calculated.
  • a column check code indicating an ECC code of the modified total data ECC_CP indicates a column check code of the ECC code of the total data before the modification, and ⁇ indicates a bitwise exclusive OR operation.
  • the method for modifying the row check code of the ECC code may be: modifying the row check code of the ECC code of the total data in the storage block to which the storage space belongs according to the written data and the original data.
  • the specific implementation process is:
  • Step 1 Determine the parity of the written data and the parity of the original data.
  • step 2 it is judged whether the parity of the written data is the same as the parity of the original data.
  • Step 3 If they are the same, the row check code of the ECC code of the total data is not modified; if different, the bit associated with the data in the byte to be written is determined in the row check code of the ECC code of the total data. Bit and reverse it.
  • the parity of the written data is the same as the parity of the original data, by analyzing the calculation method of the ECC code, it can be known that the change of the written data and the original data does not affect the row check code of the ECC code, so It is not necessary to modify the row check code of the ECC code.
  • the bit associated with Byte0 in the row check code of the ECC code is RP0, RP2, RP4, RP6, RP8, RP10, RP12, RP14, and RP16; then the determined bit is inverted, where the inversion is Refers to changing data 0 to data 1, or changing data 1 to data 0.
  • ECC_RP indicates the row check code of the ECC code before modification
  • the associated bits are RP0, RP2, RP4, RP6, RP8, RP10, RP12, and RP14.
  • the ECC code since the ECC code includes the column check code and the row check code, the ECC code of the total data in the memory block after writing the data of one byte and the line of the ECC code of the total data in the modified memory block are The check code can obtain the ECC code of the total data in the storage block, and the ECC code is the updated ECC code.
  • the embodiment of the present invention when the data is randomly written to the storage medium, the embodiment of the present invention only needs to modify the original ECC code, and the prior art must write 256 bytes of data to the storage block.
  • the problem of calculating the ECC code is such that the random writeability of the storage medium is not destroyed.
  • the embodiment of the present invention does not need to recalculate the ECC code, thereby improving the operation efficiency.
  • FIG. 2 is a schematic flowchart of a method for verifying an ECC code according to an embodiment of the present invention.
  • the method is applied to a data reading process of a storage medium, where the storage medium includes a plurality of storage blocks, and the storage block is A storage space composed of a plurality of bytes.
  • the storage block is set to a storage space of 256 bytes.
  • the flow of the method for verifying the ECC code in this embodiment as shown in the figure may include:
  • the method flow for performing parity check on the read data is:
  • Step 1 Calculate the parity of the read data.
  • Step 2 Query the parity code of the storage space where the read data is stored when the data is written.
  • each byte in the storage medium when writing data, calculates the parity code corresponding to the data in the storage space corresponding to the byte and saves it.
  • the parity code stored in the storage space where the read data is located is queried.
  • step 3 it is judged whether the calculated parity code is the same as the saved parity code.
  • step 4 if the result of the determination in step 3 is different, the parity error occurs; if the result of the determination in step 3 is the same, the parity is not in error.
  • Step S202 to perform an ECC check.
  • the embodiment of the present invention can avoid ECC check every time the data is read, and ensure that the ECC check is performed. The verification efficiency is improved while the verification efficiency is improved.
  • the storage block is divided into a plurality of sub-memory blocks in advance, such as dividing a 256-byte storage block into eight 32-byte storage blocks, when randomly reading data from the storage medium, Perform parity check on the data in the sub-memory block where the read data is located.
  • the parity check is similar to the above method. The only difference is that the parity code of the data in each byte is not saved, and 32 words are saved instead. The parity of the data in the section reduces the number of parity codes that need to be saved.
  • step S203 is performed.
  • the method for performing ECC code verification on the total data in the storage block to which the stored data belongs is:
  • Step 1 Calculate the ECC code of the total data in the storage block to which the storage space of the read data belongs.
  • the storage block to which the stored data is located is determined, and then 256 bytes of data in the storage block are read, and the ECC code corresponding to the 256-byte data is calculated.
  • Step 2 Query the parity code saved when the storage block to which the read data belongs is written in the data.
  • each memory block in the storage medium calculates the parity code corresponding to the 256-byte data in the storage block when the data is written, and saves it.
  • the storage block to which the storage space in which the read data belongs is corresponding to the saved parity code.
  • Step 3 by comparing the calculated ECC code with the saved ECC code, determining a bit bit in the read data, and inverting the bit, wherein the inversion refers to changing the data 0 Is data 1, or data 1 is changed to data 0.
  • the embodiment of the present invention first performs parity check on the read data, and performs ECC check only when the parity error occurs, thereby avoiding reading data every time. ECC verification is required to ensure the verification reliability and improve the verification efficiency.
  • FIG. 3 is a schematic structural diagram of an apparatus for updating an ECC code according to an embodiment of the present invention.
  • the apparatus of the present invention is for implementing the method of updating the ECC code provided in FIG.
  • the device for updating the ECC code in the embodiment of the present invention may include at least an ECC code acquisition module 310, a data acquisition module 320, a row and column code modification module 330, and an ECC code update module 340, where:
  • the ECC code obtaining module 310 is configured to obtain an ECC code of total data in each of the storage blocks, where the ECC code includes a column check code and a row check code.
  • the ECC code corresponding to the 256-byte data in each memory block can be calculated by the calculation method of the ECC code introduced above.
  • the ECC code calculated after the last data write is recorded locally, or the newly calculated ECC code in other cases, the ECC code is directly found, and does not need to be calculated again.
  • the purpose of obtaining the ECC code of the total data in each memory block is to obtain a new ECC code by modifying the ECC code when the data is randomly written to the storage medium.
  • the data obtaining module 320 is configured to acquire, when the data is randomly written to the storage medium, the written data, the location of the storage space where the data is written, and the storage space is written in the Raw data stored before the data.
  • the location of the storage space is used to determine a storage block to which the storage space belongs.
  • the location of the storage space may be a storage address or a serial number of a byte.
  • the serial number of the storage space Take the serial number of the storage space as an example: assume that the data randomly written to the storage medium is 0xF0, and the byte corresponding to the storage space to which the data is written is Byte9, and the storage space is before the data is written. If the stored original data is 0x31, the obtained information is 0xF0, Byte9, and 0x31.
  • a lining code modification module 330 configured to pass a column check code of an ECC code of the written data, a column check code of an ECC code of the original data, and total data in a storage block to which the storage space belongs
  • the column check code of the ECC code performs a logical operation to obtain a column check code of the ECC code of the total data in the memory block to which the storage space belongs after writing the one-byte data, and according to the written data and
  • the original data modifies a row check code of an ECC code of total data in a storage block to which the storage space belongs.
  • the row and column code modification module 330 may further include a column code calculation unit 331, a column code modification unit 332, a parity determination unit 333, and a row code modification unit 334 as shown in FIG. 4, wherein:
  • the column code calculation unit 331 is configured to calculate a column check code of the ECC code of the written data, and a column check code of the ECC code of the original data.
  • the column check code of the ECC code of the written data is calculated, and the column check code of the ECC code of the original data; according to the formula A column check code of an ECC code of total data in a memory block to which the storage space to which the one-byte data is written is calculated.
  • a column check code indicating an ECC code of the modified total data ECC_CP indicates a column check code of the ECC code of the total data before the modification, and ⁇ indicates a bitwise exclusive OR operation.
  • a column code modification unit 332 for Calculating a column check code of an ECC code of total data in a storage block to which the storage space corresponding to the byte corresponding to the one byte of data is written, wherein a column check code indicating an ECC code of the calculated total data, the ECC_CP indicating a column check code of an ECC code of the total data before calculation, and the Data_ECC_CP indicating an ECC code of the written data Column check code, the Buf_ECC_CP represents a column check code of the ECC code of the original data, and the ⁇ represents a bitwise exclusive OR operation.
  • the parity determining unit 333 is configured to determine a parity of the written data and a parity of the original data.
  • bit bits of the two data are XORed respectively. If the XOR result is 0, the parity is even. If the XOR result is 1, the parity is odd.
  • the line code modification unit 334 is configured to determine whether the parity of the written data is the same as the parity of the original data, and if yes, the row check code of the ECC code of the total data is not modified; if not, Determining, in the row check code of the ECC code of the total data, a bit associated with the data in the written byte, and inverting it, wherein the inversion refers to the data 0 becomes data 1, or data 1 becomes data 0.
  • the parity of the written data is the same as the parity of the original data, by analyzing the calculation method of the ECC code, it can be known that the change of the written data and the original data does not affect the row check code of the ECC code, so It is not necessary to modify the row check code of the ECC code.
  • the bit associated with Byte0 in the row check code of the ECC code is RP0, RP2, RP4, RP6, RP8, RP10, RP12, RP14, and RP16; then the determined bit is inverted, where the inversion is Refers to changing data 0 to data 1, or changing data 1 to data 0.
  • the ECC code update module 340 is configured to: according to the column check code of the ECC code of the total data in the storage block to which the storage space belongs after the one-byte data is written, and the modified storage of the storage space
  • the row check code of the ECC code of the total data in the block obtains the ECC code of the total data in the memory block to which the updated storage space belongs.
  • the ECC code since the ECC code includes the column check code and the row check code, the ECC code of the total data in the memory block after writing the data of one byte and the line of the ECC code of the total data in the modified memory block are The check code can obtain the ECC code of the total data in the storage block, and the ECC code is the updated ECC code.
  • FIG. 5 is a schematic structural diagram of an apparatus for verifying an ECC code according to an embodiment of the present invention.
  • the apparatus of the present invention is for implementing the method of verifying an ECC code provided in FIG.
  • the device for verifying the ECC code in the embodiment of the present invention may include at least a parity check module 510, a check judging module 520, and an ECC code check module 530, where:
  • the parity check module 510 is configured to perform parity check on the read data when the data is randomly read to the storage medium.
  • the parity check module 510 may further include a first calculating unit 511, a first query unit 512, and a code value determining unit 513 as shown in FIG. 6, wherein:
  • the first calculating unit 511 is configured to calculate a parity code of the read data.
  • the method of calculating the parity code is to obtain an XOR result for each bit bit of the read data.
  • the first query unit 512 is configured to query a parity code saved when the read data is stored in the storage space.
  • each storage space in the storage medium calculates the parity code corresponding to the data in the storage space when the data is written, and saves it.
  • the storage space of the read data is queried corresponding to the saved parity code.
  • the code value determining unit 513 is configured to determine whether the calculated parity code is the same as the saved parity code; if not, the parity error occurs; if yes, the parity is not erroneous.
  • the calculated parity code is different from the saved parity code, it indicates that the stored data has a bit inversion, resulting in writing one data, and reading another data, which is triggered at this time.
  • the ECC code check module 530 performs ECC check.
  • the embodiment of the present invention can avoid ECC check every time the data is read, and ensure that the ECC check is performed. The verification efficiency is improved while the verification efficiency is improved.
  • the verification determining module 520 is configured to determine whether the parity is in error.
  • the ECC code verification module 530 is configured to perform ECC code verification on the total data in the storage block to which the storage space of the read data belongs when the parity determination module determines that the parity error occurs.
  • the ECC code verification module 530 may further include a second calculation unit 531, a second query unit 532, and a bit inversion unit 533 as shown in FIG. 7, wherein:
  • the second calculating unit 531 is configured to calculate an ECC code of the total data in the storage block to which the storage space of the read data belongs.
  • the storage block to which the stored data is located is determined, and then 256 bytes of data in the storage block are read, and the ECC code corresponding to the 256-byte data is calculated.
  • the second query unit 532 is configured to query a parity code that is saved when the storage block to which the read data belongs is written in the data.
  • each memory block in the storage medium calculates the parity code corresponding to the 256-byte data in the storage block when the data is written, and saves it.
  • the storage block to which the storage space in which the read data belongs is corresponding to the saved parity code.
  • bit inverting unit 533 configured to determine, by comparing the calculated ECC code with the saved ECC code, a bit in which bit inversion occurs in the read data, and invert it, wherein The inversion refers to changing data 0 to data 1, or changing data 1 to data 0.
  • FIG. 8 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
  • the storage device may include: at least one processor 801, such as a CPU, at least one communication bus 802, at least one storage medium 803, and a memory. 804, input and output interface 805.
  • the communication bus 802 is used to implement connection communication between these components.
  • the storage medium 803 includes a plurality of virtual storage blocks, and the storage block is a storage space of a plurality of bytes.
  • the memory 804 can be a high speed RAM memory or can be Non-volatile memory, such as at least one disk storage.
  • the input/output interface 805 is used to provide an interface for accessing an external device to read and write data.
  • the memory 804 may also be at least one storage device located away from the foregoing processor 801. A set of program codes is stored in the memory 804.
  • the processor 801 is configured to call the program code stored in the memory 804, and perform the following operations:
  • ECC code of total data in each of the storage blocks, where the ECC code includes a column check code and a row check code;
  • the written data, the location of the storage space where the data is written, and the original data stored by the storage space before the data is written are acquired.
  • the location of the storage space is used to determine a storage block to which the storage space belongs;
  • the processor 801 passes the column check code of the ECC code of the written data, the column check code of the ECC code of the original data, and the ECC of the total data in the storage block to which the storage space belongs.
  • the column check code of the code performs a logical operation, and the specific operation of the column check code of the ECC code of the total data in the storage block to which the storage space belongs after the data of one byte is written is:
  • the specific operation of the processor 801 to modify the row check code of the ECC code of the total data in the storage block to which the storage space belongs according to the written data and the original data is:
  • the storage block is 256 bytes of storage space.
  • the processor 801 is configured to call the program code stored in the memory 804, and performs the following operations:
  • the ECC code is checked for the total data in the storage block to which the stored data of the read data belongs.
  • the specific operation of the processor 801 for performing parity check on the data in the storage space where the read data is located is:
  • the parity error occurs; if so, the parity is not erroneous.
  • the specific operation of the processor 801 to perform ECC code verification on the total data in the storage block to which the read data belongs is:
  • the storage block is 256 bytes of storage space.
  • the ECC code of the total data in the storage block can be modified only according to the written data and the original data before the writing, which can be solved in the prior art.
  • the data of one storage block must be completely written before the problem of the ECC code can be calculated, so that the random writeability of the storage medium is not damaged.
  • the read data is first performed. Parity check, only when the parity error occurs, the ECC check is performed, which can solve the problem that the ECC check can be performed after the data of one memory block is completely read every time the data is read in the prior art, thereby reducing the problem. Destruction of random readability of storage media.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Un mode de réalisation de l'invention concerne un procédé de mise à jour de code de détection et de correction d'erreurs (ECC). Le procédé est appliqué dans un processus d'écriture de données sur un support de stockage comprenant de multiples blocs de stockage. Le procédé comprend les étapes suivantes : acquérir un code d'ECC pour une quantité totale de données dans chaque bloc de stockage ; quand un octet de données est écrit aléatoirement sur le support de stockage, acquérir les données écrites, un emplacement dans un espace de stockage où les données écrites sont stockées, et des données initiales stockées dans l'espace de stockage avant l'écriture des données ; effectuer une opération logique pour acquérir un code de vérification de colonne d'un code d'ECC pour la quantité totale de données dans le bloc de stockage auquel appartient l'espace de stockage qui a stocké l'octet de données écrit, et réviser, selon les données écrites et les données initiales, un code de vérification de rangée du code d'ECC pour la quantité totale de données dans le bloc de stockage auquel appartient l'espace de stockage ; et obtenir un code d'ECC mis à jour selon le code de vérification de colonne du code d'ECC obtenu par l'opération et le code de vérification de rangée révisé du code d'ECC. L'invention peut éviter que la performance de lecture et d'écriture aléatoires d'un support de stockage se dégrade lorsqu'une vérification d'ECC est effectuée.
PCT/CN2016/091840 2015-11-26 2016-07-27 Procédé et dispositif de mise à jour de code de détection et de correction d'erreurs WO2017088507A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510844082.2A CN106802837B (zh) 2015-11-26 2015-11-26 一种更新错误检测和纠正ecc码的方法及装置
CN201510844082.2 2015-11-26

Publications (1)

Publication Number Publication Date
WO2017088507A1 true WO2017088507A1 (fr) 2017-06-01

Family

ID=58762966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/091840 WO2017088507A1 (fr) 2015-11-26 2016-07-27 Procédé et dispositif de mise à jour de code de détection et de correction d'erreurs

Country Status (2)

Country Link
CN (1) CN106802837B (fr)
WO (1) WO2017088507A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111158948A (zh) * 2019-12-30 2020-05-15 深信服科技股份有限公司 基于去重的数据存储与校验方法、装置及存储介质
CN113053451A (zh) * 2021-03-05 2021-06-29 深圳三地一芯电子有限责任公司 Nandflash内生成softbit的方法、系统、主机以及储存介质
CN117349079A (zh) * 2023-11-16 2024-01-05 苏州门海微电子科技有限公司 一种用于SPI NorFlash的ECC数据纠错方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111984457B (zh) 2019-05-23 2022-09-02 华为技术有限公司 对存储信息更新的方法和装置
CN110727541A (zh) * 2019-09-02 2020-01-24 广东紫晶信息存储技术股份有限公司 一种光盘分块存储校验方法及系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684200A (zh) * 2004-04-12 2005-10-19 恩益禧电子股份有限公司 半导体存储装置
CN101183565A (zh) * 2007-12-12 2008-05-21 深圳市硅格半导体有限公司 存储介质中数据校验方法
US7546517B2 (en) * 2004-08-03 2009-06-09 President And Fellows Of Harvard College Error-correcting circuit for high density memory
CN102110028A (zh) * 2009-12-25 2011-06-29 康佳集团股份有限公司 一种nand闪存及其数据的校验方法和装置
US8239732B2 (en) * 2007-10-30 2012-08-07 Spansion Llc Error correction coding in flash memory devices
CN102904585A (zh) * 2012-11-08 2013-01-30 杭州士兰微电子股份有限公司 动态纠错编、解码方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008027558A (ja) * 2006-07-25 2008-02-07 Hitachi Global Storage Technologies Netherlands Bv データ記録装置、記録媒体、およびエラー検出方法
US8316277B2 (en) * 2007-12-06 2012-11-20 Fusion-Io, Inc. Apparatus, system, and method for ensuring data validity in a data storage process
CN101420283A (zh) * 2008-12-01 2009-04-29 华为技术有限公司 一种同步数字体系中的数据保护方法、装置和通信设备
CN102339647B (zh) * 2010-07-23 2014-05-14 北京兆易创新科技股份有限公司 一种检错/纠错校验模块的检测方法及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684200A (zh) * 2004-04-12 2005-10-19 恩益禧电子股份有限公司 半导体存储装置
US7546517B2 (en) * 2004-08-03 2009-06-09 President And Fellows Of Harvard College Error-correcting circuit for high density memory
US8239732B2 (en) * 2007-10-30 2012-08-07 Spansion Llc Error correction coding in flash memory devices
CN101183565A (zh) * 2007-12-12 2008-05-21 深圳市硅格半导体有限公司 存储介质中数据校验方法
CN102110028A (zh) * 2009-12-25 2011-06-29 康佳集团股份有限公司 一种nand闪存及其数据的校验方法和装置
CN102904585A (zh) * 2012-11-08 2013-01-30 杭州士兰微电子股份有限公司 动态纠错编、解码方法及装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111158948A (zh) * 2019-12-30 2020-05-15 深信服科技股份有限公司 基于去重的数据存储与校验方法、装置及存储介质
CN111158948B (zh) * 2019-12-30 2024-04-09 深信服科技股份有限公司 基于去重的数据存储与校验方法、装置及存储介质
CN113053451A (zh) * 2021-03-05 2021-06-29 深圳三地一芯电子有限责任公司 Nandflash内生成softbit的方法、系统、主机以及储存介质
CN113053451B (zh) * 2021-03-05 2022-05-10 深圳三地一芯电子有限责任公司 Nandflash内生成softbit的方法、系统、主机以及储存介质
CN117349079A (zh) * 2023-11-16 2024-01-05 苏州门海微电子科技有限公司 一种用于SPI NorFlash的ECC数据纠错方法
CN117349079B (zh) * 2023-11-16 2024-05-24 苏州门海微电子科技有限公司 一种用于SPI NorFlash的ECC数据纠错方法

Also Published As

Publication number Publication date
CN106802837A (zh) 2017-06-06
CN106802837B (zh) 2020-02-21

Similar Documents

Publication Publication Date Title
WO2017088507A1 (fr) Procédé et dispositif de mise à jour de code de détection et de correction d'erreurs
TWI649759B (zh) 資料儲存裝置與將資料寫入記憶體裝置之方法
US8694855B1 (en) Error correction code technique for improving read stress endurance
TWI446350B (zh) 用來減少無法更正的錯誤之方法以及記憶裝置及其控制器
US7921339B2 (en) Flash storage device with data correction function
US8782329B2 (en) Method for performing data shaping, and associated memory device and controller thereof
KR101343262B1 (ko) 동시 판독 및 기록 메모리 동작을 수행하는 방법 및 장치
US9130597B2 (en) Non-volatile memory error correction
TWI703499B (zh) 資料儲存裝置及其共享控制器中記憶體的方法
US20140082264A1 (en) Nand flash storage chip checking method and device
KR20090028507A (ko) 비휘발성 메모리 에러 보정 시스템 및 방법
TW201541251A (zh) 快閃記憶體控制器以及資料儲存裝置以及快閃記憶體控制方法
WO2017008501A1 (fr) Procédé de récupération de données lorsqu'une erreur se produisant dans une flash nand ne peut pas être corrigée par ecc
TW201721435A (zh) 資料讀取方法、記憶體控制電路單元及記憶體儲存裝置
US10489244B2 (en) Systems and methods for detecting and correcting memory corruptions in software
US11372720B2 (en) Systems and methods for encoding metadata
US20120297115A1 (en) Program code loading and accessing method, memory controller, and memory storage apparatus
CN104299637A (zh) 快闪存储器装置及其运作方法
EP1980946B1 (fr) Procédé de production de code de correction d'erreurs et dispositif de gestion mémoire
US8966344B2 (en) Data protecting method, memory controller and memory storage device
TW201915736A (zh) 主動錯誤更正失敗處理方法
US9594629B2 (en) Data error correction from cached error correction information
KR20100031402A (ko) 프리 페이지 검출 방법 및 장치와 이를 이용한 에러 정정 코드 디코딩 방법 및 장치
TWI599904B (zh) 電子裝置及其資料驗證方法
US10025652B2 (en) Error location pointers for non volatile memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16867734

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16867734

Country of ref document: EP

Kind code of ref document: A1