WO2017082197A1 - Base substrate and substrate to which group iii-v compound semiconductor is bonded - Google Patents

Base substrate and substrate to which group iii-v compound semiconductor is bonded Download PDF

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Publication number
WO2017082197A1
WO2017082197A1 PCT/JP2016/082942 JP2016082942W WO2017082197A1 WO 2017082197 A1 WO2017082197 A1 WO 2017082197A1 JP 2016082942 W JP2016082942 W JP 2016082942W WO 2017082197 A1 WO2017082197 A1 WO 2017082197A1
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compound semiconductor
base substrate
iii
thermal expansion
expansion coefficient
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PCT/JP2016/082942
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French (fr)
Japanese (ja)
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慶一郎 下司
中山　茂
吉村　雅司
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住友電気工業株式会社
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Priority to JP2017550304A priority Critical patent/JPWO2017082197A1/en
Publication of WO2017082197A1 publication Critical patent/WO2017082197A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

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  • the present invention relates to a base substrate and a III-V compound semiconductor bonded substrate.
  • the present application claims priority based on Japanese Patent Application No. 2015-211984, which is a Japanese patent application filed on November 9, 2015. All the descriptions described in the Japanese patent application are incorporated herein by reference.
  • III-V compound semiconductors represented by GaAs and GaN are widely used as materials for optoelectronic devices such as ultrahigh-speed or ultrahigh-frequency devices, lasers and photodetectors.
  • Such semiconductors are manufactured by various methods.
  • different types of materials such as Si, SiC, and sapphire ( ⁇ -Al 2 O 3 single crystal), which have a different chemical composition from GaN but have a small difference in average linear thermal expansion coefficient
  • MOCVD metal organic chemical deposition
  • MBE molecular beam epitaxial
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2009-260391 discloses a substrate in which a thin layer of the same type of III-V compound semiconductor is bonded to a base substrate as a substrate for forming a III-V compound semiconductor epitaxial layer. Has been proposed.
  • a base substrate according to the present disclosure is a base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
  • the base substrate includes an oxide-based sintered body
  • the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient ⁇ 1 of the base substrate from 30 ° C. to 300 ° C. and the above III-
  • the average linear thermal expansion coefficient ⁇ 2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1): 0.95 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.05 (1)
  • Or the average linear thermal expansion coefficient ⁇ 3 of the base substrate from 30 ° C.
  • a group III-V compound semiconductor bonded substrate according to the present disclosure includes a group III-V compound semiconductor bonded substrate in which the base substrate described in [1] above and a group III-V compound semiconductor layer are bonded. It is a substrate.
  • FIG. 1 is a diagram illustrating a typical configuration example of a group III-V compound semiconductor bonded substrate according to one embodiment of the present invention.
  • the substrate is warped by heating when the III-V compound semiconductor epitaxial layer is formed on the substrate, and the semiconductor device of the III-V compound semiconductor epitaxial layer is formed. The characteristics sometimes deteriorated.
  • the III-V compound semiconductor bonded substrate in which the III-V compound semiconductor layer and the base substrate are bonded the occurrence of warpage when the III-V compound semiconductor epitaxial layer is formed on the bonded substrate. It is an object of the present invention to provide a base substrate that can be suppressed and a group III-V compound semiconductor bonded substrate including the base substrate. [Effects of the present disclosure] According to the present disclosure, when forming a group III-V compound semiconductor epitaxial layer on a group III-V compound semiconductor bonded substrate, a base substrate capable of suppressing the occurrence of warpage in the bonded substrate; and It is possible to provide a group III-V compound semiconductor bonded substrate including the base substrate.
  • a base substrate according to an aspect of the present invention is a base substrate for a III-V compound semiconductor bonded substrate obtained by bonding a III-V compound semiconductor layer and a base substrate,
  • the base substrate includes an oxide-based sintered body
  • the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient ⁇ 1 of the base substrate from 30 ° C. to 300 ° C. and the above III-
  • the average linear thermal expansion coefficient ⁇ 2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1): 0.95 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.05 (1)
  • Or the average linear thermal expansion coefficient ⁇ 3 of the base substrate from 30 ° C.
  • the average linear thermal expansion coefficient ⁇ 1 of the base substrate from 30 ° C. to 300 ° C. and the average linear thermal expansion coefficient ⁇ 2 of the group III-V compound semiconductor layer from 30 ° C. to 300 ° C. satisfy the relationship of the above formula (1).
  • the average linear thermal expansion coefficient ⁇ 3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient ⁇ 4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. are expressed by the above formula (2
  • the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer show the relationship of the above formula (3), the base substrate was fabricated using the base substrate.
  • the III-V compound semiconductor epitaxial layer is formed on the III-V compound semiconductor bonded substrate, it is possible to suppress the warpage of the bonded substrate.
  • the oxide-based sintered body preferably includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2, and Mg 2 AlO 4 .
  • the III-V compound semiconductor layer is preferably a GaAs layer or a GaN layer.
  • These compound semiconductors are semiconductors having excellent characteristics among III-V group compound semiconductors, and a bonded substrate is manufactured using the above-mentioned base substrate as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer. By forming an epitaxial layer on the bonded substrate, a semiconductor device having excellent characteristics can be provided.
  • the base substrate is a base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
  • the base substrate includes an oxide-based sintered body
  • the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient ⁇ 1 of the base substrate from 30 ° C. to 300 ° C. and the above III-
  • the average linear thermal expansion coefficient ⁇ 2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1): 0.95 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.05 (1)
  • the average linear thermal expansion coefficient ⁇ 3 of the base substrate from 30 ° C. to 1000 ° C.
  • the oxide-based sintered body includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 ,
  • the III-V compound semiconductor layer is preferably a base substrate which is a GaAs layer or a GaN layer. A semiconductor substrate having excellent characteristics can be obtained by using the base substrate as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer, and forming an epitaxial layer on the bonded substrate. Can be provided.
  • a group III-V compound semiconductor bonded substrate according to one embodiment of the present invention is obtained by bonding the base substrate according to any one of (1) to (4) above and a group III-V compound semiconductor layer. Further, it is a III-V compound semiconductor bonded substrate.
  • the III-V compound semiconductor bonded substrate can suppress the occurrence of warpage when the III-V compound semiconductor epitaxial layer is formed on the bonded substrate.
  • FIG. 1 is a diagram illustrating a typical configuration example of a group III-V compound semiconductor bonded substrate according to one embodiment of the present invention.
  • the group III-V compound semiconductor bonded substrate 1 is configured by bonding a group III-V compound semiconductor layer 3 made of a group III-V compound semiconductor to a base substrate 2.
  • the base substrate 2 is a molded body including an oxide-based sintered body.
  • the base substrate 2 includes an oxide-based sintered body, and the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are 30 ° C. to 300 ° C. of the base substrate.
  • the average linear thermal expansion coefficient ⁇ 1 up to 30 ° C. and the average linear thermal expansion coefficient ⁇ 2 from 30 ° C. to 300 ° C. of the III-V compound semiconductor layer are expressed by the following formula (1): 0.95 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.05 (1)
  • the average linear thermal expansion coefficient ⁇ 3 of the base substrate from 30 ° C. to 1000 ° C.
  • the average linear thermal expansion coefficient ⁇ 4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C.
  • the average linear thermal expansion coefficient is a value measured based on JIS R 1618.
  • the average linear thermal expansion coefficient ⁇ 1 or the average linear thermal expansion coefficient ⁇ 2 means an average linear thermal expansion coefficient from 30 ° C. to 300 ° C.
  • the average linear thermal expansion coefficient (alpha) 3 or average linear thermal expansion coefficient (alpha) 4 it shall mean the average linear thermal expansion coefficient from 30 degreeC to 1000 degreeC.
  • the Young's modulus is a value measured based on JIS R 1602.
  • the average linear thermal expansion coefficient ⁇ 1 of the base substrate and the average linear thermal expansion coefficient ⁇ 2 of the III-V compound semiconductor layer show the relationship of the above formula (1), or the average linear thermal expansion coefficient ⁇ 3 and III of the base substrate
  • the average linear thermal expansion coefficient ⁇ 4 of the ⁇ V group compound semiconductor layer shows the relationship of the above formula (2)
  • the average linear thermal expansion coefficient of the base substrate and the III-V group compound semiconductor layer is sufficiently approximated. Therefore, a base substrate and a group III-V compound semiconductor layer are bonded to produce a group III-V compound semiconductor bonded substrate, and the bonded substrate is used as a seed substrate for epitaxial growth of a group III-V compound semiconductor single crystal. When used, it is considered that the occurrence of peeling and cracks on the bonding surface due to heating is reduced, and an epitaxially grown layer with high crystal quality can be obtained.
  • the Young's modulus of each of the base substrate and the III-V compound semiconductor layer as well as the relationship between the average linear thermal expansion coefficients of the base substrate and the III-V compound semiconductor layer are shown.
  • the present inventors have found that the relationship affects the occurrence of warpage of the III-V compound semiconductor bonded substrate, and completed the present invention.
  • the average linear thermal expansion coefficient of each of the base substrate and the group III-V compound semiconductor layer shows the relationship of the above formula (1) or formula (2), and the base substrate and the group III-V compound semiconductor
  • the respective Young's moduli of the layers show the relationship of the above formula (3), it is possible to suppress the occurrence of warpage due to heating during III-V compound semiconductor epitaxial growth of the III-V compound semiconductor bonded substrate. I found it.
  • the average linear thermal expansion coefficient ⁇ 1 of the base substrate and the average linear thermal expansion coefficient ⁇ 2 of the III-V compound semiconductor layer are expressed by the following formula from the viewpoint of effectively suppressing the occurrence of peeling and cracks on the bonding surface accompanying heating.
  • (1-2) 0.97 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.03
  • (1-2) 0.98 ⁇ ⁇ 1 / ⁇ 2 ⁇ 1.02
  • the following formula (1-4) ⁇ 1 / ⁇ 2 1 (1-4) It is most preferable to show this relationship.
  • the average linear thermal expansion coefficient ⁇ 3 of the base substrate and the average linear thermal expansion coefficient ⁇ 4 of the III-V compound semiconductor layer are expressed by the following formula from the viewpoint of effectively suppressing the occurrence of peeling and cracks on the bonding surface accompanying heating.
  • (2-2) 0.97 ⁇ ⁇ 3 / ⁇ 4 ⁇ 1.03
  • the average linear thermal expansion coefficient ⁇ 1 or average linear thermal expansion coefficient ⁇ 3 of the base substrate can be appropriately selected according to the type of the III-V group compound semiconductor layer bonded to the base substrate.
  • the average linear thermal expansion coefficient ⁇ 1 of the base substrate is 5.9 ppm / ° C. or higher. It is preferably 3 ppm / ° C. or less, more preferably 6.0 ppm / ° C. or more and 6.2 ppm / ° C. or less, and most preferably 6.1 ppm / ° C.
  • the average linear thermal expansion coefficient ⁇ 3 of the base substrate is 5.8 ppm / ° C. or higher. It is preferably 2 ppm / ° C. or less, more preferably 5.9 ppm / ° C. or more and 6.1 ppm / ° C. or less, and most preferably 6.0 ppm / ° C.
  • the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer satisfy the relationship of the above formula (3), the occurrence of warpage of the bonded substrate due to heating can be suppressed. Note that the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer are more effectively suppressed as the respective values are larger in the range satisfying the relationship of the above formula (3). be able to.
  • the Young's modulus E1 of the base substrate can be appropriately selected according to the type of the III-V group compound semiconductor layer bonded to the base substrate.
  • the Young's modulus E1 of the base substrate is preferably 80 GPa or more, and more preferably 120 GPa or more.
  • the Young's modulus E1 of the base substrate is preferably 200 GPa or more, and more preferably 300 GPa or more.
  • oxide-based sintered body included in the base substrate 2 examples include Al 2 O 3 (alumina), MgO (magnesia), SiO 2 (silica), rare earth oxides (Y 2 O 3 , Sc 2 O 3 , CeO 2). etc) , ZrO 2 , Mg 2 AlO 4 (spinel).
  • these oxide type sintered compacts may be used independently, you may use as a complex oxide type sintered compact combining several oxide type sintered compacts.
  • the complex oxide-based sintered body examples include mullite, AlON, sialon, Y 2 SiO 5 and the like.
  • mullite is a compound of aluminum oxide (alumina) and silicon oxide (silica), in the present invention, mullite (3Al 2) obtained by mixing and sintering alumina and silica in a ratio of 3: 2. O 3 ⁇ 2SiO 2 ) can be preferably used.
  • the oxide-based sintered body preferably includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 .
  • at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 and mullite is used as the oxide-based sintered body, it is more easily close to the average linear thermal expansion coefficient of GaAs or GaN.
  • a base substrate having an average linear thermal expansion coefficient can be obtained.
  • the base substrate 2 can include a non-oxide-based sintered body in addition to the oxide-based sintered body. According to this, a base substrate having an average linear thermal expansion coefficient closer to the average linear thermal expansion coefficient of the III-V group compound semiconductor layer can be obtained.
  • Specific examples of the non-oxide-based sintered body include AlN, SiC, Si 3 N 4 , and GaN. Note that these non-oxide-based sintered bodies may be used in combination with a plurality of non-oxide-based sintered bodies as in the case of the oxide-based sintered body.
  • the base substrate 2 preferably has a surface roughness Ra of the main surface of 0.1 nm to 3.0 nm. This improves the adhesion between the base substrate and the III-V compound semiconductor layer.
  • the main surface of the base substrate is preferably as smooth as possible, and Ra is more preferably 0.1 nm to 2.0 nm, and more preferably 0.1 nm to 1.0 nm. Is more preferable.
  • the main surface means a main surface having the largest area among the surfaces.
  • the thickness of the underlying substrate 2 is not particularly limited, but it is desirable that it has sufficient strength when epitaxially growing a III-V compound semiconductor.
  • the base substrate 2 is preferably thick, but if it is too thick, it may be difficult to apply when epitaxially growing a group III-V compound semiconductor. From the above viewpoint, the thickness of the base substrate is preferably 400 ⁇ m to 700 ⁇ m.
  • the base substrate 2 can be manufactured using a normal method for manufacturing a sintered body. Therefore, it is not necessary to provide special equipment for manufacturing, and since it can be manufactured utilizing the knowledge of the conventional manufacturing method, the III-V compound semiconductor can be easily manufactured without increasing the cost.
  • a base substrate having an average linear thermal expansion coefficient close to that of the layer can be produced. An example of the manufacturing method of the base substrate 2 will be described below.
  • the powder preparation process is performed. Specifically, this is a step of preparing a powder as a material for forming the base substrate including the oxide-based sintered body described above.
  • the type and mixing ratio of the raw material powder are appropriately selected so that a base substrate having an average linear thermal expansion coefficient close to the average linear thermal expansion coefficient of the III-V compound semiconductor layer can be obtained.
  • the molding process is performed. Specifically, this is formed by press molding or CIP (Cold Isostatic Pressing). For example, it is preferable that the mixed powder prepared in the powder preparation step is first preformed by press molding, and then CIP is performed to obtain a compact. However, only one of press molding and CIP may be performed here, or both CIP may be performed after press molding, for example.
  • press molding Cold Isostatic Pressing
  • CIP Cold Isostatic Pressing
  • a pressure of 10 MPa to 300 MPa, particularly 20 MPa is preferably used, and in CIP, for example, a pressure of 160 MPa to 250 MPa, particularly 180 MPa to 230 MPa is preferably used.
  • the sintering process includes an atmospheric sintering method in which a molded body is placed and sintered in an air atmosphere, or a HIP (Hot Isostatic) in which a molded body is placed in an argon atmosphere and pressure-sintered. (Pressing; hot isostatic pressing) is preferably used. Alternatively, a hot press method may be used instead of the above method. Only one of the atmospheric sintering method and HIP may be performed, or a plurality of operations may be performed, for example, HIP is performed after the atmospheric sintering method is performed. Further, heat treatment may be performed again after HIP.
  • HIP Het Isostatic
  • the molded body is placed in an air atmosphere, heated to 1400 ° C. or higher and 1700 ° C. or lower and held for 1 hour or longer and 3 hours or shorter. In this way, a sintered body having a density of 95% or more can be formed.
  • the above sintered body (or a molded body that has not been sintered by hot pressing) is placed in an argon atmosphere and heated to 1500 ° C. or higher and 1800 ° C. or lower while applying a pressure of 150 MPa or higher and 250 MPa or lower. And sintering by holding for 1 hour or more and 3 hours or less.
  • the density of the formed sintered body can be set to a density sufficient to satisfy the conditions required for the finally formed substrate. This is because compositional deformation of the sintered body occurs due to pressurization, and voids inside the sintered body are removed to the outside by the diffusion mechanism.
  • a processing step is performed on the sintered body sintered as described above. Specifically, first, the sintered body is cut (cut) by slicing so as to have a desired thickness (of the base substrate 2). Thereby, the foundation
  • the desired thickness is preferably determined in consideration of the thickness of the base substrate 2 to be finally formed, the allowance for polishing the main surface of the base substrate 2 in a later step, and the like.
  • the base main surface of the base substrate 2 is polished. Specifically, this is a step of polishing the main surface of the base substrate 2 finally formed as described above so that the average roughness Ra becomes a desired value.
  • the main surface of the base substrate 2 is polished in order to achieve excellent flatness, it is preferable to sequentially perform three-stage polishing including rough polishing, normal polishing, and polishing using diamond abrasive grains.
  • the main surface is mirror-finished using a polishing machine.
  • the count of abrasive grains used for polishing differs between rough polishing and normal polishing.
  • the polishing as the finishing process is preferably performed using diamond abrasive grains as described above.
  • Diamond abrasive grains are extremely high in hardness, and the average grain diameter of the abrasive grains is as small as about 0.5 ⁇ m to 1.0 ⁇ m, so that they are suitable for use as abrasive grains for high-precision mirror finishing.
  • polishing is performed for 10 minutes using the abrasive grains. By doing so, it is possible to realize a main surface with high flatness, in which the above-described average roughness Ra of the main surface is not less than 0.1 nm and not more than 3.0 nm.
  • the group III-V compound semiconductor layer 3 is a layer made of a group III-V compound semiconductor, and an epitaxial growth layer is formed on this main surface.
  • the III-V compound semiconductor is a semiconductor using a group 13 element and a group 15 element in the periodic table.
  • the 13 elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).
  • the group 15 element include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).
  • Specific examples of the III-V compound semiconductor include GaAs, InP, GaN, and the like.
  • the III-V compound semiconductor layer 3 is preferably a GaAs layer or a GaN layer. These compound semiconductors are semiconductors having excellent characteristics among group III-V compound semiconductors, and the above-described base substrate is used as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer. A semiconductor device having excellent characteristics can be provided by manufacturing and forming an epitaxial layer on the bonded substrate.
  • the III-V compound semiconductor bonded substrate 1 is obtained by, for example, cleaning a III-V compound semiconductor wafer by dry etching, and then, the main surface (N surface) of the III-V compound semiconductor wafer and the main surface of the base substrate. Can be produced by bonding them in the air.
  • the pressure at the time of bonding can be, for example, 5 MPa (1000 kgf / 2 inch wafer) to 10 MPa (2000 kgf / 2 inch wafer).
  • the dry powder was preformed by press molding, followed by CIP to obtain a molded body.
  • press molding a pressure of 10 MPa was applied, and in CIP, a pressure of 200 MPa was applied.
  • the molded body was placed in an air atmosphere and sintered at 1500 ° C. for 9 hours. Further, the obtained sintered body was placed in an argon atmosphere, heated to 1600 ° C. while applying a pressure of 200 MPa, and held for 2 hours to perform HIP.
  • polishing was performed in the order of rough polishing, normal polishing, and finishing polishing. Polishing was performed using a # 800 GC grindstone for rough polishing, diamond abrasive grains having a particle diameter of 3 ⁇ m for normal polishing, and diamond abrasive grains having a particle diameter of 1 ⁇ m for final polishing.
  • III-V compound semiconductor bonded substrate After the GaAs wafer is cleaned by dry etching, the main surface of the GaAs wafer (size ⁇ 100 mm ⁇ thickness 250 ⁇ m) and the main surface of the base substrate (size ⁇ 100 mm ⁇ thickness 500 ⁇ m) are bonded together in the atmosphere to form a III-V group compound A semiconductor bonded substrate was produced (size ⁇ 100 mm ⁇ thickness 750 ⁇ m).
  • the pressure at the time of bonding was 7 MPa (1400 kgf / 2 inch wafer).
  • III-V compound semiconductor bonded substrate (Evaluation of III-V compound semiconductor bonded substrate) The III-V compound semiconductor bonded substrate obtained above was allowed to stand in an atmosphere of 300 ° C. for 60 minutes. 300 ° C. is the maximum temperature used in the step of epitaxially growing GaAs on the bonded substrate. Thereafter, the amount of warpage of the bonded substrate was measured. The amount of warpage is a value measured with a non-contact warpage measuring machine. A case where the amount of warpage is less than 0.20 mm is judged as good. The results are shown in Table 1.
  • a base substrate was produced in the same manner as in Production Example 1 using the type and blending ratio of the oxide-based sintered powder shown in Table 1.
  • III-V compound semiconductor bonded substrate was fabricated using the compound semiconductor wafer and the base substrate in the same manner as in Production Example 1.
  • III-V compound semiconductor bonded substrate, 2 base substrate, III-V compound semiconductor layer.

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Abstract

A base substrate for a substrate to which a group III-V compound semiconductor is bonded, in which a group III-V compound semiconductor layer and the base substrate are bonded to each other, wherein: the base substrate contains an oxide-based sintered body; the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are such that the average linear thermal expansion coefficient α1 of the base substrate from 30°C to 300°C and the average linear thermal expansion coefficient α2 of the group III-V compound semiconductor layer from 30°C to 300°C have the following relationship (1): 0.95 ≤ α1/α2 ≤ 1.05 (Formula 1), or the average linear thermal expansion coefficient α3 of the base substrate from 30°C to 1000°C and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30°C to 1000°C have the following relationship (2): 0.95 ≤ α3/α4 ≤ 1.05 (Formula 1); and the Young's modulus E1 of the base substrate and the Young's modulus E2 of the group III-V compound semiconductor layer have the following relationship (3): E1/E2 ≥ 1.00 (Formula 3).

Description

下地基板及びＩＩＩ－Ｖ族化合物半導体貼り合せ基板Base substrate and III-V compound semiconductor bonded substrate
　本発明は、下地基板及びＩＩＩ－Ｖ族化合物半導体貼り合せ基板に関する。本出願は、２０１５年１１月９日に出願した日本特許出願である特願２０１５－２１９８０４号に基づく優先権を主張する。当該日本特許出願に記載された全ての記載内容は、参照によって本明細書に援用される。 The present invention relates to a base substrate and a III-V compound semiconductor bonded substrate. The present application claims priority based on Japanese Patent Application No. 2015-211984, which is a Japanese patent application filed on November 9, 2015. All the descriptions described in the Japanese patent application are incorporated herein by reference.
　ＧａＡｓやＧａＮに代表されるＩＩＩ－Ｖ族化合物半導体は、超高速あるいは超高周波デバイス、レーザー・光検出器等のオプトエレクトロニクスデバイス用材料として広く使用されている。 III-V compound semiconductors represented by GaAs and GaN are widely used as materials for optoelectronic devices such as ultrahigh-speed or ultrahigh-frequency devices, lasers and photodetectors.
　このような半導体は、種々の方法により作製されている。例えば、ＧａＮ半導体の場合には、一つの方法として、ＧａＮと化学組成が異なるが、平均線熱膨張係数の差が小さいＳｉ、ＳｉＣ、サファイア（α－Ａｌ２Ｏ３の単結晶）などの異種基板上に、ＭＯＣＶＤ（有機金属化学堆積）法やＭＢＥ（分子線エピタキシャル）法などにより、ＧａＮエピタキシャル層を形成させる方法がある。 Such semiconductors are manufactured by various methods. For example, in the case of a GaN semiconductor, as one method, different types of materials such as Si, SiC, and sapphire (α-Al 2 O 3 single crystal), which have a different chemical composition from GaN but have a small difference in average linear thermal expansion coefficient There is a method of forming a GaN epitaxial layer on a substrate by MOCVD (metal organic chemical deposition) method, MBE (molecular beam epitaxial) method or the like.
　たとえば、特許文献１（特開２００９－２６０３９１号公報）には、ＩＩＩ－Ｖ族化合物半導体エピタキシャル層の形成用基板として、同種のＩＩＩ－Ｖ族化合物半導体の薄い層を下地基板に貼り合わせた基板が提案されている。 For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2009-260391) discloses a substrate in which a thin layer of the same type of III-V compound semiconductor is bonded to a base substrate as a substrate for forming a III-V compound semiconductor epitaxial layer. Has been proposed.
特開２００９－２６０３９１号公報JP 2009-260391 A
　［１］本開示に係る下地基板は、ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板用の下地基板であって、
　上記下地基板は、酸化物系焼結体を含み、
　上記下地基板の平均線熱膨張係数と、上記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、上記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
０．９５≦α１／α２≦１．０５　　（１）
の関係を示す、又は、上記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：
０．９５≦α３／α４≦１．０５　　（２）
の関係を示し、
　上記下地基板のヤング率Ｅ１と、上記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
Ｅ１／Ｅ２≧１．００　　（３）
の関係を示す、
　下地基板である。 [1] A base substrate according to the present disclosure is a base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
The base substrate includes an oxide-based sintered body,
The average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C. and the above III- The average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1):
0.95 ≦ α1 / α2 ≦ 1.05 (1)
Or the average linear thermal expansion coefficient α3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. The following formula (2):
0.95 ≦ α3 / α4 ≦ 1.05 (2)
Shows the relationship
The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
E1 / E2 ≧ 1.00 (3)
Showing the relationship
It is a base substrate.
　［２］本開示に係るＩＩＩ－Ｖ族化合物半導体貼り合せ基板は、上記［１］に記載の下地基板と、ＩＩＩ－Ｖ族化合物半導体層とが貼り合わされた、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板である。 [2] A group III-V compound semiconductor bonded substrate according to the present disclosure includes a group III-V compound semiconductor bonded substrate in which the base substrate described in [1] above and a group III-V compound semiconductor layer are bonded. It is a substrate.
図１は、本発明の一態様にかかるＩＩＩ－Ｖ族化合物半導体貼り合せ基板の代表的な構成例を説明する図である。FIG. 1 is a diagram illustrating a typical configuration example of a group III-V compound semiconductor bonded substrate according to one embodiment of the present invention.
[本開示が解決しようとする課題]
　しかしながら、このような半導体層貼り合わせ基板においては、基板上にＩＩＩ－Ｖ族化合物半導体エピタキシャル層を形成する際の加熱により、基板に反りが発生し、ＩＩＩ－Ｖ族化合物半導体エピタキシャル層の半導体デバイス特性が低下する場合があった。 [Problems to be solved by this disclosure]
However, in such a semiconductor layer bonded substrate, the substrate is warped by heating when the III-V compound semiconductor epitaxial layer is formed on the substrate, and the semiconductor device of the III-V compound semiconductor epitaxial layer is formed. The characteristics sometimes deteriorated.
　そこで、ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板において、貼り合せ基板上にＩＩＩ－Ｖ族化合物半導体エピタキシャル層を形成する際の反りの発生を抑制することのできる下地基板、及び、該下地基板を含むＩＩＩ－Ｖ族化合物半導体貼り合せ基板を提供することを目的とする。
[本開示の効果]
　本開示によれば、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板上にＩＩＩ－Ｖ族化合物半導体エピタキシャル層を形成する際に、貼り合せ基板に反りが発生することを抑制することのできる下地基板、及び、該下地基板を含むＩＩＩ－Ｖ族化合物半導体貼り合せ基板を提供することが可能となる。 Therefore, in the III-V compound semiconductor bonded substrate in which the III-V compound semiconductor layer and the base substrate are bonded, the occurrence of warpage when the III-V compound semiconductor epitaxial layer is formed on the bonded substrate. It is an object of the present invention to provide a base substrate that can be suppressed and a group III-V compound semiconductor bonded substrate including the base substrate.
[Effects of the present disclosure]
According to the present disclosure, when forming a group III-V compound semiconductor epitaxial layer on a group III-V compound semiconductor bonded substrate, a base substrate capable of suppressing the occurrence of warpage in the bonded substrate; and It is possible to provide a group III-V compound semiconductor bonded substrate including the base substrate.
　［本発明の実施形態の説明］
　最初に本発明の実施態様を列記して説明する。 [Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described.
　（１）本発明の一態様に係る下地基板は、ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板用の下地基板であって、
　上記下地基板は、酸化物系焼結体を含み、
　上記下地基板の平均線熱膨張係数と、上記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、上記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
０．９５≦α１／α２≦１．０５　　（１）
の関係を示す、又は、上記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：０．９５≦α３／α４≦１．０５　　（２）
の関係を示し、
　上記下地基板のヤング率Ｅ１と、上記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
Ｅ１／Ｅ２≧１．００　　（３）
の関係を示す、
　下地基板である。 (1) A base substrate according to an aspect of the present invention is a base substrate for a III-V compound semiconductor bonded substrate obtained by bonding a III-V compound semiconductor layer and a base substrate,
The base substrate includes an oxide-based sintered body,
The average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C. and the above III- The average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1):
0.95 ≦ α1 / α2 ≦ 1.05 (1)
Or the average linear thermal expansion coefficient α3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. The following formula (2): 0.95 ≦ α3 / α4 ≦ 1.05 (2)
Shows the relationship
The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
E1 / E2 ≧ 1.00 (3)
Showing the relationship
It is a base substrate.
　下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、上記式（１）の関係を示す、又は、下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、上記式（２）の関係を示し、さらに、下地基板のヤング率Ｅ１と、ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とが、上記式（３）の関係を示すと、該下地基板を用いて作製されたＩＩＩ－Ｖ族化合物半導体貼り合せ基板上に、ＩＩＩ－Ｖ族化合物半導体エピタキシャル層を形成する際に、貼り合せ基板に反りが発生すること抑制することができる。 The average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C. and the average linear thermal expansion coefficient α2 of the group III-V compound semiconductor layer from 30 ° C. to 300 ° C. satisfy the relationship of the above formula (1). Or the average linear thermal expansion coefficient α3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. are expressed by the above formula (2 Further, when the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer show the relationship of the above formula (3), the base substrate was fabricated using the base substrate. When the III-V compound semiconductor epitaxial layer is formed on the III-V compound semiconductor bonded substrate, it is possible to suppress the warpage of the bonded substrate.
　（２）上記酸化物系焼結体は、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２、希土類酸化物、ＺｒＯ２及びＭｇ２ＡｌＯ４からなる群より選択される少なくとも１種類を含むことが好ましい。これらの酸化物系焼結体を用いると、より容易に、ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数に近い平均線熱膨張係数を有する下地基板を得ることができる。 (2) The oxide-based sintered body preferably includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2, and Mg 2 AlO 4 . By using these oxide-based sintered bodies, a base substrate having an average linear thermal expansion coefficient close to the average linear thermal expansion coefficient of the III-V compound semiconductor layer can be obtained more easily.
　（３）上記ＩＩＩ－Ｖ族化合物半導体層は、ＧａＡｓ層又はＧａＮ層であることが好ましい。これらの化合物半導体は、ＩＩＩ－Ｖ族化合物半導体の内でも特性の優れた半導体であり、上記下地基板を、ＧａＡｓ半導体層又はＧａＮ半導体層との貼り合わせ用下地基板として用いて貼り合せ基板を作製し、該貼り合せ基板上にエピタキシャル層を形成することにより、特性に優れた半導体デバイスを提供することができる。 (3) The III-V compound semiconductor layer is preferably a GaAs layer or a GaN layer. These compound semiconductors are semiconductors having excellent characteristics among III-V group compound semiconductors, and a bonded substrate is manufactured using the above-mentioned base substrate as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer. By forming an epitaxial layer on the bonded substrate, a semiconductor device having excellent characteristics can be provided.
　（４）上記下地基板は、ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板用の下地基板であって、
　上記下地基板は、酸化物系焼結体を含み、
　上記下地基板の平均線熱膨張係数と、上記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、上記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
０．９５≦α１／α２≦１．０５　　（１）
の関係を示す、又は、上記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：
０．９５≦α３／α４≦１．０５　　（２）
の関係を示し、
　上記下地基板のヤング率Ｅ１と、上記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
Ｅ１／Ｅ２≧１．００　　（３）
の関係を示し、
　上記酸化物系焼結体は、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２、希土類酸化物、ＺｒＯ２及びＭｇ２ＡｌＯ４からなる群より選択される少なくとも１種類を含み、
　上記ＩＩＩ－Ｖ族化合物半導体層は、ＧａＡｓ層又はＧａＮ層である、下地基板であることが好ましい。上記下地基板を、ＧａＡｓ半導体層又はＧａＮ半導体層との貼り合わせ用下地基板として用いて貼り合せ基板を作製し、該貼り合せ基板上にエピタキシャル層を形成することにより、特性に優れた半導体デバイスを提供することができる。 (4) The base substrate is a base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
The base substrate includes an oxide-based sintered body,
The average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C. and the above III- The average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1):
0.95 ≦ α1 / α2 ≦ 1.05 (1)
Or the average linear thermal expansion coefficient α3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. The following formula (2):
0.95 ≦ α3 / α4 ≦ 1.05 (2)
Shows the relationship
The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
E1 / E2 ≧ 1.00 (3)
Shows the relationship
The oxide-based sintered body includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 ,
The III-V compound semiconductor layer is preferably a base substrate which is a GaAs layer or a GaN layer. A semiconductor substrate having excellent characteristics can be obtained by using the base substrate as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer, and forming an epitaxial layer on the bonded substrate. Can be provided.
　（５）本発明の一態様に係るＩＩＩ－Ｖ族化合物半導体貼り合せ基板は、上記（１）～（４）のいずれかに記載の下地基板と、ＩＩＩ－Ｖ族化合物半導体層とが貼り合わされた、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板である。該ＩＩＩ－Ｖ族化合物半導体貼り合せ基板は、貼り合せ基板上にＩＩＩ－Ｖ族化合物半導体エピタキシャル層を形成する際の反りの発生を抑制することができる。 (5) A group III-V compound semiconductor bonded substrate according to one embodiment of the present invention is obtained by bonding the base substrate according to any one of (1) to (4) above and a group III-V compound semiconductor layer. Further, it is a III-V compound semiconductor bonded substrate. The III-V compound semiconductor bonded substrate can suppress the occurrence of warpage when the III-V compound semiconductor epitaxial layer is formed on the bonded substrate.
　［本発明の実施形態の詳細］
　本発明の実施形態にかかる下地基板及びＩＩＩ－Ｖ族化合物半導体貼り合せ基板の具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、請求の範囲によって示され、請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。 [Details of the embodiment of the present invention]
Specific examples of the base substrate and the III-V compound semiconductor bonded substrate according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.
　［ＩＩＩ－Ｖ族化合物半導体貼り合せ基板の構成］
　図１は、本発明の一態様にかかるＩＩＩ－Ｖ族化合物半導体貼り合せ基板の代表的な構成例を説明する図である。図１に示されるように、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板１は、下地基板２に、ＩＩＩ－Ｖ族化合物半導体からなるＩＩＩ－Ｖ族化合物半導体層３を貼り合わせて構成されている。下地基板２は、酸化物系焼結体を含む成形体である。 [Configuration of Group III-V Compound Semiconductor Bonded Substrate]
FIG. 1 is a diagram illustrating a typical configuration example of a group III-V compound semiconductor bonded substrate according to one embodiment of the present invention. As shown in FIG. 1, the group III-V compound semiconductor bonded substrate 1 is configured by bonding a group III-V compound semiconductor layer 3 made of a group III-V compound semiconductor to a base substrate 2. The base substrate 2 is a molded body including an oxide-based sintered body.
　［下地基板］
　下地基板２は、酸化物系焼結体を含み、上記下地基板の平均線熱膨張係数と、上記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、上記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
０．９５≦α１／α２≦１．０５　　（１）
の関係を示す、又は、上記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、上記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：
０．９５≦α３／α４≦１．０５　　（２）
の関係を示し、
上記下地基板のヤング率Ｅ１と、上記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
　Ｅ１／Ｅ２≧１．００　　（３）
の関係を示す。 [Base substrate]
The base substrate 2 includes an oxide-based sintered body, and the average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are 30 ° C. to 300 ° C. of the base substrate. The average linear thermal expansion coefficient α1 up to 30 ° C. and the average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the III-V compound semiconductor layer are expressed by the following formula (1):
0.95 ≦ α1 / α2 ≦ 1.05 (1)
Or the average linear thermal expansion coefficient α3 of the base substrate from 30 ° C. to 1000 ° C. and the average linear thermal expansion coefficient α4 of the group III-V compound semiconductor layer from 30 ° C. to 1000 ° C. The following formula (2):
0.95 ≦ α3 / α4 ≦ 1.05 (2)
Shows the relationship
The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
E1 / E2 ≧ 1.00 (3)
The relationship is shown.
　本明細書中、平均線熱膨張係数とは、ＪＩＳ　Ｒ　１６１８に基づいて測定される値である。以下、平均線熱膨張係数α１又は平均線熱膨張係数α２と記載した場合は、３０℃から３００℃までの平均線熱膨張係数を意味するものとする。また、平均線熱膨張係数α３又は平均線熱膨張係数α４と記載した場合は、３０℃から１０００℃までの平均線熱膨張係数を意味するものとする。また、ヤング率とは、ＪＩＳ　Ｒ　１６０２に基づいて測定される値である。 In this specification, the average linear thermal expansion coefficient is a value measured based on JIS R 1618. Hereinafter, the average linear thermal expansion coefficient α1 or the average linear thermal expansion coefficient α2 means an average linear thermal expansion coefficient from 30 ° C. to 300 ° C. Moreover, when it describes as average linear thermal expansion coefficient (alpha) 3 or average linear thermal expansion coefficient (alpha) 4, it shall mean the average linear thermal expansion coefficient from 30 degreeC to 1000 degreeC. The Young's modulus is a value measured based on JIS R 1602.
　下地基板の平均線熱膨張係数α１とＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数α２とが、上記式（１）の関係を示す、又は、下地基板の平均線熱膨張係数α３とＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数α４とが、上記式（２）の関係を示すと、下地基板とＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数が十分に近似しているため、下地基板とＩＩＩ－Ｖ族化合物半導体層とを貼り合わせてＩＩＩ－Ｖ族化合物半導体貼り合せ基板を作製し、該貼り合せ基板をＩＩＩ－Ｖ族化合物半導体単結晶のエピタキシャル成長用の種基板として用いた場合に、加熱に伴う貼り合わせ面での剥離やクラックの発生が減少し、結晶品質の高いエピタキシャル成長層を得ることができると考えられる。 The average linear thermal expansion coefficient α1 of the base substrate and the average linear thermal expansion coefficient α2 of the III-V compound semiconductor layer show the relationship of the above formula (1), or the average linear thermal expansion coefficient α3 and III of the base substrate When the average linear thermal expansion coefficient α4 of the −V group compound semiconductor layer shows the relationship of the above formula (2), the average linear thermal expansion coefficient of the base substrate and the III-V group compound semiconductor layer is sufficiently approximated. Therefore, a base substrate and a group III-V compound semiconductor layer are bonded to produce a group III-V compound semiconductor bonded substrate, and the bonded substrate is used as a seed substrate for epitaxial growth of a group III-V compound semiconductor single crystal. When used, it is considered that the occurrence of peeling and cracks on the bonding surface due to heating is reduced, and an epitaxially grown layer with high crystal quality can be obtained.
　しかしながら、本発明者らは、下地基板とＩＩＩ－Ｖ族化合物半導体層のそれぞれの平均線熱膨張係数が、上記式（１）又は式（２）の関係を示す場合であっても、エピタキシャル成長時に貼り合せ基板に反りが発生し、結晶品質の高いエピタキシャル成長層を得られず、半導体デバイス特性が低下することを見出した。 However, even when the average linear thermal expansion coefficients of the underlying substrate and the III-V group compound semiconductor layer show the relationship of the above formula (1) or formula (2), the present inventors It was found that the bonded substrate was warped, an epitaxial growth layer with high crystal quality could not be obtained, and the semiconductor device characteristics were deteriorated.
　そこで、本発明者らが鋭意検討した結果、下地基板とＩＩＩ－Ｖ族化合物半導体層のそれぞれの平均線熱膨張係数の関係とともに、下地基板とＩＩＩ－Ｖ族化合物半導体層のそれぞれのヤング率の関係が、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板の反りの発生に影響を与えていることを見出し、本発明を完成させた。具体的には、下地基板とＩＩＩ－Ｖ族化合物半導体層のそれぞれの平均線熱膨張係数が、上記式（１）又は式（２）の関係を示すとともに、下地基板とＩＩＩ－Ｖ族化合物半導体層のそれぞれのヤング率が、上記式（３）の関係を示す場合に、ＩＩＩ－Ｖ族化合物半導体貼り合せ基板の、ＩＩＩ－Ｖ族化合物半導体エピタキシャル成長時の加熱に伴う反りの発生を抑制できることを見出した。 Therefore, as a result of intensive studies by the present inventors, the Young's modulus of each of the base substrate and the III-V compound semiconductor layer as well as the relationship between the average linear thermal expansion coefficients of the base substrate and the III-V compound semiconductor layer are shown. The present inventors have found that the relationship affects the occurrence of warpage of the III-V compound semiconductor bonded substrate, and completed the present invention. Specifically, the average linear thermal expansion coefficient of each of the base substrate and the group III-V compound semiconductor layer shows the relationship of the above formula (1) or formula (2), and the base substrate and the group III-V compound semiconductor When the respective Young's moduli of the layers show the relationship of the above formula (3), it is possible to suppress the occurrence of warpage due to heating during III-V compound semiconductor epitaxial growth of the III-V compound semiconductor bonded substrate. I found it.
　下地基板の平均線熱膨張係数α１とＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数α２は、加熱に伴う貼り合わせ面での剥離やクラックの発生を効果的に抑制する観点から、下記式（１－２）
　０．９７≦α１／α２≦１．０３　　（１－２）
の関係を示すことが好ましく、下記式（１－３）
　０．９８≦α１／α２≦１．０２　　（１－３）
の関係を示すことがさらに好ましく、下記式（１－４）
　α１／α２＝１　　（１－４）
の関係を示すことが最も好ましい。 The average linear thermal expansion coefficient α1 of the base substrate and the average linear thermal expansion coefficient α2 of the III-V compound semiconductor layer are expressed by the following formula from the viewpoint of effectively suppressing the occurrence of peeling and cracks on the bonding surface accompanying heating. (1-2)
0.97 ≦ α1 / α2 ≦ 1.03 (1-2)
It is preferable that the following formula (1-3)
0.98 ≦ α1 / α2 ≦ 1.02 (1-3)
More preferably, the following formula (1-4)
α1 / α2 = 1 (1-4)
It is most preferable to show this relationship.
　下地基板の平均線熱膨張係数α３とＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数α４は、加熱に伴う貼り合わせ面での剥離やクラックの発生を効果的に抑制する観点から、下記式（２－２）
　０．９７≦α３／α４≦１．０３　　（２－２）
の関係を示すことが好ましく、下記式（２－３）
　０．９８≦α３／α４≦１．０２　　（２－３）
の関係を示すことがさらに好ましく、下記式（２－４）
　α３／α４＝１　　（２－４）
の関係を示すことが最も好ましい。 The average linear thermal expansion coefficient α3 of the base substrate and the average linear thermal expansion coefficient α4 of the III-V compound semiconductor layer are expressed by the following formula from the viewpoint of effectively suppressing the occurrence of peeling and cracks on the bonding surface accompanying heating. (2-2)
0.97 ≦ α3 / α4 ≦ 1.03 (2-2)
The following relationship (2-3)
0.98 ≦ α3 / α4 ≦ 1.02 (2-3)
More preferably, the following formula (2-4)
α3 / α4 = 1 (2-4)
It is most preferable to show this relationship.
　下地基板の平均線熱膨張係数α１又は平均線熱膨張係数α３は、下地基板と貼り合わされるＩＩＩ－Ｖ族化合物半導体層の種類に応じて、適宜選択することができる。 The average linear thermal expansion coefficient α1 or average linear thermal expansion coefficient α3 of the base substrate can be appropriately selected according to the type of the III-V group compound semiconductor layer bonded to the base substrate.
　例えば、ＩＩＩ－Ｖ族化合物半導体層としてＧａＡｓ層（平均線熱膨張係数α２：６．１ｐｐｍ／℃）を用いる場合は、下地基板の平均線熱膨張係数α１は、５．９ｐｐｍ／℃以上６．３ｐｐｍ／℃以下であることが好ましく、６．０ｐｐｍ／℃以上６．２ｐｐｍ／℃以下であることがさらに好ましく、６．１ｐｐｍ／℃であることが最も好ましい。 For example, when a GaAs layer (average linear thermal expansion coefficient α2: 6.1 ppm / ° C.) is used as the III-V group compound semiconductor layer, the average linear thermal expansion coefficient α1 of the base substrate is 5.9 ppm / ° C. or higher. It is preferably 3 ppm / ° C. or less, more preferably 6.0 ppm / ° C. or more and 6.2 ppm / ° C. or less, and most preferably 6.1 ppm / ° C.
　例えば、ＩＩＩ－Ｖ族化合物半導体層としてＧａＮ層（平均線熱膨張係数α２：６．０ｐｐｍ／℃）を用いる場合は、下地基板の平均線熱膨張係数α３は、５．８ｐｐｍ／℃以上６．２ｐｐｍ／℃以下であることが好ましく、５．９ｐｐｍ／℃以上６．１ｐｐｍ／℃以下であることがさらに好ましく、６．０ｐｐｍ／℃であることが最も好ましい。 For example, when a GaN layer (average linear thermal expansion coefficient α2: 6.0 ppm / ° C.) is used as the III-V group compound semiconductor layer, the average linear thermal expansion coefficient α3 of the base substrate is 5.8 ppm / ° C. or higher. It is preferably 2 ppm / ° C. or less, more preferably 5.9 ppm / ° C. or more and 6.1 ppm / ° C. or less, and most preferably 6.0 ppm / ° C.
　下地基板のヤング率Ｅ１と、ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、上記式（３）の関係を満たせば、加熱に伴う貼り合せ基板の反りの発生を抑制することができる。なお、下地基板のヤング率Ｅ１及びＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２は、上記式（３）の関係を満たす範囲において、それぞれの値が大きいほど、効果的に反りの発生を抑制することができる。 When the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer satisfy the relationship of the above formula (3), the occurrence of warpage of the bonded substrate due to heating can be suppressed. Note that the Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V group compound semiconductor layer are more effectively suppressed as the respective values are larger in the range satisfying the relationship of the above formula (3). be able to.
　下地基板のヤング率Ｅ１は、下地基板と貼り合わされるＩＩＩ－Ｖ族化合物半導体層の種類に応じて、適宜選択することができる。 The Young's modulus E1 of the base substrate can be appropriately selected according to the type of the III-V group compound semiconductor layer bonded to the base substrate.
　例えば、ＩＩＩ－Ｖ族化合物半導体層としてＧａＡｓ層（ヤング率Ｅ２：８０ＧＰａ）を用いる場合は、下地基板のヤング率Ｅ１は、８０ＧＰａ以上であることが好ましく、１２０ＧＰａ以上であることがさらに好ましい。 For example, when a GaAs layer (Young's modulus E2: 80 GPa) is used as the III-V group compound semiconductor layer, the Young's modulus E1 of the base substrate is preferably 80 GPa or more, and more preferably 120 GPa or more.
　例えば、ＩＩＩ－Ｖ族化合物半導体層としてＧａＮ層（ヤング率Ｅ２：２００ＧＰａ）を用いる場合は、下地基板のヤング率Ｅ１は、２００ＧＰａ以上であることが好ましく、３００ＧＰａ以上であることがさらに好ましい。 For example, when a GaN layer (Young's modulus E2: 200 GPa) is used as the III-V group compound semiconductor layer, the Young's modulus E1 of the base substrate is preferably 200 GPa or more, and more preferably 300 GPa or more.
　下地基板２に含まれる酸化物系焼結体としては、Ａｌ２Ｏ３（アルミナ）、ＭｇＯ（マグネシア）、ＳｉＯ２（シリカ）、希土類酸化物(Ｙ２Ｏ３、Ｓｃ２Ｏ３、ＣｅＯ２等）
、ＺｒＯ２、Ｍｇ２ＡｌＯ４（スピネル）を挙げることができる。なお、これらの酸化物系焼結体は、単独で用いてもよいが、複数の酸化物系焼結体を組み合わせた、複合酸化物系焼結体として用いてもよい。複合酸化物系焼結体としては、ムライト、ＡｌＯＮ、サイアロン、Ｙ２ＳｉＯ５等を挙げることができる。なお、ムライトは酸化アルミニウム（アルミナ）と酸化ケイ素（シリカ）の化合物であるが、本発明においては、アルミナとシリカを３：２の割合で混合して焼結して得られたムライト（３Ａｌ２Ｏ３・２ＳｉＯ２）を好ましく使用することができる。 Examples of the oxide-based sintered body included in the base substrate 2 include Al 2 O 3 (alumina), MgO (magnesia), SiO 2 (silica), rare earth oxides (Y 2 O 3 , Sc 2 O 3 , CeO 2). etc)
, ZrO 2 , Mg 2 AlO 4 (spinel). In addition, although these oxide type sintered compacts may be used independently, you may use as a complex oxide type sintered compact combining several oxide type sintered compacts. Examples of the complex oxide-based sintered body include mullite, AlON, sialon, Y 2 SiO 5 and the like. In addition, although mullite is a compound of aluminum oxide (alumina) and silicon oxide (silica), in the present invention, mullite (3Al 2) obtained by mixing and sintering alumina and silica in a ratio of 3: 2. O 3 · 2SiO 2 ) can be preferably used.
　酸化物系焼結体は、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２、希土類酸化物、ＺｒＯ２及びＭｇ２ＡｌＯ４からなる群より選択される少なくとも１種類を含むことが好ましい。中でも、酸化物系焼結体として、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２及びムライトからなる群より選択される少なくとも１種類を用いると、より容易に、ＧａＡｓやＧａＮの平均線熱膨張係数に近い平均線熱膨張係数を有する下地基板を得ることができる。 The oxide-based sintered body preferably includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 . In particular, when at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 and mullite is used as the oxide-based sintered body, it is more easily close to the average linear thermal expansion coefficient of GaAs or GaN. A base substrate having an average linear thermal expansion coefficient can be obtained.
　下地基板２は、酸化物系焼結体に加えて、非酸化物系焼結体を含むことができる。これによると、よりＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数に近い平均線熱膨張係数の下地基板を得ることができる。具体的な非酸化物系焼結体としては、ＡｌＮ、ＳｉＣ、Ｓｉ３Ｎ４、ＧａＮ等を挙げることができる。なお、これらの非酸化物系焼結体も、酸化物系焼結体の場合と同様に、複数の非酸化物系焼結体を組み合わせて用いてもよい。 The base substrate 2 can include a non-oxide-based sintered body in addition to the oxide-based sintered body. According to this, a base substrate having an average linear thermal expansion coefficient closer to the average linear thermal expansion coefficient of the III-V group compound semiconductor layer can be obtained. Specific examples of the non-oxide-based sintered body include AlN, SiC, Si 3 N 4 , and GaN. Note that these non-oxide-based sintered bodies may be used in combination with a plurality of non-oxide-based sintered bodies as in the case of the oxide-based sintered body.
　下地基板２は、主表面の面粗さＲａが０．１ｎｍ～３．０ｎｍであることが好ましい。これにより、下地基板とＩＩＩ－Ｖ族化合物半導体層との接着性が向上する。接着性向上の観点から、下地基板の主表面は可能な限り平滑であることが好ましく、上記Ｒａは０．１ｎｍ～２．０ｎｍであることがより好ましく、０．１ｎｍ～１．０ｎｍであることが更に好ましい。なお、ここで主表面とは、表面のうち最も面積の大きい主要な面をいう。 The base substrate 2 preferably has a surface roughness Ra of the main surface of 0.1 nm to 3.0 nm. This improves the adhesion between the base substrate and the III-V compound semiconductor layer. From the viewpoint of improving adhesiveness, the main surface of the base substrate is preferably as smooth as possible, and Ra is more preferably 0.1 nm to 2.0 nm, and more preferably 0.1 nm to 1.0 nm. Is more preferable. Here, the main surface means a main surface having the largest area among the surfaces.
　下地基板２の厚さは特に限定されないが、ＩＩＩ－Ｖ族化合物半導体をエピタキシャル成長させる際において充分な強度を持っていることが望ましい。下地基板２の厚さは、化合物半導体層の厚さよりも大きいと、ＩＩＩ－Ｖ族化合物半導体エピタキシャル成長時の加熱に伴う反りの発生を効果的に抑制することができる。下地基板２の厚さは、厚い方が好ましいが、厚すぎると、ＩＩＩ－Ｖ族化合物半導体をエピタキシャル成長させる際において適用が困難になる可能性がある。上記の観点から下地基板の厚さは、４００μｍ～７００μｍであることが好ましい。 The thickness of the underlying substrate 2 is not particularly limited, but it is desirable that it has sufficient strength when epitaxially growing a III-V compound semiconductor. When the thickness of the base substrate 2 is larger than the thickness of the compound semiconductor layer, it is possible to effectively suppress the occurrence of warp accompanying heating during III-V compound semiconductor epitaxial growth. The base substrate 2 is preferably thick, but if it is too thick, it may be difficult to apply when epitaxially growing a group III-V compound semiconductor. From the above viewpoint, the thickness of the base substrate is preferably 400 μm to 700 μm.
　［下地基板の製造方法］
　下地基板２は、通常の焼結体の製造方法を用いて製造できる。したがって、製造に際して特別な設備などを設ける必要がなく、また、従来の製造方法の知識を活用して製造することができるため、コストの上昇を招くことなく、容易に、ＩＩＩ－Ｖ族化合物半導体層に近い平均線熱膨張係数を有する下地基板を製造することができる。下地基板２の製造方法の一例について、以下に説明する。 [Manufacturing method of base substrate]
The base substrate 2 can be manufactured using a normal method for manufacturing a sintered body. Therefore, it is not necessary to provide special equipment for manufacturing, and since it can be manufactured utilizing the knowledge of the conventional manufacturing method, the III-V compound semiconductor can be easily manufactured without increasing the cost. A base substrate having an average linear thermal expansion coefficient close to that of the layer can be produced. An example of the manufacturing method of the base substrate 2 will be described below.
　まず粉末準備工程を実施する。これは具体的には、上述した酸化物系焼結体を含む下地基板を形成する材料としての粉末を準備する工程である。該粉末準備工程では、ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数に近い平均線熱膨張係数を有する下地基板を得ることができるように、原料粉末の種類及び混合比率を適宜選択する。 First, the powder preparation process is performed. Specifically, this is a step of preparing a powder as a material for forming the base substrate including the oxide-based sintered body described above. In the powder preparation step, the type and mixing ratio of the raw material powder are appropriately selected so that a base substrate having an average linear thermal expansion coefficient close to the average linear thermal expansion coefficient of the III-V compound semiconductor layer can be obtained.
　次に成形工程を実施する。これは具体的には、プレス成形又はＣＩＰ（Ｃold　Ｉsostatic　Ｐressing；冷間等方圧加工法）により成形する。たとえば粉末準備工程で準備した混合粉末を、まずプレス成形により予備成形した後、ＣＩＰを行ない、成形体を得ることが好ましい。ただしここではプレス成形とＣＩＰとのいずれか一方のみを行なってもよいし、たとえばプレス成形を行なった後にＣＩＰを行なうなど、両方を行なってもよい。 Next, the molding process is performed. Specifically, this is formed by press molding or CIP (Cold Isostatic Pressing). For example, it is preferable that the mixed powder prepared in the powder preparation step is first preformed by press molding, and then CIP is performed to obtain a compact. However, only one of press molding and CIP may be performed here, or both CIP may be performed after press molding, for example.
　ここでプレス成形においてはたとえば１０ＭＰａ以上３００ＭＰａ以下、特に２０ＭＰａの圧力を用いることが好ましく、ＣＩＰにおいてはたとえば１６０ＭＰａ以上２５０ＭＰａ以下、特に１８０ＭＰａ以上２３０ＭＰａ以下の圧力を用いることが好ましい。 Here, in press molding, for example, a pressure of 10 MPa to 300 MPa, particularly 20 MPa is preferably used, and in CIP, for example, a pressure of 160 MPa to 250 MPa, particularly 180 MPa to 230 MPa is preferably used.
　次に焼結工程を実施する。焼結工程として具体的には、大気雰囲気下に成形体を載置して焼結する大気焼結法や、たとえばアルゴン雰囲気下に成形体を載置して加圧焼結するＨＩＰ（Ｈot　Ｉsostatic　Ｐressing；熱間等方加圧）を用いることが好ましい。あるいは上記方法の代わりにホットプレス法を用いてもよい。大気焼結法とＨＩＰなどとのいずれかのみを行なってもよいし、たとえば大気焼結法を行なった後にＨＩＰを行なうなど、複数を行なってもよい。さらにＨＩＰ後に再度熱処理を行なってもよい。 Next, the sintering process is performed. Specifically, the sintering process includes an atmospheric sintering method in which a molded body is placed and sintered in an air atmosphere, or a HIP (Hot Isostatic) in which a molded body is placed in an argon atmosphere and pressure-sintered. (Pressing; hot isostatic pressing) is preferably used. Alternatively, a hot press method may be used instead of the above method. Only one of the atmospheric sintering method and HIP may be performed, or a plurality of operations may be performed, for example, HIP is performed after the atmospheric sintering method is performed. Further, heat treatment may be performed again after HIP.
　大気焼結法においては具体的には、成形体を大気雰囲気中に載置し、１４００℃以上１７００℃以下に加熱し、１時間以上３時間以下保持することが好ましい。このようにすれば、密度が９５％以上の焼結体を形成することができる。またＨＩＰにおいては、上記焼結体を（あるいはホットプレスによる焼結を行なっていない成形体を）アルゴン雰囲気中に載置し、１５０ＭＰａ以上２５０ＭＰａ以下の圧力を加えながら１５００℃以上１８００℃以下に加熱し、１時間以上３時間以下保持することにより焼結する。上述した圧力及び温度により焼結を行なえば、形成される焼結体の密度を、最終的に形成される基板に要求される条件を満たすに足りる密度とすることができる。これは加圧により焼結体の組成変形が起こるとともに、拡散機構により当該焼結体内部の空孔が外部へ除去されるためである。 Specifically, in the air sintering method, it is preferable that the molded body is placed in an air atmosphere, heated to 1400 ° C. or higher and 1700 ° C. or lower and held for 1 hour or longer and 3 hours or shorter. In this way, a sintered body having a density of 95% or more can be formed. In HIP, the above sintered body (or a molded body that has not been sintered by hot pressing) is placed in an argon atmosphere and heated to 1500 ° C. or higher and 1800 ° C. or lower while applying a pressure of 150 MPa or higher and 250 MPa or lower. And sintering by holding for 1 hour or more and 3 hours or less. If the sintering is performed with the pressure and temperature described above, the density of the formed sintered body can be set to a density sufficient to satisfy the conditions required for the finally formed substrate. This is because compositional deformation of the sintered body occurs due to pressurization, and voids inside the sintered body are removed to the outside by the diffusion mechanism.
　以上により焼結がなされた焼結体に対して、加工工程を行う。これは具体的には、まず上記焼結体を所望の（下地基板２の）厚みとなるようにスライス加工により切断（切削加工）する。これにより、所望の厚みを有する下地基板２の下地が完成する。なおここで所望の厚みとは、最終的に形成したい下地基板２の厚みと、後工程における下地基板２の主表面の研磨しろ等を考慮した上で決定することが好ましい。 A processing step is performed on the sintered body sintered as described above. Specifically, first, the sintered body is cut (cut) by slicing so as to have a desired thickness (of the base substrate 2). Thereby, the foundation | substrate of the base substrate 2 which has desired thickness is completed. Here, the desired thickness is preferably determined in consideration of the thickness of the base substrate 2 to be finally formed, the allowance for polishing the main surface of the base substrate 2 in a later step, and the like.
　次に、上記下地基板２の下地の主表面を研磨する。具体的には、上述したように最終的に形成される下地基板２の主表面を、平均粗さＲａが所望の値となるように研磨する工程である。 Next, the base main surface of the base substrate 2 is polished. Specifically, this is a step of polishing the main surface of the base substrate 2 finally formed as described above so that the average roughness Ra becomes a desired value.
　下地基板２の主表面を、優れた平坦度を達成するために研磨する場合は、粗研磨と通常研磨と、ダイヤ砥粒を用いた研磨との３段階の研磨を順に行なうことが好ましい。具体的には、第１段階である粗研磨及び第２段階である通常研磨において、研磨機を用いて主表面を鏡面加工する。ここで粗研磨と通常研磨とでは、研磨に用いる砥粒の番手が異なる。具体的には、粗研磨においては砥粒の番手が＃８００～＃２０００であるＧＣ砥石を、通常研磨においては砥粒の粒径が３～５μｍであるダイヤモンド砥石を用いることが好ましい。 When the main surface of the base substrate 2 is polished in order to achieve excellent flatness, it is preferable to sequentially perform three-stage polishing including rough polishing, normal polishing, and polishing using diamond abrasive grains. Specifically, in the first stage of rough polishing and the second stage of normal polishing, the main surface is mirror-finished using a polishing machine. Here, the count of abrasive grains used for polishing differs between rough polishing and normal polishing. Specifically, it is preferable to use a GC grindstone with an abrasive grain number of # 800 to # 2000 for rough polishing, and a diamond grindstone with an abrasive grain diameter of 3 to 5 μm for normal polishing.
　次に第３段階である仕上げ加工としての研磨は、上述したようにダイヤ砥粒を用いて行うことが好ましい。ダイヤ砥粒は硬度が非常に高く、かつ砥粒の平均粒径が０．５μｍ～１．０μｍ程度と非常に小さいことから、高精度な鏡面加工用の砥粒として用いることに適している。当該砥粒を用いて例えば１０分間研磨加工を行なう。このようにすれば、上述した主表面の平均粗さＲａが０．１ｎｍ以上３．０ｎｍ以下である平坦性の高い主表面を実現することができる。 Next, the polishing as the finishing process, which is the third stage, is preferably performed using diamond abrasive grains as described above. Diamond abrasive grains are extremely high in hardness, and the average grain diameter of the abrasive grains is as small as about 0.5 μm to 1.0 μm, so that they are suitable for use as abrasive grains for high-precision mirror finishing. For example, polishing is performed for 10 minutes using the abrasive grains. By doing so, it is possible to realize a main surface with high flatness, in which the above-described average roughness Ra of the main surface is not less than 0.1 nm and not more than 3.0 nm.
　［ＩＩＩ－Ｖ族化合物半導体層］
　ＩＩＩ－Ｖ族化合物半導体層３は、ＩＩＩ－Ｖ族化合物半導体からなる層であり、この主面上にエピタキシャル成長層が形成される。 [III-V compound semiconductor layer]
The group III-V compound semiconductor layer 3 is a layer made of a group III-V compound semiconductor, and an epitaxial growth layer is formed on this main surface.
　ＩＩＩ－Ｖ族化合物半導体とは、周期律表の１３族元素と１５族元素とを用いた半導体である。１３元素としては、ホウ素（Ｂ）、アルミニウム(Ａｌ)、ガリウム(Ｇａ)、インジウム(Ｉｎ)、タリウム（Ｔｌ）が挙げられる。１５族元素としては、窒素(Ｎ)、リン(Ｐ)、ヒ素(Ａｓ)、アンチモン(Ｓｂ)、ビスマス（Ｂｉ）が挙げられる。ＩＩＩ－Ｖ族化合物半導体の具体例としては、ＧａＡｓ、ＩｎＰ、ＧａＮ等が挙げられる。 The III-V compound semiconductor is a semiconductor using a group 13 element and a group 15 element in the periodic table. Examples of the 13 elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). Examples of the group 15 element include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Specific examples of the III-V compound semiconductor include GaAs, InP, GaN, and the like.
　ＩＩＩ－Ｖ族化合物半導体層３は、ＧａＡｓ層又はＧａＮ層であることが好ましい。これらの化合物半導体は、ＩＩＩ－Ｖ族化合物半導体の内でも特性の優れた半導体であり、上記の下地基板を、ＧａＡｓ半導体層又はＧａＮ半導体層との貼り合わせ用下地基板として用いて貼り合せ基板を作製し、該貼り合せ基板上にエピタキシャル層を形成することにより、特性に優れた半導体デバイスを提供することができる。 The III-V compound semiconductor layer 3 is preferably a GaAs layer or a GaN layer. These compound semiconductors are semiconductors having excellent characteristics among group III-V compound semiconductors, and the above-described base substrate is used as a base substrate for bonding with a GaAs semiconductor layer or a GaN semiconductor layer. A semiconductor device having excellent characteristics can be provided by manufacturing and forming an epitaxial layer on the bonded substrate.
　［ＩＩＩ－Ｖ族化合物半導体貼り合せ基板の製造方法］
　ＩＩＩ－Ｖ族化合物半導体貼り合せ基板１は、例えば、ＩＩＩ－Ｖ族化合物半導体ウエハをドライエッチングにより清浄した後、ＩＩＩ－Ｖ族化合物半導体ウエハの主表面（Ｎ面）と下地基板の主表面とを、大気中で、貼り合わせることにより作製することができる。貼り合わせ時の圧力は、例えば、５ＭＰａ（１０００ｋｇｆ／２インチウエハ）～１０ＭＰａ（２０００ｋｇｆ／２インチウエハ）とすることができる。また、接着強度を増加させるためには、大気中で、室温（例えば２０℃～３０℃）から２００℃～３００℃までの温度に、数時間かけて加熱することが好ましい。 [Production Method of Group III-V Compound Semiconductor Bonded Substrate]
The III-V compound semiconductor bonded substrate 1 is obtained by, for example, cleaning a III-V compound semiconductor wafer by dry etching, and then, the main surface (N surface) of the III-V compound semiconductor wafer and the main surface of the base substrate. Can be produced by bonding them in the air. The pressure at the time of bonding can be, for example, 5 MPa (1000 kgf / 2 inch wafer) to 10 MPa (2000 kgf / 2 inch wafer). In order to increase the adhesive strength, it is preferable to heat in the air from room temperature (for example, 20 ° C. to 30 ° C.) to 200 ° C. to 300 ° C. over several hours.
　本発明を実施例によりさらに具体的に説明する。ただし、これらの実施例により本発明が限定されるものではない。 The present invention will be described more specifically with reference to examples. However, the present invention is not limited to these examples.
　［製造例１］
　（ＩＩＩ－Ｖ族化合物半導体層の準備）
　ＩＩＩ－Ｖ族化合物半導体層として、φ１００ｍｍ×厚さ２５０μｍのＧａＡｓウエハを準備した。 [Production Example 1]
(Preparation of III-V compound semiconductor layer)
A GaAs wafer having a diameter of 100 mm and a thickness of 250 μm was prepared as a III-V group compound semiconductor layer.
　（下地基板の作製）
　はじめに、酸化物系焼結体の粉末として、Ａｌ２Ｏ３（アルミナ）、及び、ＭｇＯ（マグネシア）を、モル比（Ａｌ２Ｏ３／ＭｇＯ）が３．６０となるように準備した。これらの粉末を、エタノール中で、ボールミルを用いて、１２時間混合した後、乾燥した。 (Preparation of base substrate)
First, Al 2 O 3 (alumina) and MgO (magnesia) were prepared as an oxide-based sintered powder so that the molar ratio (Al 2 O 3 / MgO) was 3.60. These powders were mixed in ethanol using a ball mill for 12 hours and then dried.
　乾燥粉末をプレス成形により予備成形し、続いてＣＩＰを行なって成形体を得た。プレス成形においては１０ＭＰａの圧力をかけ、ＣＩＰにおいては２００ＭＰａの圧力をかけた。 The dry powder was preformed by press molding, followed by CIP to obtain a molded body. In press molding, a pressure of 10 MPa was applied, and in CIP, a pressure of 200 MPa was applied.
　続いて、上記成形体を大気雰囲気下に載置し、１５００℃で、９時間、保持することにより焼結を行った。更に、得られた焼結体をアルゴン雰囲気中に載置し、２００ＭＰａの圧力を加えながら１６００℃に加熱し、２時間、保持することによりＨＩＰを行った。 Subsequently, the molded body was placed in an air atmosphere and sintered at 1500 ° C. for 9 hours. Further, the obtained sintered body was placed in an argon atmosphere, heated to 1600 ° C. while applying a pressure of 200 MPa, and held for 2 hours to perform HIP.
　上記ＨＩＰ後の焼結体を、７００μｍの厚みとなるようにダイシング加工をして下地基板を得た。続いて該下地基板の主表面の研磨を行った。研磨は、粗研磨、通常研磨、仕上げ加工の研磨の順で行った。粗研磨では♯８００のＧＣ砥石を、通常研磨では粒径が３μｍのダイヤモンド砥粒を、仕上げ加工の研磨では粒径が１μｍのダイヤモンド砥粒を用いて研磨を行った。 The above sintered body after HIP was diced to a thickness of 700 μm to obtain a base substrate. Subsequently, the main surface of the base substrate was polished. Polishing was performed in the order of rough polishing, normal polishing, and finishing polishing. Polishing was performed using a # 800 GC grindstone for rough polishing, diamond abrasive grains having a particle diameter of 3 μm for normal polishing, and diamond abrasive grains having a particle diameter of 1 μm for final polishing.
　（平均線熱膨張係数の測定）
　作製されたＨＩＰ後の下地基板用焼結体からφ２０ｍｍ×厚さ２．５ｍｍのサンプルを切り出し、線膨張係数測定装置（理学電機製の商品名「ＴＭＡ８１４０」）を用いて窒素中で、３０～３００℃までの平均線熱膨張係数（ＣＴＥ：coefficient　of　linear　thermal　expansion）α１を測定した。ＧａＡｓウエハについても、同様の方法で、平均線熱膨張係数α２を測定した。結果を表１に示す。 (Measurement of average linear thermal expansion coefficient)
A sample having a diameter of 20 mm and a thickness of 2.5 mm was cut out from the manufactured sintered body for the base substrate after HIP, and a sample of 30 to 30 mm in nitrogen was measured using a linear expansion coefficient measuring apparatus (trade name “TMA8140” manufactured by Rigaku Corporation). The average coefficient of linear thermal expansion (CTE) α1 up to 300 ° C. was measured. For the GaAs wafer, the average linear thermal expansion coefficient α2 was measured by the same method. The results are shown in Table 1.
　（ヤング率の測定）
　ＧａＡｇウエハ、及び、作製されたＨＩＰ後の下地基板用焼結体について、ＪＩＳ　Ｒ　１６０２に準拠して、ヤング率測定装置（ミネベア（株）社製の商品名「万能材料試験機」）を用いてヤング率Ｅ１，Ｅ２を測定した。結果を表１に示す。 (Measurement of Young's modulus)
Using the Young's modulus measuring device (trade name “Universal Material Testing Machine” manufactured by Minebea Co., Ltd.) for the GaAg wafer and the manufactured sintered body for the base substrate after HIP according to JIS R 1602. Young's modulus E1 and E2 were measured. The results are shown in Table 1.
　（ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板の作製）
　ＧａＡｓウエハをドライエッチングにより清浄した後、ＧａＡｓウエハ（サイズφ１００ｍｍ×厚み２５０μｍ）の主表面と下地基板（サイズφ１００ｍｍ×厚み５００μｍ）の主表面とを、大気中で、貼り合わせ、ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板を作製した（サイズφ１００ｍｍ×厚み７５０μｍ）。貼り合わせ時の圧力は、７ＭＰａ（１４００ｋｇｆ／２インチウエハ）とした。また、接着強度を増加させるために、室温から２００℃までの温度に、３時間かけて加熱した。 (Production of III-V compound semiconductor bonded substrate)
After the GaAs wafer is cleaned by dry etching, the main surface of the GaAs wafer (size φ100 mm × thickness 250 μm) and the main surface of the base substrate (size φ100 mm × thickness 500 μm) are bonded together in the atmosphere to form a III-V group compound A semiconductor bonded substrate was produced (size φ100 mm × thickness 750 μm). The pressure at the time of bonding was 7 MPa (1400 kgf / 2 inch wafer). Moreover, in order to increase adhesive strength, it heated over 3 hours to the temperature from room temperature to 200 degreeC.
　（ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板の評価）
　上記で得られたＩＩＩ－Ｖ族化合物半導体貼り合わせ基板を、３００℃の雰囲気下に６０分間静置した。３００℃は、貼り合せ基板上にＧａＡｓをエピタキシャル成長させる工程で用いる最高温度である。その後、該貼り合せ基板の反りの量を測定した。なお、反りの量は、非接触式反り測定機で測定された値である。反りの量が０．２０ｍｍ未満である場合を良好と判断する。結果を表１に示す。 (Evaluation of III-V compound semiconductor bonded substrate)
The III-V compound semiconductor bonded substrate obtained above was allowed to stand in an atmosphere of 300 ° C. for 60 minutes. 300 ° C. is the maximum temperature used in the step of epitaxially growing GaAs on the bonded substrate. Thereafter, the amount of warpage of the bonded substrate was measured. The amount of warpage is a value measured with a non-contact warpage measuring machine. A case where the amount of warpage is less than 0.20 mm is judged as good. The results are shown in Table 1.
　［製造例２～９］
　（ＩＩＩ－Ｖ族化合物半導体層の準備）
　ＩＩＩ－Ｖ族化合物半導体層として、表１に示される種類の化合物半導体ウエハを準備した。 [Production Examples 2 to 9]
(Preparation of III-V compound semiconductor layer)
A compound semiconductor wafer of the type shown in Table 1 was prepared as a III-V group compound semiconductor layer.
　（下地基板の作製）
　表１に示される酸化物系焼結体粉末の種類及び配合割合を用いて、製造例１と同様の方法で、下地基板を作製した。 (Preparation of base substrate)
A base substrate was produced in the same manner as in Production Example 1 using the type and blending ratio of the oxide-based sintered powder shown in Table 1.
　（平均線熱膨張係数、及び、ヤング率の測定）
　化合物半導体ウエハ、及び、作製されたＨＩＰ後の焼結体について、製造例１と同様の方法で、平均線熱膨張係数、及び、ヤング率を測定した。なお、製造例６では、３０～１０００℃までの平均線熱膨張係数を測定した。結果を表１に示す。 (Measurement of average linear thermal expansion coefficient and Young's modulus)
About the compound semiconductor wafer and the produced sintered body after HIP, the average linear thermal expansion coefficient and Young's modulus were measured by the same method as in Production Example 1. In Production Example 6, the average linear thermal expansion coefficient from 30 to 1000 ° C. was measured. The results are shown in Table 1.
　（ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板の作製）
　上記の化合物半導体ウエハ、及び、下地基板を用いて、製造例１と同様の方法で、ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板を作製した。 (Production of III-V compound semiconductor bonded substrate)
A III-V compound semiconductor bonded substrate was fabricated using the compound semiconductor wafer and the base substrate in the same manner as in Production Example 1.
　（ＩＩＩ－Ｖ族化合物半導体貼り合わせ基板の評価）
　上記で得られたＩＩＩ－Ｖ族化合物半導体貼り合わせ基板について、製造例１と同様の方法で反りの量を測定した。なお、製造例６では、１０００℃の雰囲気下に６０分間静置した。１０００℃は、貼り合せ基板上にＧａＮをエピタキシャル成長させる工程で用いる最高温度である。反りの量が０．２０ｍｍ未満である場合を良好と判断する。結果を表１に示す。 (Evaluation of III-V compound semiconductor bonded substrate)
The amount of warpage of the III-V compound semiconductor bonded substrate obtained above was measured in the same manner as in Production Example 1. In Production Example 6, the sample was allowed to stand in an atmosphere of 1000 ° C. for 60 minutes. 1000 ° C. is the highest temperature used in the step of epitaxially growing GaN on the bonded substrate. A case where the amount of warpage is less than 0.20 mm is judged as good. The results are shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　今回開示された実施の形態及び実施例はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した実施の形態ではなく請求の範囲によって示され、請求の範囲と均等の意味、及び範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiments and examples disclosed this time are examples in all respects and are not restrictive. The scope of the present invention is shown not by the embodiments described above but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.
１　ＩＩＩ－Ｖ族化合物半導貼り合わせ基板、２　下地基板、３　ＩＩＩ－Ｖ族化合物半導体層。 1 III-V compound semiconductor bonded substrate, 2 base substrate, III-V compound semiconductor layer.

Claims (5)

  1. 　ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板用の下地基板であって、
    　前記下地基板は、酸化物系焼結体を含み、
    　前記下地基板の平均線熱膨張係数と、前記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、前記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、前記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
    ０．９５≦α１／α２≦１．０５　　（１）
    の関係を示す、又は、前記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、前記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：
    ０．９５≦α３／α４≦１．０５　　（２）
    の関係を示し、
    　前記下地基板のヤング率Ｅ１と、前記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
    Ｅ１／Ｅ２≧１．００　　（３）
    の関係を示す、
    　下地基板。     A base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
    The base substrate includes an oxide-based sintered body,
    The average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C., and the III- The average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1):
    0.95 ≦ α1 / α2 ≦ 1.05 (1)
    Or an average linear thermal expansion coefficient α3 from 30 ° C. to 1000 ° C. of the base substrate and an average linear thermal expansion coefficient α4 from 30 ° C. to 1000 ° C. of the III-V compound semiconductor layer. The following formula (2):
    0.95 ≦ α3 / α4 ≦ 1.05 (2)
    Shows the relationship
    The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
    E1 / E2 ≧ 1.00 (3)
    Showing the relationship
    Ground substrate.
  2. 　前記酸化物系焼結体は、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２、希土類酸化物、ＺｒＯ２及びＭｇ２ＡｌＯ４からなる群より選択される少なくとも１種類を含む、
    　請求項１に記載の下地基板。     The oxide-based sintered body includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 .
    The base substrate according to claim 1.
  3. 　前記ＩＩＩ－Ｖ族化合物半導体層は、ＧａＡｓ層又はＧａＮ層である、
    　請求項１又は請求項２に記載の下地基板。     The III-V compound semiconductor layer is a GaAs layer or a GaN layer.
    The base substrate according to claim 1 or 2.
  4. 　ＩＩＩ－Ｖ族化合物半導体層と下地基板とを貼り合せたＩＩＩ－Ｖ族化合物半導体貼り合せ基板用の下地基板であって、
    　前記下地基板は、酸化物系焼結体を含み、
    　前記下地基板の平均線熱膨張係数と、前記ＩＩＩ－Ｖ族化合物半導体層の平均線熱膨張係数とは、前記下地基板の３０℃から３００℃までの平均線熱膨張係数α１と、前記ＩＩＩ－Ｖ族化合物半導体層の３０℃から３００℃までの平均線熱膨張係数α２とが、下記式（１）：
    ０．９５≦α１／α２≦１．０５　　（１）
    の関係を示す、又は、前記下地基板の３０℃から１０００℃までの平均線熱膨張係数α３と、前記ＩＩＩ－Ｖ族化合物半導体層の３０℃から１０００℃までの平均線熱膨張係数α４とが、下記式（２）：
    ０．９５≦α３／α４≦１．０５　　（２）
    の関係を示し、
    　前記下地基板のヤング率Ｅ１と、前記ＩＩＩ－Ｖ族化合物半導体層のヤング率Ｅ２とは、下記式（３）：
    Ｅ１／Ｅ２≧１．００　　（３）
    の関係を示し、
    　前記酸化物系焼結体は、Ａｌ２Ｏ３、ＭｇＯ、ＳｉＯ２、希土類酸化物、ＺｒＯ２及びＭｇ２ＡｌＯ４からなる群より選択される少なくとも１種類を含み、
    　前記ＩＩＩ－Ｖ族化合物半導体層は、ＧａＡｓ層又はＧａＮ層である、
    　下地基板。     A base substrate for a group III-V compound semiconductor bonded substrate obtained by bonding a group III-V compound semiconductor layer and a base substrate,
    The base substrate includes an oxide-based sintered body,
    The average linear thermal expansion coefficient of the base substrate and the average linear thermal expansion coefficient of the group III-V compound semiconductor layer are the average linear thermal expansion coefficient α1 of the base substrate from 30 ° C. to 300 ° C., and the III- The average linear thermal expansion coefficient α2 from 30 ° C. to 300 ° C. of the group V compound semiconductor layer is expressed by the following formula (1):
    0.95 ≦ α1 / α2 ≦ 1.05 (1)
    Or an average linear thermal expansion coefficient α3 from 30 ° C. to 1000 ° C. of the base substrate and an average linear thermal expansion coefficient α4 from 30 ° C. to 1000 ° C. of the III-V compound semiconductor layer. The following formula (2):
    0.95 ≦ α3 / α4 ≦ 1.05 (2)
    Shows the relationship
    The Young's modulus E1 of the base substrate and the Young's modulus E2 of the III-V compound semiconductor layer are expressed by the following formula (3):
    E1 / E2 ≧ 1.00 (3)
    Shows the relationship
    The oxide-based sintered body includes at least one selected from the group consisting of Al 2 O 3 , MgO, SiO 2 , rare earth oxide, ZrO 2 and Mg 2 AlO 4 ,
    The III-V compound semiconductor layer is a GaAs layer or a GaN layer.
    Ground substrate.
  5. 　請求項１～請求項４のいずれか１項に記載の下地基板と、ＩＩＩ－Ｖ族化合物半導体層とが貼り合わされた、
    　ＩＩＩ－Ｖ族化合物半導体貼り合せ基板。     The base substrate according to any one of claims 1 to 4 and the III-V group compound semiconductor layer are bonded together.
    III-V compound semiconductor bonded substrate.
PCT/JP2016/082942 2015-11-09 2016-11-07 Base substrate and substrate to which group iii-v compound semiconductor is bonded WO2017082197A1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005060195A (en) * 2003-08-19 2005-03-10 Toyohashi University Of Technology Nitride semiconductor substrate and its manufacturing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005060195A (en) * 2003-08-19 2005-03-10 Toyohashi University Of Technology Nitride semiconductor substrate and its manufacturing method

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