WO2017076419A1

WO2017076419A1 - Active balun

Info

Publication number: WO2017076419A1
Application number: PCT/EP2015/075371
Authority: WO
Inventors: Dror Regev; Shimi Shilo; Doron Ezri
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2015-11-02
Filing date: 2015-11-02
Publication date: 2017-05-11
Also published as: CN108141200A

Abstract

The disclosure relates to an active balun (300), including: a first terminal (303); a second terminal (305, 306); a first transistor (M1) comprising a first current path (D1-S1, l_DS) and a control path (G1-S1, V_GS) for controlling the first current path (D1-S1, l_DS), wherein the first current path (D1-S1, l_DS) is coupled between the first terminal (303) and the second terminal (305, 306) and the control path (G1-S1, V_GS) is coupled between a reference potential (304b, G1) and the first terminal (303, S1); and an inverter (301) comprising a second current path (S2-D2-D3-S3), wherein the second current path (S2-D2-D3-S3) is coupled in parallel to the first current path (D1-S1) of the first transistor (M1).

Description

Active balun

TECHNICAL FIELD The present disclosure relates to an active balun, in particular to an active balun with reduced power consumption and enhanced linearity.

BACKGROUND Baluns may serve in communication, e.g. in radio frequency transceivers 200 as depicted in Figure 2, for converting an antenna RF signal that is single ended 223, 224 into a differential signal 221 , 222 at the integrated circuit (RFIC) 201 of the RF transceiver 200 or vice versa. Baluns 205, 207 are applied in both transmit and receive channels. Off chip, magnetic coupling transformer based Baluns were popular in the past. Such Baluns (not depicted in Fig. 2) were placed on a board between the antenna 215 and the low-noise amplifier (LNA) 21 1 in the receive path and/or between the power amplifier (PA) 209 and the antenna 215 in the transmit path.

The MIMO (multiple input multiple output) communication trend as well as needs for form factor reduction have changed the situation and today most implementations include on- chip Baluns 205, 207 and only single ended RFIC input/outputs 223, 224. Power efficiency, dynamic range and superior RF performance of GaAs, GaN or other non- CMOS technology advantages justified the employment of discrete RF front end modules (RFFE) 203 between antennas 215 and RFIC 201 . Such RF front end modules may include a power amplifier (PA) 209, a low-noise amplifier (LNA) 21 1 and a

Transmit/Receive (T/R) switch 213.

In receive mode the external LNA 21 1 may relax the noise figure (NF) requirements from the on chip Balun 207. On the other hand, the Balun linearity requirements are of higher importance.

A balun 207 in receive mode can be implemented in a passive or active form. In the passive form, baluns are mostly transformer based with no linearity concerns, however some signal loss occurs and a relatively high chip area is required for implementation. In the active form, linearity and power consumption are major concerns. Advantages of passive baluns are that the balun linearity is not a critical issue, the receive linearity is determined after the balun and balun DC consumption is about zero.

Disadvantages of passive baluns are their size, for example at 5.5 GHz a size of

250χ300μηι² was demonstrated; and the area will increase for lower frequency baluns; their narrow band performance, their passive losses for example the insertion loss at 5.5 GHz may be about 2.4 dB; their lack of reverse isolation that may enable high LO (local oscillator) leakage; and may enable an antenna match will depend on the baseband (IQ) loading.

Advantages of active baluns are their wide band performance, e.g. between 0.2 and 5.2 GHz, with gain, the voltage gain depends on its output load and a theoretical current gain of 2:1 may be realized when the output load is symmetrical; the size of the active balun is quite small, e.g. about 80x1 10 μηι² was demonstrated; and the active balun shows a reverse isolation, and hence reduced LO leakage. Disadvantages of active baluns are their non-linearity, for example an IIP3 greater than 0 dBm may not be sufficient for high dynamic range solutions; and the power consumption of active baluns is high, for example about 21 mW. Next-generation wireless technologies (such as LTE-A, 1 1 ax, etc.) and the use of multiple RF chains (MIMO) drive the requirements for on-chip small size, wide band, high linearity and lower power consumption baluns. Advantages of the on-chip active balun such as wide bandwidth, small size, reverse isolation and power gain provide motivation to investigate topologies with similar advantages but with improved linearity and reduced power consumption.

SUMMARY

It is the objective of the invention to provide an improved balun, in particular with low current consumption and a small size.

This object is achieved by the features of the independent claim. Further implementation forms are apparent from the dependent claims, the description and the figures. A basic idea of the invention is to apply a transistor which control terminal is connected to a reference potential such as ground in parallel to an inverter such that the inverter inverts the input signal while the transistor amplifies or transfers the input signal "in-phase". The linearity of this circuit depends mostly on the linearity of the inverter branch as the transistor nonlinearity cancels out at the differential output.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

RF: Radio Frequency

LNA: Low Noise Amplifier

PA: Power Amplifier

T/R: Transmit/Receive

RFIC: Radio Frequency Integrated Circuit

RFFE: Radio Frequency Front End

CMOS: Complementary Metal Oxide Semiconductor

BAL: Balun

ANT: Antenna

MIMO: multi-input multi-output

NMOS: n-type Metal Oxide Semiconductor

PMOS p-type Metal Oxide Semiconductor

In the following, baluns and active baluns are described. A balun 100 as exemplary depicted in Figure 1 is an electrical device that converts between a balanced signal 104 (differential) and an unbalanced signal 102 (single ended signal working against ground). The balanced signal 104 may be a differential signal, for example having a non-inverting potential 105 at a first terminal 105 and an inverting potential 107 at a second terminal 107. The unbalanced signal 102 may be a single ended signal, e.g. having a single-ended potential 101 working against a reference potential 103 such as ground.

In the following, current paths of transistors and inverters are described. A current path of a transistor is, in contrast to a control path, the path in which a controlled current flows, e.g. a switching current or an amplified current. In an inverter, the current path is the path in which, when applying an input current, the inverted input current flows. In a MOS transistor, the current path is the path between drain and source electrode; in a bipolar transistor, the current path is the path between emitter and collector electrode.

In the following, differential signals and differential signaling are described. Differential signaling is a method for electrically transmitting information using two complementary signals. The same electrical signal is sent as a differential pair of signals, each in its own conductor. A differential signal may include a first signal at a first potential, for example a plus potential and a complementary second signal at a second potential, for example a minus potential or vice versa. The opposite technique is called single-ended signaling. In single-ended signaling, one wire carries a varying voltage that represents the signal, while the other wire is connected to a reference voltage, usually ground.

In the following, transconductance and transconductance gain are described.

Transconductance or also called transconductance gain is a property of certain electronic components, e.g. transistors or amplifiers. While conductance is defined as the reciprocal of resistance, transconductance is defined as the ratio of the current variation at the output to the voltage variation at the input. It is written as g_m. For small signal alternating current, the definition is

In the following sections, transconductance gain is simply denoted as gain.

According to a first aspect, the invention relates to an active balun, comprising: a first terminal; a second terminal; a first transistor comprising a first current path and a control path for controlling the first current path, wherein the first current path is coupled between the first terminal and the second terminal and the control path is coupled between a reference potential and the first terminal; and an inverter comprising a second current path, wherein the second current path is coupled in parallel to the first current path of the first transistor.

Such an active balun provides a high linear behaviour that is mainly determined by the linearity of the inverter which may be produced as a high linear component when implemented as active electrical component. The first transistor together with the inverter may be manufactured in a space saving and thus current saving manner, thereby providing a highly linear active balun with low current consumption at a small size. In a first possible implementation form of the active balun according to the first aspect, a current source, configured to bias the first transistor.

This provides the advantage that the current source may be used for biasing the first transistor, thereby activating a basic operation mode of the balun.

In a second possible implementation form of the active balun according to the first aspect as such or according to the first implementation form of the first aspect, the second terminal is a differential terminal having a non-inverting terminal for providing a first potential of a differential signal and an inverting terminal for providing a second potential of the differential signal.

This provides the advantage that the active balun can transform a single-ended signal, e.g., a voltage or current against a ground potential into a differential signal, e.g. a voltage or current having both + and - potential. Please note that the active balun is only useful in transforming Single Ended signals to differential signals.

In a third possible implementation form of the active balun according to the second implementation form of the first aspect, the inverter is configured to inhibit a reverse transfer of the first terminal to the differential signal at the second terminal.

This provides the advantage that the active balun is useful for single-ended to differential transformation but not vice versa. Transformation in the reverse direction will be inhibited. In a fourth possible implementation form of the active balun according to any of the second and third implementation forms of the first aspect, the active balun comprises a differential load coupled between the non-inverting terminal and the inverting terminal.

This provides the advantage that the differential load can be used for biasing the first transistor.

In a fifth possible implementation form of the active balun according to any of the second to the fourth implementation forms of the first aspect, the first transistor is configured to in- phase transfer an input signal at the first terminal to a first output current or potential of a differential output signal at the non-inverting terminal. This provides the advantage that a first polarity of the input signal is transferred into the same first polarity of the first potential of the differential output signal. Hence phase variations are suppressed.

In a sixth possible implementation form of the active balun according to the fifth implementation form of the first aspect, the inverter is configured to transfer the input signal to a second output current or potential of the differential output signal at the inverting terminal.

This provides the advantage that a second polarity of the input signal is transferred into the opposite second polarity of the second potential of the differential output signal. Hence phase variations from the opposite second polarity are suppressed. In a seventh possible implementation form of the active balun according to any of the second to the sixth implementation forms of the first aspect, the inverter comprises a second transistor and a third transistor, wherein a current path of the second transistor is arranged in series with a current path of the third transistor. This provides the advantage of an easy implementation of the inverter. These two transistors can be implemented on a chip in a space-saving manner. Furthermore, the two transistors implementing the inverter can be driven by a low current, thereby achieving low total current consumption of the active balun. In an eighth possible implementation form of the active balun according to the seventh implementation form of the first aspect, the second transistor is configured to bias the third transistor and the third transistor is configured to bias the second transistor.

This provides the advantage that mutual biasing can be applied in order to avoid use of any dedicated bias device or circuit for biasing the second and third amplifying transistors. Therefore, the current source is only required to bias the first transistor but the second and third transistor of the inverter are self-biased. In a ninth possible implementation form of the active balun according to any of the seventh to the eighth implementation forms of the first aspect, the second transistor is a PMOS transistor and the third transistor is an NMOS transistor. This provides the advantage, that the electrical properties of both transistors are inverse with respect to each other. Thus, a respective connection of both PMOS and NMOS transistors may be formed such that nonlinear properties of the applied signals can be cancelled out. Hence, an inverter comprising these two PMOS and NMOS transistors has a high linear electrical characteristic.

In a tenth possible implementation form of the active balun according to any of the seventh to the ninth implementation forms of the first aspect, an absolute value of a first gain of the second transistor driven by a gate-source voltage is designed to equal an absolute value of a second gain of the third transistor driven by the inverse gate-source voltage.

This provides the advantage, that both transistors implement an optimal active inverter. Therefore a series connection of both PMOS and NMOS transistors has a high linear electrical characteristic.

In an eleventh possible implementation form of the active balun according to any of the seventh to the tenth implementation forms of the first aspect, the second transistor and the third transistor are configured to reuse a same bias current contributing to the total gain of the inverter.

This provides the advantage that only one bias current is required to bias both transistors, thereby saving current.

In a twelfth possible implementation form of the active balun according to the eleventh implementation form of the first aspect, the total gain of the inverter is essentially equal to a sum of a first gain of the second transistor and a second gain of the third transistor.

This provides the advantage that both gains can be added to obtain the total gain of the inverter. In a thirteenth possible implementation form of the active balun according to the twelfth implementation form of the first aspect, the second transistor and the third transistor are configured such that variations of the respective first and second gains with an input signal at the first terminal over the bias current have inverted slopes.

This provides the advantage that these variations of the respective first and second gains with the input signal cancel out each other, thereby providing an active balun with increased linearity. In a fourteenth possible implementation form of the active balun according to the thirteenth implementation form of the first aspect, the slopes of the first and second gains with the input signal cancel out each other.

This provides the advantage that variations of slopes of the respective first and second gains with the input signal cancel out each other, thereby providing an active balun with yet increased linearity.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a block diagram illustrating a balun 100;

Fig. 2 shows a block diagram illustrating a radio frequency transceiver 200;

Fig. 3 shows a circuit diagram illustrating an active balun 300 according to an

implementation form;

Fig. 4 shows a circuit diagram illustrating an inverter 400 for an active balun 300 which includes two transistors according to an implementation form; Fig. 5a shows a performance diagram illustrating an exemplary drain source current l_ds over a gate source voltage V_Gs of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor; Fig. 5b shows a performance diagram illustrating an exemplary gain g_m over a gate source voltage V_Gs of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor; and

Fig. 6 shows a performance diagram illustrating the characteristic performance of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor.

DETAILED DESCRIPTION OF EMBODIMENTS In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise. Fig. 3 shows a circuit diagram illustrating an active balun 300 according to an

implementation form.

The active balun 300 includes a first terminal 303; a second terminal 305, 306; a first transistor M1 and an inverter 301 . The first transistor (M1 ) comprises a first current path (D1 -S1 , l_Ds) and a control path (G 1 - S1 , VQS) for controlling the first current path (D1 -S1 , l_Ds), wherein the first current path (D1 -S1 , IDS) is coupled between the first terminal (303) and the second terminal (305, 306) and the control path (G1 -S1 , V_Gs) is coupled between a reference potential (304b, G 1 ) and the first terminal (303, S1 );

The first transistor M1 has a first current path D1 -S1 from drain electrode D1 to source electrode S1 . The first current path D1 -S1 , l_DS is coupled between the first terminal 303 and the second terminal 305, 306. The first transistor M1 has a control path G1 -S1 , V_GS that is used to control the first current path D1 -S1 , l_DS. The control terminal G 1 is coupled between a reference potential 304b, G 1 , e.g. a ground potential, and the first terminal 303, S1 . The inverter 301 has a second current path S2-D2-D3-S3 between a first inverter terminal T1 and a second inverter terminal T2. The second current path S2-D2-D3-S3 is coupled in parallel to the first current path D1 -S1 of the first transistor M1 .

When using CMOS technology the first current path may be formed between drain and source terminals and the control path may be formed between gate and source terminals, i.e. VQS (voltage between gate and source terminals) controls \_DS (current between drain and source terminals). Hence, the control function is delivered to the source terminal S1 and the gate terminal G1 is connected to a reference potential such as ground, i.e., it forms a so-called "common-gate" amplifier.

In Fig. 3, the inverter 301 exemplary includes two CMOS transistors M2, M3 forming the inverter 301 . However, any other structure for forming the inverter 301 may be used as well. In one embodiment the inverter 301 may be formed by bipolar transistors. In a further embodiment the inverter 301 may be formed by operational amplifiers. In a further embodiment the inverter 301 may be formed by comparator elements. The inverter 301 may be produced in CMOS or in bipolar technology. When using bipolar technology, the first transistor M1 may be replaced by a transistor in bipolar technology which base terminal is connected to a reference potential such a ground. In bipolar technology the first current path may be formed between collector and emitter terminals and the control path may be formed between base and emitter terminals, i.e. V_BE controls ICE- In the active balun 300 depicted in Fig. 3, a current source 314 may be connected to the source terminal S1 of the first transistor M1 . The current source 314 biases the first transistor M1 . A differential load 313 may be coupled between terminals 305 and 306.

The second terminal 305, 306 may be a differential terminal having a non-inverting terminal 305 for providing a first output current lout+ or potential Vout+ of a differential signal and an inverting terminal 306 for providing a second output current lout- or potential Vout- of the differential signal. The load 313 is only the biasing load for the branch of the first transistor M1 , it is not the load of the balun. The inverter eliminates the need for a "biasing load" since the second transistor M2 (e.g. PMOS) serves as a "biasing load" for the third transisitor M3 (e.g. NMOS) whereas the third transistor M3 (e.g. NMOS) serves as a "biasing load" for the second transistor M2 (e.g. PMOS).

The first transistor M1 may in-phase transfer an input signal Vin at the first terminal 303 to a first output current lout+ or potential Vout+ of a differential output signal at the non- inverting terminal 305. That means, the first output current lout+ or potential Vout+ of the differential output signal may have the same phase or nearly the same phase as the input signal Vin. The first output current lout+ or potential Vout+ of the differential output signal may be an amplified version of the input signal Vin.

The inverter 301 inhibits a reverse transfer of the differential signal from the second terminal 305, 306 to the first terminal 303. Hence, the active balun is not reciprocal like the passive balun and that is why it has "reverse isolation" as a positive attribute. This balun is useful for single ended to differential transformation but not vice versa.

The inverter 301 may transfer the input signal Vin to a second output current lout- or potential Vout- of the differential output signal at the inverting terminal 306. The phase of the second output current lout- or potential Vout- may be opposite to the phase of the first output current lout+ or potential Vout+. The second output current lout- or potential Vout- of the differential output signal may have the opposite phase or nearly the opposite phase as the input signal Vin. The second output current lout- or potential Vout- of the differential output signal may be an inverted version of the input signal Vin. As mentioned above, the active balun is not reciprocal and provides an advantageous "reverse isolation" for inhibiting the reverse direction. That means, the active balun is useful for single ended to differential transformation but not vice versa.

The inverter 301 may include a second transistor M2, e.g. a CMOS transistor with source S2, drain D2 and gate G2, and a third transistor M3, e.g. a CMOS transistor with source S3, drain D3 and gate G3. A current path S2-D2 of the second transistor M2 may be arranged in series with a current path D3-S3 of the third transistor M3.

The second transistor M2 may have a gate terminal G2 that is connected to a gate terminal G3 of the third transistor M3. Both gate terminals G2, G3 may be coupled to the first terminal 303.

The second transistor M2 may have a drain terminal D2 that is connected to a drain terminal D3 of the third transistor M3. Both drain terminals D2, D3 may be coupled to the inverting terminal 306 of the active balun 300.

The second transistor M2 may be a PMOS transistor and the third transistor M3 may be an NMOS transistor, e.g. as depicted in Figures 5 and 6. An absolute value of a first gain g_{m p} of the second transistor M2 when driven by a gate- source voltage V_Gs may be designed to equal an absolute value of a second gain g_m__n of the third transistor M3 when driven by the inverse gate-source voltage -V_Gs, as described below with reference to Figures 5 and 6. The second transistor M2 and the third transistor M3 may be configured to reuse a same bias current I0 contributing to a total gain g_m of the inverter 301 , e.g. as described below with respect to Figure 4.

The gain g_m of the inverter 301 may be essentially equal to a sum of a first gain g_{m p} of the second transistor M2 and a second gain g_m__n of the third transistor M3, as described below with reference to Figures 5 and 6.

The second transistor M2 and the third transistor M3 may be chosen and configured such that variations of the respective first and second gains g_{m p}, g_m__n with an input signal Vin at the first terminal 303 over the bias current 10 have inverted slopes 601 , 602, as described below with reference to Figures 5 and 6.

The slopes 601 , 602 of the first and second gains g_{m p}, g_m__n with the input signal Vin may cancel out each other, as described below with reference to Figure 6.

The active balun may be manufactured as an on-chip circuit. The on-chip active balun may have no magnetic transformer spirals. The on-chip active balun may be produced without significant inductive elements.

The active balun 300 may be integrated on a radio frequency integrated circuit, e.g. an RFIC 201 as depicted in Fig. 2. The receive balun 207 depicted in Fig. 2 may be implemented as active balun 300 according to Figure 3. Fig. 4 shows a circuit diagram illustrating an inverter 400 for an active balun 300 which includes two transistors according to an implementation form. The inverter 400 is a possible implementation form of the inverter 301 described above with respect to Fig. 3.

The inverter 400 may include a second transistor M2 and a third transistor M3 coupled in series, i.e. a current path S2-D2 of the second transistor M2 may be arranged in series with a current path D3-S3 of the third transistor M3. The inverter may have a first inverter terminal T1 , a second inverter terminal T2, an input terminal 303 and an output terminal 306. The second transistor M2 may have a gate terminal G2 connected to a gate terminal G3 of the third transistor M3. Both gate terminals G2, G3 may be coupled to the first terminal 303. The first inverter terminal T1 may be a supply terminal for supplying the inverter with a supply voltage. The second inverter terminal T2 may be a common terminal, e.g. a ground terminal. When an input voltage Vin is applied between the input terminal 303 and the second inverter terminal T2 an output current i_0Lrt may flow at the output terminal 306.

The second transistor M2 may have a drain terminal D2 connected to a drain terminal D3 of the third transistor M3. Both drain terminals D2, D3 may be coupled to the output terminal 306. The second transistor M2 may be a PMOS transistor and the third transistor M3 may be an NMOS transistor or vice versa. In one implementation form, g_m - the transconductance gain of the inverting branch, depends on the current through the inverter 400 and is modulated by the gate-source ac input signal V_Gs and this g_m modulation may be used to compensate non-linear performance. The inverter 400 may employ two amplifying transistors, an NMOS M3 and a PMOS M2 reusing the same current l₀ and both contributing to the total g_m according to the following relation: g , = g + g

Both transistors M2, M3 reuse the same bias current, hence the total gain g_m__toiai targeted for the inverter 400 takes advantage of two transistors M2, M3 and therefore requires a lower bias current. In addition no power is wasted on passive or active biasing load. All current drawn by this path (S2-D2-D3-S3) is serving for amplification.

Furthermore the g_m modulation for the NMOS transistor M3 and the PMOS transistor M2 act to compensate each other for a useful range of the gate-source ac input signal V_Gs, hence providing an operation of higher linear performance. The inverter 400 is highly current efficient and highly linear.

In one example, the inverter 400 is realized in 65-nm CMOS technology. Fig. 5a shows a performance diagram illustrating an exemplary drain source current l_ds over a gate source voltage V_Gs of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor. Fig. 5b shows a performance diagram illustrating an exemplary gain g_m over a gate source voltage V_Gs of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor.

Figures 5a/b illustrate the characteristic behavior (i.e., the inverter linearity) of the inverter 400: The Input RF voltage v_in=Vg_{S p}=v_{gs n} and NMOS and PMOS g_m variations with input voltage signal over respective v_gs bias values have inverted slopes 501 , 502. Hence, g_m__P + g_m_n variations, are cancelled (at least partially within a reasonable v_in range) and the inverter amplifier is "linearized".

Fig. 6 shows a performance diagram illustrating the characteristic performance of an inverter 400 as depicted in Fig. 4 which includes a PMOS and an NMOS transistor. The inverted slopes 601 , 602 of the gain g_{m p} of the second transistor M2 and the gain g_m__n of the third transistor M3 cancel out each other; A common point of both slopes 601 , 602 lies at Gain/Source voltage V_Gs=0. This characteristic behavior provides a highly linear inverter 400 and thus a highly linear active balun 300.

The present disclosure also supports a method for transferring an input signal at a first terminal to an output signal at a second terminal of an active balun, e.g. an active balun 300 as described above with respect to Figure 3. The method includes the following blocks: Using a first transistor M1 of the active balun for transferring the input signal to a first potential of a differential output signal at a non-inverting terminal of the active balun; and using an inverter 301 of the active balun for transferring the input signal to a second potential of the differential output signal at a non-inverting terminal of the active balun.

The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps as described herein, in particular the method described above. Such a computer program product may include a readable storage medium storing program code thereon for use by a computer. The program code may perform the method as described above.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be

appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein. Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1 . An active balun (300), comprising: a first terminal (303); a second terminal (305, 306); a first transistor (M1 ) comprising a first current path (D1 -S1 , l_Ds) and a control path (G1 -S1 , V_GS) for controlling the first current path (D1 -S1 , l_DS), wherein the first current path (D1 -S1 , l_DS) is coupled between the first terminal (303) and the second terminal (305, 306) and the control path (G1 -S1 , V_GS) is coupled between a reference potential (304b, G 1 ) and the first terminal (303, S1 ); and an inverter (301 ) comprising a second current path (S2-D2-D3-S3), wherein the second current path (S2-D2-D3-S3) is coupled in parallel to the first current path (D1 -S1 , IDS) of the first transistor (M1 ).

2. The active balun (300) of claim 1 , comprising: a current source (314), configured to bias the first transistor (M 1 ).

3. The active balun (300) of claim 1 or 2, wherein the second terminal (305, 306) is a differential terminal having a non- inverting terminal (305) for providing a first potential of a differential signal and an inverting terminal (306) for providing a second potential of the differential signal.

4. The active balun (300) of claim 3, wherein the inverter (301 ) is configured to inhibit a reverse transfer of the first terminal (303) to the differential signal at the second terminal (305, 306) .

5. The active balun (300) of claim 3 or 4, comprising: a differential load (313) coupled between the non-inverting terminal (305) and the inverting terminal (306).

6. The active balun (300) of one of claims 3 to 5, wherein the first transistor (M1 ) is configured to in-phase transfer an input signal (Vin) at the first terminal (303) to a first output current (lout+) or potential (Vout+) of a differential output signal at the non-inverting terminal (305).

7. The active balun (300) of claim 6, wherein the inverter (301 ) is configured to transfer the input signal (Vin) to a second output current (lout-) or potential (Vout-) of the differential output signal at the inverting terminal (306).

8. The active balun (300) of one of claims 3 to 7, wherein the inverter (301 ) comprises a second transistor (M2) and a third transistor (M3), wherein a current path (S2-D2) of the second transistor (M2) is arranged in series with a current path (D3-S3) of the third transistor (M3).

9. The active balun (300) of claim 8, wherein the second transistor (M2) is configured to bias the third transistor (M3); and wherein the third transistor (M3) is configured to bias the second transistor (M2).

10. The active balun (300) of claim 8 or 9, wherein the second transistor (M2) is a PMOS transistor and the third transistor (M3) is an NMOS transistor.

1 1 . The active balun (300) of one of claims 8 to 10, wherein an absolute value of a first gain (g_{m p}) of the second transistor (M2) driven by a gate-source voltage (V_Gs) is designed to equal an absolute value of a second gain (g_{m n}) of the third transistor (M3) driven by the inverse gate-source voltage (-V_Gs)-

12. The active balun (300) of one of claims 8 to 1 1 , wherein the first transistor (M2) and the third transistor (M3) are configured to reuse a same bias current (I0) contributing to a total gain (g_m) of the inverter (301 ).

13. The active balun (300) of claim 12, wherein the total gain (g_m) of the inverter (301 ) is essentially equal to a sum of a first gain (g_m__P) of the second transistor (M2) and a second gain (g_m__n) of the third transistor (M3).

14. The active balun (300) of claim 13, wherein the second transistor (M2) and the third transistor (M3) are configured such that variations of the respective first and second gains (g_{m p}, g_{m n}) with an input signal (Vin) at the first terminal (303) over the bias current (I0) have inverted slopes (601 , 602).

15. The active balun (300) of claim 14, wherein the slopes (601 , 602) of the first and second gains (g_m__P, g_m_n) with the input signal (Vin) cancel out each other.