Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
  • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
  • G06F7/724—Finite field arithmetic
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes
  • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
  • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/373—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
  • H03M13/3761—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
  • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
  • H03M13/615—Use of computational or mathematical techniques
  • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes
  • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
  • H03M13/1515—Reed-Solomon codes

Definitions

• the present invention lies in the field of the computation of vector-matrix multiplications.
• the present invention relates to an optimizer for determining an optimal sequence of operations for computing a product of a vector with a matrix, wherein the matrix is a binary matrix or a coding matrix over GF 2 ⁇ ).
• the present invention also relates to a storage controller configured to encode data, and to a storage controller configured to recover part-erased data.
• the present invention further relates to methods for determining optimal sequences of operations for computing vector-matrix products and to a method for recovering part-erased data.
• the present invention also relates to a computer-readable storage medium storing program code, the program code comprising instructions for carrying out such a method.
• Erasure coding is commonly used in storage systems in order to provide protection against various kinds of failures.
• the controller of a storage system needs to implement some algorithms for computing parity symbols from data, as well as for recovering lost (erased) symbols from non-erased ones. In general, these algorithms reduce to vector-matrix multiplication.
• modern storage media, such as SSD provide extremely high performance, so that the computational performance of the controller may become a bottleneck in the system.
• the existing solutions to this problem include hardware RAID controllers, which can efficiently compute XOR of large blocks of data, and software RAID implementations, which may include fast algorithms for multiplication by matrices which define the erasure code.
• These algorithms may be code-specific, or generic, i.e. those which do not take into account the algebraic properties of the code.
• i t are indices of non-failed devices participating in repair
• P is a permutation matrix, which maps s ⁇ j s , 1 ⁇ s ⁇ t, t + s' ⁇ i s >, 1 ⁇ s' ⁇ I.
• Hardware RAID controllers which fully or partially implement multiplication by some pre-defined matrices (typically for r ⁇ 2).
• Williams algorithm is 0 ( l0 ⁇ fe )- Th e latter one is, however, difficult to apply for the case of vectors in GF(2 m ).
• An objective of the present invention includes providing an optimizer and a method for determining an optimal sequence of operations for computing a product of a vector with a binary matrix, wherein the optimizer and the method overcome one or more of the problems of the prior art.
• Another objective of the present invention is related to providing a storage controller and a method for recovering part-erased data, wherein the storage controller and the method overcome one or more of the problems of the prior art.
• an objective of the invention can include reducing the latency of erasure coding and decoding operations in storage systems.
• a first aspect of the invention provides an optimizer configured to determine an optimal sequence of operations for computing a product of a vector x with a binary matrix A, the optimizer being configured to carry out the steps:
• the subset P can also be selected according to P ⁇ ⁇ 0, ... , m - 1 ⁇ .
• Embodiments of the optimizer of the first aspect can achieve a reduction of the number of arithmetic operations needed to implement multiplication of an arbitrary vector by a given matrix A and/or a reduction of the overall computation latency.
• the optimizer of the first aspect can be implemented in a device that is separate from a computation device which is configured to carry out the vector-matrix computations according to the optimal sequence determined with the optimizer of the first aspect. This can be advantageous because for a given matrix A the optimal sequence needs to be determined only once. Subsequently, the computation device can carry out the optimal sequence for different choices of vectors x. If the computation device should be configured to carry out vector-matrix computations for different matrices A, the optimizer can be configured to pre-compute optimal sequences for different choices of matrix A , and store these optimal sequences such that the computation device can look-up and retrieve an optimal sequence for a given matrix A.
• the optimizer of the first aspect can be included in a computation device for computing the vector-matrix computations. This can be advantageous in particular if the computation device should be configured to carry out vector-matrix computations for a large number of different matrices. Thus, it may be preferable that the computation device itself can determine the optimal sequence for carrying out the product of a vector-matrix computation.
• the linear combination of elements of the first partial result y-p and elements of the input x is:
• the subset is selected randomly.
• Selecting the subset randomly can include using a pseudo-random algorithm.
• a random selection of the subset has the advantage that for completely different choices of the subset P it can be determined how many operations are necessary and an optimal subset can be chosen.
• a mailman algorithm is used.
• the mailman algorithm represents an efficient way of computing the vector-matrix computation of the first partial result.
• a second aspect of the invention refers to an optimizer for determining an optimal sequence of operations for computing a product of a vector with a coding matrix over GF(2 tl ), the optimizer comprising:
• a computing unit for decomposing the coding matrix into a product of a non-binary matrix and a binary matrix
• an optimizer for determining a sequence of operations for computing a product of the vector with the binary matrix according to the first aspect.
• the problem of determining an optimal sequence for computing a product of a vector with a coding matrix which is not necessarily a binary matrix, can be reduced to the problem of determining an optimal sequence for computing a product of a vector with a binary matrix - which can be solved with the optimizer according to the first aspect.
• the methods according to the fifth and sixth aspect of the invention can be performed by the optimizer according to the first and second aspect of the invention, respectively. Further features or implementations of the method according to the fifth and sixth aspect of the invention can perform the functionality of the optimizer according to the first and second aspect of the invention and its different implementation forms.
• the coding matrix is a check matrix of a linear block code for encoding data for storage on a plurality of storage devices.
• the separate optimization of the sequence of operations with the optimizer of the second aspect is of particular advantage if used for matrices of a linear block code for encoding data for storage on a plurality of storage devices.
• this is advantageous because the matrix can be determined based on one of several possible storage configurations.
• the optimizer of the second aspect can determine an optimal sequence of operations for computing a vector-matrix multiplication with this coding matrix.
• the optimal sequences can be stored on a storage controller which thus has access to an optimal sequence for each of the possible storage configurations.
• a third aspect of the invention refers to a storage controller configured to encode data for storage on a plurality of storage devices, comprising:
• a detector for detecting a storage configuration of the plurality of storage devices
• controller for determining a coding matrix for encoding the data according to the storage configuration
• an optimizer for determining an optimal sequence of operations for computing a product of a vector with the coding matrix M in particular an optimizer according the second aspect
• a programmable logic circuit programmable to encode the data using the determined sequence of operations.
• the storage controller of the third aspect can both detect a storage configuration, determine the corresponding coding matrix and determine a corresponding optimal sequence of operations for computing a product of a vector with the coding matrix.
• the storage controller can be configured to determine a new optimal sequence of operations whenever the detector has detected that a storage configuration has changed.
• the storage controller itself can determine the optimal sequence of operations and thus the optimal way of computing the vector-matrix multiplications that are necessary when storing data on the plurality of storage devices according to the current storage configuration.
• a fourth aspect of the invention refers to a storage controller, configured to recover part-erased data from a plurality of storage devices, comprising:
• a detector for detecting a failure configuration of the part-erased data
• a controller for determining a coding matrix M for recovering data according to the failure configuration
• an optimizer for determining a sequence of operations for computing a product of a vector with the coding matrix M, in particular an optimizer according to the second aspect
• a programmable logic circuit programmable to decode the data using the determined sequence of operations.
• the storage controller of the fourth aspect may be configured to recover part-erased data that was encoded with a storage controller according to the third aspect.
• a storage controller of the fourth aspect may also be a storage controller of the third aspect, i.e., the same storage controller may be configured to encode data and to recover-part erased data.
• the programmable logic circuit comprises a field-programmable gate array.
• Field-programmable gate arrays FPGA can be configured after manufacturing and can efficiently carry out the configured operations.
• the FPGA can be configured to carry out the optimal sequence of operations as determined by the optimizer.
• a fifth aspect of the invention refers to a method for determining an optimal sequence of operations for computing a product of a vector x with a binary matrix H, comprising:
• the subset P can also be selected according to P ⁇ 0, ... , m— 1 ⁇ .
• a sixth aspect of the invention refers to a method for determining an optimal sequence of operations for computing a product of a vector with a coding matrix over
• a seventh aspect of the invention refers to a method for recovering part-erased data, comprising:
• An eighth aspect of the invention refers to a computer-readable storage medium storing program code, the program code comprising instructions for carrying out the method of the fifth, sixth or seventh aspect or one of the implementations of the fifth, sixth or seventh aspect.
• FIG. 1 is a block diagram illustrating a first optimizer in accordance with a first embodiment of the present invention
• FIG. 2 is a block diagram illustrating a second optimizer in accordance with a second embodiment of the present invention
• FIG. 3 is a block diagram illustrating a storage controller in accordance with a further embodiment of the present invention.
• FIG. 4 is a block diagram of a storage system architecture in accordance with an embodiment of the present invention.
• FIG. 5 is a flow chart of a method for determining an optimal sequence of operations for computing a product of a vector x with a binary matrix H in accordance with a further embodiment of the present invention
• FIG. 6 is a flow chart of a method for determining an optimal sequence of operations for computing a product of a vector with a coding matrix over G (2 ⁇ X ) in accordance with a further embodiment of the present invention
• FIG. 7 is a flow chart of a method for recovering part-erased data in accordance with a further embodiment of the present invention.
• FIG. 8 is a diagram illustrating the encoding complexity of a method in accordance with the present invention in comparison with alternative methods.
• FIG. 1 is a block diagram illustrating a first optimizer 100 in accordance with a first embodiment of the present invention.
• the first optimizer 100 is optionally connected with a programmable logic circuit 110, indicated with dashed lines in FIG. 1, wherein the programmable logic circuit 110 is optionally connected to a plurality of storage devices 120.
• the optimizer 110 is configured to determine an optimal sequence of operations and the programmable logic circuit 110 can be configured to carry out the optimal sequence of operations.
• the programmable logic circuit 120 can carry out the optimal sequence of coding operations in order to compute an encoding of data for storage on the plurality of storage devices.
• the matrices used for encoding and erasure recovery need to be changed every time the system configuration changes, any storage device fails or is replaced.
• the proposed storage system architecture can include a control unit, which detects changes in system configuration, including device failure and recovery, and constructs appropriate matrices for erasure coding and recovery. Then the above described method is used to construct sequences of arithmetic operations, which implement multiplication by these matrices. These sequences are represented as a VHDL specification, which is translated and loaded into FPGA. All data access operations, which require erasure coding or recovery, invoke the FPGA in order to perform the corresponding multiplication operations.
• FIG. 2 is a block diagram illustrating a second optimizer 200 in accordance with a second embodiment of the present invention.
• the second optimizer 200 comprises a computing unit 210 and a first optimizer 100.
• the first optimizer 100 can be the optimizer of FIG. 1.
• the computing unit 210 can be configured to decompose the coding matrix into a product of a non-binary matrix and a binary matrix. For the binary matrix, the optimizer 100 can determine an optimal sequence for computing a product of a vector with the binary matrix.
• FIG. 3 is a block diagram illustrating a storage controller 300.
• the storage controller 300 comprises a detector 310, a controller 320, an optimizer 330 and a programmable logic circuit 340.
• the storage controller can be configured in the following:
• the detector 310 is configured to detecting a storage configuration of the plurality of storage devices.
• the controller 320 is configured to determine a coding matrix M for encoding the data according to the storage configuration.
• the optimizer 330 is configured to determine a sequence of operations for computing a product of a vector with the coding matrix M, in particular an optimizer as illustrated in FIG. 2.
• the programmable logic circuit 340 is programmed to encode the data using the sequence of operations that the optimizer 330 has determined.
• the components of the storage controller 300 can also be configured as follows:
• the detector 310 is configured to detect a failure configuration of the part-erased data.
• the controller 320 is configured to determine a coding matrix M for recovering data according to the failure configuration.
• the optimizer 330 is configured to determine a sequence of operations for computing a product of a vector with the coding matrix M, in particular an optimizer according as illustrated in FIG. 2.
• the programmable logic circuit 340 is programmable, e.g. programmable by the optimizer 330, to decode the data using the sequence of operations determined by the optimizer.
• the components of the storage controller can be configured to contribute both to the encoding of data for storage on the plurality of storage devices and for the recovery of part-erased data from the plurality of storage devices.
• the storage controller is connected to a plurality of storage devices 350.
• the programmable logic circuit 340 can be connected directly to the plurality of storage devices 350, but in other embodiments of the invention also other components of the storage controller 300, e.g., the detector 310, the controller 320 and/or the optimizer 330 can be connected directly to the plurality of storage devices 350.
• the plurality of storage devices 350 can include SSDs, hard drives and/or a combination of both.
• FIG. 4 is a block diagram illustrating a storage system architecture 400 in accordance with an embodiment of the present invention.
• the architecture 400 comprises a control unit 410 which detects a configuration of a plurality of storage devices 450.
• the control unit 410 is configured to provide information about the detected configuration of the plurality of storage devices to a unit 430 for generating a sequence of operations for encoding an erasure decoding.
• the unit 430 is configured to provide the determined optimal sequence to a VHDL translator 435 which is configured to provide a programming for a FPGA 440.
• An application 420 (e.g. executed on a general purpose computer) provides data to the FPGA 440 which is programmed to encode the data using the optimal sequence and to write the encoded data to the plurality of storage devices 450.
• FIG. 5 is a flow chart of a method for determining an optimal sequence of operations for computing a product of a vector x with a binary matrix H in accordance with a further embodiment of the present invention.
• the method comprises a first step 510 of determining a set S of low- weight vectors z in a row space of a systematic matrix H 6 GF (2) nxm that comprises the binary matrix A.
• Selecting the subset P can be performed randomly, e.g. using a pseudo-random algorithm.
• the subset P can also be selected as the entire set ⁇ 0, ... , m— 1 ⁇ , that is, according to P ⁇ 0, ... , m— 1 ⁇ .
• a third step 530 involves selecting a sub-matrix Ap as the columns of A not having indices in the subset P.
• a fourth step 540 involves estimating a number of algorithmic operations required to:
• a fifth step 550 the first to fourth steps 510-540 are performed for different subsets P and a sequence of operations is selected for computing the product xA based on a preferred subset P that yields a smallest number of algorithmic operations.
• the first to fourth steps can be performed for example a predetermined number of times.
• the fast algorithm can be translated for vector-matrix multiplication, obtained as described above, into VHDL code, and the corresponding calculations can be offloaded to an FPGA attached to the system.
• the FPGA needs to be reconfigured as soon as the configuration of a storage system changes, or any of its devices fail or recover.
• y xAL
• L is a mr x r block-diagonal matrix with blocks (a 0 , ... , a" 1-1 ) 7" on its main diagonal
• A is a binary k x mr matrix consisting of A jit elements.
• the proposed approach can involve the following steps:
• FIG. 6 is a flow chart of a method for determining an optimal sequence of operations for computing a product of a vector with a coding matrix over GF(2 ) in accordance with a further embodiment of the present invention.
• the method comprises a first step 610 of decomposing the coding matrix into a product of a non-binary matrix and a binary matrix and a second step 620 of determining a sequence of operations for computing a product of the vector with the binary matrix.
• FIG. 7 is a flow chart of a method for recovering part-erased data in accordance with a further embodiment of the present invention.
• the method comprises a first step 710 of detecting a failure configuration of the part-erased data. This is of importance because the specific failure configuration determines the coding matrix that is necessary for recovering the data.
• a second step 720 a coding matrix M for recovering data according to the failure configuration is determined.
• step 730 an optimal sequence of operations for computing a product of a vector with the coding matrix M is determined.
• step 740 the original data are recovered from the part-erased data using the determined optimal sequence of operations.
• FIG. 8 shows the number of summations needed to implement multiplication by a n x n binary matrix for the case of proposed method, mailman algorithm, and standard method.
• the proposed matrix multiplication algorithm enables one to reduce the number of arithmetic operations compared to the case of straightforward multiplication (commonly used in today storage) and mailman algorithm. It can be seen that up to 15% gain is achieved. Observe that it is possible to further reduce the number of arithmetic operations by eliminating common sub-expressions arising from equation (1), but this can cause higher computation latency.
• Table 1 illustrates the latency of systematic encoding of various Reed-Solomon codes using the FPGA simulator ICARUS for the case of Altera EP2C70F896C6-R device.
• important points include: A method for obtaining a fast algorithm for multiplication of a vector by a matrix over GF(2 m ), which involves decomposition of a matrix into a product of a binary and a non-binary matrices, selection of a submatrix of the binary matrix, construction of a fast algorithm for multiplication by the submatrix of the binary matrix, identifying linear expressions, which relate the remaining components of the product of a vector of a binary matrix with computed ones and input values, and selecting those which require the smallest number of operations.
• a storage system which employs an erasure code, and the algorithms derived using the above method for computing check symbols and recovering erased symbols.
• 3 A storage system as above, which includes and FPGA device, which is used to offload the erasure coding and recovery calculations corresponding to the algorithms obtained according to the above method.

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