WO2017058494A1

WO2017058494A1 - Memory system with cached memory module operations

Info

Publication number: WO2017058494A1
Application number: PCT/US2016/051141
Authority: WO
Inventors: Frederick A. Ware; Kenneth L. Wright; John E. Linstadt; Craig Hampel
Original assignee: Rambus Inc.
Priority date: 2015-10-01
Filing date: 2016-09-09
Publication date: 2017-04-06
Also published as: CN108139978A; CN108139978B; EP3356943A4; US20240160587A1; CN116560563A; US20180267911A1; US11836099B2; EP3356943A1; US20220171721A1; US20200364164A1; US10678719B2; US11210242B2; EP3356943B1

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

Description

MEMORY SYSTEM WITH CACHED MEMORY MODULE OPERATIONS

TECHNICAL FIELD

[0001] The disclosure herein relates to memory systems, memory modules, memory controllers, memory devices, and associated methods.

BACKGROUND

[0002] Successive generations of dynamic random access memory components (DRAM) have appeared in the marketplace with steadily shrinking lithographic feature size. As a result, the device storage capacity from each generation has increased. However, it is increasingly becoming more difficult to scale DRAM devices and obtain sufficient capacitive performance for charge storage. DRAM device manufacturing can also be costly.

[0003] Various non-volatile memory technologies, such as resistive random access memory (RRAM) and phase change random access memory (PCRAM), to name a few, are relatively inexpensive to manufacture. However, many of the non- volatile memory technologies have yet to attain the performance of their DRAM counterparts.

[0004] It would be desirable to employ memory in a memory system that has the cost advantages of many non- volatile technologies with the performance of DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0006] FIG. 1 illustrates one embodiment of a memory system that employs a first memory module that mounts only DRAM components, and a second module that mounts both DRAM components and storage class memory (SCM) memory components.

[0007] FIGs. 2A-I illustrates various examples of module interconnection schemes further described herein.

[0008] FIG. 3 illustrates steering circuitry within a data buffer component.

[0009] FIGs. 4A-4F illustrate various cache operations corresponding two different memory module configurations.

[0010] FIG. 5 illustrates a tag data structure as it correlates to SCM memory space.

[0011] FIG. 6 illustrates a point-to-point memory architecture utilizing a first memory module with DRAM components and a second memory module with SCM components.

[0012] FIG. 7 illustrates a memory architecture similar to figure 6 utilizing four memory modules.

[0013] FIGs. 8A-8F illustrate a variety of cache operations corresponding to various memory module configurations.

[0014] FIG. 9 illustrates further detail of a memory system according to one embodiment. [0015] FIGs. 10-13 illustrate various timing diagrams regarding cache operations in the memory system of figure 9.

[0016] FIG. 14 illustrates circuitry relating to tag matching distributed across a module.

[0017] FIGs. 15A-15I illustrate a configuration taxonomy for various memory module configurations utilizing both SCM memory components and DRAM memory components.

[0018] FIGs. 16A-16F illustrate various cache operations for the memory module configuration shown in figure 15 A.

[0019] FIGs. 17A-17F illustrate various cache operations for the memory module configuration shown in figure 15B.

[0020] FIGs. 18A-18F illustrate various cache operations for the memory module configuration shown in figure 15C.

[0021] FIGs. 19A-19F illustrate various cache operations for the memory module configuration shown in figure 15D.

[0022] FIGs. 20A-20F illustrate various cache operations for the memory module configuration shown in figure 15E.

[0023] FIGs. 21A-21F illustrate various cache operations for the memory module configuration shown in figure 15F.

[0024] FIGs. 22A-22F illustrate various cache operations for the memory module configuration shown in figure 151.

[0025] FIGs. 23A-23F illustrate various cache operations for the memory module configuration shown in figure 151.

[0026] FIGs. 24A-24F illustrate various cache operations for the memory module configuration shown in figure 151. [0027] FIG. 25 illustrates a performance comparison between various memory module configurations.

[0028] FIG. 26 illustrates a power comparison between various memory module

configurations.

[0029] FIG. 27 illustrates further detail regarding the memory system configuration of FIG. 15A.

[0030] FIG. 28 illustrates further detail regarding the memory system configuration of FIG. 15 C.

[0031] FIG. 29 illustrates further detail regarding the memory system configuration of FIG. 15E.

[0032] FIGs. 30 - 36 illustrate further detail regarding various cache operations with respect to various system configurations.

[0033] FIGs. 37 - 42 illustrate timing diagrams showing the timing of various cache operations in various system embodiments.

[0034] FIGs. 43 - 45 illustrate various system configurations.

[0035] FIGs. 46 - 49 illustrate various timing diagrams.

[0036] FIG. 50 illustrates further detail regarding DRAM package structure.

[0037] FIG. 51 illustrates a further system embodiment.

[0038] FIG. 52 illustrates a high-level system embodiment.

DETAILED DESCRIPTION

[0039] Memory modules, memory controllers, devices and associated methods are disclosed. In one embodiment, a memory module is disclosed that includes a pin interface for coupling to a data bus having a first width. The module is capable of operating in a first legacy mode that utilizes the full first width of the data bus. The module may also be operated in a second mode where the module utilizes less than all of first width of the data bus. The module includes at least one storage class memory (SCM) device and at least one DRAM memory device. This basic architecture enables the DRAM device to provide a caching function for transactions directed to the SCM device, thereby providing high performance for a memory system that is primarily populated with lower-cost SCM devices.

[0040] Referring now to FIG. 1, a memory system according to a first embodiment, generally designated 100, is shown. The system includes a first DRAM module 102 and a second module 104 that incorporates both DRAM memory components or devices 106 and storage class memory (SCM) devices 108. Storage class memory devices include, for example, memory components that have characteristics often associated with non- volatile memory devices such as phase change memory (PCM), resistive random access memory (RRAM), and flash memory. The first and second modules 102 and 104 are interconnected to a memory controller 105 via a legacy point-to-2-point (multi drop) architecture including primary data paths DQu and DQv and control address C/A paths CA, CSy and CSx. For one embodiment, the DRAM components in the hybrid module 104 are configured to form a cache memory, thus providing cache

functionality for transactions involving the memory controller 105 and the SCM memory devices 108. Utilizing a legacy multi drop link architecture, however, may involve a fixed ratio of the DRAM cache memoryto the SCM memory on the hybrid module 104. Thus, expanding the cache region to a secondary module may involve additional transfers on the primary links, which may impact the bandwidth of those links.

[0041] Further referring to FIG. 1, each of the memory devices (DRAM and/or SCM) 106 and 108 may include one or more stacks of memory die. The structure of the SCM stacks will be described, with the understanding that the DRAM stacks may be configured in a similar manner. As noted earlier, the memory die may be of a nonvolatile-type of memory technology other than DRAM, such as such as resistive random access memory (RRAM), phase change random access memory (PCRAM), and flash, to name but a few. Each stack of devices may contain, for example, eight SCM memory components. One example of a stacked set of devices is shown in the magnified view 1-1, illustrating stacked SCM memory components 116 within a single package 118. For some configurations, the opposite side of the SCM module substrate 120 may mount memory components, such as at 122. The interface of each SCM memory component may be connected in parallel using through-silicon-vias, wire bonding, any other connection method. Other stacking configurations such as package-on-package stacking are also possible.

[0042] FIGs. 2A-2C illustrate various high-level configuration diagrams. FIG. 2A shows interconnections between a memory controller 202 and one hybrid DRAM/SCM module 204, while FIGs. 2B - 21 show interconnections between the memory controller 202 and two modules including the hybrid module 204 and a second module 206 that includes DRAM components only, or both DRAM and SCM components. The configuration of FIG. 2A includes the memory controller 202 that has a tag memory comparison circuit 208 with the controller being connected to the hybrid memory module 204 via two 36b independent channels or one 72b locks tep channel. The hybrid module 204 includes both DRAM and SCM memory components 210 and 212. FIG. 2B shows a two module configuration where the memory controller 202 couples to the hybrid module 204 and the second module 206 that includes only DRAM components 210. The two modules 204 and 206 are coupled to the memory controller 202 via a multi-drop

configuration, where a given link of the controller is shared by corresponding links associated with each module. Lastly, FIG. 2C illustrates a further multi-drop two-module configuration where both modules 204 and 206 are hybrid modules that include both SCM and DRAM memory components 210 and 212.

[0043] FIGs. 2D- 2F illustrate memory module configurations involving a point-to-point connection between the memory controller 202 and one or each of the two modules 204 and 206, and each of two sockets, each socket capable of holding one module. As shown in FIG. 2D, the memory controller 202 includes the tag memory comparison circuit 208, and a first point-to- point link 214 that couples a portion of the tag memory comparison circuit to the hybrid memory module 204. A second portion of the tag memory compare circuit, at 217, connects to the hybrid memory module 204 via a point-to-point link 216 routed through a continuity module 218. The continuity module is configured to plug into a module socket to provide point-to-point connectivity between the memory controller 202 and at least one other module. As such, the continuity module does not employ memory devices, and merely provides a connectivity function. As a result of the added connectivity, the single hybrid memory module 202 may interface with the memory controller 202 through multiple point-to-point links, half of the links directly coupled to the memory controller, and half of the links routed through the continuity module to the controller. The link 216 may form a back channel that is directly coupled between the hybrid memory module 204 and the continuity module 218. As more fully described below, for one embodiment, the back channel link may provide a connection for balancing loads between memory modules.

[0044] Fig. 2E illustrates a similar configuration as FIG. 2D, but instead of utilizing a continuity module in the second module socket, a second memory module 206 employing DRAM memory components 210 is plugged into the socket, thus connecting to the memory controller 202 in a point-to-point fashion. For one embodiment, the DRAM memory components provide non-cached DRAM storage. FIG. 2F shows a further alternative embodiment where the second memory module 206 is a hybrid memory module employing both SCM and DRAM memory components 210 and 212.

[0045] FIGs. 2G-2I illustrate possible load-balancing examples for the system configuration of FIG. 2E. FIG. 2G illustrates a load-balancing example where half the bandwidth of the system is directed to the first module 204 and half the bandwidth of the system is directed to the second module 206. For this case, the back channel link 216 between the two modules does not provide a balancing function. FIG. 2H illustrates a load balancing example where the full bandwidth of the system is allocated to the hybrid module 204 by utilizing the back channel 216 to bypass data transfers from the memory controller 202 through the second memory module 206 to the hybrid memory module 204. FIG. 21 illustrates an example where the full bandwidth of the system is allocated to the second module 206, a DRAM-only module, through activation of the back channel 216 to direct data transfers through the hybrid module 204 to the DRAM module 206. Load balancing may be carried out in a similar manner as in the system configuration of FIG. 2F.

[0046] FIG. 3 illustrates one embodiment of steering logic 300 that may be utilized with a data buffer DB component of each of the memory modules described above. The steering logic 300 includes a primary interface 302 that has a nibble pair of DQ/DQS I/O circuits, and a secondary interface 304 that also includes a corresponding nibble pair of DQ/DQS I O circuits. Each nibble pair of the primary interface 302 is associated with a receive path 306 for write data and a transmit path 308 for read data. Each transmit path 308 is fed by an output of a multiplexer 310 which receives data from a selected receive path 312 associated with the secondary nibble pairs and the other receive path 306 of the primary nibble pair. The nibble pair circuitry for the secondary interface is similar to the primary interface, but with the receive and transmit paths corresponding to read and write data, respectively. The steering logic 300 essentially allows data from any of the DQ/DQS I/O circuits to be steered to any of the other DQ/DQS I/O circuits, thus providing for a bypass function, and enabling load balancing for systems with point-to-point topologies (such as FIGs. 2D-2I).

[0047] FIGs. 4A through 4F illustrate various cache operations associated with hybrid DRAM and SCM modules, where a tag comparison circuit 402 is located on a memory controller 404. In general, a portion of an overall DRAM capacity defined by DRAM components on each module is designated as a cache for the SCM memory. For a given memory operation, an address is requested by the controller 404, at 402. If the address is held in the DRAM cache, then the data in the addressed cache space may be fed and provided to the controller directly, as shown in FIG. 4A. As shown in FIG. 4B, in the event that the address is not in the cache, often referred to as a "miss", the contents still need to be read out for a tag comparison. This is carried out as a first step, at 406. An additional step is carried out, at 408, where the SCM memory is read for the data. Referring now to FIG. 4C, should the miss involve "dirty" data, then in addition to the read operations 406 and 408 from the DRAM and SCM modules described above with respect to FIG. 4B, a write operation back to the old location in the SCM memory is carried out, at 410. The second and third steps 408 and 410 may be carried out in any order. FIGs. 4D through 4F show corresponding cache operations for write transactions.

[0048] FIG. 5 illustrates one embodiment of the relationship, or mapping, between a given cache line in DRAM space, to multiple address lines in the SCM memory space. This may be referred to as a DRAM to SCM mapping for single-set (direct-map) cache organization. For the example shown, any of eight cacheline locations in the SCM space, such as at 502, can be loaded in a single cacheline in the DRAM space, such as at 504. One embodiment of a data structure 506 that may be stored in the DRAM cacheline includes a tag address field 508 that identifies a 3-bit tag address, a 72B data field 510, an error code EDC field 512 that protects the entire data structure, and respective parity 514, valid 516 and dirty fields 518. For one embodiment, the EDC field 512 may protect the DATA and TAG fields 510 and 508 with an error

correction/detection code. The EDC field 512 might also protect the VALID, DIRTY, and PARITY fields 514, 516 and 518 in some embodiments, and may not protect the fields in other embodiments. The PARITY field 514 may protect the TAG field 508 with an error detection code (this code will be redundant with the code used in the EDC field). The PARITY field 514 might also protect the VALID field 516, and the DIRTY field 518 in some embodiments.

[0049] FIG. 6 illustrates one embodiment of a memory system 600 that exhibits a point-to- point architecture. The system 600 includes a first memory module 602 that employs DRAM memory components 604 that are buffered from a memory controller 606 by multiple data buffer components DB and a command/address (CA) buffer component RCD. The first memory module 602 couples to the memory controller 606 through a point-to-point data nibble or link DQv, and a point-to-point CA link CS/CAx. The system 600 includes a second memory module 608 that employs SCM memory components 610 that are also buffered from the memory controller 606 by multiple data buffer DB and CA buffer components RCD. The second module 608 includes a point-to-point connection to the memory controller via data nibble DQu. A CA link CS/CAy couples the CA signal lines of the second module 608 to the memory controller 606 in a point-to-point manner. The first module 602 and the second module 608 may communicate with each other via a backchannel signal path DQt. For the described two-module configuration, half the total data width of the controller may be allocated to one module, and half the total data width may be allocated to the second module. For one embodiment, at least a portion of the DRAM memory space of the first module 602 is allocated to cache for operations involving the SCM memory of the second memory module 608. For one embodiment, the back channel path DQt provides for cache transfers between the two modules 602 and 608, such that no transfer bandwidth is needed on the primary links DQu and DQv for cache transfers. The back channel DQt may also provide for dynamic load balancing operations.

[0050] The memory system of FIG. 6 may be expanded while still maintaining a point-to- point architecture, as shown in FIG. 7. Four modules 702, 704, 706 and 708 are shown, with two of the modules 704 and 708 employing DRAM components to provide a cache for the two other modules 702 and 706 that employ SCM memory components. In such an embodiment, a total data width of a memory controller 710 may be allocated into halves, where direct point-to-point data connections are made to the first DRAM module 708 via nibble link DQu, and a second point-to-point connection made to the second DRAM module 704 via nibble link DQv. Point-to- point CA connections between the DRAM modules 708 and 704 and the memory controller 710 are made via links CS/CAx and CS/CAy. Back channel links, at 712 and 714, for CA signaling are provided between the DRAM modules 708, 704 and the SCM modules 706, 702 via links CS/CAx' and CS/CAy'. The SCM modules 706 and 702interface with the DRAM modules 708 and 704 for data signal transfers via back channel link connections along links DQu' and DQv' . As more fully explained below, the back channel connections 714 and 712 allow for cache operations between modules with little impact to the bandwidth of the primary interface point-to- point links DQu and DQv.

[0051] FIGs. 8A - 8F illustrate cache operations between the DRAM memory module 602, SCM memory module 608, and the memory controller 606 of FIG. 6. The operations assume that cache tag comparison circuitry 802 resides on the DRAM module 602, and that there is no writeback of dirty read miss data, and no allocation of a cacheline in the DRAM when there is a read miss. This means that the read-miss-dirty case and the write-miss-clean cases will not occur (they have been crossed out). This simplification allows the cached system to have the highest read and write bandwidth, at the cost of most reads accessing the SCM location.

[0052] FIG. 8A shows a read hit case, where the address in the DRAM cache, at 800, matches a requested address (carried out by the tag comparison circuit 802), resulting in the data being transferred from the DRAM module 602 to the memory controller 604 directly (in only one step since the data was already read from the DRAM space 800 and provided to both the tag circuit 802 and the data buffer). For one embodiment, the read data is delayed by a time interval in an effort to match a latency associated with a read miss case. When the read hit data is delayed to match the delay of the read miss data, there will be no conflict on the data bus between a read hit and an earlier read miss to a different address.

[0053] For a read miss case, shown in FIG. 8B, the DRAM 800 is first read so that the tag contents can be determined via the tag circuit 802, and compared to the incoming requested address. When the data is determined to be a "miss", the SCM memory module 606 is then accessed for a read operation to transfer the requested read data from the SCM module 606, along the back channel link, at 804, (between the DRAM module and the SCM module), then transferred from the DRAM module 602 via a bypass connection configured through the data buffer DB steering logic 300 described above with respect to FIG. 3. FIG. 8C merely confirms that a particular embodiment described here does not provide any writeback for "dirty" read miss cases.

[0054] A write hit case is illustrated by FIG. 8D, where in a first step, at 810, the tag contents are first read from the DRAM 800, and in a second step, at 812, the write data is written to the DRAM module 602. For one embodiment, for write hit cases, the write operations are directed to alternate odd and even nibbles of the DRAM module 602. When alternate odd and even nibbles are used, then it is possible to perform the tag read and the data write in two different cycles in the odd nibble, and to perform a second tag read and the data write in two different cycles in the even nibble, resulting in a throughput of one cached write operation per tCC interval (the same as an uncached DRAM system).

[0055] FIG. 8E shows that for the embodiment described, no operations for a write miss case are carried out. For write miss dirty operations, after the tag contents are compared in a first step, at 814, the tag contents are transferred via the back channel link 804 to the SCM memory, and the write data written to the DRAM 800, as shown at 816 in FIG. 8F.

[0056] FIG. 9 illustrates further detail of the memory system of FIGs. 6, 7 and 8A-8F, with special emphasis on the buffer circuitry for the DRAM and the SCM modules. To reiterate, this particular embodiment employs a point-to-point connection between a memory controller 902 and at least one DRAM module 904, and also incorporates tag compare circuitry 906 on the DRAM module, and for one embodiment, specifically in a CA buffer RCD_D. Data transfers between the memory controller 902 and an SCM module 908 are passed through the DRAM module 904 via a back channel connection DQu' between the DRAM module 904 and the SCM module 908. The memory controller 902 includes respective read and write data queues 910 and 912 coupled to data nibble DQu, which serves as a primary data link for coupling to a DRAM module data buffer component DBD. The memory controller 902 further includes respective read and write address queues 914 and 916 that are selectively coupled, via a multiplexer 918, to CA link CS/CAx, which serves as a primary CA link for coupling the memory controller 902 to the DRAM module CA buffer RCDD. Status circuitry "STATUS" 920 interfaces with the DRAM CA buffer component RCD_D via a status link STx, which provides information concerning tag compare operations, as described below.

[0057] Further referring to FIG. 9, the each buffer component DBD on the DRAM module 904 employs steering logic described above with respect to FIG. 3, such that the primary data interface I/O circuits coupled to links DQu and DQu' (the backchannel link) may be selectively coupled to either of the secondary data I/O circuits DQus (respective even and odd cache DRAM nibbles) via multiplexer circuitry appropriately placed in the data transfer paths of the steering logic. For read hit cases, delay circuitry "DATA DELAY MATCH" 922 may be employed in the data buffer DBD to match the latency of read miss cases, which may maximize the bandwidth of the primary data link DQu between the DRAM module 904 and the memory controller 902. Alternatively, the delay circuitry 922 may be omitted, and a similar delay provided by delaying address commands with delay circuitry in the DRAM CA buffer RCD_D. As described earlier, delaying the read hit data to match the read miss data allows the maximum read data bandwidth, at a cost of increased latency in the read hit case.

[0058] With continued reference to FIG. 9, the DRAM CA buffer RCD_D includes a DRAM write address buffer circuit 924 that provides buffered write addresses to DRAM memory components 926. The tag compare circuit 906 also resides on the CA buffer component RCD_D, which receives new tag information for a requested address with old tag information provided by the DRAM data buffer via a tag communication path TAGOLD . The results of the tag comparison are then fed back to the memory controller 902 via the status link STx, so that the controller can dispatch any commands necessary for additional cache operations associated with "miss" cases. CA information passed to the DRAM module 904 via the CA link CS/CAx link is redriven by the DRAM module to the SCM module 908 via a CA backchannel link CS/CAx' . [0059] The SCM memory module data buffer components DBs and CA buffer component RCDs are configured similar to their DRAM module counterparts. However, since the connections between the memory controller 902 and the memory modules 904 and 908 are made through the DRAM module 904, the steering logic for the data buffers DB_D and DBs generally provides steering capability between one primary data circuit (the back channel link), to either of the secondary data I/O circuits. As to the CA buffer component RCDs, no tag comparison circuitry is provided (or provided optionally). However, to control the back channel link

CS/CAx', bypass compare logic 928 is employed.

[0060] FIGs. 10-13 illustrate various timing diagrams that show the relative timing of various cache operations discussed above with respect to FIGs. 6, 7, 8A-8F, and 9. Referring now to FIG. 10, the relative timing for a series of operations are shown relating to a cache "read hit" and a cache read miss (clean) case. The top half of the labeled links shown in the chart (CAx to STx) correspond to signals associated with the DRAM module such as 904 (FIG. 9), while the lower signals (CAx' to DQu' relate to signals associated with the SCM module such as 908

(FIG. 9). To evaluate the contents of the tag memory, a read transaction, corresponding to commands "ACT" and "RD", to read the tag address from the DRAM is dispatched along CA link CAx, and redriven by the CA buffer along an "even" secondary CA link CAxs. The tag address data Q is accessed several cycles later, and optionally delayed. A delay of the tag data

(address) to match the latency of a read miss data operation may help maximize the bandwidth of the primary data link DQu. The tag compare circuitry 906 evaluates the requested address and the tag address and indicates a hit or miss signal "H/M" on the status link STx. Concurrent with the DRAM module transaction to read the contents of the tag memory, a speculative SCM memory access operation is carried out by dispatching a read command along the back channel

CA link CAx' which is redriven by the CA buffer RCDs along the secondary CA interface path CAx's. Alternatively, the SCM read access could wait to start until the tag was read in the DRAM and a read miss was confirmed. This increases the read miss latency, however. The resulting read data Q from the SCM module 908 may then be transferred, in the case of a "read miss clean" case, to the memory controller 902 along primary link DQu. For a read "hit" case, the data accessed from the DRAM is transferred to the memory controller 902.

[0061] FIG. 11 illustrates a timing diagram similar to that of FIG. 10, for "read hit" and "read miss clean" cases, but instead of delaying the read data accessed from the DRAM module 904, the address information is delayed along the secondary CA link CAxs in the DRAM CA buffer RCDD. Like the data delay option, described in FIG. 10, the address delay may improve the bandwidth of the primary data link DQu.

[0062] FIG. 12 illustrates the timing for a "write hit" and "dirty write miss" case. A write operation (commands "ACT" and "WR") is dispatched by the memory controller 902 along primary CA link CAx. The CA buffer component RCD_D receives the write command, address information and the associated data, and retransmits the command as a read operation "RD" (accomplished by the CA buffer RCDD) to read the contents of the tag memory. The new write data and new address tag information is then stored in the DRAM write buffer. For a write miss dirty case (determined after evaluating the tag information), a further write operation is carried out with a write command "WR" along link CAx' to place the old data and tag information in an SCM write buffer. Storing the old and new tag information in the buffers in this manner helps maximize the bandwidth of the primary data link DQu.

[0063] FIG. 13 illustrates the relative timing involved for various operations undertaken to accomplish odd/even nibble sequencing for cache write hit and miss cases. The sequencing takes advantage of the temporary storage of the tag and data in the buffers for the write operations of FIG. 12. Alternating read and write operations for odd and even nibbles attached to the data buffers minimizes turnaround time latency, and maximizes the bandwidth of the channel.

[0064] FIG. 14 shows a portion of a DRAM module, such as that shown in FIG. 9, with tag matching circuitry distributed across the DRAM module via multiple data buffer components DB, rather than being employed in the single CA buffer RCD, such as in FIG. 9, at 904 . Also shown is a portion of a data buffer 1400 that includes tag compare circuitry 1404. The status link STx interfaces the memory controller 902 to the CA buffer component RCD_D. A match link 1402 is routed along the modules between the various data buffers DB allows the data buffers DB to communicate the results of each match for each buffer along the match link to the CA buffer RCD, such that the results can be sent to the memory controller 902 to control cache operations. The tag compare circuitry 1404 is replicated in each data buffer DB and includes an XOR circuit 1406, which receives as its input old tag information TAGOLD [i] and new tag information TAG EWH (from the tag field). The XOR output, at 1408, is then masked or ORed by an OR gate 1410 with an output from a control register 1412 (set at initialization). The output from the OR gate 1410 may then undergo a timing adjustment, at 1414, and transmitted out along the match link 1402 to the CA buffer RCD. Distributing the tag status information in this manner may reduce pin counts. Alternatively the TAGOLD from the DRAM read can be transferred from the DB component to the RCD component where the TAG comparison is done. This may require more pins on the buffer components.

[0065] FIGs. 15A-15I illustrate high-level system configuration diagrams for various embodiments that may serve as alternatives to the systems, modules, and memory devices described above. The embodiments of FIG. 15E and FIG. 20 are similar to the DV4 system in FIG. 8, except that the embodiment of FIG. 8 uses a no-allocate-on-read cache policy, whereas the embodiment of FIGs. 15E and 20 will allow allocation on read operations (as will the other configurations). For instance, FIG. 15A shows a high-level diagram of a first pair of DRAM and SCM modules 1502 and 1504 coupled together via a back channel connection 1506, with the DRAM module 1502 connected to a memory controller 1508. A second pair of DRAM and SCM modules 1510 and 1512 are configured similarly. For this embodiment, tag comparison circuitry 1514 resides on the memory controller 1508. Associated cache operations for the embodiment of FIG. 15A are shown in FIGs. 16A - 16F. A read hit operation involves reading the DRAM module 1502 directly, and providing the data directly to the memory controller 1508, as shown in FIG. 16A. For a read miss clean, shown in FIG. 16B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502, and sending the read data to the memory controller 1508. For a read miss dirty, shown in FIG. 16C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 1516, and writing it to the SCM module 1504, at 1518. FIGs. 16D-16F illustrate the counterpart write cache operations.

[0066] FIG. 15B shows an alternative system configuration similar to that of FIG. 15A, but instead of interfacing the DRAM modules 1502 and 1510 to the memory controller 1508, the

SCM modules 1504 and 1512 communicate directly to the memory controller via point-to-point links 1520 and 1522. The associated cache operations for read and writes are illustrated in FIGs.

17A-17F. A read hit operation involves reading the DRAM module 1502 via the back channel link (utilizing the bypass formed by the steering logic in the buffer circuitry of the SCM module

1504, and providing the data to the memory controller 1508, as shown in FIG. 17A. For a read miss clean, shown in FIG. 17B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502, and sending the read data to the memory controller 1508. For a read miss dirty, shown in FIG. 17C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 1702, and writing it to the SCM module 1504, at 1704. FIGs. 17D-17F illustrate the counterpart write cache operations.

[0067] FIG. 15C illustrates a further system embodiment similar to FIG. 15A, with the DRAM modules coupled directly to the memory controller 1508. The tag comparison circuitry 1514 however, is disposed on each SCM module 1504 and 1512, instead of the memory controller 1508. The associated cache operations are shown in FIGs. 18A-18F. A read hit operation involves reading the DRAM module 1502 directly, providing the tag information to the tag comparison circuit 1514 via the back channel 1520, and providing the data directly to the memory controller 1508, as shown in FIG. 18A. For a read miss clean, shown in FIG. 18B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502, and sending the read data to the memory controller 1508. For a read miss dirty, shown in FIG. 18C, the first cache operation is augmented by writing the tag and address information to the SCM module 1504, at 1802. FIGs. 18D-18F illustrate the counterpart write cache operations.

[0068] FIG. 15D illustrates yet another system embodiment similar to FIG. 15A, but incorporating the tag comparison circuitry 1514 on each SCM module 1504 and 1512, and directly connecting the SCM modules to the memory controller 1508 (instead of the DRAM modules). The associated cache operations are shown in FIGs. 19A-19F. A read hit operation involves reading the DRAM module 1502 via the back channel link 1520, providing the tag information to the tag compare circuit 1514, and providing the data to the memory controller 1508, as shown in FIG. 19A. For a read miss clean, shown in FIG. 19B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502, and sending the read data directly to the memory controller 1508. For a read miss dirty, shown in FIG. 19C, the first cache operation is augmented by writing the tag and address information to the SCM module 1504, at 1902. FIGs. 19D-19F illustrate the counterpart write cache operations.

[0069] FIG. 15E illustrates a four-module embodiment similar to the embodiment shown above with respect to FIGs. 7-14, utilizing the tag comparison circuitry 1514 on each DRAM module 1502 and 1510, and coupling the DRAM modules directly to the memory controller 1508. The associated cache operations are shown in FIGs. 20A-20F. A read hit operation involves reading the DRAM module 1502 directly, and providing the data directly to the memory controller 1508, as shown in FIG. 20A. For a read miss clean, shown in FIG. 20B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 via the back channel link 1520 as a write operation to the DRAM module 1502, and sending the read data directly to the memory controller 1508. For a read miss dirty, shown in FIG. 20C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 2002, and writing it to the SCM module 1504, at 2004. FIGs. 20D-20F illustrate the counterpart write cache operations.

[0070] FIG. 15F illustrates yet another system embodiment similar to FIG. 15A, but incorporating the tag comparison circuitry 1514 on each DRAM module 1502 and 1510, and directly connecting the SCM modules 1504 and 1512 to the memory controller 1508 (instead of the DRAM modules). The associated cache operations are shown in FIGs. 21A-21F. A read hit operation involves reading the DRAM module 1502 via the back channel link 1520, comparing the tag information with the tag compare circuitry 1514, and providing the data to the memory controller 1508, as shown in FIG. 21A. For a read miss clean, shown in FIG. 21B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502 (via the back channel link 1520), and sending the read data from the SCM module 1504 directly to the memory controller 1508. For a read miss dirty, shown in FIG. 21C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 2102, and writing it to the SCM module 1504, at 2104. FIGs. 21D-21F illustrate the counterpart write cache operations.

[0071] FIG. 15G illustrates a high-level diagram showing a 3-module system configuration that employs a first DRAM module 1524 interconnected to an SCM module 1526 via a first back channel connection 1528. The SCM module interfaces with a second DRAM module 1530 via a second back channel connection 1532, such that both DRAM modules 1524 and 1530 interface with the memory controller 1508 directly.

[0072] FIG. 15H illustrates a high-level 3-module configuration similar to FIG. 15G, but incorporates a first SCM module 1532 interconnected to a DRAM module 1534 via a first backchannel connection 1536. The DRAM module interfaces with a second SCM module 1538 via a second back channel connection 1540, such that both SCM modules 1532 and 1538 interface with the memory controller 1508 directly.

[0073] FIG. 151 illustrates a high-level dual-module system configuration that generally employs an SCM module 1542 and a DRAM module 1544 that are interconnected by a back channel connection 1546, and where both modules are coupled to the memory controller 1508 via point-to-point links. FIGs. 22A - 22F illustrate cache operations associated with the system configuration of FIG. 151, where the tag comparison circuitry is disposed on the memory controller. A read hit operation involves reading the DRAM module 1502 directly, and providing the data directly to the memory controller 1508, as shown in FIG. 22A. For a read miss clean, shown in FIG. 22B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502 via the back channel link 1514, and sending the read data directly to the memory controller 1508. For a read miss dirty, shown in FIG. 22C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 2202, and writing it to the SCM module 1504, at 2204. FIGs. 22D-22F illustrate the counterpart write cache operations.

[0074] FIGs. 23A - 23F illustrate cache operations associated with the system configuration of 151, where both of the memory modules 1502 and 1504 are directly coupled to the memory controller 1508, and the tag comparison circuitry 1514 is disposed on the SCM memory module 1504. A read hit operation involves reading the DRAM module 1502 directly, providing the tag information to the tag comparison circuit 1514 via the back channel link 1520, and providing the data directly to the memory controller 1508, as shown in FIG. 23A. For a read miss clean, shown in FIG. 23B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502 (via the back channel link 1520), and sending the read data directly from the SCM module 1504 to the memory controller 1508. For a read miss dirty, shown in FIG. 23C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 2302, and writing it to the SCM module 1504, at 2304. FIGs. 23D-23F illustrate the counterpart write cache operations.

[0075] FIGs. 24A - 24F illustrate cache operations associated with the system configuration of 151, where the tag comparison circuitry is disposed on the DRAM memory module 1502. A read hit operation involves reading the DRAM module 1502 directly, comparing the tag information with the tag comparison circuitry 1514 and providing the data directly to the memory controller 1508, as shown in FIG. 24A. For a read miss clean, shown in FIG. 24B, an additional step is carried out that involves reading the tag information and data from the SCM module 1504 as a write operation to the DRAM module 1502 via the back channel link 1520, and sending the read data directly from the SCM module 1504 to the memory controller 1508. For a read miss dirty, shown in FIG. 24C, the first cache operation is augmented by reading the tag and address information from the DRAM module 1502, at 2402, and writing it to the SCM module 1504, at 2404. FIGs. 24D-24F illustrate the counterpart write cache operations.

[0076] FIG. 25 illustrates a chart that compares various performance characteristics between the various system configurations described above with respect to FIGs. 15A-15I. The comparison provides a continuous bandwidth summary in comparison to a baseline (such as a fraction of, for example, 25.4 GB/s or 36b at 6.4 Gb/s, with alternate accesses to odd and even nibbles. The first column notes the particular module configuration nomenclature (corresponding to the notation at the bottom portion of the chart), while the top row lists the cache operation involved, such as a read hit "RH", read miss clean "RMC", read miss dirty "RMD", write hit "WH", write hit clean "WHC" and write hit dirty "WHD."

[0077] FIG. 26 illustrates a chart that compares various power characteristics between the various system configurations described above with respect to FIGs. 15A-15I. The configuration and cache operation nomenclature of the first column and first row corresponds to that of FIG. 25.

[0078] FIG. 27 illustrates further detail of the memory system of FIG. 15 A, similar to FIG. 9, with special emphasis on the buffer circuitry for the DRAM and the SCM modules. To reiterate, this particular embodiment employs a point-to-point connection between a memory controller 2702, at least one DRAM module 2704, an SCM memory module 2706, with tag compare circuitry 2708 being disposed on the memory controller 2702. Data transfers between the memory controller 2702 and the SCM module 2706 are passed through the DRAM module 2704 via the backchannel connection DQu' and CS/CAx' between the DRAM module 2704 and SCM module 2706. The memory controller 2702 includes respective read and write data queues 2710 and 2712 coupled to data nibble DQu, which serves as a primary data link for coupling to a DRAM module data buffer component DBD. The controller 2702 further includes respective read and write address queues 2714 and 2716 that are selectively coupled, via a multiplexer 2718, to CA link CS/CAx, which serves as a primary CA link for coupling the controller 2702 to the DRAM module CA buffer RCDD. Since the tag comparison circuitry 2708 resides on the memory controller 2702 for this embodiment, no status circuitry or link is employed by the memory modules 2704 and 2706. The tag comparison circuitry 2708 receives old tag information read from the DRAM module 2704, and new tag information provided with new request information as part of a new memory operation.

[0079] Further referring to FIG. 27, the each buffer component DBD on the DRAM module 2704 employs steering logic described above with respect to FIG. 3, such that the primary data interface I/O circuits coupled to links DQu and DQu' (the backchannel link) may be selectively coupled to either of the secondary data I/O circuits DQus (respective even and odd cache DRAM nibbles) via multiplexers 2720, 2722, and 2724 appropriately placed in the data transfer paths of the steering logic.

[0080] With continued reference to FIG. 27, the SCM data buffer DBs is configured similar to the DRAM module counterpart, but includes an SCM write data buffer circuit 2726 that buffers write data to SCM memory components 2728 and 2730. In a similar manner, the SCM module CA buffer RCDs includes an SCM write address buffer circuit 2732 that provides buffered write addresses to the SCM memory components 2728 and 2730. Since the connections between the memory controller 2702 and the memory modules 2704 and 2706 are made through the DRAM module 2704, the steering logic for the data buffers DB_D and DBs generally provides steering capability between one primary data circuit (the backchannel link DQu'), to either of the secondary data I/O circuits DQus and DQu's. However, to control the backchannel link DQu', bypass compare logic may be employed.

[0081] FIG. 28 illustrates a memory system configuration, with special emphasis on the buffer component circuitry, similar to FIG. 27, with tag comparison circuitry 2802 resident on an SCM module CA buffer component RCDs, rather than in a memory controller 2804. With the tag comparison circuitry 2802 residing on the SCM CA buffer RCDs, a status link STx couples the SCM CA buffer RCDs to the memory controller 2804 to provide the cache status information. Most of the remaining system construction is similar to the system of FIG. 27.

[0082] FIG. 29 illustrates a memory system configuration similar to that shown in FIG. 9, without optional data delay circuitry in the DRAM data buffer DB_D, nor optional address delay circuitry in the DRAM CA buffer component RCD_D. This particular embodiment employs a point-to-point connection between a memory controller 2902 and at least one DRAM module 2904, and also incorporates tag compare circuitry 2906 on the DRAM module. Data transfers between the memory controller 2902 and an SCM module 2908 are passed through the DRAM module 2904 via a back channel connection DQu' between the DRAM module 2904 and the SCM module 2908. The memory controller 2902 includes respective read and write data queues 2910 and 2912 coupled to data nibble DQu, which serves as a primary data link for coupling to a DRAM module data buffer component DBD. The memory controller 2902 further includes respective read and write address queues 2914 and 2916 that are selectively coupled, via a multiplexer 2918, to CA link CS/CAx, which serves as a primary CA link for coupling the memory controller 2902 to a DRAM module CA buffer RCDD. Status circuitry "STATUS" 2920 interfaces with the DRAM CA buffer component RCD_D via a status link STx, which provides information concerning tag compare operations, as described below.

[0083] Further referring to FIG. 29, the each buffer component DBD on the DRAM module 2904 employs steering logic described above with respect to FIG. 3, such that the primary data interface I/O circuits coupled to links DQu and DQu' (the backchannel link) may be selectively coupled to either of the secondary data I/O circuits DQus (respective even and odd cache DRAM nibbles) via multiplexer circuitry appropriately placed in the data transfer paths of the steering logic.

[0084] With continued reference to FIG. 29, the DRAM CA buffer RCD_D includes a DRAM write address buffer circuit 2924 that provides buffered write addresses to DRAM memory components 2926. The tag compare circuit 2906 also resides on the CA buffer component RCD_D, which receives new tag information for a requested address with old tag information provided by the DRAM data buffer via a tag communication path TAGOLD . The results of the tag comparison are then fed back to the memory controller 2902 via the status link STx, so that the controller can dispatch any commands necessary for additional cache operations associated with "miss" cases. CA information passed to the DRAM module 2904 via the CA link CS/CAx link is redriven by the DRAM module to the SCM module 2908 via a CA backchannel link CS/CAx'.

[0085] The SCM memory module data buffer components DBs and CA buffer component RCDs are configured similar to their DRAM module counterparts. However, since the connections between the memory controller 2902 and the memory modules 2904 and 2908 are made through the DRAM module 2904, the steering logic for the data buffers DB_D and DBs generally provides steering capability between one primary data circuit (the back channel link), to either of the secondary data I/O circuits.

[0086] FIG. 30 illustrates the memory system configuration of FIG. 29, highlighted to show the various signal paths operative during cache operations involving a read hit. As shown, a first read operation takes place where a read command is dispatched, at 3002, along primary DRAM CA path CS/CAx to the DRAM CA buffer component RCDD. The command propagates to the secondary CA path CS/CAxs, and is fed to a first rank (rank 0) of the DRAM cache memory, at 3004. The old cacheline data and tag information is accessed, read out and transferred first along the secondary data path DQus, to the data buffer component DBD, and steered by the buffer steering logic to the primary data interface path DQu. Concurrently, for one embodiment, the old cacheline tag information TAGOLD is passed from the data buffer DB_D along, for example, an extension to a BCOM bus, at 3006, that interconnects all of the data buffers DBD on the DRAM module with the CA buffer component RCDD. The tag compare logic, at 3008, on the CA buffer receives the old tag information via the BCOM bus, and new tag information received from the primary CA path CS/CAx when the original DRAM read command was received. The output of the tag comparison is then driven along the status line STx to the memory controller, at 3010. For some embodiments, the BCOM bus may be further extended to allow for the propagation of tag compare information or partial tag status information. The memory controller then uses the received tag status to determine whether or not the data read from the DRAM cache is the current data for the requested address (a read hit case).

[0087] FIG. 31 illustrates the memory system of FIG. 30, including the highlighting relating to a read hit condition, but also includes highlighted signaling paths involved in cache operations where the status of the tag compare results in a read miss clean case. The operations involved in reading the DRAM cache, and comparing the tag information are still the same as described above with respect to FIG. 30, but additional cache operations are carried out regarding the SCM module. To provide the controller with the correct data, the SCM memory module is read by dispatching a read command along the primary CA link CS/CAx, and directing the command through the DRAM CA buffer RCDD, along the backchannel connection CS/CAx', to the SCM CA buffer RCDs, at 3102. The command is then fed along the secondary CA link CS/CAx' s, at 3104, to a first rank (rank 0) of the SCM memory, at 3106. New cacheline data and tag information is then accessed from the SCM memory, passed along secondary data link DQu's, at 3108, and through an SCM data buffer component DBs. The new data and tag information is then transferred along the backchannel link DQu', at 3110, and received at the DRAM data buffer component DBD. The data is then steered by the buffer steering logic to both the memory controller, via primary data path DQu, at 3112, and the DRAM write buffer, at 3114. The buffer contents may then be written to DRAM cache at an appropriate timing interval.

[0088] Referring now to FIG. 32, for a read miss dirty case, the cache operations are similar to those described above, with the addition of loading the old data and old tag information to the SCM write buffers, at 3202 and 3204. The information may then be written to the SCM memory at an appropriate time interval.

[0089] FIGs. 33-35 illustrate cacheline operations similar to those described above in FIGs. 30-32, but for write operations rather than read operations.

[0090] FIG. 36 illustrates a cacheline operation involving retiring a cacheline in the write buffer. The retire operations will typically be initiated by a bit field in a read or write column command, possibly with a static delay. Generally, the operations involve transferring old data and tag information from SCM write buffers (data and address), at 3602 and 3604, to the SCM memory, at 3606. The new data and tag information is transferred from the DRAM write buffers (data and address), at 3608 and 3610, to the DRAM memory, at 3612.

[0091] FIGs. 37-42 illustrate various timing charts relating to various cacheline operations consistent with the operations described above. FIG. 37 illustrates various operations and relative timing parameters associated with one embodiment of a cache read miss dirty sequence. FIG. 38 illustrates various operations and relative timing parameters associated with one embodiment of a cache write miss dirty sequence. FIG. 39 illustrates various timing parameters associated with a retire operation involving retiring one cache entry from each of three write buffers. FIG. 40 illustrates the minimum latency associated with read miss dirty cache operations. FIG. 41 illustrates a constant latency for read hit miss and dirty operations. FIG. 42 illustrates timing associated with back-to-back-to-back read miss dirty, write miss dirty, and read miss dirty sequences.

[0092] FIG. 43 illustrates a high-level embodiment of a dual-module memory system, similar to embodiments described above, where a first portion of a DRAM memory module 4302 is utilized as cache memory, at 4304, while a second portion of the DRAM memory is uncached, at 4306. This system is similar to the SU4 system shown in FIG.15D and FIG. 19.

[0093] FIG. 44 illustrates further detail of the circuitry employed by respective data buffers and CA buffers on the DRAM and SCM modules of the memory system shown in FIG. 43, and associated cache operations for read operations. [0094] FIG. 45 illustrates further detail of the circuitry employed by respective data buffers and CA buffers on the DRAM and SCM modules of the memory system shown in FIG. 43, similar to FIG. 44 and associated cache operations for write operations.

[0095] FIGs. 46 and 47 illustrate timing diagrams with operations associated with cache read hit and miss conditions, for the system shown in FIG. 43.

[0096] FIG. 48 illustrates a timing diagram with operations associated with uncached DRAM and SCM memory read operations for the system of FIG. 43.

[0097] FIG. 49 illustrates a timing diagram with operations associated with both cached and uncached DRAM and SCM memory write operations for the system of FIG. 43.

[0098] FIG. 50 illustrates further detail regarding DRAM package structure and various interconnections between the DRAM package and the data and CA buffer circuitry.

[0099] FIG. 51 illustrates a further system embodiment that employs a first DRAM memory module 5102, and a second memory module 5104 including both DRAM and SCM memory components 5106 and 5108. Similar to various other memory system configurations described herein, the memory modules 5102 and 5104 connect to a memory controller 5110 via point-to- point links, and connect to each other via a backchannel link DQt to provide for cache transfers between modules. This shows the FC2 system, first described in FIG. 2E.

[00100] FIG. 52 illustrates a further high-level system embodiment similar to that shown in FIG. 43. This figure is applicable to all the previously discussed systems which employ DRAM and SCM memory regions. In this example there is one DRAM module 5202 and one SCM module 5204. Each module can be used by a memory controller 5206 with both a cached region such as at 5208 and 5210, and an uncached region, such as at 5212 and 5214. The region size can be set by a control register (not shown) at initialization. Accesses to the uncached region may generally involve an access to a single memory type. Accesses to the cached region of the SCM memory may generally involve accesses to the cached DRAM region, as described in the previous examples.

[00101] When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[00102] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice- versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be "activated" when a signal is asserted on the signal line, and "deactivated" when the signal is deasserted.

Additionally, the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., '

< signal name > ') is also used to indicate an active low signal. The term "coupled" is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device "programming" may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term "exemplary" is used to express an example, not a preference or requirement.

[00103] While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS We Claim:

1. A memory module comprising:

interface for coupling to a bus, the bus having a first width;

storage class memory space including at least one storage class memory (SCM) component;

dynamic random access memory space including at least one DRAM component; and

wherein the memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

2. The memory module of claim 1, wherein a region of the DRAM memory space is operated as a cached region of the SCM memory space.

3. The memory module of claim 2, wherein:

the DRAM memory space includes a second region that is operable as directly accessed memory; and

the SCM memory includes a second region that is operable as directly accessed memory.

4. The memory module of claim 1, further comprising:

buffer circuitry to buffer operations between the at least one SCM component and a memory controller, the buffer circuitry including a primary interface and a secondary interface coupled to the at least one SCM component.

5. The memory module of claim 4, wherein the buffer circuitry includes steering logic to route data between any one of multiple paths coupled to the primary interface and any one of multiple paths coupled to the secondary interface.

6. The memory module of claim 5, wherein the steering logic further comprises bypass circuitry to route data between any one of the multiple paths coupled to the primary interface to any other of the multiple paths coupled to the primary interface.

7. The memory module of claim 6, wherein the bypass circuitry is further operable to pass a transaction through the memory module between a first half-width port for coupling to the primary interface, and a second memory module.

8. The memory module of claim 4, wherein the buffer circuitry further comprises:

tag comparison circuitry to compare an incoming tag address to a stored tag address associated with the DRAM cache.

9. The memory module of claim 8, further comprising:

a match link distributed along the memory module, the match link to communicate a match signal to each of the buffer circuits.

10. A memory system including:

a memory controller;

a first memory module coupled to the memory controller, the first memory module including multiple dynamic random access memory (DRAM) components that define a DRAM memory space;

a second memory module coupled to the memory controller and including multiple storage class memory (SCM) components that define an SCM memory space;

wherein each module is operable to perform independent half-data width memory transactions; and

wherein a region of the DRAM memory space is operated as a cached region of the SCM memory space.

11. The memory system of claim 10, wherein the first memory module is configurable to perform full-width memory transactions.

12. The memory system of claim 10, wherein the DRAM memory space includes multiple cachelines, and wherein:

each cacheline includes an address tag indicating its backing location in the SCM memory space.

13. The memory system of claim 12, wherein:

each cacheline includes an error code field covering the address tag and data associated with the cacheline.

14. The memory system of claim 13, wherein the error code field comprises parity information.

15. The memory system of claim 13, wherein the error code field corrects the entire cacheline when a tag error is detected.

16. The memory system of claim 12, wherein the address tag includes a dirty field indicating a cache miss dirty status.

17. The memory system of claim 12, wherein the address tag includes a valid field.

18. The memory system of claim 10, further comprising tag comparison circuitry.

1 . The memory system of claim 18, wherein the tag comparison circuitry resides in the memory controller.

20. The memory system of claim 18, wherein the tag comparison circuitry resides in the DRAM memory module.

21. The memory system of claim 18, wherein the tag comparison circuitry resides in the SCM memory module.

22. The memory system of claim 18, further comprising buffer circuitry disposed on each of the DRAM and SCM memory modules, and wherein the tag comparison circuitry resides in the buffer circuitry.

23. The memory system of claim 10, wherein the first memory module is coupled to the second memory module via a back channel link, and wherein cacheline operations between the first module and the second module are carried out via the back channel link.

24. A method of operation in a memory system including a first memory module having a first memory space, and a second memory module having a second memory space, wherein a portion of the second memory space serves as a cache for the first memory space, the method comprising:

initiating a first memory transaction involving the first memory module;

performing cacheline operations between the first memory module and the second memory module via a back channel link connected between the first memory module and the second memory module.