CN110097919A - Storage system, the method for determining its mistake and the electronic equipment including it - Google Patents

Abstract

It provides a kind of storage system, determine the method for its mistake and the electronic equipment including it.Storage system includes: storage device, including buffer die, the core bare die being arranged on buffer die, multiple channels and wears silicon access, wears silicon access and is configured as sending signal between buffer die and at least one core bare die；Storage control is configured as to the storage device output command signal and address signal, receives data-signal to storage device outputting data signals, and from storage device；And plug-in part, including multiple channel paths for connecting storage control and multiple channels, wherein the storage device further includes for changing the path selector of the connection status between multiple channels and multiple channel paths, when detecting mistake under the first connection status between multiple channels and multiple channel paths, the first connection status is changed into the second connection status by path selector.

Description

Storage system, the method for determining its mistake and the electronic equipment including it

Cross reference to related applications

This application claims the South Korea patent applications submitted on January 31st, 2018 at Korean Intellectual Property Office (KIPO) The priority of No.10-2018-0012200, the entire disclosure are incorporated herein by reference.

Technical field

The exemplary embodiment of present inventive concept be related to storage system, determine storage system mistake method and including The electronic equipment of the storage system.

Background technique

In general, high bandwidth memory (HBM) includes multi-channel memory and connecting multi-channel memory and storage control Channel path.

When include multi-channel memory storage system in when the error occurs, it may be difficult to determine occur mistake position It sets.For example, mistake is likely to occur within the storage system or in the channel path of connecting multi-channel memory and storage control.

In addition, when in order to detect mistake and by storage system switching (transmit) to it is independent mistake determine system rather than When true workload system, mistake does not reproduce, it is thus possible to can not determine the position of mistake.

Summary of the invention

In the exemplary embodiment for the storage system conceived according to the present invention, the storage system includes: storage device, The storage device includes buffer die, the multiple cores bare die being arranged on the buffer die, multiple channels and wears Silicon access, described at least one core wearing silicon access and being configured as in the buffer die and the multiple core bare die Signal is sent between bare die；Storage control, the storage control are configured as to the storage device output command signal And address signal, Xiang Suoshu storage device outputting data signals, and data-signal is received from the storage device；And interpolation Part, the plug-in part include multiple channel paths for connecting the storage control and the multiple channel, wherein described Storage device further includes for changing the Path selection of the connection status between the multiple channel and the multiple channel path Device, wherein when detecting the storage under the first connection status between the multiple channel and the multiple channel path When the mistake of system, the path selector connects described first between the multiple channel and the multiple channel path State changes into the second connection status.

In the method that the determination conceived according to the present invention includes the mistake of the storage system of storage device and storage control Exemplary embodiment in, which comprises storage device multiple channels and the storage system multiple passways The mistake of the storage system is detected under the first connection status between diameter, the multiple channel path connects the multiple channel It is connected to the storage control, the storage device includes buffer die, multiple cores for being arranged on the buffer die Heart bare die and wear silicon access, it is described wear at least one core bare die that silicon access is configured as in the multiple core bare die with Signal is sent between the buffer die；When detecting the mistake of the storage system, by the multiple channel with it is described Connection status between multiple channel paths changes into the second connection status from first connection status；And described second The mistake of the storage system is detected under connection status.

In the exemplary embodiment for the electronic equipment conceived according to the present invention, the electronic equipment includes application processing Device；Storage system, the storage system are configured as being operated by the application processor.Wherein the storage system includes: Storage device, the storage device includes buffer die, the multiple cores bare die being arranged on the buffer die, multiple Channel and silicon access is worn, it is described to wear at least one core bare die and institute that silicon access is configured as in the multiple core bare die It states and sends signal between buffer die；Storage control, the storage control are configured as exporting to the storage device Command signal and address signal, Xiang Suoshu storage device outputting data signals, and data-signal is received from the storage device； And plug-in part, the plug-in part include multiple channel paths for connecting the storage control and the multiple channel, Wherein, the storage device further includes for changing the connection status between the multiple channel and the multiple channel path Path selector, wherein when detecting institute under the first connection status between the multiple channel and the multiple channel path When stating the mistake of storage system, the path selector is by described between the multiple channel and the multiple channel path One connection status changes into the second connection status.

Detailed description of the invention

By reference to the attached drawing exemplary embodiment that present inventive concept is described in detail, the above and other of present inventive concept is special Sign will be apparent, in which:

Fig. 1 is to show the block diagram of the storage system for the exemplary embodiment conceived according to the present invention；

Fig. 2 is to show the diagram of the storage system of Fig. 1 for the exemplary embodiment conceived according to the present invention；

Fig. 3 is to show the diagram of the storage device of Fig. 2 for the exemplary embodiment conceived according to the present invention；

Fig. 4 is to show the core bare die of the storage device of Fig. 2 of the exemplary embodiment conceived according to the present invention to show Figure；

Fig. 5 is to show the block diagram of the core bare die of the Fig. 2 for the exemplary embodiment conceived according to the present invention；

Fig. 6 A is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of first connection status of diameter selector；

Fig. 6 B is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of second connection status of diameter selector；

Fig. 7 A is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of first connection status of diameter selector；

Fig. 7 B is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of second connection status of diameter selector；

Fig. 8 A is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of first connection status of diameter selector；

Fig. 8 B is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of second connection status of diameter selector；

Fig. 9 A is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of first connection status of diameter selector；

Fig. 9 B is to show the road of the exemplary embodiment conceived according to the present invention being arranged on the buffer die of Fig. 2 The diagram of second connection status of diameter selector；

Figure 10 A is to show being arranged on the buffer die of Fig. 2 of the exemplary embodiment conceived according to the present invention The diagram of first connection status of path selector；

Figure 10 B is to show being arranged on the buffer die of Fig. 2 of the exemplary embodiment conceived according to the present invention The diagram of second connection status of path selector；

Figure 11 is to show the diagram of the storage system for the exemplary embodiment conceived according to the present invention；

Figure 12 A is to show being arranged on the buffer die of Figure 11 of the exemplary embodiment conceived according to the present invention The diagram of first connection status of path selector；

Figure 12 B is to show being arranged on the buffer die of Figure 11 of the exemplary embodiment conceived according to the present invention The diagram of second connection status of path selector；

Figure 12 C is to show being arranged on the buffer die of Figure 11 of the exemplary embodiment conceived according to the present invention The diagram of the third connection status of path selector；And

Figure 13 is to show the frame of the electronic equipment including storage system for the exemplary embodiment conceived according to the present invention Figure.

Specific embodiment

The exemplary embodiment of present inventive concept is described more fully with below with reference to attached drawing.However, present inventive concept can To be embodied in many different forms, and it should not be construed as being limited to embodiments described herein.Through the application, phase Same appended drawing reference may refer to identical element.

Fig. 1 is to show the block diagram of the storage system 1000 for the exemplary embodiment conceived according to the present invention.Fig. 2 is to show The diagram of the storage system 1000 of the Fig. 1 for the exemplary embodiment conceived according to the present invention.

Referring to Figures 1 and 2, storage system 1000 includes storage control 1100 and storage device 1200.Storage system 1000 can also include the plug-in part 1300 being arranged between storage control 1100 and storage device 1200.Storage control 1100 and storage device 1200 can for example be arranged on plug-in part 1300.For example, plug-in part 1300 can be silicon plug-in part.Example Such as, storage control 1100 and storage device 1200 can be set in the same plane.Storage system 1000 can also include envelope Fill substrate 1400.Plug-in part 1300 can be set on package substrate 1400.

First convex block BP1 can be set between plug-in part 1300 and storage control 1100.Second convex block BP2 can be set It sets between plug-in part 1300 and storage device 1200.Third convex block BP3 can be set in package substrate 1400 and plug-in part Between 1300.The size of third convex block BP3 can be greater than the size of the first convex block BP1 and each convex block in the second convex block BP2.

Storage device 1200 may include buffer die BD and at least one core for being arranged on buffer die BD Bare die (for example, CD1, CD2, CD3 and CD4).

Buffer die BD may include multiple buffers.Buffer be connected to channel path CP1, CP2, CP3, CP4, CP5, CP6, CP7, CP8, CP9, CP10, CP11, CP12, CP13, CP14, CP15 and CP16, and channel path CP1 will be passed through To CP16 send data-signal DQ be output to channel C H1, CH2, CH3, CH4, CH5, CH6, CH7, CH8, CH9, CH10, CH11, CH12, CH13, CH14, CH15 and CH16.

Storage device 1200 may include channel C H1 to CH16.For example, the first core being arranged on buffer die BD Bare die CD1 may include first passage CH1 to fourth lane CH4.For example, the second core on the first core bare die CD1 is arranged in Heart bare die CD2 may include Five-channel CH5 to the 8th channel C H8.For example, the third on the second core bare die CD2 is arranged in Core bare die CD3 may include the 9th channel C H9 to the 12nd channel CH12.For example, being arranged on third core bare die CD3 4th core bare die CD4 may include the tenth triple channel CH13 to the 16th channel C H16.For example, storage device 1200 can be Dynamic random access memory (DRAM) equipment.

It can be by wearing silicon access (through silicon via) in buffer die BD and core bare die CD1 to CD4 Between send signal.

Plug-in part 1300 may include connecting the channel C H1 to CH16 of storage device 1200 and leading to for storage control 1100 Path CP1 to CP16.The channel C H1 to CH16 of storage device 1200 can be connected to CP16 by channel path CP1 and be deposited Store up controller 1100.Although for clarity, Fig. 2 illustrates only two channel paths CP1 and CP2, it should be understood that rest channels Path CP3 to CP16 is connected in a similar fashion to the first convex block BP1 of storage control 1100.Plug-in part 1300 can also wrap Include the channel C H1 to CH16 of connection storage device 1200 and at least one reparation channel path RP of storage control 1100.When Channel path CP1 at a channel path into CP16 when the error occurs, storage control 1100 can be logical by repairing Path RP is communicated with the channel C H1 to CH16 of storage device 1200.

Storage control 1100 can be defeated by command signal CMD and address signal ADDR by channel path CP1 to CP16 Storage device 1200 is arrived out.Data-signal DQ can be output to by channel path CP1 to CP16 and be deposited by storage control 1100 Storage device 1200, and data-signal DQ is received from storage device 1200 by channel path CP1 to CP16.

Fig. 3 is to show the diagram of the storage device 1200 of the Fig. 2 for the exemplary embodiment conceived according to the present invention.

Referring to figs. 1 to Fig. 3, buffer die BD and core bare die CD1 to CD4 can be stacked.Buffer die BD and core Heart bare die CD1 to CD4 can be connected to each other by wearing silicon access.

It wears silicon access and is electrically connected to the internal circuit of core bare die CD1 to CD4 and the internal circuit of buffer die BD.Example Such as, wearing being electrically connected between silicon access and the internal circuit of core bare die CD1 to CD4 and the internal circuit of buffer die BD can By selectively cutting off electric fuse or selectively off and on switching circuit being formed in response to controlling signal.

Second core bare die CD2 can be arranged directly on the first core bare die CD1.Third core bare die CD3 can be straight It connects and is arranged on the second core bare die CD2.4th core bare die CD4 can be arranged directly on third core bare die CD3.Example Such as, it may be electrically connected to the inside of the first core bare die CD1 for sending the silicon access of wearing of the first common chip selection signal CS1 The internal circuit of circuit and third core bare die CD3.Silicon access of wearing for sending the second common chip selection signal CS2 can be with It is electrically connected to the internal circuit of the second core bare die CD2 and the internal circuit of the 4th core bare die CD4.For sending command address The silicon access of wearing of signal CA may be electrically connected to each core bare die of the first core bare die CD1 into the 4th core bare die CD4 Internal circuit.Silicon access of wearing for sending data-signal DQ may be electrically connected to the first core bare die CD1 to the 4th core The internal circuit of each core bare die in bare die CD4.

Fig. 4 is to show the core bare die of the storage device 1200 of the Fig. 2 for the exemplary embodiment conceived according to the present invention The diagram of CD1 to CD4.

Referring to figs. 1 to Fig. 4, storage device 1200 may include multiple cores bare die or core layer CD1 to CDK.Here, K It is equal to or greater than 2 positive integer.

Core bare die CD1 to CDK (also referred to as the first core bare die to K core bare die) is sent by wearing silicon access TSV Signal.It is arranged and multiple wears silicon access TSV.First core bare die CD1 can pass through buffer die BD and storage control 1100 Communication.

First core bare die CD1 to K core bare die CDK is respectively included for driving memory cell array region (or to deposit Storage area domain) 1210 peripheral circuit 1220.For example, peripheral circuit 1220 may include: driving memory cell array region 1210 Wordline line driver (for example, X- driver)；Drive the row driver (example of the bit line in memory cell array region 1210 Such as, Y driver)；The data of control data-signal output and input output and input part；For receiving command signal CMD With the commands buffer for buffer command signals CMD；And for receiving address signal ADDR and for buffer address signals The address buffer of ADDR.Can external from the first core bare die CD1 to K core bare die CDK receive command signal CMD and Address signal ADDR.

First core bare die CD1 can also include control logic circuit.Control logic circuit is based on command signal CMD and ground Location signal ADDR controls the access to storage region 1210, and generates the control signal to access storage areas domain 1210.Alternatively, Control logic circuit can be set on buffer die BD.

Fig. 5 is to show the block diagram of the core bare die CD1 of the Fig. 2 for the exemplary embodiment conceived according to the present invention.

Referring to figs. 1 to Fig. 5, core bare die CD1 includes control logic circuit 210, refresh control circuit 215, address deposit Device 220, memory bank (memory bank) control logic circuit 230, row address multiplexer (RA MUX) 240, column address lock Storage 250, line decoder are (for example, 260a to 260d), column decoder are (for example, 270a to 270d), memory cell array (example Such as, 280a to 280d), sense amplifier unit are (for example, 285a to 285d), 290 sum number of input/output (I/O) gating circuit According to I/O buffer 295.

Memory cell array (for example, 280a to 280d) may include multiple bank arrays, for example, the first memory bank battle array Arrange 280a, the second bank array 280b, third bank array 280c and the 4th bank array 280d.Line decoder can To include multiple memory bank line decoders, for example, being connected respectively to the first bank array 280a, the second bank array The first memory bank line decoder 260a of 280b, third bank array 280c and the 4th bank array 280d, the second storage Body line decoder 260b, third memory bank line decoder 260c and the 4th memory bank line decoder 260d.Column decoder can wrap Multiple memory bank column decoders are included, for example, being connected respectively to the first bank array 280a, the second bank array 280b, The first memory bank column decoder 270a, the second memory bank column decoding of three bank array 280c and the 4th bank array 280d Device 270b, third memory bank column decoder 270c and the 4th memory bank column decoder 270d.Sense amplifier unit may include Multiple memory bank sense amplifiers, for example, being connected respectively to the first bank array 280a, the second bank array 280b, The first memory bank sense amplifier 285a, the second memory bank of three bank array 280c and the 4th bank array 280d is read Amplifier 285b, third memory bank sense amplifier 285c and the 4th memory bank sense amplifier 285d.First bank array 280a to the 4th bank array 280d, the first memory bank line decoder 260a are to the 4th memory bank line decoder 260d, first Memory bank column decoder 270a to the 4th memory bank column decoder 270d and the first memory bank sense amplifier 285a to the 4th Memory bank sense amplifier 285d can be respectively formed the first memory bank, the second memory bank, third memory bank and the 4th memory bank. For example, the first bank array 280a, the first memory bank line decoder 260a, the first memory bank column decoder 270a and first are deposited Storage body sense amplifier 285a can form the first memory bank；Second bank array 280b, the second memory bank line decoder 260b, the second memory bank column decoder 270b and the second memory bank sense amplifier 285b can form the second memory bank；Third Bank array 280c, third memory bank line decoder 260c, third memory bank column decoder 270c and third memory bank are read Amplifier 285c can form third memory bank；4th bank array 280d, the 4th memory bank line decoder 260d, the 4th deposit Storage body column decoder 270d and the 4th memory bank sense amplifier 285d can form the 4th memory bank.Although Fig. 5 shows packet The core bare die CD1 of four memory banks is included, but core bare die CD1 may include any number of memory bank.For example, core is naked Piece CD1 may include less than four memory banks or more than four memory banks.

It includes storage that address register 220 can be received from storage control (for example, storage control 1100 in Fig. 1) The address AD DR of body address BANK_ADDR, row address ROW_ADDR and column address COL_ADDR.Address register 220 can incite somebody to action The bank-address BANK_ADDR received is supplied to memory bank control logic circuit 230, the row address that can will be received ROW_ADDR is supplied to row address multiplexer 240, the column address COL_ADDR received can be supplied to column address latch 250。

Memory bank control logic circuit 230 can generate memory bank in response to receiving bank-address BANK_ADDR Control signal.Signal is controlled in response to the memory bank generated by memory bank control logic circuit 230, the first memory bank can be activated Line decoder 260a is corresponding with the bank-address BANK_ADDR received into the 4th memory bank line decoder 260d to be deposited Store up body line decoder.In addition, controlling signal in response to the memory bank generated by memory bank control logic circuit 230, can activate First memory bank column decoder 270a into the 4th memory bank column decoder 270d with the bank-address BANK_ADDR that receives Corresponding memory bank column decoder.

Refresh control circuit 215 can generate refresh address REF_ADDR in response to receiving refresh command.For example, Refresh control circuit 215 may include refresh counter, the refresh counter be configured as according to memory cell array (for example, First address of 280a to 280d) is to memory cell array (for example, the last one address of 280a to 280d), comes sequentially Change refresh address REF_ADDR.

Row address multiplexer 240 can receive row address ROW_ADDR from address register 220, and can be from brush New control circuit 215 receives refresh address REF_ADDR.Export row address to 240 property of can choose of row address multiplexer ROW_ADDR or refresh address REF_ADDR.The row address exported from row address multiplexer 240 is (for example, row address ROW_ ADDR or refresh address REF_ADDR) the first memory bank line decoder 260a to the 4th memory bank line decoder can be applied to 260d。

Activated memory bank row of the first memory bank line decoder 260a into the 4th memory bank line decoder 260d is translated Code device can decode the row address exported from row address multiplexer 240, and can activate and the row address pair The wordline answered.For example, word line driving voltage can be applied to and row ground by activated memory bank line decoder (such as 260a) The corresponding wordline in location.

Column address latch 250 can receive column address COL_ADDR from address register 220, and can temporarily store The column address COL_ADDR received.Column address latch 250 can be by column address COL_ that is temporarily storing or receiving ADDR is applied to the first memory bank column decoder 270a to the 4th memory bank column decoder 270d.

Activated memory bank column of the first memory bank column decoder 270a into the 4th memory bank column decoder 270d are translated Code device can decode the column address COL_ADDR exported from column address latch 250, and can control I/O gating electricity Road 290 exports data corresponding with column address COL_ADDR.

I/O gating circuit 290 may include the circuit for gating I/O data.For example, I/O gating circuit 290 can wrap Include input data mask logic, for storing the data exported from the first bank array 280a to the 4th bank array 280d Reading data latches and for writing data into the first bank array 280a writing to the 4th bank array 280d Enter driver.

It to be read out from a bank array of the first bank array 280a into the 4th bank array 280d Data can be sensed by the sense amplifier (for example, 285a) for being couple to a bank array (for example, 280a), and can To be stored in read data latch.The data being stored in read data latch can be via data I/O buffer 295 Storage control 1100 is supplied to data/address bus/data terminal DQ.First can will be written from storage control 1100 to deposit The data of a bank array of the volume array 280a into the 4th bank array 280d are stored up via data/address bus/data terminal DQ is supplied to data I/O buffer 295.Data I/O buffer is supplied to by what data/address bus/data terminal DQ was received 295 data can be written to a bank array (for example, 280a) by write driver.

Control logic circuit 210 can control the operation of core bare die CD1.For example, control logic circuit 210 can be generated Control signal for core bare die CD1 is to execute write operation or read operation.Control logic circuit 210 may include to from The command decoder 211 that the order CMD that storage control 1100 receives is decoded, and the behaviour of setting core bare die CD1 The mode register 212 of operation mode.For example, command decoder 211 can be by write-in enable signal (for example,/WE), row ground Location gating signal (for example,/RAS), column address gating signal (for example,/CAS), chip select signal (for example,/CS) etc. carry out Decoding, to generate control signal corresponding with CMD is ordered.Control logic circuit 210 can also be received in a synchronous manner To operate the clock signal (for example, CLK) and clock enable signal (for example,/CKE) of core bare die CD1.

Fig. 6 A is shown on the buffer die BD that Fig. 2 is arranged in for the exemplary embodiment conceived according to the present invention The diagram of first connection status of path selector.Fig. 6 B is to show the setting for the exemplary embodiment conceived according to the present invention The diagram of second connection status of the path selector on the buffer die BD of Fig. 2.

Referring to figs. 1 to Fig. 6 B, buffer die BD may include multiple buffers.Buffer is connected to channel path CP1 To CP16, and the data-signal DQ sent by channel path CP1 to CP16 is output to channel C H1 to CH16.Buffer is naked Piece BD may include for changing channel C H1 to CH16 and channel path CP1 to the path selector connecting between CP16 MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7 and MUX8.For example, path selector MUX1 to MUX8 can be multichannel Multiplexer.It is defeated that storage control 1100 can will control signal for changing the connection of the state of path selector MUX1 to MUX8 Path selector MUX1 to MUX8 is arrived out.

Path selector MUX1 to MUX8 can be in a normal operation mode by channel C H1 to CH16 and channel path CP1 The first connection status is set as to the connection between CP16.In other words, path selector MUX1 to MUX8 can be in the first behaviour The first connection status is set by channel C H1 to CH16 and channel path CP1 to the connection between CP16 under operation mode.

When occurring the mistake of storage system 1000 in the first connection status, storage control 1100 detects storage system 1000 mistake.

Then, connection control signal is output to path selector MUX1 to MUX8 by storage control 1100, so that channel CH1 to CH16 and channel path CP1 changes into the second connection status to the connection between CP16 from the first connection status.In other words It says, when an error occurs, changes connection status.Storage control 1100 detection channel C H1 to CH16 and channel path CP1 extremely The mistake of storage system 1000 under the second connection status of CP16.

When detecting mistake at identical channel path under the first connection status and the second connection status, storage control Device 1100 processed can determine that the mistake of storage system 1000 is the mistake of channel path.In other words, when in the first connection status With under both states of the second connection status all in the CP1 of first passage path when the error occurs, determine that mistake appears in first In channel path CP1.

When detecting mistake at different channel paths under the first connection status and the second connection status, storage control Device 1100 processed can determine that the mistake of storage system 1000 is the mistake in the channel of storage device 1200.

Referring to Fig. 2, Fig. 6 A and Fig. 6 B, in the present example embodiment, storage device 1200 may include that four cores are naked Piece CD1 to CD4, and each core bare die CD1 to CD4 may include four channels of the channel C H1 into CH16.In addition, In the present exemplary embodiment, each of path selector MUX1 to MUX8 may be coupled to two channels, and path is selected Selecting each of device MUX1 to MUX8 may be coupled to two channels adjacent to each other in same core bare die.Therefore, it deposits Storage device 1200 may include eight path selector MUX1 to MUX8.

Although storage device 1200 includes four core bare dies in the present example embodiment, present inventive concept is unlimited In this.In addition, present inventive concept is not limited to although each core bare die includes four channels in the present example embodiment This.

For example, the first core bare die CD1 includes first passage CH1 and second channel CH2.First path selector MUX1 connects It is connected to first passage CH1 and second channel CH2.Referring to Fig. 6 A, first path selector MUX1 is under the first connection status by One channel C H1 is connected to first passage path CP1, and second channel CH2 is connected to second channel path CP2.Referring to figure First passage CH1 is connected to second channel path CP2 under the second connection status by 6B, first path selector MUX1, and Second channel CH2 is connected to first passage path CP1.

When detected at the first passage path CP1 for being connected to first passage CH1 under the first connection status first mistake Accidentally, and first mistake is detected at the first passage path CP1 for being connected to second channel CH2 under the second connection status When, storage control 1100 can determine mistake present in the CP1 of first passage path.

In other words, when same channel path detects mistake, although the channel path has been switched to not in real time Same channel, also can determine that mistake at channel path (rather than channel).

For example, the mistake of channel path may be by the mistake for the data-signal for being sent to the channel of storage device 1200 and Generate, or the data-signal caused by the crosstalk between adjacency channel path distortion and generate.For example, channel The mistake in path is also likely to be the distortion of the data-signal caused by the bridge joint between adjacency channel path and generates.Example Such as, the mistake of channel path may be the number caused by the mistake of the pin between storage control 1100 and channel path It is believed that number distortion and generate.

It is logical to repair when the reparation channel path RP in plug-in part 1300 when the error occurs, can be used at channel path The mistake of path.

When detected at the first passage path CP1 for being connected to first passage CH1 under the first connection status second mistake Accidentally, and second mistake is detected at the second channel path CP2 for being connected to first passage CH1 under the second connection status When, storage control 1100 can determine mistake present in the channel of storage device 1200.

In other words, it when switching in real time due to channel path and detect mistake at different channel paths, determines wrong Accidentally at channel (rather than channel path).

For example, the mistake in channel may be the read error generated at the storage unit (cell) in channel and/or write-in Mistake.For example, the mistake in channel may be the holding mistake (retention error) generated at the storage unit in channel. For example, the mistake in channel may be that the signal generated at the storage unit in channel sends mistake.

It to form reparation unit in the channel and repair line when the error occurs, can be used at channel and repairs channel Mistake.

For example, the first core bare die CD1 includes third channel CH3 and fourth lane CH4.Second path selector MUX2 connects It is connected to third channel CH3 and fourth lane CH4.As shown in Figure 6A, the second path selector MUX2 will under the first connection status Third channel CH3 is connected to third channel path CP3, and fourth lane CH4 is connected to fourth lane path CP4.Such as figure Shown in 6B, third channel CH3 is connected to fourth lane path CP4 under the second connection status by the second path selector MUX2, And fourth lane CH4 is connected to third channel path CP3.

When detected at the third channel path CP3 for being connected to third channel CH3 under the first connection status first mistake Accidentally, and first mistake is detected at the third channel path CP3 for being connected to fourth lane CH4 under the second connection status When, storage control 1100 can determine mistake present in the CP3 of third channel path.

When detected at the third channel path CP3 for being connected to third channel CH3 under the first connection status second mistake Accidentally, and second mistake is detected at the fourth lane path CP4 for being connected to third channel CH3 under the second connection status When, storage control 1100 can determine mistake present in the channel of storage device 1200.

As shown in Figure 6 A and 6 B, third path selector MUX3 to the 8th path selector MUX8 can with the first via Diameter selector MUX1 and the identical mode of the second path selector MUX2 are operated.

According to the present exemplary embodiment, as the channel C H1 to CH16 and channel path CP1 to CP16 in storage device 1200 The first connection status under when detecting the mistake of storage system 1000, channel C H1 to CH16 and channel path CP1 are to CP16's Connection status becomes the second connection status from the first connection status, and in channel C H1 to CH16 and channel path CP1 to CP16 The second connection status under detect the mistake of storage system 1000 again.Hence, it can be determined that the mistake of storage system is to deposit The mistake in the channel of storage device 1200 or the mistake of channel path.Furthermore it is possible to which determination is deposited in real work load system The mistake of storage system 1000 determines system without storage system 1000 is transferred to independent mistake.

Fig. 7 A is shown on the buffer die BD that Fig. 2 is arranged in for the exemplary embodiment conceived according to the present invention The diagram of the first connection status of path selector MUX1 to MUX8.Fig. 7 B is to show the exemplary reality conceived according to the present invention Apply the diagram of the second connection status of the path selector MUX1 to MUX8 on the buffer die BD that Fig. 2 is set of example.

Referring to figs. 1 to Fig. 5, Fig. 7 A and Fig. 7 B, in the present example embodiment, storage device 1200 may include four cores Heart bare die CD1 to CD4, and each core bare die CD1 to CD4 may include four channels of the channel C H1 into CH16.Separately Outside, in the present example embodiment, each of path selector MUX1 to MUX8 may be coupled to two channels, and road Each of diameter selector MUX1 to MUX8 may be coupled to two channels in different core bare die.Therefore, it stores Device 1200 may include eight path selector MUX1 to MUX8.

For example, the first core bare die CD1 includes first passage CH1, the second core bare die CD2 includes Five-channel CH5.The One path selector MUX1 is connected to first passage CH1 and Five-channel CH5.As shown in Figure 7 A, first path selector MUX1 First passage CH1 is connected to first passage path CP1 under the first connection status, and Five-channel CH5 is connected to Five-channel path CP5.As shown in Figure 7 B, first path selector MUX1 connects first passage CH1 under the second connection status First passage path CP1 is connected to Five-channel path CP5, and by Five-channel CH5.

When detected at the first passage path CP1 for being connected to first passage CH1 under the first connection status first mistake Accidentally, and first mistake is detected at the first passage path CP1 for being connected to Five-channel CH5 under the second connection status When, storage control 1100 can determine mistake present in the CP1 of first passage path.

When detected at the first passage path CP1 for being connected to first passage CH1 under the first connection status second mistake Accidentally, and second mistake is detected at the Five-channel path CP5 for being connected to first passage CH1 under the second connection status When, storage control 1100 can determine mistake present in the channel of storage device 1200.

For example, third core bare die CD3 includes the 9th channel C H9, the 4th core bare die CD4 includes the tenth triple channel CH13.Second path selector MUX2 is connected to the 9th channel C H9 and the tenth triple channel CH13.As shown in Figure 7 A, the second path 9th channel C H9 is connected to the 9th channel path CP9 under the first connection status by selector MUX2, and by the tenth triple channel CH13 is connected to the tenth threeway path CP13.As shown in Figure 7 B, the second path selector MUX2 will under the second connection status 9th channel C H9 is connected to the tenth threeway path CP13, and the tenth triple channel CH13 is connected to the 9th channel path CP9。

When detected at the 9th channel path CP9 for being connected to the 9th channel C H9 under the first connection status first mistake Accidentally, and detected at the 9th channel path CP9 for being connected to the tenth triple channel CH13 under the second connection status this first When mistake, storage control 1100 can determine mistake present in the 9th channel path CP9.

When detected at the 9th channel path CP9 for being connected to the 9th channel C H9 under the first connection status second mistake Accidentally, and detected at the tenth threeway path CP13 for being connected to the 9th channel C H9 under the second connection status this second When mistake, storage control 1100 can determine mistake present in the channel of storage device 1200.

Such as Fig. 7 A and Fig. 7 B, third path selector MUX3 to the 8th path selector MUX8 can be to select with first path It selects device MUX1 and the identical mode of the second path selector MUX2 operates.

According to the present exemplary embodiment, the mistake of storage system 1000 is detected under the first connection status and the second connection status Accidentally, the mistake so as to determining storage system is the mistake in the channel of storage device 1200 or the mistake of channel path.Separately Outside, the mistake that storage system 1000 can be determined in real work load system, without storage system 1000 to be transferred to Independent mistake determines system.

In addition, path selector MUX1 to MUX8 may be coupled to the channel of different core bare die CD1 to CD4, and can To switch connection status, so as to improve the reliability that mistake determines.

Fig. 8 A is shown on the buffer die BD that Fig. 2 is arranged in for the exemplary embodiment conceived according to the present invention The diagram of the first connection status of path selector MUX1 to MUX4.Fig. 8 B is to show the exemplary reality conceived according to the present invention Apply the diagram of the second connection status of the path selector MUX1 to MUX4 on the buffer die BD that Fig. 2 is set of example.

Referring to figs. 1 to Fig. 5, Fig. 8 A and Fig. 8 B, in the present example embodiment, storage device 1200 may include four cores Heart bare die CD1 to CD4, and each core bare die CD1 to CD4 may include four channels of the channel C H1 into CH16.Separately Outside, in the present example embodiment, each of path selector MUX1 to MUX4 may be coupled to four channels, and road Each of diameter selector MUX1 to MUX4 may be coupled to four channels in same core bare die.Therefore, it stores Device 1200 may include four path selector MUX1 to MUX4.

For example, the first core bare die CD1 includes first passage CH1 to fourth lane CH4.First path selector MUX1 connects First passage CH1 is connected to fourth lane CH4.As shown in Figure 8 A, first path selector MUX1 will under the first connection status First passage CH1 is connected to first passage path CP1, and second channel CH2 is connected to second channel path CP2, third is led to Road CH3 is connected to third channel path CP3, and fourth lane CH4 is connected to fourth lane path CP4.As shown in Figure 8 B, First passage CH1 is connected to fourth lane path CP4 under the second connection status by first path selector MUX1, and second is led to Road CH2 is connected to third channel path CP3, and third channel CH3 is connected to second channel path CP2, and by fourth lane CH4 is connected to first passage path CP1.

Using above-mentioned path selector MUX1 to MUX4, determine that the mistake of storage system 1000 is the logical of storage device 1200 The mistake in road or the mistake of channel path.

It should be appreciated that first path selector MUX1 can be formed to be connected with first in order to improve the reliability that mistake determines Connect the state third connection status different with the second connection status.For example, first path selector MUX1 can be connected in third First passage CH1 is connected to second channel path CP2 under state, second channel CH2 is connected to third channel path CP3, Third channel CH3 is connected to fourth lane path CP4, fourth lane CH4 is connected to first passage path CP1.

As shown in Figure 8 A and 8 B, the second path selector MUX2 to the 4th path selector MUX4 can with the first via The identical mode of diameter selector MUX1 is operated.

According to the present exemplary embodiment, the mistake of storage system 1000 is detected under the first connection status and the second connection status Accidentally, permit a determination that the mistake of storage system 1000 is the mistake in the channel of storage device 1200 or the mistake of channel path Accidentally.Furthermore it is possible to the mistake of storage system 1000 be determined in real work load system, without by 1000 turns of storage system It is connected to independent mistake and determines system.

In addition, path selector (for example, MUX1, MUX2, MUX3 or MUX4) can also detect under third connection status The mistake of storage system 1000, so as to improve the reliability that mistake determines.

Fig. 9 A is shown on the buffer die BD that Fig. 2 is arranged in for the exemplary embodiment conceived according to the present invention The diagram of the first connection status of path selector MUX1 and MUX2.Fig. 9 B is to show the exemplary reality conceived according to the present invention Apply the diagram of the second connection status of the path selector MUX1 and MUX2 on the buffer die BD that Fig. 2 is set of example.

Referring to figs. 1 to Fig. 5, Fig. 9 A and Fig. 9 B, in the present example embodiment, storage device 1200 may include four cores Heart bare die CD1 to CD4, and each core bare die CD1 to CD4 may include four channels of the channel C H1 into CH16.Separately Outside, in the present example embodiment, each of path selector MUX1 and MUX2 may be coupled to eight channels, and road Each of diameter selector MUX1 and MUX2 may be coupled to four adjacency channels and adjacent core in same core bare die Four adjacency channels in heart bare die.Therefore, storage device 1200 may include two path selectors MUX1 and MUX2.

For example, the first core bare die CD1 includes first passage CH1 to fourth lane CH4, the second core bare die CD2 includes Five-channel CH5 to the 8th channel C H8.First path selector MUX1 is connected to first passage CH1 to the 8th channel C H8.Such as Shown in Fig. 9 A, first passage CH1 is connected to first passage path under the first connection status by first path selector MUX1 Second channel CH2 is connected to second channel path CP2 by CP1, and third channel CH3 is connected to third channel path CP3, will Fourth lane CH4 is connected to fourth lane path CP4, and Five-channel CH5 is connected to Five-channel path CP5, the 6th is led to Road CH6 is connected to the 6th channel path CP6, and the 7th channel C H7 is connected to the 7th channel path CP7, and by the 8th channel CH8 is connected to the 8th channel path CP8.

As shown in Figure 9 B, first passage CH1 is connected to the 8th under the second connection status by first path selector MUX1 Channel path CP8, is connected to the 7th channel path CP7 for second channel CH2, and third channel CH3 is connected to the 6th passway Diameter CP6, is connected to Five-channel path CP5 for fourth lane CH4, and Five-channel CH5 is connected to fourth lane path CP4, 6th channel C H6 is connected to third channel path CP3, the 7th channel C H7 is connected to second channel path CP2, and will 8th channel C H8 is connected to first passage path CP1.

Using above-mentioned path selector MUX1 and MUX2, it can determine that the mistake of storage system 1000 is storage device 1200 Channel mistake or channel path mistake.

It should be appreciated that first path selector MUX1 can be formed to be connected with first in order to improve the reliability that mistake determines Connect the state third connection status different with the second connection status.

As shown in fig. 9 a and fig. 9b, the second path selector MUX2 can be with side identical with first path selector MUX1 Formula operation.

According to the present exemplary embodiment, the mistake of storage system 1000 is detected under the first connection status and the second connection status Accidentally, the mistake for allowing to determine storage system 1000 is the mistake in the channel of storage device 1200 or the mistake of channel path Accidentally.Furthermore it is possible to the mistake of storage system 1000 be determined in real work load system, without by 1000 turns of storage system It is connected to independent mistake and determines system.

In addition, path selector (for example, MUX1 or MUX2) can also detect storage system under third connection status 1000 mistake, so as to improve the reliability that mistake determines.

In addition, path selector (for example, MUX1 and MUX2) may be coupled to the channel of different core bare die and can be with Switch connection status, so as to improve the reliability that mistake determines.

Figure 10 A is shown on the buffer die BD that Fig. 2 is arranged in for the exemplary embodiment conceived according to the present invention Path selector MUX1 the first connection status diagram.Figure 10 B is to show the exemplary implementation conceived according to the present invention The diagram of the second connection status of path selector MUX1 on the buffer die BD that Fig. 2 is set of example.

Referring to figs. 1 to Fig. 5, Figure 10 A and Figure 10 B, in the present example embodiment, storage device 1200 may include four Core bare die CD1 to CD4, and each core bare die CD1 to CD4 may include four channels of the channel C H1 into CH16.Separately Outside, path selector MUX1 may be coupled to all channel C H1 to CH16.Therefore, storage device 1200 may include a road Diameter selector MUX1.

For example, first path selector MUX1 is connected to first passage CH1 to the 16th channel C H16.As shown in Figure 10 A, First path selector MUX1 can sequentially connect first passage CH1 to the 16th channel C H16 under the first connection status To first passage path CP1 to the 16th channel path CP16.

As shown in Figure 10 B, first path selector MUX1 can be under the second connection status by first passage CH1 to the tenth Six channel C H16 are sequentially connected to the 16th channel path CP16 to first passage path CP1.

Using above-mentioned path selector MUX1, it can determine that the mistake of storage system 1000 is the channel of storage device 1200 Mistake or channel path mistake.

It should be appreciated that first path selector MUX1 can be formed to be connected with first in order to improve the reliability that mistake determines Connect the state various connection status different with the second connection status.

According to the present exemplary embodiment, the mistake of storage system 1000 is detected under the first connection status and the second connection status Accidentally, it may thereby determine that the mistake of storage system 1000 is the mistake in the channel of storage device 1200 or the mistake of channel path Accidentally.Furthermore it is possible to the mistake of storage system 1000 be determined in real work load system, without by 1000 turns of storage system It is connected to independent mistake and determines system.

In addition, path selector MUX1 can also be in the various connections different from the first connection status and the second connection status The mistake of storage system 1000 is detected under state, so as to improve the reliability that mistake determines.

In addition, path selector MUX1 may be coupled to the channel of different core bare die and can switch connection status, So as to improve the reliability that mistake determines.

Figure 11 is to show the diagram of the storage system 1000 for the exemplary embodiment conceived according to the present invention.Figure 12 A is Show the path selector on the buffer die BD that Figure 11 is set for the exemplary embodiment conceived according to the present invention The diagram of the first connection status of MUX1 to MUX16.Figure 12 B is to show setting for the exemplary embodiment conceived according to the present invention Set the diagram of the second connection status of the path selector MUX1 to MUX16 on the buffer die BD of Figure 11.Figure 12 C is to show The path selector MUX1 on the buffer die BD that Figure 11 is set for the exemplary embodiment conceived according to the present invention is gone out To the diagram of the third connection status of MUX16.

Other than the storage device of the present exemplary embodiment further includes reference channel, depositing according to the present exemplary embodiment The storage system of storage system and the foregoing example embodiment illustrated referring to figs. 1 to Figure 10 B is essentially identical.Therefore, identical attached Icon note will be used for the same or similar component of component described in the exemplary embodiment of expression and Fig. 1 to Figure 10 B.It can be with Omit any repeated explanation about said elements.

Referring to Fig.1 1 to Figure 12 C, storage system 1000 includes storage control 1100 and storage device 1200.Storage system 1000 can also include the plug-in part 1300 for connecting storage control 1100 and storage device 1200.

Storage device 1200 may include multiple channel C H1 to CH16.Storage device 1200 can also include reference channel. Plug-in part 1300 can also include the reference channel path for reference channel to be connected to storage control 1100.For example, depositing Storage device 1200 may include multiple reference channel RCH1, RCH2, RCH3 and RCH4.For example, each core bare die CD1 to CD4 It include reference channel.For example, the first core bare die CD1 being arranged on buffer die BD may include first passage CH1 To fourth lane CH4 and the first reference channel RCH1.For example, the second core bare die CD2 being arranged on the first core bare die CD1 It may include Five-channel CH5 to the 8th channel C H8 and the second reference channel RCH2.For example, being arranged in the second core bare die CD2 On third core bare die CD3 may include the 9th channel C H9 to the 12nd channel CH12 and third reference channel RCH3.Example Such as, the 4th core bare die CD4 being arranged on third core bare die CD3 may include the tenth triple channel CH13 to the 16th channel CH16 and the 4th reference channel RCH4.

The error rate of reference channel RCH1 to RCH4 can be less than the error rate of channel C H1 to CH16.For example, and channel CH1 to CH16 is compared, reference channel RCH1 to RCH4 can in the manufacturing step of storage device 1000 by it is tightened up can By property test.

In the present example embodiment, storage device 1200 may include four core bare die CD1 to CD4, and core Each core bare die of the bare die CD1 into CD4 may include four channels of the channel C H1 into CH16.Core bare die CD1 is extremely Each core bare die in CD4 may include reference channel RCH1, RCH2, RCH3 or RCH4 respectively.In addition, in this exemplary reality It applies in example, each of path selector MUX1 to MUX16 may be coupled to a channel and a reference channel, and road Each of diameter selector MUX1 to MUX16 may be coupled to a channel in same core bare die and a reference is logical Road.Therefore, storage device 1200 may include 16 path selector MUX1 to MUX16.

Although storage device 1200 includes four core bare die CD1 to CD4 in the present example embodiment, of the invention Conceive without being limited thereto.In addition, although each core bare die CD1 to CD4 includes four channels in the present example embodiment, Present inventive concept is without being limited thereto.In addition, although each core bare die CD1 to CD4 includes a ginseng in the present example embodiment Channel is examined, but present inventive concept is without being limited thereto.Alternatively, at least one of core bare die CD1 to CD4 may include multiple ginsengs Examine channel.Alternatively, the number of reference channel can be less than the number of core bare die, therefore, at least one of core bare die can Not include reference channel.

For example, the first core bare die CD1 includes first passage CH1 to fourth lane CH4.First path selector MUX1 connects It is connected to first passage CH1 and the first reference channel RCH1.As illustrated in fig. 12, first path selector MUX1 connects shape first First passage CH1 is connected to first passage path CP1, and the first reference that the first reference channel RCH1 is connected under state Channel path RCP1.As shown in Figure 12 B, first path selector MUX1 connects first passage CH1 under the second connection status First passage path CP1 is connected to the first reference channel path RCP1, and by the first reference channel RCH1.

Second path selector MUX2 is connected to second channel CH2 and the first reference channel RCH1.As illustrated in fig. 12, Second channel CH2 is connected to second channel path CP2 under the first connection status by two path selector MUX2, by the first reference Channel RCH1 is connected to the first reference channel path RCP1.As indicated in fig. 12 c, the second path selector MUX2 connects shape in third Second channel CH2 is connected to the first reference channel path RCP1 under state, the first reference channel RCH1 is connected to second channel Path CP2.

Using above-mentioned path selector MUX1 and MUX2, it can determine that the mistake of storage system 1000 is storage device 1200 Channel mistake or channel path mistake.In the present example embodiment, using its reliability is high in channel C H1 extremely The reference channel RCH1 to RCH4 of the reliability of CH16 determines the mistake of storage system 1000.

As illustrated in figs. 12 a and 12b, third path selector MUX3 to the 16th path selector MUX16 can with First path selector MUX1 and the identical mode of the second path selector MUX2 operate.

According to the present exemplary embodiment, the mistake of storage system 1000 is detected under the first connection status and the second connection status Accidentally, the mistake for allowing to determine storage system 1000 is the mistake in the channel of storage device 1200 or the mistake of channel path Accidentally.Furthermore it is possible to the mistake of storage system 1000 be determined in real work load system, without by 1000 turns of storage system It is connected to independent mistake and determines system.

In addition, the reference of data reliability of the storage device 1200 using data reliability higher than channel C H1 to CH16 is logical Road RCH1 to RCH4 allows to improve the reliability that mistake determines.

Figure 13 is to show the electronic equipment 2000 including storage system for the exemplary embodiment conceived according to the present invention Block diagram.

Referring to figs. 1 to Figure 13, electronic equipment 2000 includes the application processor 2100 communicated via bus, connection electricity Road 2200, storage system (VM) 2300, Nonvolatile memory system (NVM) 2400, user interface 2500 and power supply 2600.Example Such as, electronic equipment 2000 can be mobile device.

Application processor 2100 can execute the application such as web browser, game application, video player.Connection electricity Road 2200 can execute wire communication or wireless communication with external equipment.Nonvolatile memory system 2400 can store for opening The starting image of dynamic electronic equipment 2000.User interface 2500 may include at least one input unit (such as keyboard, touch screen Deng) and at least one output equipment (such as loudspeaker, display device etc.).Power supply 2600 can be provided to electronic equipment 2000 Supply voltage.Storage system 2300 can store by the processed data of application processor 2100, or may be used as work and deposit Reservoir.As illustrated by the exemplary embodiment above with reference to present inventive concept, storage system 2300 can change logical in real time Connection status between road and channel path determines thereby executing mistake.

Above-described embodiment can be in storage system, various equipment or system including storage system, such as movement is electric Words, smart phone, personal digital assistant (PDA), portable media player (PMP), digital camera, field camera, DTV, set-top box, music player, portable game machine, navigation device, personal computer (PC), server computer, It is work station, tablet computer, notebook computer, smart card, printer, wearable system, Internet of Things (IoT) system, virtual Real (VR) system, augmented reality (AR) system etc..

The exemplary embodiment conceived according to the present invention storage system, determine storage system mistake method and packet It includes in the electronic equipment of storage system, is connected to storage control in the channel of storage device and by the channel of the storage device The mistake of storage system is detected under the first connection status between channel path；The first connection shape between channel and channel path State changes into the second connection status；The mistake of storage system is detected under the second connection status between channel and channel path, It may thereby determine that mistake occurs in the storage device or in channel path.

In addition, the storage system for the exemplary embodiment conceived according to the present invention determines system without being transferred to independent mistake System.The mistake that storage system can be determined in real work load system, without storage system is transferred to independent mistake Accidentally determine system.

Although present inventive concept is specifically illustrated and described by reference to exemplary embodiment of the present invention, for this Field those of ordinary skill is it is readily apparent that in the spirit and model for not departing from the present inventive concept being defined by the following claims In the case where enclosing, various changes can be carried out to these exemplary embodiments in form and details.

Claims (20)

1. a kind of storage system, comprising:

Storage device, the storage device include buffer die, the multiple cores bare die being arranged on the buffer die, Multiple channels are configured as in the buffer die and the multiple core bare die with silicon access, the silicon access of wearing is worn Signal is sent between at least one core bare die；

Storage control, the storage control are configured as to the storage device output command signal and address signal, to The storage device outputting data signals, and data-signal is received from the storage device；And

Plug-in part, the plug-in part include multiple channel paths for connecting the storage control and the multiple channel,

Wherein, the storage device further includes for changing the connection shape between the multiple channel and the multiple channel path The path selector of state, and

Wherein, when detecting the storage under the first connection status between the multiple channel and the multiple channel path When the mistake of system, the path selector connects described first between the multiple channel and the multiple channel path State changes into the second connection status.

2. storage system according to claim 1 further includes package substrate,

Wherein, the storage device and the storage control are arranged on the plug-in part, and

Wherein, the plug-in part is set on the package substrate.

3. storage system according to claim 1, wherein the buffer die is connected to the multiple channel path,

Wherein, the buffer die includes multiple buffers, wherein the multiple buffer is configured as will be by described more It is logical that the data-signal that at least one channel path in a channel path is sent is output at least one of the multiple channel Road, and

Wherein, the multiple core bare die includes the multiple channel.

4. storage system according to claim 3, wherein the path selector is arranged on the buffer die On.

5. storage system according to claim 3, wherein the first core bare die packet on the buffer die is arranged in First passage and second channel are included,

Wherein, the path selector, which is configured as the first passage is connected to first under first connection status, leads to Path and the second channel is connected to second channel path, and

Wherein, the path selector is configured as under second connection status for the first passage being connected to described Two channel paths and the second channel is connected to the first passage path.

6. storage system according to claim 3, wherein the first core bare die packet on the buffer die is arranged in First passage is included, and the second core bare die being arranged on the first core bare die includes second channel,

Wherein, the path selector, which is configured as the first passage is connected to first under first connection status, leads to Path and the second channel is connected to second channel path, and

Wherein, the path selector is configured as under second connection status for the first passage being connected to described Two channel paths and the second channel is connected to the first passage path.

7. storage system according to claim 3, wherein the first core bare die packet on the buffer die is arranged in First passage, second channel, third channel and fourth lane are included,

Wherein, the path selector, which is configured as the first passage is connected to first under first connection status, leads to The second channel is connected to second channel path by path, and the third channel is connected to third channel path, and The fourth lane is connected to fourth lane path, and

Wherein, the path selector is configured as under second connection status for the first passage being connected to described The second channel is connected to the third channel path, the third channel is connected to described second by four-way path Channel path, and the fourth lane is connected to the first passage path.

8. storage system according to claim 3, wherein the path selector is connected to the multiple core bare die All the multiple channels, and

Wherein, all connections under first connection status between the multiple channel and the multiple channel path are different In all connections under second connection status between the multiple channel and the multiple channel path.

9. storage system according to claim 3, wherein the storage device further includes reference channel, described with reference to logical The error rate in road is less than the error rate in the multiple channel, and

Wherein, the plug-in part further includes reference channel path.

10. storage system according to claim 9, wherein the path selector includes:

It is connected to the first path selector of first passage and the reference channel；And

It is connected to the second path selector of second channel and the reference channel.

11. storage system according to claim 10, wherein the first path selector is configured as described first The first passage is connected to first passage path under connection status and is connected to the reference channel described with reference to logical Path,

Wherein, the first path selector is configured as that the first passage is connected to institute under second connection status It states reference channel path and the reference channel is connected to the first passage path,

Wherein, second path selector is configured as under first connection status for the second channel being connected to Two channel paths and the reference channel is connected to the reference channel path, and

Wherein, second path selector is configured as that the second channel is connected to institute under second connection status It states reference channel path and the reference channel is connected to the second channel path.

12. a kind of method that determination includes the mistake of the storage system of storage device and storage control, which comprises

Under the first connection status between multiple channels of the storage device and multiple channel paths of the storage system The mistake of the storage system is detected, the multiple channel is connected to the storage control, institute by the multiple channel path Storage device is stated to include buffer die, the multiple cores bare die being arranged on the buffer die and wear silicon access, it is described Silicon access is worn to be configured as at least one core bare die in the multiple core bare die and send out between the buffer die The number of delivering letters；

When detecting the mistake of the storage system, by the connection shape between the multiple channel and the multiple channel path State changes into the second connection status from first connection status；And

The mistake of the storage system is detected under second connection status.

13. the method according to claim 11, the method also includes: it is being connected to when under first connection status The first mistake is detected at the first passage path of first passage, and to be connected to second logical under second connection status When detecting first mistake at the first passage path in road, determine that the mistake of the storage system is described first logical The mistake of path.

14. the method according to claim 11, the method also includes: it is being connected to when under first connection status The second mistake is detected at the first passage path of the first passage, and is being connected under second connection status When detecting second mistake at the second channel path of the first passage, the mistake of the storage system is determined It is the mistake of the first passage.

15. according to the method for claim 12, wherein the buffer die is connected to the multiple channel path,

Wherein, the buffer die includes multiple buffers, wherein the multiple buffer is configured as will be by described more It is logical that the data-signal that at least one channel path in a channel path is sent is output at least one of the multiple channel Road, and

Wherein, the multiple core bare die is arranged on the buffer die, wherein the multiple core bare die includes institute State multiple channels.

16. according to the method for claim 15, wherein be configured as changing the multiple channel and the multiple passway The path selector of connection status between diameter is arranged on the buffer die.

17. according to the method for claim 16, wherein the first core bare die being arranged on the buffer die includes First passage and second channel,

Wherein, the path selector, which is configured as the first passage is connected to first under first connection status, leads to Path, and the second channel is connected to second channel path, and

Wherein, the path selector is configured as under second connection status for the first passage being connected to described Two channel paths, and the second channel is connected to the first passage path.

18. according to the method for claim 16, wherein the first core bare die being arranged on the buffer die includes First passage, and the second core bare die being arranged on the first core bare die includes second channel,

Wherein, the path selector, which is configured as the first passage is connected to first under first connection status, leads to Path, and the second channel is connected to second channel path, and

Wherein, the path selector is configured as under second connection status for the first passage being connected to described Two channel paths, and the second channel is connected to the first passage path.

19. according to the method for claim 16, wherein the storage device further includes reference channel, the reference channel Error rate be less than the multiple channel error rate, the storage system further includes reference channel path,

Wherein the path selector includes:

It is connected to the first path selector of first passage and the reference channel；And

It is connected to the second path selector of second channel and the reference channel,

Wherein, the first path selector is configured as under first connection status for the first passage being connected to One channel path, and the reference channel is connected to the reference channel path,

Wherein, the first path selector is configured as that the first passage is connected to institute under second connection status Reference channel path is stated, and the reference channel is connected to the first passage path,

Wherein, second path selector is configured as under first connection status for the second channel being connected to Two channel paths, and the reference channel is connected to the reference channel path, and

Wherein, second path selector is configured as that the second channel is connected to institute under second connection status Reference channel path is stated, and the reference channel is connected to the second channel path.

20. a kind of electronic equipment, comprising:

Application processor；And

Storage system, the storage system are configured as being operated by the application processor,

Wherein, the storage system includes:

Storage device, the storage device include buffer die, the multiple cores bare die being arranged on the buffer die, Multiple channels and wear silicon access, described at least one core bare die wearing silicon access and being configured as in the multiple core bare die Signal is sent between the buffer die；

Storage control, the storage control are configured as to the storage device output command signal and address signal, to The storage device outputting data signals, and data-signal is received from the storage device；And

Plug-in part, the plug-in part include multiple channel paths for connecting the storage control and the multiple channel,

Wherein, the storage device further includes for changing the connection shape between the multiple channel and the multiple channel path The path selector of state, and

Wherein, when detecting the storage under the first connection status between the multiple channel and the multiple channel path When the mistake of system, the path selector connects described first between the multiple channel and the multiple channel path State changes into the second connection status.