WO2017054541A1 - 一种处理器及其处理任务的方法、存储介质 - Google Patents

一种处理器及其处理任务的方法、存储介质 Download PDF

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Publication number
WO2017054541A1
WO2017054541A1 PCT/CN2016/088140 CN2016088140W WO2017054541A1 WO 2017054541 A1 WO2017054541 A1 WO 2017054541A1 CN 2016088140 W CN2016088140 W CN 2016088140W WO 2017054541 A1 WO2017054541 A1 WO 2017054541A1
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instruction
calculation module
vector
task
pbuf
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French (fr)
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文博
曹庆新
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Definitions

  • the present invention relates to processor technology, and more particularly to a processor, a method for processing the same, and a storage medium.
  • MIMO Multiple Input Multiple Output
  • LTE and LTE-A baseband signal processing by using a vector DSP processor with vector operation function. Based on this, how to improve the performance of the vector processor becomes the key to determine the performance of the soft baseband chip.
  • processor performance has improved mainly by increasing the processor's frequency.
  • this method is unsustainable because the power consumption and the heating cost caused by the frequency increase are too large and the processor performance improvement effect is not obvious.
  • processor performance is significantly improved.
  • the widespread use of Intel's multi-core desktop processors and ARM's multi-core mobile processors proves that multi-core technology is an effective way to improve processor performance.
  • the most common parallel approach to multicore processors is task level parallelism.
  • single-core processing can only perform each task serially, while multi-core processors can assign tasks without dependencies to different cores, which is a significant performance improvement.
  • This parallel approach does not apply to tasks that have dependencies before and after, ie the input to the subsequent task is the output of the previous task.
  • pipelines can be used in parallel, that is, different tasks are handled by different cores, and tasks are pipelined.
  • vector operations are not all of the operations, because some parameter calculations are required before vector operations. These parameter calculations are scalar operations, so you can split a task into two parts: scalar operation and vector operation. If scalar and vector operations enable pipeline parallelism, the performance of the vector processor can be significantly improved.
  • multi-core processors use shared memory to implement inter-core communication. If existing multi-core technology is used to implement scalar operation and vector operation in parallel, and parameters are stored on shared memory, due to memory access speed and multi-core synchronization time overhead, Task switching takes a certain amount of time, so that the benefits of parallel pipelines are offset by a portion.
  • the embodiment of the invention provides a processor, a method for processing the same, and a storage medium, which overcomes the problem that the multi-core processor pipeline parallel task switching time is large.
  • the scalar calculation module performs parameter calculation of the current task, and stores the calculated parameter in a parameter buffer (PBUF, Parameter Buffer); when the parameter calculation of the current task is completed, executes a first instruction for inter-core synchronization Or a second instruction, and storing the first instruction or the second instruction in the PBUF;
  • PBUF parameter buffer
  • the vector calculation module reads parameters from the PBUF and stores the read parameters to the shadow In a shadow register; when the first instruction or the second instruction is read from the PBUF, all modified parameters in the shadow register are stored into a work register in one cycle ;
  • the vector calculation module performs a vector calculation of the current task based on the parameters in the work register.
  • the method further includes:
  • the vector calculation module After the vector calculation module performs the vector calculation of the current task, executing a third instruction, where the third instruction is used to update parameters of the next task.
  • the first instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the first instruction carries indication information indicating an address of the calling vector calculation module subroutine.
  • the second instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the second instruction is used to instruct the vector calculation module to execute the program in a preset order.
  • the method further includes:
  • the scalar calculation module After the scalar calculation module stores the first instruction or the second instruction into the PBUF, it continues to calculate parameters of the next task.
  • the processor provided by the embodiment of the present invention includes: a scalar calculation module, a vector calculation module, and a PBUF, where the vector calculation module includes: a shadow register and a work register;
  • the scalar calculation module is configured to perform parameter calculation of the current task, and store the calculated parameter into the PBUF; when the parameter calculation of the current task is completed, execute a first instruction for inter-core synchronization or a second instruction, and storing the first instruction or the second instruction in the PBUF;
  • the shadow register is configured to read a parameter from the PBUF and store the read parameter
  • the work register is configured to store all the modified parameters in the shadow register in one cycle when the first instruction or the second instruction is read from the PBUF;
  • the vector calculation module is configured to perform vector calculation of a current task according to parameters in the work register.
  • the work register is further configured to: when the first instruction or the second instruction is read from the PBUF, and the vector calculation module is in an idle state or executes a third instruction, All modified parameters in the shadow register are stored in one cycle.
  • the vector calculation module is further configured to execute a third instruction after performing vector calculation of the current task, where the third instruction is used to update parameters of the next task.
  • the first instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the first instruction carries indication information indicating an address of the calling vector calculation module subroutine.
  • the second instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the second instruction is used to instruct the vector calculation module to execute the program in a preset order.
  • the scalar calculation module is further configured to continue to calculate parameters of the next task after storing the first instruction or the second instruction in the PBUF.
  • a computer program stored in a storage medium according to an embodiment of the present invention, the computer program A method configured to perform the described processor processing tasks.
  • the scalar calculation module performs parameter calculation of the current task, and stores the calculated parameter into the PBUF; when the parameter calculation of the current task is completed, performs the first for inter-core synchronization. And the second instruction is stored in the PBUF; the vector calculation module reads the parameter from the PBUF, and stores the read parameter into the shadow register; When the first instruction or the second instruction is read from the PBUF, all the modified parameters in the shadow register are stored into the work register in one cycle; the vector calculation module is based on the work register The parameter performs a vector calculation of the current task.
  • the processor of the embodiment of the present invention uses the scalar calculation module and the vector calculation module to respectively perform the scalar processing portion and the vector processing portion of each task, and uses the PBUF as a parameter buffer for the scalar processing output and the vector processing input, so that the scalar processing program can be made. Executing in parallel with vector handlers significantly improves processor performance. In addition, due to the one-time update strategy of the shadow register to the work register, the task switching of the vector calculation module has almost no additional time overhead.
  • the vector calculation module has the function of scalar operation, that is, the scalar kernel is a functional subset of the vector kernel, and the scalar kernel and the vector kernel adopt a compatible instruction set, so that the scalar task and the vector task can be flexibly cut and the maximum program optimization can be performed.
  • the scalar calculation module is responsible for task control, which can flexibly schedule the vector calculation module, control the execution trajectory of the vector calculation module, and facilitate programming.
  • FIG. 1 is a schematic diagram of a multi-core parallel implementation
  • FIG. 2 is a schematic diagram of parallel and synchronization of a processor according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a method for processing a task by a processor according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • FIG. 5 is a structural block diagram of a processor according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of dual-core inter-core communication according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a PBUF data format according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a method for processing a task by a processor according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic flowchart of a scalar core processing task according to an embodiment of the present invention.
  • FIG. 10 is a schematic flowchart diagram of a vector core processing task according to an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart of a PBUF operation according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a simple microcode example of a dual-core DSP and a program code corresponding to a single core executing the same task;
  • FIG. 13 is a structural block diagram of a processor according to another embodiment of the present invention.
  • FIG. 14 is a schematic diagram of parallel and synchronous processing of a processor according to another embodiment of the present invention.
  • FIG. 15 is a schematic flowchart diagram of a method for processing a task by a processor according to another embodiment of the present invention.
  • 16 is a schematic flowchart of a scalar core processing task according to another embodiment of the present invention.
  • FIG. 17 is a schematic flow chart of a vector core processing task according to another embodiment of the present invention.
  • the scalar calculation module is also referred to as a scalar core
  • the vector calculation module is also referred to as a vector core.
  • the first instruction is a fork instruction of the indicator quantity kernel
  • the second instruction is a synchronization instruction of the indicator quantity kernel
  • the third instruction is especially a sync instruction of the vector core.
  • each task is divided into a scalar processing portion and a vector processing portion (e.g., task 1 is divided into a scalar processing portion S1 and a vector processing portion V1).
  • the scalar processing part must be executed first, and then the vector processing part is executed, and the execution efficiency is low.
  • the scalar processing part and the vector processing part are respectively processed by the scalar kernel and the vector core, and are guaranteed by a strict dual-core synchronization mechanism. Now that scalar processing and vector processing are performed simultaneously, the time to complete the task is significantly shortened.
  • the scalar kernel executes the fork instruction after executing the scalar processing S1.
  • the purpose of the fork instruction is to notify that the vector kernel parameter is ready, and the vector kernel can start performing the vector operation.
  • the fork instruction also specifies the address of the calling vector core subroutine.
  • the function of the sync instruction is also to inform the vector core that it can start performing vector operations, but it differs from the fork instruction in that it does not have a vector kernel subroutine address, meaning that the vector core is to execute the program sequentially instead of starting from the new subroutine start address. .
  • the vector core After the vector core is triggered, it starts to run from the start address of the subroutine, and executes the sync instruction after executing the vector processing V1.
  • the function of the vector core sync instruction is to indicate that the vector processing of the current task has been completed, and the parameters of the next task need to be passed over for the calculation of the next task.
  • the next task parameter calculation completion flag is read from the PBUF, that is, the scalar core sync instruction corresponding to S2
  • all the modified shadow register values are copied to the corresponding work register in one cycle, and then vector processing is started. . Subsequent tasks are also handled as described above.
  • FIG. 3 is a schematic flowchart of a method for processing a task by a processor according to Embodiment 1 of the present invention. As shown in FIG. 3, the method for processing a task by the processor includes the following steps:
  • Step 301 The scalar calculation module performs parameter calculation of the current task, and stores the calculated parameter into the PBUF; when the parameter calculation of the current task is completed, executing the first instruction or the second instruction for inter-core synchronization, And storing the first instruction or the second instruction into the PBUF.
  • the method further includes:
  • the scalar calculation module After the scalar calculation module stores the first instruction or the second instruction into the PBUF, it continues to calculate parameters of the next task.
  • Step 302 The vector calculation module reads a parameter from the PBUF, and stores the read parameter into a shadow register.
  • the first instruction or the second instruction is read from the PBUF, Store all modified parameters in the shadow register to work during the cycle In the register.
  • the first instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the first instruction carries indication information indicating an address of the calling vector calculation module subroutine.
  • the second instruction executed by the scalar calculation module is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the second instruction is used to instruct the vector calculation module to execute the program in a preset order.
  • the preset order is the order in which the instructions are discharged in the program memory.
  • Step 303 The vector calculation module performs vector calculation of the current task according to the parameters in the work register.
  • the method further includes:
  • the third instruction is executed, and the third instruction is used to update the parameters of the next task.
  • the processor includes: a scalar calculation module 41, a vector calculation module 42, and a PBUF 43, the vector calculation module includes: a shadow register 44, Work register 45;
  • the scalar calculation module 41 is configured to perform parameter calculation of the current task, and store the calculated parameter into the PBUF 43; after the parameter calculation of the current task is completed, execute the first instruction for inter-core synchronization Or a second instruction, and storing the first instruction or the second instruction Stored in the PBUF 43;
  • the shadow register 45 is configured to read parameters from the PBUF 43 and store the read parameters
  • the work register 45 is configured to store all the modified parameters in the shadow register 44 in one cycle when the first instruction or the second instruction is read from the PBUF 43;
  • the vector calculation module 42 is configured to perform vector calculation of the current task based on parameters in the work register 45.
  • the work register 45 is further configured to store in a period when the first instruction or the second instruction is read from the PBUF 43 and the vector calculation module is in an idle state or executing a third instruction All of the modified parameters in the shadow register 44.
  • the vector calculation module 42 is further configured to execute a third instruction after performing vector calculation of the current task, where the third instruction is used to update parameters of the next task.
  • the first instruction executed by the scalar calculation module 41 is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the first instruction carries indication information indicating an address of the calling vector calculation module subroutine.
  • the second instruction executed by the scalar calculation module 41 is used to notify the vector calculation module that the parameter calculation of the current task is completed;
  • the second instruction is used to instruct the vector calculation module to execute the program in a preset order.
  • the scalar calculation module 41 is further configured to continue to calculate parameters of the next task after storing the first instruction or the second instruction in the PBUF.
  • the embodiment of the present invention further provides a processor, as shown in FIG. 5, which is a structural block diagram of a processor according to an embodiment of the present invention.
  • the processor of the embodiment of the invention includes the following modules: SPM, Scalar Program Memory 51, Vector Program Memory (VPM) 52, data memory (DM, Data Memory) 53, direct memory access (DMA, Direct Memory Access) 54;
  • the processor further includes: a scalar core (SCORE, Scalar Core) 55, a vector core (VCORE, Vector Core) 56, a parameter buffer (PBUF, Parameter Buffer) 57, wherein the SCORE 55 contains a parameter register, and the VCORE 56 contains a shadow register. And the work register.
  • a scalar core (SCORE, Scalar Core) 55
  • VCORE Vector Core
  • PBUF Parameter Buffer
  • SPM51 and VPM52 are program memory of scalar core and vector core, respectively, and scalar core and vector core shared data memory DM53.
  • the DMA 54 is responsible for program and data handling.
  • the two cores perform inter-core communication through the parameter buffer PBUF57.
  • the scalar processing part provides parameters for the vector processing part.
  • the scalar kernel is responsible for the scalar processing part, and the vector kernel is responsible for the vector processing part (which also has the scalar operation function).
  • the scalar kernel calculates the parameters necessary for vector processing, stores it in the parameter register, and writes the parameters to PBUF57.
  • the parameter calculation of each task of the scalar core also executes the fork instruction or the sync instruction (fork vector core subroutine address, sync is not included), and writes the instruction information to PBUF57, in order to separate the parameters of different tasks. And dual core synchronization.
  • the parameters read from the PBUF 57 are sequentially written into the corresponding shadow registers of the vector core.
  • the scalar core can continue to calculate the parameters of the subsequent tasks and write them to the PBUF 57.
  • processing by scalar kernel and vector kernel, and using PBUF57 to transfer parameters and synchronization information dual-core parallel computing, as well as pipeline operations and fast switching of continuous tasks can be realized.
  • the processor is especially a DSP, which adopts a Haval structure, a scalar core and a vector core shared data memory DM.
  • the DMA54 is responsible for program and data transfer.
  • the program can be transferred from the external storage space to the SPM51 and VPM52 inside the DSP through the AXI bus. It can also be used in external storage space.
  • the two cores perform inter-core communication through the parameter buffer PBUF57.
  • the scalar kernel is responsible for the scalar processing part, and the vector kernel is responsible for the vector processing part (which also has the scalar operation function).
  • the scalar kernel calculates the parameters necessary for vector processing, stores it in the parameter register, and writes the parameters to PBUF57.
  • the parameter calculation for each task of the scalar core also executes the fork or sync instruction (fork vector core subroutine address, sync is not included), and writes the instruction information to PBUF57, in order to isolate the parameters of different tasks and Dual core synchronization.
  • the parameters read from the PBUF 57 are sequentially written into the corresponding shadow registers of the vector core.
  • the fork or sync information is read, and the vector core is in an idle state or the previous task processing is completed (the vector core is executed to the sync instruction as a flag), Then all shadow register values are copied to the corresponding work register in one cycle, and then the vector kernel starts vector calculation according to the parameters carried in the work register.
  • the scalar core can continue to calculate the parameters of the subsequent tasks and write them to the PBUF 57.
  • processing by scalar kernel and vector kernel, and using PBUF57 to transfer parameters and synchronization information dual-core parallel computing, as well as pipeline operations and fast switching of continuous tasks can be realized.
  • FIG. 6 is a schematic diagram of dual-core inter-core communication according to an embodiment of the present invention.
  • PBUF is a buffer of FIFO structure, which stores the parameter values sent by the scalar core and the synchronization instruction information. Inside the scalar core, there are some parameter registers, such as aa, qq, ll, pq, etc. These parameters are written to the PBUF. As can be seen from the PBUF, each group of parameters p1, p2, p3, etc. are isolated by the fork or sync flag. The parameters in PBUF are first written to the shadow registers of the vector core, such as aa.s, qq.s, ll.s, and so on.
  • the shadow register Because the update of these registers is done in the background.
  • the shadow register When the vector core executes the sync instruction, if the shadow register corresponding to the parameter required by the next task has been updated (ie, the fork or sync flag of the corresponding task is read), the shadow register value is copied to the corresponding work register at one time. It can be seen that the switching of the vector core task only consumes one cycle, that is, the cycle of executing the sync instruction. Therefore, when the number of cycles used by the task is large, the time overhead caused by task switching is negligible.
  • FIG. 7 is a schematic diagram of a PBUF data format according to an embodiment of the present invention.
  • the data in the PBUF includes parameters (aa, qq, ll, pq, etc.) and synchronization instructions (fork, sync).
  • the PBUF data is encoded. When reading data from the PBUF, the data needs to be parsed for corresponding processing.
  • FIG. 8 is a schematic flowchart diagram of a method for processing a task by a processor according to Embodiment 2 of the present invention. As shown in FIG. 8, the method for processing a task by the processor includes the following steps:
  • Step 801 The scalar core performs parameter calculation, and writes the calculation result into the parameter register and the PBUF. After a set of parameters used by a task is calculated, the scalar core executes a fork or sync instruction for inter-core synchronization and writes the instruction information to the PBUF.
  • Step 802 Read parameters from the PBUF and copy the parameter values to the shadow register.
  • the fork or sync instruction information is read from the PBUF, and the vector core is in an idle state or a sync instruction is executed, all modified shadow register values are copied to the work register in one cycle.
  • Step 803 The vector core performs vector calculation according to parameters carried in the work register. After the calculation is completed, execute the sync instruction to update the parameters required for the next task. While the vector kernel is being calculated, the scalar kernel is also calculating the parameters of the next task to achieve parallel task pipelines.
  • FIG. 9 is a schematic flow chart of a scalar core processing task according to an embodiment of the present invention.
  • the figure illustrates the task control and scheduling role of the scalar core, as shown in Figure 9, the process includes the following steps:
  • Step 901 Perform parameter calculation: For the parameter calculation result, both the parameter register and the PBUF need to be written.
  • Step 902 Execute a fork or sync instruction: the fork instruction will specify the VCORE subroutine address to be called, and the sync instruction will be executed in the default VCORE order. The fork or sync instruction information is written to the PBUF.
  • Step 903 Determine whether a new set of parameters needs to be calculated. If so, step 901 is re-executed; otherwise, the scalar core ends working.
  • FIG. 10 is a schematic flowchart diagram of a vector core processing task according to an embodiment of the present invention. Because the vector core is the called core, it is initially idle. As shown in FIG. 10, the process includes the following steps:
  • Step 1001 In the idle state, it is seen whether the information read from the PBUF is a fork or sync instruction information. If yes, the next step is performed; if not, it remains in the idle state.
  • Step 1002 Copy all modified shadow register values to the corresponding work register at one time. This operation is done quickly in one cycle.
  • Step 1003 VCORE starts a subroutine or executes sequentially from the address specified by fork.
  • Step 1004 VCORE executes a sync instruction to see if the fork or sync instruction information is read from the PBUF. If so, the shadow register value is copied to the work register; if not, the idle state is entered. After entering the idle state, continue to wait for the fork or sync instruction information.
  • FIG. 11 is a schematic flowchart of a write PBUF operation according to an embodiment of the present invention. As shown in FIG. 11, the process includes the following steps:
  • Step 1101 Initially, the PBUF is empty, and the parameters of the scalar core and the synchronization instruction information can be written.
  • Step 1102 Determine whether the PBUF is not full. If yes, go to step 1103. Otherwise, go to step 1104.
  • the PBUF readout is blocked due to special reasons, it is possible that the PBUF is filled by the scalar core.
  • the clock of the scalar core needs to be turned off, so that the scalar core stops running and the PBUF cannot be written.
  • Step 1103 The parameters of the scalar core and the fork and sync information can be written.
  • Step 1104 The scalar core turns off the clock, making it impossible to write to the PBUF.
  • Figure 12 is a schematic diagram of a simple microcode example of a dual core DSP.
  • the scalar kernel first provides the calculation of the ld(load) instruction address a2 for the vector core.
  • the ".s" in the code "a2.s” indicates that the result of the parameter register a2 will be passed to the shadow register a2.s through the PBUF, and then passed to the work register a2 of the vector core.
  • the vector core VC_SUBROUTINE1 subroutine is called using the fork instruction.
  • the ld instruction uses the a2 calculated by the scalar kernel to perform a vector load operation, and then ends the operation using the sync instruction.
  • the scalar kernel provides the calculation of the ld(load) instruction address a4 for the vector core.
  • the scalar core uses the sync instruction. This time, the sync command of the scalar core causes the vector core to execute sequentially. It can be seen that the vector core continues to execute the vector load operation of the ld instruction using the scalar kernel calculation, and then ends the operation using the sync instruction.
  • Figure 12 also shows the program code corresponding to a single core executing the same task, and the visible code is serially executed. Since the scalar kernel is a functional subset of the vector kernel and the instruction set is compatible, the task can be completed by the vector core single core. In other words, the scalar processing portion can be flexibly cut into two parts, which are respectively assigned to the scalar kernel and the vector kernel. A typical application is that the scalar processing portion is all allocated to the scalar core. However, for a specific application, it is possible to achieve the maximum efficiency of dual-core, flexible cutting of the scalar processing part and the processing limits of the scalar kernel and the vector core.
  • FIG. 13 is a structural block diagram of a processor according to another embodiment of the present invention, as shown in FIG.
  • This embodiment eliminates the PBUF 57 as compared to the previous embodiment, but requires the scalar core 55 to output fork or sync instruction information to the vector core 56, and also requires the vector core 56 to output sync instruction information to the scalar core 55.
  • the value written by the scalar core 55 to the parameter register is simultaneously written to the shadow register of the vector core 56.
  • This embodiment reduces resource overhead compared to the previous embodiment, but has an impact on processor performance, as will be explained in connection with FIG.
  • the scalar core must wait until the vector core is in the idle state or the vector core is executed to the sync instruction when executing the fork or sync instruction and the next task parameter calculation is to be performed.
  • the scalar kernel wait is to prevent the shadow register value from being overwritten by the scalar kernel when it has not been copied to the work register.
  • the next task vector calculation is performed if the scalar core is in a wait state or the scalar core executes to a fork or sync instruction, otherwise the vector core enters an idle state.
  • the vector core enters the idle state in order to wait for the scalar core to calculate the corresponding parameters.
  • the shadow register value is used when the scalar core executes the fork or sync instruction and the vector core is in the idle state, or when the vector core executes the sync instruction and the scalar core is in the wait state, or the scalar core executes the fork or sync instruction and the vector core executes the sync instruction. Copy to the work register once.
  • FIG. 15 is a schematic flowchart of a method for processing a task by a processor according to another embodiment of the present invention, and implementing dual-core parallel computing and interaction according to the following steps:
  • Step 1501 The scalar core performs parameter calculation, and writes the calculation result into the parameter register and the shadow register of the vector core. After a set of parameters used by a task is calculated, the scalar core executes a fork or sync instruction for inter-core synchronization and passes the instruction information to the vector core.
  • Step 1502 When the vector core obtains the fork or sync instruction information from the scalar core, and the vector core is in an idle state or executes a sync instruction, all the modified shadow register values are copied to the work register in one cycle.
  • Step 1503 The vector core performs vector calculation according to parameters carried in the work register. Calculated The sync command is executed afterwards to update the parameters required for the next task. At the same time, the vector core needs to feed back the sync instruction information to the scalar core, and inform the scalar core to perform new parameter calculation. While the vector kernel is being calculated, the scalar kernel is also calculating the parameters of the next task to achieve parallel task pipelines.
  • FIG. 16 is a schematic flowchart diagram of a scalar core processing task according to another embodiment of the present invention.
  • the processing of a scalar core is as follows:
  • Step 1601 Perform parameter calculation: For the parameter calculation result, both the parameter register and the shadow register need to be written.
  • Step 1602 Execute a fork or sync instruction: the fork instruction will specify the VCORE subroutine address to be called, and the sync instruction will be executed in the default VCORE order. The fork or sync command information is sent to VCORE.
  • Step 1603 Determine if there is a new set of parameters that need to be calculated. If not, SCORE ends the work; if so, step 1604 is performed.
  • Step 1604 Determine if the VCORE is in an idle state or is executing a sync instruction. If the VCORE is in an idle state or is executing a sync instruction, then return to step 1601 of the parameter calculation, otherwise step 1605 is performed.
  • Step 1605 SCORE stops waiting until VCORE executes the sync instruction.
  • FIG. 17 is a schematic flow chart of a vector core processing task according to another embodiment of the present invention.
  • the process of vector core is as follows:
  • Step 1701 In the idle state, if the SCORE sends a fork or sync instruction message or the SCORE is in the stop state, the next operation is performed; otherwise, the VCORE continues to remain in the idle state.
  • Step 1702 Copy all modified shadow register values to the corresponding work register at one time. This operation is done quickly in one cycle.
  • Step 1703 The VCORE starts the subroutine or executes sequentially from the address specified by the fork.
  • Step 1704 The VCORE executes a sync instruction to determine whether the SCORE sends a fork or sync instruction message or the SCORE is in a stop state. If so, the shadow register value is copied to the work register; if not, the idle state is entered. After entering the idle state, continue to wait for the fork or sync instruction information.
  • Embodiments of the present invention also describe a storage medium in which a computer program is stored, the computer program being configured to perform a method of processing a task by a processor of the foregoing embodiments.
  • the disclosed method and smart device may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the processor of the present invention uses the scalar calculation module and the vector calculation module to respectively perform the scalar processing portion and the vector processing portion of each task, and uses the PBUF as a parameter buffer for the scalar processing output and the vector processing input, so that the scalar processing program and the vector can be made.
  • Processors execute in parallel, significantly improving processor performance.
  • the task switching of the vector calculation module has almost no additional time overhead.
  • the vector calculation module has the function of scalar operation, that is, the scalar kernel is a functional subset of the vector kernel, and the scalar kernel and the vector kernel adopt a compatible instruction set, so that the scalar task and the vector task can be flexibly cut and the maximum program optimization can be performed.

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Abstract

一种处理器及其处理任务的方法、存储介质，所述方法包括：标量计算模块执行当前任务的参数计算，并将计算得到的参数存储至PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中(301)；矢量计算模块从所述PBUF中读取参数，并将读取到的参数存储至shadow寄存器中；当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中(302)；矢量计算模块根据所述work寄存器中的参数执行当前任务的矢量计算(303)。

Description

一种处理器及其处理任务的方法、存储介质 技术领域
本发明涉及处理器技术，尤其涉一种处理器及其处理任务的方法、存储介质。
背景技术
在移动通信市场，存在着第二代(2G，2Generation)、第三代(3G，3Generation)、第四代(4G，4Generation)共存的局面，通信技术协议也在不断的向前发展。面对如此多的通信制式和快速更新的协议版本，采用软件定义无线电(SDR，Software Defined Radio)技术实现基带信号处理是一个好的发展方向。SDR技术采用的是数字信号处理器(DSP，Digital Signal Processor)软基带方案，相比传统专用集成电路(ASIC，Application Specific Integrated Circuit)实现方式，具有更高的灵活性和更快的产品推出速度。4G长期演进(LTE，Long Term Evolution)以及后续的长期演进升级版(LTE-A，Long Term Evolution-Advanced)技术都以正交频分复用(OFDM，Orthogonal Frequency Division Multiplexing)和多输入多输出(MIMO，Multiple Input Multiple Output)作为主要技术特征，这些技术特征决定了所处理的基带信号具有矩阵运算较多的特点。所以采用具有矢量运算功能的矢量DSP处理器实现LTE及LTE-A基带信号处理是合适的。基于此，如何提高矢量处理器的性能成为决定软基带芯片性能的关键。
以往，处理器性能的提升主要靠提高处理器主频。但随着处理器频率越来越高，这种方法难以为继，原因是频率提高带来的功耗和发热代价太大并且处理器性能提升效果不明显。现在处理器朝着多核方向发展，通过在一个处理器内集成多个处理器核，并令多个处理器核并行工作，在不提 高处理器频率的情况下，显著地提高了处理器性能。Intel公司的多核桌面处理器和ARM公司的多核移动处理器的广泛应用，证明采用多核技术是提升处理器性能行之有效的方法。多核处理器最常见的并行方式是任务级并行。如图1所示，单核处理只能串行执行每个任务，而多核处理器可以将没有依赖关系的任务分配给不同的核，这样带来的性能提升显而易见。这种并行方式并不适用前后有依赖关系的任务，即后面任务的输入是前面任务的输出。对于有依赖关系的任务，可以采用流水线并行的方式，即不同的任务分别交由不同的核处理，任务进行流水操作。
具体到矢量处理器，对于某个任务，矢量运算并不是所有运算的全部，因为在矢量运算之前，需要一些参数计算。这些参数计算属于标量运算，所以可以把某个任务分割为标量运算和矢量运算两部分。如果标量运算和矢量运算能够实现流水线并行，则可以显著提高矢量处理器的性能。当前多核处理器多采用共享存储器的方式实现核间通信，如果使用现有多核技术实现标量运算和矢量运算并行，将参数存于共享存储器上，则由于存储器访问速度和多核同步时间开销的原因，任务切换需要花费一定的时间，使得流水线并行带来的益处被抵消掉一部分。
发明内容
本发明实施例提供了一种处理器及其处理任务的方法、存储介质，克服了多核处理器流水线并行任务切换时间开销大的问题。
本发明实施例提供的处理器处理任务的方法包括：
标量计算模块执行当前任务的参数计算，并将计算得到的参数存储至参数缓冲器(PBUF，Parameter Buffer)中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中；
矢量计算模块从所述PBUF中读取参数，并将读取到的参数存储至影 子(shadow)寄存器中；当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至工作(work)寄存器中；
矢量计算模块根据所述work寄存器中的参数执行当前任务的矢量计算。
本发明实施例中，所述当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中，包括：
当从所述PBUF中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行所述第三指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中。
本发明实施例中，所述方法还包括：
所述矢量计算模块执行所述当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
本发明实施例中，所述标量计算模块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
本发明实施例中，所述标量计算模块执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
本发明实施例中，所述方法还包括：
所述标量计算模块将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
本发明实施例提供的处理器包括：标量计算模块、矢量计算模块、PBUF，所述矢量计算模块包括：shadow寄存器、work寄存器；
所述标量计算模块，配置为执行当前任务的参数计算，并将计算得到的参数存储至所述PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中；
所述shadow寄存器，配置为从所述PBUF中读取参数，并存储读取到的参数；
所述work寄存器，配置为当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内存储所述shadow寄存器中所有被修改的参数；
所述矢量计算模块，配置为根据所述work寄存器中的参数执行当前任务的矢量计算。
本发明实施例中，所述work寄存器，还配置为当从所述PBUF中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行第三指令时，在一个周期内存储所述shadow寄存器中所有被修改的参数。
本发明实施例中，所述矢量计算模块，还配置为执行所述当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
本发明实施例中，所述标量计算模块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
本发明实施例中，所述标量计算模块执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
本发明实施例中，所述标量计算模块，还配置为将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
本发明实施例记载的存储介质中存储有计算机程序，所述计算机程序 配置为执行所述的处理器处理任务的方法。
本发明实施例的技术方案中，标量计算模块执行当前任务的参数计算，并将计算得到的参数存储至PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中；矢量计算模块从所述PBUF中读取参数，并将读取到的参数存储至shadow寄存器中；当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中；矢量计算模块根据所述work寄存器中的参数执行当前任务的矢量计算。本发明实施例的处理器使用标量计算模块和矢量计算模块分别执行每个任务的标量处理部分和矢量处理部分，并利用PBUF作为标量处理输出和矢量处理输入的参数缓存器，可以使标量处理程序和矢量处理程序并行执行，显著提高了处理器性能。此外，由于shadow寄存器到work寄存器的一次性更新策略，矢量计算模块的任务切换几乎没有额外的时间开销。矢量计算模块兼具标量运算功能，即标量核是矢量核的功能子集，而且标量核和矢量核采用兼容的指令集，因而可以灵活地进行标量任务和矢量任务的切割以及最大程度程序优化。标量计算模块负责任务控制可以对矢量计算模块进行灵活调度，控制矢量计算模块的执行轨迹，方便编程。
附图说明
图1为多核并行实现方式的示意图；
图2为本发明实施例的处理器并行和同步示意图；
图3为本发明实施例一的处理器处理任务的方法的流程示意图；
图4为本发明实施例的处理器的结构组成示意图；
图5为本发明实施例的处理器的结构框图；
图6为本发明实施例的双核核间通信示意图；
图7为本发明实施例的PBUF数据格式示意图；
图8为本发明实施例二的处理器处理任务的方法的流程示意图；
图9是为本发明实施例的标量核处理任务的流程示意图；
图10为本发明实施例的矢量核处理任务的流程示意图；
图11为本发明实施例的写PBUF操作的流程示意图；
图12是双核DSP简单的微码示例示意图以及单核执行相同任务对应的程序代码示意图；
图13为本发明另一实施例的处理器的结构框图；
图14为本发明另一实施例的处理器并行和同步示意图；
图15为本发明另一实施例的处理器处理任务的方法的流程示意图；
图16为本发明另一实施例的标量核处理任务的流程示意图；
图17为本发明是另一实施例的矢量核处理任务的流程示意图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。
为了便于理解本发明实施例的技术方案，本发明实施例中将标量计算模块也称为标量核，将矢量计算模块也称为矢量核。本发明实施例中的第一指令尤指标量核的fork指令，第二指令尤指标量核的sync指令，第三指令尤指矢量核的sync指令。
图2为本发明实施例的处理器并行和同步示意图。如图2所示，每个任务分为标量处理部分和矢量处理部分(如任务1分为标量处理部分S1和矢量处理部分V1)。如果是单核执行的话，必须先执行标量处理部分，再执行矢量处理部分，执行效率较低。将标量处理部分和矢量处理部分分别交由标量核和矢量核处理，再配以严格的双核同步机制加以保障，可以实 现标量处理和矢量处理同时进行，完成任务的时间明显缩短。图中标量核执行完标量处理S1之后执行fork指令，fork指令的目的是通知矢量核参数已准备完毕，矢量核可以开始执行矢量运算。此外，fork指令还指定了调用矢量核子程序的地址。只要PBUF未满，标量核就可以继续执行下一个任务的标量处理S2，然后再执行sync指令。sync指令的作用也是通知矢量核可以开始执行矢量运算，但它和fork指令的区别是不带有矢量核子程序地址，意思是矢量核要顺序执行程序而不是另外从新的子程序起始地址开始运行。矢量核被触发后开始从子程序起始地址运行，执行完矢量处理V1后再执行sync指令。矢量核sync指令的作用是指示当前任务的矢量处理已经完成，需要下一个任务的参数传递过来进行下一任务的计算。当从PBUF读到下一任务参数计算完成标志时，即与S2对应的标量核sync指令，则将全部被修改的shadow寄存器值在一个周期内拷贝到对应的work寄存器，然后开始执行矢量处理V2。后续任务也是按照前面所述方式进行处理的。
图3为本发明实施例一的处理器处理任务的方法的流程示意图，如图3所示，所述处理器处理任务的方法包括以下步骤：
步骤301：标量计算模块执行当前任务的参数计算，并将计算得到的参数存储至PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中。
本发明实施例中，所述方法还包括：
所述标量计算模块将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
步骤302：矢量计算模块从所述PBUF中读取参数，并将读取到的参数存储至shadow寄存器中；当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work 寄存器中。
本发明实施例中，所述当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至工作work寄存器中，包括：
当从所述PBUF中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行第三指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中。
本发明实施例中，所述标量计算模块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
所述标量计算模块执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
这里，预设顺序是指令在程序存储器中的排放顺序。
步骤303：矢量计算模块根据所述work寄存器中的参数执行当前任务的矢量计算。
本发明实施例中，所述方法还包括：
矢量计算模块执行当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
图4为本发明实施例的处理器的结构组成示意图，如图4所示，所述处理器包括：标量计算模块41、矢量计算模块42、PBUF43，所述矢量计算模块包括：shadow寄存器44、work寄存器45；
所述标量计算模块41，配置为执行当前任务的参数计算，并将计算得到的参数存储至所述PBUF43中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存 储至所述PBUF43中；
所述shadow寄存器45，配置为从所述PBUF43中读取参数，并存储读取到的参数；
所述work寄存器45，配置为当从所述PBUF43中读取到所述第一指令或第二指令时，在一个周期内存储所述shadow寄存器44中所有被修改的参数；
所述矢量计算模块42，配置为根据所述work寄存器45中的参数执行当前任务的矢量计算。
所述work寄存器45，还配置为当从所述PBUF43中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行第三指令时，在一个周期内存储所述shadow寄存器44中所有被修改的参数。
所述矢量计算模块42，还配置为执行所述当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
所述标量计算模41块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
所述标量计算模块41执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
所述标量计算模块41，还配置为将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
结合具体实际应用中的功能模块，本发明实施例还提供了一种处理器，如图5所示，图5为本发明实施例的处理器的结构框图。
本发明实施例的处理器包括以下模块：标量程序存储器(SPM，Scalar Program Memory)51、矢量程序存储器(VPM，Vector Program Memory) 52、数据存储器(DM，Data Memory)53、直接存储器存取(DMA，Direct Memory Access)54；
所述处理器还包括：标量核(SCORE，Scalar Core)55、矢量核(VCORE，Vector Core)56、参数缓冲器(PBUF，Parameter Buffer)57，其中SCORE55中含有参数寄存器，VCORE56中含有shadow寄存器和work寄存器。
上述模块中，SPM51和VPM52分别是标量核和矢量核的程序存储器，标量核和矢量核共享数据存储器DM53。DMA54负责程序和数据搬运。两个核通过参数缓冲器PBUF57进行核间通信。对于每段任务程序可以分为标量处理部分和矢量处理部分。其中，标量处理部分为矢量处理部分提供参数。标量核负责标量处理部分，矢量核负责矢量处理部分(兼具标量运算功能)。标量核计算矢量处理所必需的参数，存于参数寄存器，并将参数写入PBUF57。标量核每完成一个任务的参数计算还会执行fork指令或sync指令(fork带矢量核子程序地址，sync不带)，并将该指令信息写入PBUF57，目的是将不同任务的参数隔离区分开来以及双核同步。从PBUF57读出的参数依次写入矢量核的相应shadow寄存器，当读到fork或sync信息时，并且矢量核处于空闲状态或者已完成上个任务处理(以矢量核执行到sync指令为标志)，则所有shadow寄存器值在一个周期内被一次性拷贝到对应的work寄存器，然后矢量核根据work寄存器携带的参数开始矢量计算。在矢量核进行某个任务矢量计算的同时，标量核可以继续后面任务的参数计算并将其写入PBUF57。通过对每个任务进行标量处理和矢量处理切割，分别由标量核和矢量核处理，并利用PBUF57传递参数和同步信息，可以实现双核并行运算，以及连续任务的流水操作和快速切换。
此外，处理器尤指DSP，采用哈弗结构，标量核和矢量核共享数据存储器DM。DMA54负责程序和数据搬运，可以将程序通过AXI总线从外部存储空间搬运到DSP内部的SPM51和VPM52，也可以在外部存储空间和 DM之间进行双向数据搬运。两个核通过参数缓冲器PBUF57进行核间通信。标量核负责标量处理部分，矢量核负责矢量处理部分(兼具标量运算功能)。标量核计算矢量处理所必需的参数，存于参数寄存器，并将参数写入PBUF57。标量核每完成一个任务的参数计算还会执行fork或sync指令(fork带矢量核子程序地址，sync不带)，并将该指令信息写入PBUF57，目的是将不同任务的参数隔离区分开来以及双核同步。从PBUF57读出的参数依次写入矢量核的相应shadow寄存器，当读到fork或sync信息时，并且矢量核处于空闲状态或者已完成上个任务处理(以矢量核执行到sync指令为标志)，则所有shadow寄存器值在一个周期内被一次性拷贝到对应的work寄存器，然后矢量核根据work寄存器携带的参数开始矢量计算。在矢量核进行某个任务矢量计算的同时，标量核可以继续后面任务的参数计算并将其写入PBUF57。通过对每个任务进行标量处理和矢量处理切割，分别由标量核和矢量核处理，并利用PBUF57传递参数和同步信息，可以实现双核并行运算，以及连续任务的流水操作和快速切换。
图6为本发明实施例的双核核间通信示意图。PBUF是一个FIFO结构的缓冲器，里面存储的是标量核发送的参数值以及同步指令信息。在标量核内部，有一些参数寄存器，如aa、qq、ll、pq等，这些参数会被写到PBUF。从PBUF可以看到，各组参数p1、p2、p3等被fork或sync标志隔离开来。PBUF里面的参数首先被写到矢量核的shadow寄存器，如aa.s、qq.s、ll.s等。之所以叫做shadow寄存器，是因为这些寄存器的更新是在后台进行的。当矢量核执行sync指令时，如果下一任务所需参数对应的shadow寄存器都已更新完毕(即读到相应任务的fork或sync标志)，则一次性将shadow寄存器值拷贝到对应的work寄存器。由此可见，矢量核任务的切换只消耗了一个周期，即执行sync指令的周期。所以当任务所用周期数较大时，任务切换所带来的时间开销是可以忽略不计的。
图7为本发明实施例的PBUF数据格式示意图。PBUF里面的数据包括参数(aa、qq、ll、pq等)和同步指令(fork、sync)。实际上，对PBUF数据进行了编码处理。当从PBUF读取数据时，需要对数据进行解析以做相应的处理。
图8为本发明实施例二的处理器处理任务的方法的流程示意图。如图8所示，所述处理器处理任务的方法包括以下步骤：
步骤801：标量核执行参数计算，并将计算结果写入参数寄存器和PBUF。一个任务所用的一组参数计算完成后，标量核执行用于核间同步的fork或sync指令，并将该指令信息写入PBUF。
步骤802：从PBUF读取参数，并将参数值拷贝到shadow寄存器。当从PBUF读到fork或sync指令信息时，并且矢量核处于空闲状态或执行sync指令时，在一个周期内将所有被修改的shadow寄存器值一次性拷贝到work寄存器。
步骤803：矢量核根据work寄存器携带的参数进行矢量计算。计算完成后执行sync指令，用于更新下一任务所需的参数。在矢量核进行计算的同时，标量核也在对下一任务的参数进行计算，实现任务流水线并行。
图9是为本发明实施例的标量核处理任务的流程示意图。该图体现了标量核的任务控制和调度作用，如图9所示，所述流程包括以下步骤：
步骤901：执行参数计算：对于参数计算结果，既需要写入参数寄存器，又需要写入PBUF。
步骤902：执行fork或sync指令：fork指令将指定所调用VCORE子程序地址，sync指令默认VCORE顺序执行。fork或sync指令信息被写入PBUF。
步骤903：判断是否有新的一组参数需要计算。如果有，则重新执行步骤901；否则，标量核结束工作。
图10为本发明实施例的矢量核处理任务的流程示意图。因为矢量核是被调用核，所以一开始是处于空闲状态的。如图10所示，所述流程包括以下步骤：
步骤1001：在空闲状态下，看从PBUF读到的是否是fork或sync指令信息。如果是，则执行下一步操作；如果不是，则继续维持在空闲状态。
步骤1002：将所有被修改的shadow寄存器值一次性拷贝到对应的work寄存器。该操作在一个周期内快速完成。
步骤1003：VCORE从fork指定的地址开始运行子程序或顺序执行。
步骤1004：VCORE执行sync指令，看是否从PBUF读出fork或sync指令信息。如果是，则执行shadow寄存器值拷贝到work寄存器的操作；如果不是，则进入空闲状态。进入空闲状态后，继续等待fork或sync指令信息。
图11为本发明实施例的写PBUF操作的流程示意图。如图11所示，所述流程包括以下步骤：
步骤1101：一开始，PBUF是空的，可以接受标量核的参数和同步指令信息写入。
步骤1102：判断PBUF是否非满，是时执行步骤1103，否时，执行步骤1104。
但如果由于特殊原因导致PBUF读出阻塞，有可能PBUF被标量核填满。为了防止PBUF上溢，这时需要将标量核的时钟关闭，从而使标量核停止运行，进而无法继续写PBUF。
步骤1103：可以接受标量核的参数和fork、sync信息写入。
步骤1104：标量核关钟，使其无法写入PBUF。
此外，对于读PBUF操作，在PBUF为空时，将不进行读操作。当PBUF为非空时，如果读到的是参数，则将其写入对应的shadow寄存器。当从 PBUF读到的是fork或sync指令信息时，需要看矢量核是否处于空闲状态或者已经执行到sync指令，如果是则执行被修改的shadow寄存器到work寄存器的拷贝，如果不是则继续等待矢量核sync指令的到来。
图12是双核DSP简单的微码示例示意图。标量核首先为矢量核提供ld(load)指令地址a2的计算。代码中“a2.s”中的“.s”表示参数寄存器a2的结果将会通过PBUF传递到shadow寄存器a2.s，进而传递到矢量核的work寄存器a2。a2计算完成后，使用fork指令调用矢量核VC_SUBROUTINE1子程序。在矢量核VC_SUBROUTINE1子程序中，ld指令使用标量核计算得到的a2进行矢量load操作，然后使用sync指令结束此操作。下一个任务，标量核为矢量核提供ld(load)指令地址a4的计算。计算完成后，标量核使用sync指令。这一次，标量核的sync指令令矢量核顺序执行，可以看到矢量核继续执行的是ld指令使用标量核计算得到的a4进行矢量load操作，然后使用sync指令结束此操作。
图12也示出了单核执行相同任务对应的程序代码，可见代码是串行执行。由于标量核是矢量核的功能子集，且指令集兼容，该任务可以由矢量核单核完成，换句话说，标量处理部分可以灵活切割成两部分，分别分配给标量核和矢量核。典型应用是标量处理部分全部分配给标量核。但针对某一具体应用，可以做到为了达到双核效率最大化，灵活切割标量处理部分以及标量核和矢量核的处理界限。
图13为本发明另一实施例的处理器的结构框图，如图13所示。与前述实施例相比，该实施例取消了PBUF57，但需要标量核55输出fork或sync指令信息到矢量核56，也需要矢量核56输出sync指令信息到标量核55。标量核55写到参数寄存器的值被同时写到矢量核56的shadow寄存器。该实施例相比前述实施例减小了资源开销，但会对处理器性能造成影响，这一点将会结合图14进行阐述。
如图14所示，因为没有了PBUF缓存参数，标量核在执行到fork或sync指令且将要执行下一任务参数计算时，必须等到矢量核处于空闲状态或者矢量核执行到sync指令时才能执行下一任务参数计算。标量核等待是为了防止shadow寄存器值在还没有被拷贝到work寄存器时就被标量核写覆盖。矢量核在执行到sync指令且将要执行下一任务矢量计算时，如果标量核处于等待状态或者标量核执行到fork或sync指令则进行下一任务矢量计算，否则矢量核进入空闲状态。矢量核进入空闲状态是为了等待标量核将相应的参数计算完成。在标量核执行fork或sync指令且矢量核处于空闲状态时，或者矢量核执行sync指令且标量核处于等待状态时，或者标量核执行fork或sync指令且矢量核执行sync指令时，将shadow寄存器值一次性拷贝到work寄存器。
由图14可知，另一实施例相比前述实施例，由于没有了PBUF缓存参数，造成矢量核有空闲状态，所以处理器性能会有损失。如果想要达到或接近前述实施例的性能，则需要在软件编程时进行更为精确的标量和矢量划分以及任务划分，尽量使得标量和矢量部分均衡以及各个任务均衡，所以对软件编程提出更高的要求。
图15为本发明另一实施例的处理器处理任务的方法的流程示意图，按照以下的步骤，实现双核并行计算和交互：
步骤1501：标量核执行参数计算，并将计算结果写入参数寄存器和矢量核的shadow寄存器。一个任务所用的一组参数计算完成后，标量核执行用于核间同步的fork或sync指令，并将该指令信息传递到矢量核。
步骤1502：当矢量核从标量核得到fork或sync指令信息时，并且矢量核处于空闲状态或执行sync指令时，在一个周期内将所有被修改的shadow寄存器值一次性拷贝到work寄存器。
步骤1503：矢量核根据work寄存器携带的参数进行矢量计算。计算完 成后执行sync指令，用于更新下一任务所需的参数。同时，矢量核需要将sync指令信息反馈给标量核，通知标量核可以进行新的参数计算。在矢量核进行计算的同时，标量核也在对下一任务的参数进行计算，实现任务流水线并行。
图16为本发明另一实施例的标量核处理任务的流程示意图。标量核的处理过程如下：
步骤1601：执行参数计算：对于参数计算结果，既需要写入参数寄存器，又需要写入shadow寄存器。
步骤1602：执行fork或sync指令：fork指令将指定所调用VCORE子程序地址，sync指令默认VCORE顺序执行。fork或sync指令信息被送至VCORE。
步骤1603：判断是否有新的一组参数需要计算，如果没有，则SCORE结束工作；如果有，则执行步骤1604。
步骤1604：判断VCORE是否处于空闲状态或正在执行sync指令。如果VCORE处于空闲状态或正在执行sync指令，则回到参数计算的步骤1601，否则执行步骤1605。
步骤1605：SCORE停钟等待直到VCORE执行sync指令。
图17为本发明是另一实施例的矢量核处理任务的流程示意图。矢量核的处理过程如下：
步骤1701：在空闲状态下，如果SCORE发来fork或sync指令信息或者SCORE处于停钟等待状态，则执行下一步操作；否则VCORE继续维持在空闲状态。
步骤1702：将所有被修改的shadow寄存器值一次性拷贝到对应的work寄存器。该操作在一个周期内快速完成。
步骤1703：VCORE从fork指定的地址开始运行子程序或顺序执行。
步骤1704：VCORE执行sync指令，判断是否SCORE发来fork或sync指令信息或者SCORE处于停钟等待状态。如果是，则执行shadow寄存器值拷贝到work寄存器的操作；如果不是，则进入空闲状态。进入空闲状态后，继续等待fork或sync指令信息。
本发明实施例还记载了一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行前述各实施例的处理器处理任务的方法。
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
在本发明所提供的几个实施例中，应该理解到，所揭露的方法和智能设备，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个第二处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可 轻易想到变化或替换，都应涵盖在本发明的保护范围之内。
工业实用性
本发明的处理器使用标量计算模块和矢量计算模块分别执行每个任务的标量处理部分和矢量处理部分，并利用PBUF作为标量处理输出和矢量处理输入的参数缓存器，可以使标量处理程序和矢量处理程序并行执行，显著提高了处理器性能。此外，由于shadow寄存器到work寄存器的一次性更新策略，矢量计算模块的任务切换几乎没有额外的时间开销。矢量计算模块兼具标量运算功能，即标量核是矢量核的功能子集，而且标量核和矢量核采用兼容的指令集，因而可以灵活地进行标量任务和矢量任务的切割以及最大程度程序优化。

Claims (13)

  1. 一种处理器处理任务的方法，所述方法包括：
    标量计算模块执行当前任务的参数计算，并将计算得到的参数存储至参数缓冲器PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中；
    矢量计算模块从所述PBUF中读取参数，并将读取到的参数存储至影子shadow寄存器中；当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至工作work寄存器中；
    矢量计算模块根据所述work寄存器中的参数执行当前任务的矢量计算。
  2. 根据权利要求1所述的处理器处理任务的方法，其中，所述当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中，包括：
    当从所述PBUF中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行第三指令时，在一个周期内将所述shadow寄存器中所有被修改的参数存储至work寄存器中。
  3. 根据权利要求1所述的处理器处理任务的方法，其中，所述方法还包括：
    所述矢量计算模块执行所述当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
  4. 根据权利要求1所述的处理器处理任务的方法，其中，所述标量计算模块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
    所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
  5. 根据权利要求1所述的处理器处理任务的方法，其中，
    所述标量计算模块执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
    所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
  6. 根据权利要求1至5任一项所述的处理器处理任务的方法，其中，所述方法还包括：
    所述标量计算模块将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
  7. 一种处理器，所述处理器包括：标量计算模块、矢量计算模块、PBUF，所述矢量计算模块包括：shadow寄存器、work寄存器；
    所述标量计算模块，配置为执行当前任务的参数计算，并将计算得到的参数存储至参数缓冲器PBUF中；当所述当前任务的参数计算完成后，执行用于核间同步的第一指令或第二指令，并将所述第一指令或第二指令存储至所述PBUF中；
    所述shadow寄存器，配置为从所述PBUF中读取参数，并存储读取到的参数；
    所述work寄存器，配置为当从所述PBUF中读取到所述第一指令或第二指令时，在一个周期内存储所述shadow寄存器中所有被修改的参数；
    所述矢量计算模块，配置为根据所述work寄存器中的参数执行当前任务的矢量计算。
  8. 根据权利要求7所述的处理器，其中，所述work寄存器，还配置为当从所述PBUF中读取到所述第一指令或第二指令时，且所述矢量计算模块处于空闲状态或执行第三指令时，在一个周期内存储所述shadow寄存器中所有被修改的参数。
  9. 根据权利要求7所述的处理器，其中，所述矢量计算模块，还配置为执行所述当前任务的矢量计算完成后，执行第三指令，所述第三指令用于更新下一个任务的参数。
  10. 根据权利要求7所述的处理器，其中，所述标量计算模块执行的第一指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
    所述第一指令携有指示调用矢量计算模块子程序的地址的指示信息。
  11. 根据权利要求7所述的处理器，其中，所述标量计算模块执行的第二指令用于通知所述矢量计算模块所述当前任务的参数计算完成；
    所述第二指令用于指示所述矢量计算模块按照预设顺序执行程序。
  12. 根据权利要求7至11任一项所述的处理器，其中，所述标量计算模块，还用于将所述第一指令或第二指令存储至所述PBUF中之后，继续计算下一个任务的参数。
  13. 一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行权利要求1至6任一项所述的处理器处理任务的方法。
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