WO2017054353A1

WO2017054353A1 - Film process-based preparation method for radio frequency identification tag

Info

Publication number: WO2017054353A1
Application number: PCT/CN2015/099637
Authority: WO
Inventors: 吴为敬; 夏兴衡; 李冠明; 张立荣; 周雷; 徐苗; 王磊; 彭俊彪
Original assignee: 华南理工大学
Priority date: 2015-09-28
Filing date: 2015-12-29
Publication date: 2017-04-06
Also published as: CN105184356B; CN105184356A

Abstract

A film process-based preparation method for a radio frequency identification tag, wherein the radio frequency identification tag mainly comprises an antenna, an analog front end, a clock and digital logic circuit, and an EEPROM memory circuit, wherein the EEPROM memory circuit comprises a storage device and a peripheral read and write circuit, the antenna mainly comprises metal coils, the analog front end and the clock and digital logic circuit comprise conventional thin film transistors, and the EEPROM memory circuit mainly comprises conventional thin film transistors and memory thin film transistors. Provided is a method that employs the film process to integrally prepares, on the same substrate, the entire radio frequency identification tag comprising four parts: an antenna, an analog front end, a clock and digital logic circuit, and an EEPROM memory circuit. The method is capable of overcoming the drawbacks of traditional RFID tags, wherein, among others, the cost of integration between IC chips and external antennae is high, and the process is complex, thereby reducing costs.

Description

Radio frequency identification label preparation method based on thin film process

Technical field

The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a method for preparing a radio frequency identification tag based on a thin film process.

Background technique

Radio Frequency Identification (RFID) is a key technology for realizing the Internet of Things. It is widely used in various industries such as production, retail, logistics, transportation, and finance. A typical RFID system architecture consists of three parts: an application system, a reader, and an RFID tag. The application system is responsible for data processing, transmission and control. The reader is primarily responsible for two-way communication with the electronic tag while accepting control commands from the application system. The RFID tag has a unique electronic code and stores the relevant information of the identified object, and is the real data carrier of the RFID system. The 13.56MHz passive RFID tag is currently the most used, and it is mainly composed of a monocrystalline silicon integrated circuit (IC) chip and an external antenna. The IC chip is mainly composed of a module such as a modulation and demodulation circuit, a rectification and voltage stabilization circuit, a clock and a digital logic circuit, and an EEPROM (Electrically Erasable Programmable Read Only Memory) storage circuit. Such a conventional RFID tag has the disadvantages of high integration cost and complicated process of the IC chip and the external antenna, and cannot be made into a flexible form of the label.

With the maturity and development of thin film process technology, thin film transistor devices have become a research hotspot for researchers at home and abroad. People gradually began to try to replace the traditional monocrystalline silicon process with TFT technology to prepare RFID tags to solve the problem of integration of IC chips and antennas of traditional RFID tags. The ultimate goal is to implement flexible RFID tags. However, for RFID tags, they generally include antennas, analog front-end circuits, clocks, digital logic circuits, and EEPROM memory circuits. For thin film processes, they are used to prepare analog front-end circuits and clocks and digital logic. The structure of a conventional thin film transistor of a circuit and the structure of a memory thin film transistor used for preparing a memory device have a large difference, so it is difficult to integrate the two on the same substrate by the same process, that is, in the same It is very difficult to integrate a radio frequency identification tag including an antenna, an analog front end circuit, a clock, a digital logic circuit, and an EEPROM storage circuit on one substrate. Therefore, there is an urgent need to design a fabrication method for a circuit capable of simultaneously integrating a conventional thin film transistor and a memory thin film transistor, thereby realizing integration using a thin film process on a substrate. Radio frequency identification tag consisting of four parts: antenna, analog front end circuit, clock and digital logic circuit and EEPROM memory circuit.

technical problem

In order to overcome the shortcomings and deficiencies of the prior art, the present invention provides a method for preparing a radio frequency identification tag based on a thin film process.

Problem solution

Technical solution

The invention adopts the following technical solutions:

A radio frequency identification tag manufacturing method based on a thin film process, the radio frequency identification tag comprises an antenna, an analog front end circuit, a clock and a digital logic circuit and an EEPROM storage circuit, wherein the EEPROM storage circuit comprises a memory device and a peripheral read/write circuit, including The following steps:

S1 forming a first gate metal pattern and a second gate metal pattern on the substrate;

S2 forming a SiNx layer having a thickness of A on the first gate metal pattern;

S3 forming a memory TFT floating gate of thickness B on the SiNx layer and the second gate metal pattern of thickness A, wherein the floating gate of the storage TFT is a SiNx layer;

S4 forming a SiO ₂ insulating layer having a thickness C on the floating gate of the storage TFT above the first gate metal pattern;

S5 forming a tunneling insulating layer having a thickness D on the SiO ₂ insulating layer and the floating gate of the memory TFT, wherein the tunneling insulating layer is also a SiO ₂ layer;

S6 forms an active layer pattern on the tunneling insulating layer;

S7 forming an SiO ₂ etch stop layer at an intermediate position on the active layer above the first and second gate metal patterns, respectively;

S8 forms a source/drain electrode pattern and an antenna pattern on the SiO ₂ etch barrier layer to obtain a radio frequency identification tag.

a first gate metal pattern and a SiNx layer sequentially formed thereon, a memory TFT floating gate, a SiO ₂ insulating layer, a memory TFT tunneling insulating layer, an active layer pattern, a SiO ₂ etch barrier layer, and a source/drain electrode pattern Forming a conventional thin film transistor, realizing functions of an analog front end circuit and a read/write circuit of a clock, a digital logic circuit, and an EEPROM, the second gate metal pattern and a memory TFT floating gate formed thereon, a storage TFT tunneling insulating layer, The active layer pattern, the SiO ₂ etch stop layer, and the source/drain electrode pattern constitute a memory thin film transistor, which realizes the function of the EEPROM memory device, and the antenna pattern is realized by the source and drain metal.

The thickness of the SiNx layer of the conventional thin film transistor is A+B, the thickness of the insulating layer SiO ₂ of the conventional thin film transistor is C+D, and the thickness of the SiNx layer of the memory thin film transistor is B, and the thickness of the SiO ₂ of the memory thin film transistor is D ;

Wherein 100 nm ≤ A ≤ 400 nm, 20 nm ≤ B ≤ 80 nm, 20 nm ≤ C ≤ 80 nm, and 5 nm ≤ D ≤ 15 nm.

The gate insulating layer is composed of a SiNx layer/SiO ₂ layered layer structure.

A method for preparing a radio frequency identification tag based on a thin film process, the radio frequency identification tag comprising an antenna, an analog front end circuit, a clock and a digital logic circuit, comprising the following steps:

S1 forms a gate metal pattern on the substrate;

S2 forming a gate insulating layer on the gate metal pattern;

S3 forms an active layer pattern on the gate insulating layer;

S4 forming an SiO ₂ etch stop layer on the active layer pattern;

S5 forms a source/drain electrode pattern and an antenna pattern on the SiO ₂ etch barrier layer to obtain a conventional thin film transistor, which constitutes a radio frequency identification tag.

The analog front end circuit, clock and digital logic circuit are all realized by conventional thin film transistors, and the antenna pattern is realized by source and drain metal.

The substrate is a glass substrate or a flexible substrate.

A radio frequency identification tag manufacturing method based on a thin film process, the radio frequency identification tag only includes an EEPROM storage circuit, and the EEPROM storage circuit includes a memory device and a peripheral read/write circuit, and the method includes the following steps:

S1 forms a first gate metal pattern and a second gate metal pattern at a distance from each other on the substrate;

S6 forms an active layer pattern on the tunneling insulating layer;

S8 forms a source/drain electrode pattern on the SiO ₂ etch barrier layer to obtain an EEPROM memory circuit of the radio frequency identification tag.

a first gate metal pattern and a SiNx layer sequentially formed thereon, a memory TFT floating gate, a SiO ₂ insulating layer, a memory TFT tunneling insulating layer, an active layer pattern, a SiO ₂ etch barrier layer, and a source/drain electrode pattern Forming a conventional thin film transistor, realizing a read/write circuit of an EEPROM, the second gate metal pattern and a memory TFT floating gate formed thereon, a storage TFT tunneling insulating layer, an active layer pattern, an SiO ₂ etch barrier layer, The source/drain electrode patterns constitute a memory thin film transistor, and an EEPROM memory device is realized.

The thickness of the SiNx layer of the conventional thin film transistor is A+B, the thickness of the insulating layer SiO ₂ of the conventional thin film transistor is C+D, and the thickness of the SiNx layer of the memory thin film transistor is B, and the thickness of the SiO ₂ of the memory thin film transistor Is D;

Advantageous effects of the invention

Beneficial effect

The beneficial effects of the invention:

(1) The conventional RFID tag has the disadvantages of high integration cost and complicated process of the IC chip and the external antenna, and cannot be made into a flexible form of the tag. The invention can realize integrated integration of passive RFID tags (including antennas and integrated circuits) based on thin film technology on glass or flexible substrates, solve the problem of integration of IC chips and antennas of traditional RFID tags, and reduce the cost thereof;

(2) The invention is prepared by a thin film process, and the cost of the raw materials, the production equipment, the energy consumption, etc. can be reduced compared with the CMOS of the silicon process, thereby realizing the low cost of the RFID tag, and facilitating the promotion of the RFID in each Commercial applications in the field;

(3) The thin film process of the present invention can adopt a low temperature preparation process, and can realize integration of an integrated RFID tag on a flexible substrate, thereby increasing the application range of the RFID.

Brief description of the drawing

DRAWINGS

1 is a schematic structural view of a conventional thin film transistor;

2 is a schematic structural view of a memory thin film transistor;

3 is a schematic structural view of step 1 in Embodiment 1 of the present invention;

4 is a schematic structural view of step 2 in Embodiment 1 of the present invention;

Figure 5 is a schematic structural view of step 3 in Embodiment 1 of the present invention;

Figure 6 is a schematic structural view of step 4 in Embodiment 1 of the present invention;

Figure 7 is a schematic structural view of step 5 in Embodiment 1 of the present invention;

8 is a schematic structural diagram of step 6 in Embodiment 1 of the present invention;

9 is a schematic structural diagram of step 7 in Embodiment 1 of the present invention;

FIG. 10 is a schematic structural diagram of step 8 in Embodiment 1 of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be further described in detail below with reference to the embodiments and drawings, but the embodiments of the present invention are not limited thereto.

Example 1

A method for fabricating a radio frequency identification tag based on a thin film process, the radio frequency identification tag comprising an antenna, an analog front end circuit, a clock and a digital logic circuit, and an EEPROM storage circuit, the EEPROM storage circuit including a memory device and a peripheral read/write circuit. The analog front end circuit, the clock and digital logic circuit, and the EEPROM peripheral read/write circuit are composed of conventional thin film transistors, and the EEPROM memory device is composed of a memory thin film transistor. A conventional thin film transistor adopts an etch barrier structure, as shown in FIG. 1, the substrate 1 is a glass substrate or a flexible substrate, and the gate electrode 2 is formed by conventional Mo, physical sputter deposition, wet etching patterning. The thickness of the gate insulating layer is 200 nm; the gate insulating layer is formed by a SiNx/SiO ₂ stacked structure (including 3, 4, 5, and 6) by plasma enhanced chemical vapor deposition and dry etching, wherein the thickness of SiNx is 250 nm. The thickness of SiO ₂ is 50 nm; the active layer 7 is made of a semiconductor material, deposited by radio frequency magnetron sputtering, patterned by wet etching, and has a thickness of 30 nm; the etch barrier layer 8 is made of SiO ₂ material, and plasma enhanced chemical vapor phase is used. Deposition, dry etching patterning, thickness 200 nm; source/drain electrodes 9 using MoAlMo laminated metal, physical sputter deposition, wet etching patterning, thickness 50 nm / 100 nm / 50 nm, respectively. The memory thin film transistor adopts a floating gate structure. As shown in FIG. 2, the substrate 1 is a glass substrate, and the gate electrode 2 is formed by conventional Mo, physical sputter deposition, wet etching, and the thickness is 200 nm. The storage TFT floating gate layer 4 is made of SiNx material, plasma enhanced chemical vapor deposition, dry etching patterning, wherein the thickness of SiNx is 50 nm, and the TFT tunneling insulating layer 6 is deposited by atomic layer using SiO ₂ , dry etching The etched pattern has a thickness of 10 nm; the active layer 7 is made of a semiconductor material, RF magnetron sputtering, wet etching, and has a thickness of 30 nm; the etch stop layer 8 is made of SiO ₂ and is enhanced by plasma. Chemical vapor deposition, dry etching patterning, thickness 200nm; source/drain electrode 9 and antenna pattern using MoAlMo laminated metal, physical sputter deposition, wet etching patterning, thickness 50nm/100nm/50nm . The structural difference between the two thin film transistors is the thickness of the insulating layer, and the present invention utilizes the following process steps to form different insulating layer thicknesses:

As shown in Figure 3, step 1, forming a gate metal pattern 2 having a thickness of 200 nm on the substrate 1, the gate metal pattern forming a gate electrode 2;

As shown in FIG. 4, step 2, forming a SiNx layer 3 having a thickness of 200 nm on the first gate metal pattern;

As shown in FIG. 5, in step 3, a memory TFT floating gate layer 4 having a thickness of 50 nm is formed on the SiNx layer and the second gate metal pattern having a thickness of A, which is also a SiNx layer;

As shown in FIG. 6, step 4, forming a SiO ₂ insulating layer 5 having a thickness of 40 nm on the floating gate of the memory TFT above the first gate metal pattern;

As shown in FIG. 7, in step 5, a memory TFT tunneling insulating layer 6 having a thickness of 10 nm is formed on the SiO ₂ insulating layer and the floating gate of the memory TFT, which is also a SiO ₂ layer;

As shown in FIG. 8, in step 6, a pattern of an active layer 7 having a thickness of 30 nm is formed on the tunnel insulating layer;

As shown in FIG. 9, step 7, respectively, forming a SiO ₂ etch stop layer 8 having a thickness of 200 nm at an intermediate position on the active layer above the first and second gate metal patterns;

As shown in FIG. 10, in step 8, a source/drain electrode 9 and an antenna pattern having a thickness of 200 nm are formed on the SiO ₂ etch barrier layer.

Example 2

The second embodiment is a method for preparing a radio frequency identification tag based on a thin film process, and the radio frequency identification tag is composed of an antenna, an analog front end circuit, a clock, and a digital logic circuit. The analog front end circuit, clock and digital logic circuit are composed of conventional thin film transistors. A conventional thin film transistor adopts an etch barrier structure. The structure is as shown in FIG. 1. The substrate 1 is a glass substrate, and the gate electrode 2 is formed by conventional Mo, physical sputtering deposition, wet etching, and thickness. 200 nm; the gate insulating layer is a SiNx/SiO ₂ stacked structure (including 3, 4, 5 and 6), plasma-enhanced chemical vapor deposition, dry etching patterning, wherein the thickness of SiNx is 250 nm, the thickness of SiO ₂ 50 nm; the active layer 7 is made of a semiconductor material, RF magnetron sputtering deposition, wet etching patterning, thickness of 30 nm; etching barrier layer 8 is made of SiO ₂ material, plasma enhanced chemical vapor deposition, dry method The etching was patterned to a thickness of 200 nm; the source/drain electrodes 9 were laminated with MoAlMo, physically sputter deposited, and wet etched with a thickness of 50 nm/100 nm/50 nm, respectively. The invention utilizes the following process steps to form an integration of an antenna, an analog front end circuit, a clock, and a digital logic circuit:

Step 1, forming a gate metal pattern having a thickness of 200 nm on the substrate 1, the gate metal pattern forming a gate electrode 2;

Step 2, forming SiNx layers 3 and 4 having a thickness of 250 nm and 50 nm of SiO ₂ insulating layers 5 and 6, forming a gate insulating layer pattern;

Step 3, forming a pattern of the active layer 7 having a thickness of 30 nm;

Step 4, forming a SiO ₂ etch stop layer 8 having a thickness of 200 nm;

In step 5, a source/drain electrode 9 having a thickness of 200 nm and an antenna pattern are formed.

Example 3

The third embodiment is a method for preparing a radio frequency identification tag based on a thin film process. The radio frequency identification tag comprises an analog front end circuit, a clock and a digital logic circuit, and an EEPROM storage circuit. The EEPROM storage circuit includes a memory device and a peripheral read/write circuit. The analog front end circuit, the clock and digital logic circuit, and the EEPROM peripheral read/write circuit are composed of conventional thin film transistors, and the EEPROM memory device is composed of a memory thin film transistor. A conventional thin film transistor adopts an etch barrier structure. The structure is as shown in FIG. 1. The substrate 1 is a glass substrate, and the gate electrode 2 is formed by conventional Mo, physical sputtering deposition, wet etching, and thickness. 200 nm; the gate insulating layer is a SiNx/SiO ₂ stacked structure (including 3, 4, 5 and 6), plasma-enhanced chemical vapor deposition, dry etching patterning, wherein the thickness of SiNx is 250 nm, the thickness of SiO ₂ 50 nm; the active layer 7 is made of a semiconductor material, RF magnetron sputtering deposition, wet etching patterning, thickness of 30 nm; etching barrier layer 8 is made of SiO ₂ material, plasma enhanced chemical vapor deposition, dry method The etching was patterned to a thickness of 200 nm; the source/drain electrodes 9 were laminated with MoAlMo, physically sputter deposited, and wet etched with a thickness of 50 nm/100 nm/50 nm, respectively. The memory thin film transistor adopts a floating gate structure. As shown in FIG. 2, the substrate 1 is a glass substrate, and the gate electrode 2 is formed by conventional Mo, physical sputter deposition, wet etching, and the thickness is 200 nm. The floating gate layer 4 is made of SiNx material by plasma enhanced chemical vapor deposition, dry etching and patterning, wherein the thickness of SiNx is 50 nm, the tunneling insulating layer 6 is deposited by atomic layer using SiO ₂ , and is patterned by dry etching. The thickness of the active layer 7 is semiconductor material, RF magnetron sputtering deposition, wet etching patterning, thickness of 30 nm; etching barrier layer 8 is made of SiO ₂ material, plasma enhanced chemical vapor deposition The dry etching is patterned to have a thickness of 200 nm; the source/drain electrodes 9 are made of MoAlMo laminated metal, physically sputter deposited, and wet etched patterned to have a thickness of 50 nm/100 nm/50 nm, respectively. The structural difference between the two thin film transistors is the thickness of the insulating layer, and the present invention utilizes the following process steps to form different insulating layer thicknesses:

Step 1, forming a first and second gate metal pattern having a thickness of 200 nm on the substrate 1 to form a gate electrode 2;

Step 2, forming a SiNx layer 3 having a thickness of 200 nm on the first gate metal pattern;

Step 3, forming a memory TFT floating gate layer 4 having a thickness of 50 nm on the SiNx layer and the second gate metal pattern having a thickness of A, which is also a SiNx layer;

Step 4, forming a SiO ₂ insulating layer 5 having a thickness of 40 nm on the floating gate of the memory TFT above the first gate metal pattern;

Step 5, forming a memory TFT tunneling insulating layer 6 having a thickness of 10 nm on the SiO ₂ insulating layer and the floating gate of the memory TFT, which is also a SiO ₂ layer;

Step 6, forming a pattern of the active layer 7 having a thickness of 30 nm in the tunneling insulating layer;

Step 7, respectively, forming an SiO ₂ etch stop layer 8 having a thickness of 200 nm at an intermediate position on the active layer above the first and second gate metal patterns;

In step 8, a source/drain electrode 9 having a thickness of 200 nm is formed on the SiO ₂ etch barrier layer.

The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the embodiments, and any other changes, modifications, substitutions, and combinations may be made without departing from the spirit and scope of the present invention. And simplifications, all of which are equivalent replacement means, are included in the scope of protection of the present invention.

Claims

A radio frequency identification tag manufacturing method based on a thin film process, the radio frequency identification tag comprises an antenna, an analog front end circuit, a clock and a digital logic circuit and an EEPROM storage circuit, wherein the EEPROM storage circuit comprises a memory device and a peripheral read/write circuit, wherein The feature is that the following steps are included:

S1 forming a first gate metal pattern and a second gate metal pattern on the substrate;

S2 forming a SiNx layer having a thickness of A on the first gate metal pattern;

S3 forming a memory TFT floating gate of thickness B on the SiNx layer and the second gate metal pattern of thickness A, wherein the floating gate of the storage TFT is a SiNx layer;

S4 forming a SiO 2 insulating layer having a thickness C on the floating gate of the storage TFT above the first gate metal pattern;

S5 forming a tunneling insulating layer having a thickness D on the SiO 2 insulating layer and the floating gate of the memory TFT, wherein the tunneling insulating layer is also a SiO 2 layer;

S6 forms an active layer pattern on the tunneling insulating layer;

S7 forming an SiO 2 etch stop layer at an intermediate position on the active layer above the first and second gate metal patterns, respectively;

S8 forms a source/drain electrode pattern and an antenna pattern on the SiO 2 etch barrier layer to obtain a radio frequency identification tag.
The method for preparing a radio frequency identification tag according to claim 1, wherein the first gate metal pattern and the SiNx layer sequentially formed thereon, the memory TFT floating gate, the SiO 2 insulating layer, the storage TFT tunneling insulating layer, The active layer pattern, the SiO 2 etch stop layer, and the source/drain electrode pattern constitute a conventional thin film transistor, and realize the functions of an analog front end circuit and a read/write circuit of a clock, a digital logic circuit, and an EEPROM, and the second gate metal pattern and The storage TFT floating gate, the storage TFT tunneling insulating layer, the active layer pattern, the SiO 2 etch barrier layer, and the source/drain electrode pattern formed thereon constitute a memory thin film transistor, and realize the function of the EEPROM memory device, and the antenna pattern is Implemented with source drain metal.
The method for preparing a radio frequency identification tag according to claim 2, wherein the thickness of the SiNx layer of the conventional thin film transistor is A+B, and the thickness of the insulating layer SiO 2 of the conventional thin film transistor is C+D, and the thickness of the memory thin film transistor is The thickness of the SiNx layer is B, and the thickness of the SiO 2 of the memory thin film transistor is D;

Wherein 100 nm ≤ A ≤ 400 nm, 20 nm ≤ B ≤ 80 nm, 20 nm ≤ C ≤ 80 nm, and 5 nm ≤ D ≤ 15 nm.
The radio frequency identification tag manufacturing method according to claim 1, wherein the gate insulating layer is composed of a SiNx layer/SiO 2 layer structure.
A method for preparing a radio frequency identification tag based on a thin film process, the radio frequency identification tag comprising an antenna, an analog front end circuit, a clock and a digital logic circuit, wherein the radio frequency identification tag comprises the following steps:

S1 forms a gate metal pattern on the substrate;

S2 forming a gate insulating layer on the gate metal pattern;

S3 forms an active layer pattern on the gate insulating layer;

S4 forming an SiO 2 etch stop layer on the active layer pattern;

S5 forms a source/drain electrode pattern and an antenna pattern on the SiO 2 etch barrier layer to obtain a conventional thin film transistor, which constitutes a radio frequency identification tag.
The radio frequency identification tag manufacturing method according to claim 5, wherein the analog front end circuit, the clock and the digital logic circuit are all realized by a conventional thin film transistor, and the antenna pattern is realized by a source drain metal.
The radio frequency identification tag manufacturing method according to claim 5, wherein the substrate is a glass substrate or a flexible substrate.
A radio frequency identification tag manufacturing method based on a thin film process, wherein the radio frequency identification tag includes only an EEPROM storage circuit, and the EEPROM storage circuit includes a storage device and a peripheral read/write circuit, and the method includes the following steps:

S1 forming a first gate metal pattern and a second gate metal pattern on the substrate;

S2 forming a SiNx layer having a thickness of A on the first gate metal pattern;

S3 forming a memory TFT floating gate of thickness B on the SiNx layer and the second gate metal pattern of thickness A, wherein the floating gate of the storage TFT is a SiNx layer;

S4 forming a SiO 2 insulating layer having a thickness C on the floating gate of the storage TFT above the first gate metal pattern;

S5 forming a tunneling insulating layer having a thickness D on the SiO 2 insulating layer and the floating gate of the memory TFT, wherein the tunneling insulating layer is also a SiO 2 layer;

S6 forms an active layer pattern on the tunneling insulating layer;

S7 forming an SiO 2 etch stop layer at an intermediate position on the active layer above the first and second gate metal patterns, respectively;

S8 forms a source/drain electrode pattern on the SiO 2 etch barrier layer to obtain an EEPROM memory circuit of the radio frequency identification tag.
The method for preparing a radio frequency identification tag according to claim 8, wherein the first gate metal pattern and the SiNx layer sequentially formed thereon, the memory TFT floating gate, the SiO 2 insulating layer, the storage TFT tunneling insulating layer, The active layer pattern, the SiO 2 etch stop layer, the source/drain electrode pattern constitute a conventional thin film transistor, realize EEPROM read/write circuit, the second gate metal pattern and the memory TFT floating gate and the storage TFT formed thereon The tunneling insulating layer, the active layer pattern, the SiO 2 etch barrier layer, and the source/drain electrode patterns constitute a memory thin film transistor, and an EEPROM memory device is realized.
The method according to claim 8, wherein the thickness of the SiNx layer of the conventional thin film transistor is A+B, the thickness of the insulating layer SiO 2 of the conventional thin film transistor is C+D, and the SiNx of the thin film transistor is stored. The thickness of the layer is B, and the thickness of the SiO 2 of the memory thin film transistor is D;

Wherein 100 nm ≤ A ≤ 400 nm, 20 nm ≤ B ≤ 80 nm, 20 nm ≤ C ≤ 80 nm, and 5 nm ≤ D ≤ 15 nm.